coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: imgtec/pistachio: Add SOC_REGISTERS memory region
by gerrit＠coreboot.org 31 Dec '15

31 Dec '15

the following patch was just integrated into master: commit 7100cf2b404887e4f196286e72232153ba3f0524 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jul 24 14:29:06 2015 +0100 imgtec/pistachio: Add SOC_REGISTERS memory region When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Reviewed-on: https://review.coreboot.org/12768 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/12768 for details. -gerrit

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Patch set updated for coreboot: imgtec/pistachio: Add SOC_REGISTERS memory region
by Stefan Reinauer 31 Dec '15

31 Dec '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12768 -gerrit commit a412a50f5f24d7fd09e1719d953826b2db260bea Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jul 24 14:29:06 2015 +0100 imgtec/pistachio: Add SOC_REGISTERS memory region When used with a U-boot payload it will need this region identity mapped also, so we're defining it in preparation for that functionality. Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/arch/mips/include/arch/memlayout.h | 2 ++ src/include/symbols.h | 4 ++++ src/soc/imgtec/pistachio/include/soc/memlayout.ld | 2 ++ 3 files changed, 8 insertions(+) diff --git a/src/arch/mips/include/arch/memlayout.h b/src/arch/mips/include/arch/memlayout.h index 1fc7c74..fe05bd8 100644 --- a/src/arch/mips/include/arch/memlayout.h +++ b/src/arch/mips/include/arch/memlayout.h @@ -26,4 +26,6 @@ #define DMA_COHERENT(addr, size) REGION(dma_coherent, addr, size, 4K) +#define SOC_REGISTERS(addr, size) REGION(soc_registers, addr, size, 4) + #endif /* __ARCH_MEMLAYOUT_H */ diff --git a/src/include/symbols.h b/src/include/symbols.h index aa055ec..662f44e 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -72,6 +72,10 @@ extern u8 _dma_coherent[]; extern u8 _edma_coherent[]; #define _dma_coherent_size (_edma_coherent - _dma_coherent) +extern u8 _soc_registers[]; +extern u8 _esoc_registers[]; +#define _soc_registers_size (_esoc_registers - _soc_registers) + extern u8 _framebuffer[]; extern u8 _eframebuffer[]; #define _framebuffer_size (_eframebuffer - _framebuffer) diff --git a/src/soc/imgtec/pistachio/include/soc/memlayout.ld b/src/soc/imgtec/pistachio/include/soc/memlayout.ld index edf9c41..a0b48b2 100644 --- a/src/soc/imgtec/pistachio/include/soc/memlayout.ld +++ b/src/soc/imgtec/pistachio/include/soc/memlayout.ld @@ -29,6 +29,8 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00200000, 512K) RAMSTAGE(0x00280000, 128K) + /* 0x18100000 -> 0x18540000 */ + SOC_REGISTERS(0x18100000, 0x440000) /* * GRAM becomes the SRAM. Accessed through KSEG0 in the bootblock * and then through the identity mapping in ROM stage.

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Patch merged into coreboot/master: imgtec/pistachio: Use SYS PLL in integer mode
by gerrit＠coreboot.org 31 Dec '15

31 Dec '15

the following patch was just integrated into master: commit 1136447a37749135dfe172da56f9c06f3d50c664 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:42:01 2015 +0100 imgtec/pistachio: Use SYS PLL in integer mode Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Reviewed-on: https://review.coreboot.org/12767 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/12767 for details. -gerrit

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Patch set updated for coreboot: imgtec/pistachio: Use SYS PLL in integer mode
by Stefan Reinauer 31 Dec '15

31 Dec '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12767 -gerrit commit a5566f21741d4ca684e5a873a4dbad18e9d6ecc2 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Wed Jul 15 12:42:01 2015 +0100 imgtec/pistachio: Use SYS PLL in integer mode Use SYS PLL in integer mode by default to reduce jitter. DSMPD_MASK is defined and can be used to switch to fractional mode. Tested on pistachio bring up board. Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754 Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> --- src/soc/imgtec/pistachio/clocks.c | 40 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 38 insertions(+), 2 deletions(-) diff --git a/src/soc/imgtec/pistachio/clocks.c b/src/soc/imgtec/pistachio/clocks.c index 43bdc55..74d241c 100644 --- a/src/soc/imgtec/pistachio/clocks.c +++ b/src/soc/imgtec/pistachio/clocks.c @@ -27,13 +27,19 @@ #define SYS_PLL_CTRL4_ADDR 0xB8144048 #define SYS_INTERNAL_PLL_BYPASS_MASK 0x10000000 #define SYS_PLL_PD_CTRL_ADDR 0xB8144044 -#define SYS_PLL_PD_CTRL_PD_MASK 0x0000003F +#define SYS_PLL_PD_CTRL_PD_MASK 0x00000039 +#define SYS_PLL_DACPD_ADDR 0xB8144044 +#define SYS_PLL_DACPD_MASK 0x00000002 +#define SYS_PLL_DSMPD_ADDR 0xB8144044 +#define SYS_PLL_DSMPD_MASK 0x00000004 #define MIPS_EXTERN_PLL_BYPASS_MASK 0x00000002 #define MIPS_PLL_CTRL2_ADDR 0xB8144008 #define MIPS_INTERNAL_PLL_BYPASS_MASK 0x10000000 #define MIPS_PLL_PD_CTRL_ADDR 0xB8144004 -#define MIPS_PLL_PD_CTRL_PD_MASK 0x0F000000 +#define MIPS_PLL_PD_CTRL_PD_MASK 0x0D000000 +#define MIPS_PLL_DSMPD_ADDR 0xB8144004 +#define MIPS_PLL_DSMPD_MASK 0x02000000 /* Definitions for PLL dividers */ #define SYS_PLL_POSTDIV_ADDR 0xB8144040 @@ -126,6 +132,10 @@ struct pll_parameters { u32 internal_bypass_mask; u32 power_down_ctrl_addr; u32 power_down_ctrl_mask; + u32 dacpd_addr; + u32 dacpd_mask; + u32 dsmpd_addr; + u32 dsmpd_mask; u32 postdiv_addr; u32 postdiv1_shift; u32 postdiv1_mask; @@ -155,6 +165,14 @@ static struct pll_parameters pll_params[] = { .internal_bypass_mask = SYS_INTERNAL_PLL_BYPASS_MASK, .power_down_ctrl_addr = SYS_PLL_PD_CTRL_ADDR, .power_down_ctrl_mask = SYS_PLL_PD_CTRL_PD_MASK, + /* Noise cancellation */ + .dacpd_addr = SYS_PLL_DACPD_ADDR, + .dacpd_mask = SYS_PLL_DACPD_MASK, + .dsmpd_addr = SYS_PLL_DSMPD_ADDR, + /* 0 - Integer mode + * SYS_PLL_DSMPD_MASK - Fractional mode + */ + .dsmpd_mask = 0, .postdiv_addr = SYS_PLL_POSTDIV_ADDR, .postdiv1_shift = SYS_PLL_POSTDIV1_SHIFT, .postdiv1_mask = SYS_PLL_POSTDIV1_MASK, @@ -178,6 +196,10 @@ static struct pll_parameters pll_params[] = { .internal_bypass_mask = MIPS_INTERNAL_PLL_BYPASS_MASK, .power_down_ctrl_addr = MIPS_PLL_PD_CTRL_ADDR, .power_down_ctrl_mask = MIPS_PLL_PD_CTRL_PD_MASK, + .dacpd_addr = 0, + .dacpd_mask = 0, + .dsmpd_addr = MIPS_PLL_DSMPD_ADDR, + .dsmpd_mask = MIPS_PLL_DSMPD_MASK, .postdiv_addr = MIPS_PLL_POSTDIV_ADDR, .postdiv1_shift = MIPS_PLL_POSTDIV1_SHIFT, .postdiv1_mask = MIPS_PLL_POSTDIV1_MASK, @@ -222,6 +244,20 @@ static int pll_setup(struct pll_parameters *param, u8 divider1, u8 divider2) reg &= ~(param->power_down_ctrl_mask); write32(param->power_down_ctrl_addr, reg); + /* Noise cancellation */ + if (param->dacpd_addr) { + reg = read32(param->dacpd_addr); + reg &= ~(param->dacpd_mask); + write32(param->dacpd_addr, reg); + } + + /* Functional mode */ + if (param->dsmpd_addr) { + reg = read32(param->dsmpd_addr); + reg &= ~(param->dsmpd_mask); + write32(param->dsmpd_addr, reg); + } + if (param->feedback_addr) { assert(!((param->feedback << param->feedback_shift) & ~(param->feedback_mask)));

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Patch set updated for coreboot: WIP: cpu/qemu-x86: Run a C environment in the bootblock
by Alexandru Gagniuc 31 Dec '15

31 Dec '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11858 -gerrit commit 465ad8403245887cf872c382dfe8f11e4934e028 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Oct 10 16:35:58 2015 -0700 WIP: cpu/qemu-x86: Run a C environment in the bootblock Change-Id: Idf161d363d2daf3c55454d376ca42d492463971a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/Kconfig | 2 +- src/cpu/qemu-x86/Makefile.inc | 1 + src/cpu/qemu-x86/bootblock.S | 57 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ea2bc46..f956de5 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,4 +19,4 @@ config CPU_QEMU_X86 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP + select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index b5f8369..ef94a52 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -12,6 +12,7 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.S ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic diff --git a/src/cpu/qemu-x86/bootblock.S b/src/cpu/qemu-x86/bootblock.S new file mode 100644 index 0000000..72ce5f6 --- /dev/null +++ b/src/cpu/qemu-x86/bootblock.S @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/post_codes.h> + +#define STACK_SIZE 0x10000 +#define STACK_BASE 0xd0000 + +.intel_syntax noprefix + +#define post_code(code) \ + mov eax, code; \ + out 0x80, eax + +.global bootblock_pre_c_entry + +.section .text +bootblock_pre_c_entry: + + /* Set up a stack */ + mov esp, (STACK_BASE + STACK_SIZE - 4) + + /* + * We have the following goodies saved: + * mm0: BIST result + * mm1: TSC timestamp low 32 bits + * mm2: TSC timestamp high 32 bits + */ + movd eax, mm2 + push eax + movd eax, mm1 + push eax + movd eax, mm0 + push eax + call bootblock_main + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever

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Patch set updated for coreboot: arch/x86: Allow boot flow which runs CAR setup in bootblock
by Alexandru Gagniuc 31 Dec '15

31 Dec '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11784 -gerrit commit d0e35fb6fdb6bad28295d1e8c3f5fa408d731053 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:42:26 2015 -0700 arch/x86: Allow boot flow which runs CAR setup in bootblock Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Kconfig | 7 +++ src/arch/x86/Makefile.inc | 17 ++++-- src/arch/x86/bootblock.S | 40 --------------- src/arch/x86/bootblock.c | 60 ++++++++++++++++++++++ src/arch/x86/bootblock_legacy.S | 53 +++++++++++++++++++ src/arch/x86/bootblock_modern.S | 56 ++++++++++++++++++++ src/arch/x86/bootblock_normal.c | 2 +- src/arch/x86/bootblock_simple.c | 2 +- src/arch/x86/include/arch/bootblock_common.h | 77 ---------------------------- src/arch/x86/include/arch/bootblock_legacy.h | 77 ++++++++++++++++++++++++++++ src/arch/x86/include/bootblock.h | 19 +++++++ 11 files changed, 287 insertions(+), 123 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 738e7d1..28ec524 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -58,6 +58,13 @@ config ARCH_RAMSTAGE_X86_64 bool default n +# This is a new bootflow, in which a C environment is available in the +# bootblock. That can be achieved either by performing CAR setup is in the +# bootblock, or using memory available at boot-time (e.g. SRAM) +config C_ENVIRONMENT_BOOTBLOCK + bool + default n + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9713d52..6ed8a26 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -68,16 +68,15 @@ else LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 endif +bootblock-y += memcpy.c +bootblock-y += mmap_boot.c + # Add the assembly file that pulls in the rest of the dependencies in # the right order. Make sure the auto generated bootblock.inc is a proper # dependency. Make the same true for the linker sript. bootblock-y += id.S $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h -bootblock-y += bootblock.S -bootblock-y += walkcbfs.S -$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc - bootblock-y += bootblock.ld $(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld @@ -95,11 +94,21 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock. cat $^ >> $@.tmp mv $@.tmp $@ +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock_modern.S +bootblock-y += bootblock.c +else +bootblock-y += bootblock_legacy.S +bootblock-y += walkcbfs.S + +$(obj)/arch/x86/bootblock_legacy.bootblock.o: $(objgenerated)/bootblock.inc + $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ +endif # $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) $(objcbfs)/bootblock.debug: $$(bootblock-objs) diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S deleted file mode 100644 index 27a23eb..0000000 --- a/src/arch/x86/bootblock.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> - -#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#endif - -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock.c b/src/arch/x86/bootblock.c new file mode 100644 index 0000000..b569c9a --- /dev/null +++ b/src/arch/x86/bootblock.c @@ -0,0 +1,60 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbfs.h> +#include <bootblock.h> +#include <halt.h> + + +/* + * TODO: Implement a generic fallback/normal mechanism + */ +static const char *get_next_stage_name(void) +{ + if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) + return "fallback/romstage"; + + /* BOOTBLOCK_NORMAL not implemented */ + return "fallback/romstage"; +} + +static void enter_romstage(void *romstage_entry, uint32_t bist) +{ + asm volatile ( + "jmp *%0\n\t" + : : "r" (romstage_entry), "a" (bist) + ); +} + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) +{ + void *entry; + struct cbfs_stage *romstage; + const char* target1 = get_next_stage_name(); + + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + + /* + * TODO: Do something constructive with tsc_lo and tsc_hi + */ + if (romstage) { + entry = (void *)(uintptr_t)romstage->entry; + enter_romstage(entry, bist); + } + halt(); +} diff --git a/src/arch/x86/bootblock_legacy.S b/src/arch/x86/bootblock_legacy.S new file mode 100644 index 0000000..9cd7eaf --- /dev/null +++ b/src/arch/x86/bootblock_legacy.S @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is the original bootblock used by coreboot on x86 systems. It contains + * a monolithic code flow, assembled from the following stages: + * - reset16.inc: the reset vector + * - entry16.inc: protected mode setup + * - entry16.inc: segment descriptor setup + * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization + * - generated/bootblock.inc: ROMCC part of the bootblock + * + * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * tries to do the absolute minimum before walking CBFS and jumping to romstage. + * + * This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. + */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generated by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions at the beginning of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock_modern.S b/src/arch/x86/bootblock_modern.S new file mode 100644 index 0000000..a9023b9 --- /dev/null +++ b/src/arch/x86/bootblock_modern.S @@ -0,0 +1,56 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CR0_MP (1 << 1) +#define CR0_EM (1 << 2) + +#define CR4_OSFXSR (1 << 9) +#define CR4_OSXMMEXCPT (1 << 10) + +/* + * Include the old code for reset vector and protected mode entry. That code has + * withstood the test of time + */ +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +.intel_syntax noprefix + +bootblock_protected_mode_entry: + /* Save BIST result */ + movd mm0, eax + /* Save an early timestamp */ + rdtsc + movd mm1, eax + movd mm2, edx + +#if !IS_ENABLED(CONFIG_SSE) +enable_sse: + mov eax, cr0 + and ax, not CR0_EM /* Clear coprocessor emulation CR0.EM */ + or ax, CR0_MP /* Set coprocessor monitoring CR0.MP */ + mov cr0, eax + mov eax, cr4 + or ax, (CR4_OSFXSR | CR4_OSXMMEXCPT) + mov cr4, eax +#endif /* IS_ENABLED(CONFIG_SSE) */ + + /* We're done. Now it's up to platform-specific code */ + jmp bootblock_pre_c_entry diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index a6a877c..70a3775 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_legacy.h> #include <pc80/mc146818rtc.h> #include <halt.h> diff --git a/src/arch/x86/bootblock_simple.c b/src/arch/x86/bootblock_simple.c index 4bff360..f8fde9e 100644 --- a/src/arch/x86/bootblock_simple.c +++ b/src/arch/x86/bootblock_simple.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_legacy.h> #include <halt.h> static void main(unsigned long bist) diff --git a/src/arch/x86/include/arch/bootblock_common.h b/src/arch/x86/include/arch/bootblock_common.h deleted file mode 100644 index 939ba08..0000000 --- a/src/arch/x86/include/arch/bootblock_common.h +++ /dev/null @@ -1,77 +0,0 @@ -#include <arch/cbfs.h> -#include <cpu/x86/lapic/boot_cpu.c> -#include <pc80/mc146818rtc.h> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif - -#if CONFIG_USE_OPTION_TABLE -static void sanitize_cmos(void) -{ - if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { - unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); - if (cmos_default) { - int i; - cmos_disable_rtc(); - for (i = 14; i < 128; i++) { - cmos_write_inner(cmos_default[i], i); - } - cmos_enable_rtc(); - } - } -} -#endif - -#if CONFIG_CMOS_POST -static void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG_CMOS_POST_EXTRA - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} -#endif diff --git a/src/arch/x86/include/arch/bootblock_legacy.h b/src/arch/x86/include/arch/bootblock_legacy.h new file mode 100644 index 0000000..939ba08 --- /dev/null +++ b/src/arch/x86/include/arch/bootblock_legacy.h @@ -0,0 +1,77 @@ +#include <arch/cbfs.h> +#include <cpu/x86/lapic/boot_cpu.c> +#include <pc80/mc146818rtc.h> + +#ifdef CONFIG_BOOTBLOCK_RESETS +#include CONFIG_BOOTBLOCK_RESETS +#endif + +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#endif + +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) +{ +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT + bootblock_northbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT + bootblock_southbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_CPU_INIT + bootblock_cpu_init(); +#endif +} +#endif + +#if CONFIG_USE_OPTION_TABLE +static void sanitize_cmos(void) +{ + if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { + unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); + if (cmos_default) { + int i; + cmos_disable_rtc(); + for (i = 14; i < 128; i++) { + cmos_write_inner(cmos_default[i], i); + } + cmos_enable_rtc(); + } + } +} +#endif + +#if CONFIG_CMOS_POST +static void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG_CMOS_POST_EXTRA + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} +#endif diff --git a/src/arch/x86/include/bootblock.h b/src/arch/x86/include/bootblock.h new file mode 100644 index 0000000..f7671c2 --- /dev/null +++ b/src/arch/x86/include/bootblock.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _ARCH_X86_BOOTBLOCK_H +#define _ARCH_X86_BOOTBLOCK_H + +#include <arch/cpu.h> + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); + +#endif /* _ARCH_X86_BOOTBLOCK_H */

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Patch set updated for coreboot: WIP: cpu/qemu-x86: Run a C environment in the bootblock
by Alexandru Gagniuc 31 Dec '15

31 Dec '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11858 -gerrit commit e3d6c652f772f9f07666d229273ad3d301353a82 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Oct 10 16:35:58 2015 -0700 WIP: cpu/qemu-x86: Run a C environment in the bootblock Change-Id: Idf161d363d2daf3c55454d376ca42d492463971a Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/qemu-x86/Kconfig | 2 +- src/cpu/qemu-x86/Makefile.inc | 1 + src/cpu/qemu-x86/bootblock.S | 57 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index ea2bc46..f956de5 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -19,4 +19,4 @@ config CPU_QEMU_X86 select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select SMP + select C_ENVIRONMENT_BOOTBLOCK diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index b5f8369..ef94a52 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -12,6 +12,7 @@ ## GNU General Public License for more details. ## +bootblock-y += bootblock.S ramstage-y += qemu.c subdirs-y += ../x86/mtrr subdirs-y += ../x86/lapic diff --git a/src/cpu/qemu-x86/bootblock.S b/src/cpu/qemu-x86/bootblock.S new file mode 100644 index 0000000..72ce5f6 --- /dev/null +++ b/src/cpu/qemu-x86/bootblock.S @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2000,2007 Ronald G. Minnich <rminnich(a)gmail.com> + * Copyright (C) 2007-2008 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <console/post_codes.h> + +#define STACK_SIZE 0x10000 +#define STACK_BASE 0xd0000 + +.intel_syntax noprefix + +#define post_code(code) \ + mov eax, code; \ + out 0x80, eax + +.global bootblock_pre_c_entry + +.section .text +bootblock_pre_c_entry: + + /* Set up a stack */ + mov esp, (STACK_BASE + STACK_SIZE - 4) + + /* + * We have the following goodies saved: + * mm0: BIST result + * mm1: TSC timestamp low 32 bits + * mm2: TSC timestamp high 32 bits + */ + movd eax, mm2 + push eax + movd eax, mm1 + push eax + movd eax, mm0 + push eax + call bootblock_main + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever

1 0

Patch set updated for coreboot: arch/x86: Allow boot flow which runs CAR setup in bootblock
by Alexandru Gagniuc 31 Dec '15

31 Dec '15

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11784 -gerrit commit d3f486490feb636413010c8765d71df84f12222b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:42:26 2015 -0700 arch/x86: Allow boot flow which runs CAR setup in bootblock Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Kconfig | 7 +++ src/arch/x86/Makefile.inc | 17 ++++-- src/arch/x86/bootblock.S | 40 --------------- src/arch/x86/bootblock.c | 60 ++++++++++++++++++++++ src/arch/x86/bootblock_legacy.S | 53 +++++++++++++++++++ src/arch/x86/bootblock_modern.S | 56 ++++++++++++++++++++ src/arch/x86/bootblock_normal.c | 2 +- src/arch/x86/include/arch/bootblock_common.h | 77 ---------------------------- src/arch/x86/include/arch/bootblock_legacy.h | 77 ++++++++++++++++++++++++++++ src/arch/x86/include/bootblock.h | 19 +++++++ 10 files changed, 286 insertions(+), 122 deletions(-) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 738e7d1..28ec524 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -58,6 +58,13 @@ config ARCH_RAMSTAGE_X86_64 bool default n +# This is a new bootflow, in which a C environment is available in the +# bootblock. That can be achieved either by performing CAR setup is in the +# bootblock, or using memory available at boot-time (e.g. SRAM) +config C_ENVIRONMENT_BOOTBLOCK + bool + default n + # This is an SMP option. It relates to starting up APs. # It is usually set in mainboard/*/Kconfig. # TODO: Improve description. diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 9713d52..6ed8a26 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -68,16 +68,15 @@ else LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 endif +bootblock-y += memcpy.c +bootblock-y += mmap_boot.c + # Add the assembly file that pulls in the rest of the dependencies in # the right order. Make sure the auto generated bootblock.inc is a proper # dependency. Make the same true for the linker sript. bootblock-y += id.S $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h -bootblock-y += bootblock.S -bootblock-y += walkcbfs.S -$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc - bootblock-y += bootblock.ld $(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld @@ -95,11 +94,21 @@ $(objgenerated)/bootblock.ld: $$(filter-out $(obj)/arch/x86/bootblock.bootblock. cat $^ >> $@.tmp mv $@.tmp $@ +ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock_modern.S +bootblock-y += bootblock.c +else +bootblock-y += bootblock_legacy.S +bootblock-y += walkcbfs.S + +$(obj)/arch/x86/bootblock_legacy.bootblock.o: $(objgenerated)/bootblock.inc + $(objgenerated)/bootblock.inc: $(src)/arch/x86/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(objutil)/romcc/romcc $(OPTION_TABLE_H) $(KCONFIG_AUTOHEADER) @printf " ROMCC $(subst $(obj)/,,$(@))\n" $(CC_bootblock) $(CPPFLAGS_bootblock) -MM -MT$(objgenerated)/bootblock.inc \ $< > $(objgenerated)/bootblock.inc.d $(ROMCC) -c -S $(bootblock_romccflags) -I. $(CPPFLAGS_bootblock) $< -o $@ +endif # $(obj)/arch/x86/bootblock.bootblock.ld is part of $(bootblock-objs) $(objcbfs)/bootblock.debug: $$(bootblock-objs) diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S deleted file mode 100644 index 27a23eb..0000000 --- a/src/arch/x86/bootblock.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> - -#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#endif - -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock.c b/src/arch/x86/bootblock.c new file mode 100644 index 0000000..b569c9a --- /dev/null +++ b/src/arch/x86/bootblock.c @@ -0,0 +1,60 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbfs.h> +#include <bootblock.h> +#include <halt.h> + + +/* + * TODO: Implement a generic fallback/normal mechanism + */ +static const char *get_next_stage_name(void) +{ + if (IS_ENABLED(CONFIG_BOOTBLOCK_SIMPLE)) + return "fallback/romstage"; + + /* BOOTBLOCK_NORMAL not implemented */ + return "fallback/romstage"; +} + +static void enter_romstage(void *romstage_entry, uint32_t bist) +{ + asm volatile ( + "jmp *%0\n\t" + : : "r" (romstage_entry), "a" (bist) + ); +} + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi) +{ + void *entry; + struct cbfs_stage *romstage; + const char* target1 = get_next_stage_name(); + + romstage = cbfs_boot_map_with_leak(target1, CBFS_TYPE_STAGE, NULL); + + /* + * TODO: Do something constructive with tsc_lo and tsc_hi + */ + if (romstage) { + entry = (void *)(uintptr_t)romstage->entry; + enter_romstage(entry, bist); + } + halt(); +} diff --git a/src/arch/x86/bootblock_legacy.S b/src/arch/x86/bootblock_legacy.S new file mode 100644 index 0000000..9cd7eaf --- /dev/null +++ b/src/arch/x86/bootblock_legacy.S @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is the original bootblock used by coreboot on x86 systems. It contains + * a monolithic code flow, assembled from the following stages: + * - reset16.inc: the reset vector + * - entry16.inc: protected mode setup + * - entry16.inc: segment descriptor setup + * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization + * - generated/bootblock.inc: ROMCC part of the bootblock + * + * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * tries to do the absolute minimum before walking CBFS and jumping to romstage. + * + * This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. + */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generated by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions at the beginning of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock_modern.S b/src/arch/x86/bootblock_modern.S new file mode 100644 index 0000000..a9023b9 --- /dev/null +++ b/src/arch/x86/bootblock_modern.S @@ -0,0 +1,56 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CR0_MP (1 << 1) +#define CR0_EM (1 << 2) + +#define CR4_OSFXSR (1 << 9) +#define CR4_OSXMMEXCPT (1 << 10) + +/* + * Include the old code for reset vector and protected mode entry. That code has + * withstood the test of time + */ +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +.intel_syntax noprefix + +bootblock_protected_mode_entry: + /* Save BIST result */ + movd mm0, eax + /* Save an early timestamp */ + rdtsc + movd mm1, eax + movd mm2, edx + +#if !IS_ENABLED(CONFIG_SSE) +enable_sse: + mov eax, cr0 + and ax, not CR0_EM /* Clear coprocessor emulation CR0.EM */ + or ax, CR0_MP /* Set coprocessor monitoring CR0.MP */ + mov cr0, eax + mov eax, cr4 + or ax, (CR4_OSFXSR | CR4_OSXMMEXCPT) + mov cr4, eax +#endif /* IS_ENABLED(CONFIG_SSE) */ + + /* We're done. Now it's up to platform-specific code */ + jmp bootblock_pre_c_entry diff --git a/src/arch/x86/bootblock_normal.c b/src/arch/x86/bootblock_normal.c index a6a877c..70a3775 100644 --- a/src/arch/x86/bootblock_normal.c +++ b/src/arch/x86/bootblock_normal.c @@ -1,5 +1,5 @@ #include <smp/node.h> -#include <arch/bootblock_common.h> +#include <arch/bootblock_legacy.h> #include <pc80/mc146818rtc.h> #include <halt.h> diff --git a/src/arch/x86/include/arch/bootblock_common.h b/src/arch/x86/include/arch/bootblock_common.h deleted file mode 100644 index 939ba08..0000000 --- a/src/arch/x86/include/arch/bootblock_common.h +++ /dev/null @@ -1,77 +0,0 @@ -#include <arch/cbfs.h> -#include <cpu/x86/lapic/boot_cpu.c> -#include <pc80/mc146818rtc.h> - -#ifdef CONFIG_BOOTBLOCK_RESETS -#include CONFIG_BOOTBLOCK_RESETS -#endif - -#ifdef CONFIG_BOOTBLOCK_CPU_INIT -#include CONFIG_BOOTBLOCK_CPU_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT -#endif - -#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT -#include CONFIG_BOOTBLOCK_MAINBOARD_INIT -#else -static void bootblock_mainboard_init(void) -{ -#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT - bootblock_northbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT - bootblock_southbridge_init(); -#endif -#ifdef CONFIG_BOOTBLOCK_CPU_INIT - bootblock_cpu_init(); -#endif -} -#endif - -#if CONFIG_USE_OPTION_TABLE -static void sanitize_cmos(void) -{ - if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { - unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); - if (cmos_default) { - int i; - cmos_disable_rtc(); - for (i = 14; i < 128; i++) { - cmos_write_inner(cmos_default[i], i); - } - cmos_enable_rtc(); - } - } -} -#endif - -#if CONFIG_CMOS_POST -static void cmos_post_init(void) -{ - u8 magic = CMOS_POST_BANK_0_MAGIC; - - /* Switch to the other bank */ - switch (cmos_read(CMOS_POST_BANK_OFFSET)) { - case CMOS_POST_BANK_1_MAGIC: - break; - case CMOS_POST_BANK_0_MAGIC: - magic = CMOS_POST_BANK_1_MAGIC; - break; - default: - /* Initialize to zero */ - cmos_write(0, CMOS_POST_BANK_0_OFFSET); - cmos_write(0, CMOS_POST_BANK_1_OFFSET); -#if CONFIG_CMOS_POST_EXTRA - cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); - cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); -#endif - } - - cmos_write(magic, CMOS_POST_BANK_OFFSET); -} -#endif diff --git a/src/arch/x86/include/arch/bootblock_legacy.h b/src/arch/x86/include/arch/bootblock_legacy.h new file mode 100644 index 0000000..939ba08 --- /dev/null +++ b/src/arch/x86/include/arch/bootblock_legacy.h @@ -0,0 +1,77 @@ +#include <arch/cbfs.h> +#include <cpu/x86/lapic/boot_cpu.c> +#include <pc80/mc146818rtc.h> + +#ifdef CONFIG_BOOTBLOCK_RESETS +#include CONFIG_BOOTBLOCK_RESETS +#endif + +#ifdef CONFIG_BOOTBLOCK_CPU_INIT +#include CONFIG_BOOTBLOCK_CPU_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#include CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT +#endif + +#ifdef CONFIG_BOOTBLOCK_MAINBOARD_INIT +#include CONFIG_BOOTBLOCK_MAINBOARD_INIT +#else +static void bootblock_mainboard_init(void) +{ +#ifdef CONFIG_BOOTBLOCK_NORTHBRIDGE_INIT + bootblock_northbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_SOUTHBRIDGE_INIT + bootblock_southbridge_init(); +#endif +#ifdef CONFIG_BOOTBLOCK_CPU_INIT + bootblock_cpu_init(); +#endif +} +#endif + +#if CONFIG_USE_OPTION_TABLE +static void sanitize_cmos(void) +{ + if (cmos_error() || !cmos_chksum_valid() || IS_ENABLED(CONFIG_STATIC_OPTION_TABLE)) { + unsigned char *cmos_default = (unsigned char*)walkcbfs("cmos.default"); + if (cmos_default) { + int i; + cmos_disable_rtc(); + for (i = 14; i < 128; i++) { + cmos_write_inner(cmos_default[i], i); + } + cmos_enable_rtc(); + } + } +} +#endif + +#if CONFIG_CMOS_POST +static void cmos_post_init(void) +{ + u8 magic = CMOS_POST_BANK_0_MAGIC; + + /* Switch to the other bank */ + switch (cmos_read(CMOS_POST_BANK_OFFSET)) { + case CMOS_POST_BANK_1_MAGIC: + break; + case CMOS_POST_BANK_0_MAGIC: + magic = CMOS_POST_BANK_1_MAGIC; + break; + default: + /* Initialize to zero */ + cmos_write(0, CMOS_POST_BANK_0_OFFSET); + cmos_write(0, CMOS_POST_BANK_1_OFFSET); +#if CONFIG_CMOS_POST_EXTRA + cmos_write32(CMOS_POST_BANK_0_EXTRA, 0); + cmos_write32(CMOS_POST_BANK_1_EXTRA, 0); +#endif + } + + cmos_write(magic, CMOS_POST_BANK_OFFSET); +} +#endif diff --git a/src/arch/x86/include/bootblock.h b/src/arch/x86/include/bootblock.h new file mode 100644 index 0000000..f7671c2 --- /dev/null +++ b/src/arch/x86/include/bootblock.h @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _ARCH_X86_BOOTBLOCK_H +#define _ARCH_X86_BOOTBLOCK_H + +#include <arch/cpu.h> + +asmlinkage void bootblock_main(uint32_t bist, uint32_t tsc_lo, uint32_t tsc_hi); + +#endif /* _ARCH_X86_BOOTBLOCK_H */

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New patch to review for coreboot: util/crossgcc: Add ppc64el support
by Timothy Pearson 31 Dec '15

31 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12818 -gerrit commit cd57076793fa4f49e1c0067d3cd5647f711c7dc5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Dec 30 18:59:00 2015 -0600 util/crossgcc: Add ppc64el support Change-Id: I619f7c3cef7f0aaa6fccb3d52f2ac1f6ace6d0d6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- Makefile.inc | 14 ++++++++++---- util/crossgcc/Makefile | 5 ++++- util/crossgcc/buildgcc | 21 +++++++++++---------- 3 files changed, 25 insertions(+), 15 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 06dea87..000ad63 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -488,7 +488,7 @@ help_toolchain help:: @echo ' clang - Build coreboot clang compiler' @echo ' crossgcc-ARCH - Build cross-compiler for specific architecture' @echo ' crosstools-ARCH - Build cross-compiler with GDB for specific architecture' - @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", or "riscv"' + @echo ' ARCH can be "i386", "x64", "arm", "aarch64", "mips", "riscv", or "power8"' @echo ' Use "make [target] CPUS=#" to build toolchain using multiple cores' @echo @@ -499,9 +499,9 @@ crossgcc: clean-for-update $(MAKE) -C util/crossgcc all_without_gdb SKIP_CLANG=1 .PHONY: crossgcc crossgcc-i386 crossgcc-x64 crossgcc-arm crossgcc-aarch64 \ - crossgcc-mips crossgcc-riscv crossgcc-clean iasl clang tools \ - crosstools-i386 crosstools-x64 crosstools-arm crosstools-aarch64 \ - crosstools-mips crosstools-riscv + crossgcc-mips crossgcc-riscv crossgcc-power8 crossgcc-clean iasl \ + clang tools crosstools-i386 crosstools-x64 crosstools-arm \ + crosstools-aarch64 crosstools-mips crosstools-riscv crosstools-power8 crossgcc-i386: clean-for-update $(MAKE) -C util/crossgcc build-i386 SKIP_GDB=1 @@ -521,6 +521,9 @@ crossgcc-mips: clean-for-update crossgcc-riscv: clean-for-update $(MAKE) -C util/crossgcc build-riscv SKIP_GDB=1 +crossgcc-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 SKIP_GDB=1 + crosstools: clean-for-update $(MAKE) -C util/crossgcc all_with_gdb SKIP_CLANG=1 @@ -548,6 +551,9 @@ crosstools-mips: clean-for-update crosstools-riscv: clean-for-update $(MAKE) -C util/crossgcc build-riscv +crosstools-power8: clean-for-update + $(MAKE) -C util/crossgcc build-power8 + crossgcc-clean: clean-for-update $(MAKE) -C util/crossgcc clean diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 152115c..79e0c3c 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -61,6 +61,9 @@ build-mips: build-riscv: @$(MAKE) build_tools BUILD_PLATFORM=riscv-elf +build-power8: + @$(MAKE) build_tools BUILD_PLATFORM=powerpc64le-linux-gnu + clean_tempfiles: rm -rf build-* rm -rf binutils-* gcc-* gmp-* libelf-* mpc-* mpfr-* @@ -77,5 +80,5 @@ distclean: clean .PHONY: build_gcc build_iasl build_gdb build_clang \ all all_with_gdb all_without_gdb build_tools \ - build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv \ + build-i386 build-x64 build-armv7a build-aarch64 build-mips build-riscv build-power8 \ clean distclean clean_tempfiles diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 8b52d5f..c08c216 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -590,16 +590,17 @@ fi printversion case "$TARGETARCH" in - x86_64-elf) ;; - x86_64*) TARGETARCH=x86_64-elf;; - i386-elf) ;; - i386-mingw32) ;; - mipsel-elf) ;; - riscv-elf) ;; - i386*) TARGETARCH=i386-elf;; - arm*) TARGETARCH=armv7-a-eabi;; - aarch64*) TARGETARCH=aarch64-elf;; - *) printf "${red}WARNING: Unsupported architecture $TARGETARCH.${NC}\n\n"; ;; + x86_64-elf) ;; + x86_64*) TARGETARCH=x86_64-elf;; + i386-elf) ;; + i386-mingw32) ;; + mipsel-elf) ;; + riscv-elf) ;; + powerpc64le-linux-gnu) ;; + i386*) TARGETARCH=i386-elf;; + arm*) TARGETARCH=armv7-a-eabi;; + aarch64*) TARGETARCH=aarch64-elf;; + *) printf "${red}WARNING: Unsupported architecture $TARGETARCH.${NC}\n\n"; ;; esac # Figure out which packages to build

1 0

Patch set updated for coreboot: util/crossgcc: Bump GMP version to 6.1.0
by Timothy Pearson 31 Dec '15

31 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12811 -gerrit commit 036d543f0df0745bc88f4e4b93a7393d63186e36 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Dec 28 22:53:29 2015 -0600 util/crossgcc: Bump GMP version to 6.1.0 The previous official GMP release (6.0.0) contains a bug that prevents compilation on ppc64el systems. Increase version to the latest version (6.1.0). Bug details: gcc build on ppc64el fails with: (.text+0x4c): undefined reference to `BMOD_1_TO_MOD_1_THRESHOLD' While I don't have an exact commit hash due to Hg use upstream, a missing BMOD_1_TO_MOD_1_THRESHOLD define on ppc64el was quietly fixed in Hg before the 6.1.0 release. Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/crossgcc/buildgcc | 4 ++-- util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum | 1 - util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 77e8bbd..988e3c3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -31,7 +31,7 @@ SAVETEMPS=0 SKIPPYTHON=1 # GCC toolchain version numbers -GMP_VERSION=6.0.0 +GMP_VERSION=6.1.0 MPFR_VERSION=3.1.2 MPC_VERSION=1.0.3 LIBELF_VERSION=0.8.13 @@ -46,7 +46,7 @@ EXPAT_VERSION=2.1.0 CLANG_VERSION=3.6.1 # GCC toolchain archive locations -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}a.tar.bz2" +GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" diff --git a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum deleted file mode 100644 index 67d60bf..0000000 --- a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -360802e3541a3da08ab4b55268c80f799939fddc tarballs/gmp-6.0.0a.tar.bz2 diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum new file mode 100644 index 0000000..06db257 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum @@ -0,0 +1 @@ +db38c7b67f8eea9f2e5b8a48d219165b2fdab11f tarballs/gmp-6.1.0.tar.bz2

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coreboot-gerrit December 2015