coreboot-gerrit December 2015

coreboot-gerrit@coreboot.org

1 participants
752 discussions

Patch merged into coreboot/master: MAINTAINERS: Designate Intel maintainer for FSP 1.0 Ivy Bridge
by gerrit＠coreboot.org 29 Dec '15

29 Dec '15

the following patch was just integrated into master: commit 173fe0732b262a6c3e2b91ca7fe341a50d01f3f8 Author: Martin Roth <martinroth(a)google.com> Date: Fri Dec 4 08:42:36 2015 -0700 MAINTAINERS: Designate Intel maintainer for FSP 1.0 Ivy Bridge After several internal discussions, teams at Intel with stakes in coreboot have decided to each assign one or more maintainers. These maintainers can be expected to provide a point of contact for assistance with technical (code-related) issues, testing on real hardware, and making sure that their FSP-related areas continue to function with upstream coreboot. They understand that the inclusion of their information in the MAINTAINERS file does not give them any extra power over their areas. At the same time, nobody expects any community process to change. The one expectation is that reasonable efforts be made to contact these maintainers when making fundamental changes to their areas, or when discussing code removal. Change-Id: I33d95db12d9e394360a207c8fbcfbc15723115c6 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/12642 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: York Yang <york.yang(a)intel.com> See https://review.coreboot.org/12642 for details. -gerrit

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Patch merged into coreboot/master: device/pnp: Ability to set vendor specific logical device config
by gerrit＠coreboot.org 29 Dec '15

29 Dec '15

the following patch was just integrated into master: commit 62c0276f94ca7a02f802df2611c8c567fbcfa809 Author: Damien Zammit <damien(a)zamaudio.com> Date: Mon Dec 28 23:04:47 2015 +1100 device/pnp: Ability to set vendor specific logical device config According to the PNP ISA v1.0a spec, config registers in the range of 0xf0 up to 0xfe are vendor defined and may be used for any purpose. Config register 0xff is reserved and is defined as such. Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa are able to be set using the PNP_MSCx bit flag masks. This patch adds support for all 15 vendor specific config registers, and updates the existing superio pnp_info to use them where appropriate. Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/12808 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/12808 for details. -gerrit

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Patch merged into coreboot/master: northbridge/intel/x4x: Intel 4-series northbridge support
by gerrit＠coreboot.org 29 Dec '15

29 Dec '15

the following patch was just integrated into master: commit 43a1f780ff6809f758092136b0b38c6917c27340 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Aug 19 15:16:59 2015 +1000 northbridge/intel/x4x: Intel 4-series northbridge support Boots to console on Gigabyte GA-G41M-ES2L Ram initialization *not* included in this patch VGA native init works on analog connector Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/11305 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See https://review.coreboot.org/11305 for details. -gerrit

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Patch merged into coreboot/master: mips: add coherency argument to identity mapping
by gerrit＠coreboot.org 29 Dec '15

29 Dec '15

the following patch was just integrated into master: commit e7a336ac29b1ef5aaa1b0aa4926ed75829b491b1 Author: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Date: Fri Jul 24 15:00:20 2015 +0100 mips: add coherency argument to identity mapping In order for a U-boot payload to work properly the soc_registers region (device registers) needs to be mapped as uncached. Therefore, add a coherency argument to the identity mapping funcion which will establish the type of mapping. Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f Signed-off-by: Ionela Voinescu <ionela.voinescu(a)imgtec.com> Reviewed-on: https://review.coreboot.org/12769 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12769 for details. -gerrit

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Patch merged into coreboot/master: cbmem: Makefile: Add install target
by gerrit＠coreboot.org 29 Dec '15

29 Dec '15

the following patch was just integrated into master: commit c2b51085ca4aa3427ad788e9b402e0da46a0b1a6 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Wed Nov 11 05:40:11 2015 +0100 cbmem: Makefile: Add install target Change-Id: Ib20481e43e6ca5b56c630cdc0eb7b1b01311cbb6 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/12404 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/12404 for details. -gerrit

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Patch set updated for coreboot: util/crossgcc: Bump GMP version to 6.1.0
by Timothy Pearson 29 Dec '15

29 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12811 -gerrit commit 6f38ab7aaea0924ffa8cd010a70c81b69cf5486a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Dec 28 22:53:29 2015 -0600 util/crossgcc: Bump GMP version to 6.1.0 The previous official GMP release (6.0.0) contains a bug that prevents compilation on ppc64el systems. Increase version to the latest version (6.1.0). Bug details: gcc build on ppc64el fails with: (.text+0x4c): undefined reference to `BMOD_1_TO_MOD_1_THRESHOLD' While I don't have an exact commit hash due to Hg use upstream, a missing BMOD_1_TO_MOD_1_THRESHOLD define on ppc64el was quietly fixed in Hg before the 6.1.0 release. Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/crossgcc/buildgcc | 4 ++-- util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum | 1 - util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 77e8bbd..988e3c3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -31,7 +31,7 @@ SAVETEMPS=0 SKIPPYTHON=1 # GCC toolchain version numbers -GMP_VERSION=6.0.0 +GMP_VERSION=6.1.0 MPFR_VERSION=3.1.2 MPC_VERSION=1.0.3 LIBELF_VERSION=0.8.13 @@ -46,7 +46,7 @@ EXPAT_VERSION=2.1.0 CLANG_VERSION=3.6.1 # GCC toolchain archive locations -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}a.tar.bz2" +GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" diff --git a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum deleted file mode 100644 index 67d60bf..0000000 --- a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -360802e3541a3da08ab4b55268c80f799939fddc tarballs/gmp-6.0.0a.tar.bz2 diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum new file mode 100644 index 0000000..06db257 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum @@ -0,0 +1 @@ +db38c7b67f8eea9f2e5b8a48d219165b2fdab11f tarballs/gmp-6.1.0.tar.bz2

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Patch set updated for coreboot: superio/it8772f: Add register to set the default value of FAN speed
by Matt DeVillier 29 Dec '15

29 Dec '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12799 -gerrit commit c6abdd5455ba8df9d84be0ceedf7bf071e268f84 Author: Ted Kuo <tedkuo(a)ami.com.tw> Date: Fri Mar 27 18:59:07 2015 +0800 superio/it8772f: Add register to set the default value of FAN speed Signed-off-by: Ted Kuo <tedkuo(a)ami.com.tw> Change-Id: I70d7b572e9ae030136a39fb6fa933f486d559aef Reviewed-on: https://chromium-review.googlesource.com/262832 Reviewed-by: Shawn N <shawnn(a)chromium.org> Commit-Queue: Ted Kuo <tedkuo(a)ami.com.tw> Tested-by: Ted Kuo <tedkuo(a)ami.com.tw> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/superio/ite/it8772f/chip.h | 6 ++++++ src/superio/ite/it8772f/superio.c | 22 ++++++++++++++-------- 2 files changed, 20 insertions(+), 8 deletions(-) diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index 2ceeee0..1d84850 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -48,6 +48,12 @@ struct superio_ite_it8772f_config { u8 fan1_enable; u8 fan2_enable; u8 fan3_enable; + + /* + * Default FAN speed + */ + u8 fan2_speed; + u8 fan3_speed; }; #endif /* SUPERIO_ITE_IT8772F_CHIP_H */ diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index cac6898..2b891b2 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -137,7 +137,7 @@ static void it8772f_enable_tmpin(struct resource *res, int tmpin, /* * Setup a FAN PWM interface for software control */ -static void it8772f_enable_fan(struct resource *res, int fan) +static void it8772f_enable_fan(struct resource *res, int fan, u8 fan_speed) { u8 reg; @@ -165,8 +165,10 @@ static void it8772f_enable_fan(struct resource *res, int fan) /* Disable Smoothing */ it8772f_envc_write(res, IT8772F_FAN_CTL2_AUTO_MODE, IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); - /* Set a default medium fan speed */ - it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, 0x80); + /* Set a default fan speed */ + if (fan_speed) + it8772f_envc_write(res, IT8772F_FAN_CTL2_PWM_START, + fan_speed); break; case 3: /* Enable software operation */ @@ -175,8 +177,10 @@ static void it8772f_enable_fan(struct resource *res, int fan) /* Disable Smoothing */ it8772f_envc_write(res, IT8772F_FAN_CTL3_AUTO_MODE, IT8772F_FAN_CTL_AUTO_SMOOTHING_DIS); - /* Set a default medium fan speed */ - it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, 0x80); + /* Set a default fan speed */ + if (fan_speed) + it8772f_envc_write(res, IT8772F_FAN_CTL3_PWM_START, + fan_speed); break; } } @@ -206,11 +210,13 @@ static void it8772f_init(struct device *dev) /* Enable FANx if configured */ if (conf->fan1_enable) - it8772f_enable_fan(res, 1); + it8772f_enable_fan(res, 1, 0); if (conf->fan2_enable) - it8772f_enable_fan(res, 2); + it8772f_enable_fan(res, 2, + conf->fan2_speed ? conf->fan2_speed : 0x80); if (conf->fan3_enable) - it8772f_enable_fan(res, 3); + it8772f_enable_fan(res, 3, + conf->fan3_speed ? conf->fan3_speed : 0x80); /* * System may get wrong temperature data when SIO is in

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Patch set updated for coreboot: superio/it8772f: Add switch to enable HWM (Hardware Monitor)
by Matt DeVillier 29 Dec '15

29 Dec '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12798 -gerrit commit 16b8fe82a1285ae4fc4c8193ef7cce96d4c3979b Author: Ted Kuo <tedkuo(a)ami.com.tw> Date: Wed Mar 18 10:42:22 2015 +0800 superio/it8772f: Add switch to enable HWM (Hardware Monitor) Set up External Temperature to read via thermal diode/resistor into TMPINx register by setting thermal_mode switch. Signed-off-by: Ted Kuo <tedkuo(a)ami.com.tw> Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034 Reviewed-on: https://chromium-review.googlesource.com/260545 Reviewed-by: Shawn N <shawnn(a)chromium.org> Commit-Queue: Ted Kuo <tedkuo(a)ami.com.tw> Tested-by: Ted Kuo <tedkuo(a)ami.com.tw> (cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a) Reviewed-on: https://chromium-review.googlesource.com/262340 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/superio/ite/it8772f/chip.h | 7 +++++++ src/superio/ite/it8772f/it8772f.h | 8 +++++++ src/superio/ite/it8772f/superio.c | 44 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index 78ded22..0d80fb8 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -18,6 +18,7 @@ #define SUPERIO_ITE_IT8772F_CHIP_H #include <device/device.h> +#include "it8772f.h" struct superio_ite_it8772f_config { /* GPIO SimpleIO register values via devicetree.cb */ @@ -37,6 +38,12 @@ struct superio_ite_it8772f_config { u8 peci_tmpin; /* + * Enable thermal mode on tmpinx. + */ + enum thermal_mode tmpin1_mode; + enum thermal_mode tmpin2_mode; + + /* * Enable a FAN for sofware control. */ u8 fan1_enable; diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 8e82bef..2031fff 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -17,6 +17,13 @@ #ifndef SUPERIO_ITE_IT8772F_H #define SUPERIO_ITE_IT8772F_H +/* Supported thermal mode on TMPINx */ +enum thermal_mode { + THERMAL_MODE_DISABLED = 0, + THERMAL_DIODE, + THERMAL_RESISTOR, +}; + #define IT8772F_FDC 0x00 /* Floppy disk controller */ #define IT8772F_SP1 0x01 /* Com1 */ #define IT8772F_EC 0x04 /* Environment controller */ @@ -26,6 +33,7 @@ #define IT8772F_IR 0x0a /* Consumer IR */ /* Environmental Controller interface */ +#define IT8772F_CONFIGURATION 0x00 #define IT8772F_INTERFACE_SELECT 0x0a #define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) #define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 6c6a503..89f7cff 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <console/console.h> #include <pc80/keyboard.h> #include <arch/io.h> #include <delay.h> @@ -97,6 +98,43 @@ static void it8772f_enable_peci(struct resource *res, int tmpin) } /* + * Set up External Temperature to read via thermal diode/resistor + * into TMPINx register + */ +static void it8772f_enable_tmpin(struct resource *res, int tmpin, + enum thermal_mode mode) +{ + u8 reg; + + if (tmpin != 1 && tmpin != 2) + return; + + reg = it8772f_envc_read(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE); + + switch (mode) { + case THERMAL_DIODE: + /* Thermal Diode Mode */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + reg | tmpin); + break; + case THERMAL_RESISTOR: + /* Thermal Resistor Mode */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + reg | (tmpin << 3)); + break; + default: + printk(BIOS_ERR, "Unsupported thermal mode 0x%x on TMPIN%d\n", + mode, tmpin); + return; + } + + reg = it8772f_envc_read(res, IT8772F_CONFIGURATION); + + /* Enable the startup of monitoring operation */ + it8772f_envc_write(res, IT8772F_CONFIGURATION, reg | 0x01); +} + +/* * Setup a FAN PWM interface for software control */ static void it8772f_enable_fan(struct resource *res, int fan) @@ -160,6 +198,12 @@ static void it8772f_init(struct device *dev) /* Enable PECI if configured */ it8772f_enable_peci(res, conf->peci_tmpin); + /* Enable HWM if configured */ + if (conf->tmpin1_mode != THERMAL_MODE_DISABLED) + it8772f_enable_tmpin(res, 1, conf->tmpin1_mode); + if (conf->tmpin2_mode != THERMAL_MODE_DISABLED) + it8772f_enable_tmpin(res, 2, conf->tmpin2_mode); + /* Enable FANx if configured */ if (conf->fan1_enable) it8772f_enable_fan(res, 1);

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Patch set updated for coreboot: util/crossgcc: Bump GMP version to 6.1.0
by Timothy Pearson 29 Dec '15

29 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12811 -gerrit commit 0c1a510d7b635daf79f671ef68db07cd7c04d2a2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Dec 28 22:53:29 2015 -0600 util/crossgcc: Bump GMP version to 6.1.0 The previous official GMP release (6.0.0) contains a bug that prevents compilation on ppc64el systems. Increase version to the latest version (6.1.0). Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/crossgcc/buildgcc | 4 ++-- util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum | 1 - util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 77e8bbd..988e3c3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -31,7 +31,7 @@ SAVETEMPS=0 SKIPPYTHON=1 # GCC toolchain version numbers -GMP_VERSION=6.0.0 +GMP_VERSION=6.1.0 MPFR_VERSION=3.1.2 MPC_VERSION=1.0.3 LIBELF_VERSION=0.8.13 @@ -46,7 +46,7 @@ EXPAT_VERSION=2.1.0 CLANG_VERSION=3.6.1 # GCC toolchain archive locations -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}a.tar.bz2" +GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" diff --git a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum deleted file mode 100644 index 67d60bf..0000000 --- a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -360802e3541a3da08ab4b55268c80f799939fddc tarballs/gmp-6.0.0a.tar.bz2 diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum new file mode 100644 index 0000000..06db257 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum @@ -0,0 +1 @@ +db38c7b67f8eea9f2e5b8a48d219165b2fdab11f tarballs/gmp-6.1.0.tar.bz2

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New patch to review for coreboot: util/crossgcc: Bump GMP version to 6.1.0
by Timothy Pearson 29 Dec '15

29 Dec '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12811 -gerrit commit ddc45077eb6c11386ecad08c7426df47cf934574 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Dec 28 22:53:29 2015 -0600 util/crossgcc: Bump GMP version to 6.1.0 The previons official GMP release (6.0.0) contains a bug that prevents compilation on ppc64el systems. Increase version to the latest version (6.1.0). Change-Id: I1c05a1c194141db5f8522148c2e20e7558d34714 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- util/crossgcc/buildgcc | 4 ++-- util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum | 1 - util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum | 1 + 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 77e8bbd..988e3c3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -31,7 +31,7 @@ SAVETEMPS=0 SKIPPYTHON=1 # GCC toolchain version numbers -GMP_VERSION=6.0.0 +GMP_VERSION=6.1.0 MPFR_VERSION=3.1.2 MPC_VERSION=1.0.3 LIBELF_VERSION=0.8.13 @@ -46,7 +46,7 @@ EXPAT_VERSION=2.1.0 CLANG_VERSION=3.6.1 # GCC toolchain archive locations -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}a.tar.bz2" +GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.bz2" MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.bz2" MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" diff --git a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum deleted file mode 100644 index 67d60bf..0000000 --- a/util/crossgcc/sum/gmp-6.0.0a.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -360802e3541a3da08ab4b55268c80f799939fddc tarballs/gmp-6.0.0a.tar.bz2 diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum new file mode 100644 index 0000000..06db257 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.1.0.tar.bz2.cksum @@ -0,0 +1 @@ +db38c7b67f8eea9f2e5b8a48d219165b2fdab11f tarballs/gmp-6.1.0.tar.bz2

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coreboot-gerrit December 2015