coreboot-gerrit December 2015

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Patch set updated for coreboot: google/rikku: initial upstream migration
by Matt DeVillier 27 Dec '15

27 Dec '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12802 -gerrit commit 2211b06e57014cada81a9d8d914bee02d74aadee Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Fri Dec 25 01:36:40 2015 -0600 google/rikku: initial upstream migration Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to upstream, using google/guado as a baseline. Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/rikku/Kconfig | 64 ++++ src/mainboard/google/rikku/Kconfig.name | 2 + src/mainboard/google/rikku/Makefile.inc | 24 ++ src/mainboard/google/rikku/acpi/chromeos.asl | 19 ++ src/mainboard/google/rikku/acpi/ec.asl | 0 .../google/rikku/acpi/haswell_pci_irqs.asl | 83 +++++ src/mainboard/google/rikku/acpi/mainboard.asl | 69 +++++ src/mainboard/google/rikku/acpi/platform.asl | 71 +++++ src/mainboard/google/rikku/acpi/superio.asl | 32 ++ src/mainboard/google/rikku/acpi/thermal.asl | 340 +++++++++++++++++++++ src/mainboard/google/rikku/acpi/video.asl | 39 +++ src/mainboard/google/rikku/acpi_tables.c | 66 ++++ src/mainboard/google/rikku/board_info.txt | 7 + src/mainboard/google/rikku/chromeos.c | 101 ++++++ src/mainboard/google/rikku/cmos.layout | 135 ++++++++ src/mainboard/google/rikku/devicetree.cb | 122 ++++++++ src/mainboard/google/rikku/dsdt.asl | 57 ++++ src/mainboard/google/rikku/fadt.c | 154 ++++++++++ src/mainboard/google/rikku/gpio.h | 120 ++++++++ src/mainboard/google/rikku/hda_verb.c | 109 +++++++ src/mainboard/google/rikku/lan.c | 191 ++++++++++++ src/mainboard/google/rikku/mainboard.c | 54 ++++ src/mainboard/google/rikku/onboard.h | 42 +++ src/mainboard/google/rikku/pei_data.c | 59 ++++ src/mainboard/google/rikku/romstage.c | 63 ++++ src/mainboard/google/rikku/smihandler.c | 88 ++++++ src/mainboard/google/rikku/spd/Makefile.inc | 16 + src/mainboard/google/rikku/spd/spd.c | 37 +++ src/mainboard/google/rikku/spd/spd.h | 22 ++ src/mainboard/google/rikku/thermal.h | 55 ++++ 30 files changed, 2241 insertions(+) diff --git a/src/mainboard/google/rikku/Kconfig b/src/mainboard/google/rikku/Kconfig new file mode 100644 index 0000000..f38aebb --- /dev/null +++ b/src/mainboard/google/rikku/Kconfig @@ -0,0 +1,64 @@ +if BOARD_GOOGLE_RIKKU + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_BROADWELL + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8772F + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + +config CHROMEOS + select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC + select VIRTUAL_DEV_SWITCH + select PHYSICAL_REC_SWITCH + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +config MAINBOARD_DIR + string + default google/rikku + +config MAINBOARD_PART_NUMBER + string + default "Rikku" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + + +config MAINBOARD_FAMILY + string + depends on GENERATE_SMBIOS_TABLES + default "Google_Rikku" + +endif diff --git a/src/mainboard/google/rikku/Kconfig.name b/src/mainboard/google/rikku/Kconfig.name new file mode 100644 index 0000000..00552d0 --- /dev/null +++ b/src/mainboard/google/rikku/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_RIKKU + bool "Rikku" diff --git a/src/mainboard/google/rikku/Makefile.inc b/src/mainboard/google/rikku/Makefile.inc new file mode 100644 index 0000000..552aa06 --- /dev/null +++ b/src/mainboard/google/rikku/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += lan.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += pei_data.c +ramstage-y += pei_data.c diff --git a/src/mainboard/google/rikku/acpi/chromeos.asl b/src/mainboard/google/rikku/acpi/chromeos.asl new file mode 100644 index 0000000..bad5f47 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/chromeos.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button + Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect +}) diff --git a/src/mainboard/google/rikku/acpi/ec.asl b/src/mainboard/google/rikku/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl b/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..3244365 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/haswell_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 22 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} + diff --git a/src/mainboard/google/rikku/acpi/mainboard.asl b/src/mainboard/google/rikku/acpi/mainboard.asl new file mode 100644 index 0000000..fefb7a6 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/mainboard.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/rikku/onboard.h> + +Scope (\_SB) +{ + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +/* + * LAN connected to Root Port 3, becomes Root Port 1 after coalesce + */ +Scope (\_SB.PCI0.RP01) +{ + Device (ETH0) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { RIKKU_NIC_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (RIKKU_NIC_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} + +/* + * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce + */ +Scope (\_SB.PCI0.RP02) +{ + Device (WLAN) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { RIKKU_WLAN_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (RIKKU_WLAN_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} diff --git a/src/mainboard/google/rikku/acpi/platform.asl b/src/mainboard/google/rikku/acpi/platform.asl new file mode 100644 index 0000000..7ff90a8 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/platform.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Initialize thermal defaults */ + \_TZ.THRM._INI () + + Return(Package(){0,0}) +} diff --git a/src/mainboard/google/rikku/acpi/superio.asl b/src/mainboard/google/rikku/acpi/superio.asl new file mode 100644 index 0000000..a65b3f5 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/superio.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard +#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "superio/ite/it8772f/acpi/superio.asl" + diff --git a/src/mainboard/google/rikku/acpi/thermal.asl b/src/mainboard/google/rikku/acpi/thermal.asl new file mode 100644 index 0000000..48c49dd --- /dev/null +++ b/src/mainboard/google/rikku/acpi/thermal.asl @@ -0,0 +1,340 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (FAN4_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN4_THRESHOLD_ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/google/rikku/acpi/video.asl b/src/mainboard/google/rikku/acpi/video.asl new file mode 100644 index 0000000..1405b04 --- /dev/null +++ b/src/mainboard/google/rikku/acpi/video.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/rikku/acpi_tables.c b/src/mainboard/google/rikku/acpi_tables.c new file mode 100644 index 0000000..0af2697 --- /dev/null +++ b/src/mainboard/google/rikku/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include "thermal.h" + + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = TEMPERATURE_SENSOR_ID; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/google/rikku/board_info.txt b/src/mainboard/google/rikku/board_info.txt new file mode 100644 index 0000000..f705964 --- /dev/null +++ b/src/mainboard/google/rikku/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Acer +Board name: Chromebox CXI2 +Category: half +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rikku/chromeos.c b/src/mainboard/google/rikku/chromeos.c new file mode 100644 index 0000000..60554dd --- /dev/null +++ b/src/mainboard/google/rikku/chromeos.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/sata.h> + +#define GPIO_SPI_WP 58 +#define GPIO_REC_MODE 12 + +#define FLAG_SPI_WP 0 +#define FLAG_REC_MODE 1 +#define FLAG_DEV_MODE 2 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif + +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; +} + +#ifdef __PRE_RAM__ +void save_chromeos_gpios(void) +{ + u32 flags = 0; + + /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ + if (get_gpio(GPIO_SPI_WP)) + flags |= (1 << FLAG_SPI_WP); + + /* Recovery: GPIO12 = RECOVERY_L, active low */ + if (!get_gpio(GPIO_REC_MODE)) + flags |= (1 << FLAG_REC_MODE); + + /* Developer: Virtual */ + + pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); +} +#endif diff --git a/src/mainboard/google/rikku/cmos.layout b/src/mainboard/google/rikku/cmos.layout new file mode 100644 index 0000000..f862cd6 --- /dev/null +++ b/src/mainboard/google/rikku/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/rikku/devicetree.cb b/src/mainboard/google/rikku/devicetree.cb new file mode 100644 index 0000000..4d16ed6 --- /dev/null +++ b/src/mainboard/google/rikku/devicetree.cb @@ -0,0 +1,122 @@ +chip soc/intel/broadwell + + # Disable eDP Hotplug + register "gpu_dp_d_hotplug" = "0x00" + + # Enable DisplayPort C Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + + + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Enable FAN2 + register "fan2_enable" = "1" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end +end diff --git a/src/mainboard/google/rikku/dsdt.asl b/src/mainboard/google/rikku/dsdt.asl new file mode 100644 index 0000000..663b3c5 --- /dev/null +++ b/src/mainboard/google/rikku/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/broadwell/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <soc/intel/broadwell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/broadwell/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/rikku/fadt.c b/src/mainboard/google/rikku/fadt.c new file mode 100644 index 0000000..ace819d --- /dev/null +++ b/src/mainboard/google/rikku/fadt.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/pch.h> +#include <soc/iomap.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/rikku/gpio.h b/src/mainboard/google/rikku/gpio.h new file mode 100644 index 0000000..f58ad24 --- /dev/null +++ b/src/mainboard/google/rikku/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef RIKKU_GPIO_H +#define RIKKU_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/rikku/hda_verb.c b/src/mainboard/google/rikku/hda_verb.c new file mode 100644 index 0000000..284015d --- /dev/null +++ b/src/mainboard/google/rikku/hda_verb.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000c, // Number of jacks (NID entries) + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471cf0, + 0x01471d11, + 0x01471e11, + 0x01471f40, + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01971c11, // group 1, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f03, // connector, left panel + + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f03, // connector, left panel + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/rikku/lan.c b/src/mainboard/google/rikku/lan.c new file mode 100644 index 0000000..e5676af --- /dev/null +++ b/src/mainboard/google/rikku/lan.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include "onboard.h" + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(RIKKU_NIC_VENDOR_ID, + RIKKU_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((RIKKU_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/rikku/mainboard.c b/src/mainboard/google/rikku/mainboard.c new file mode 100644 index 0000000..5bb8fab --- /dev/null +++ b/src/mainboard/google/rikku/mainboard.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <smbios.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "onboard.h" + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +static void mainboard_init(device_t dev) +{ + lan_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/rikku/onboard.h b/src/mainboard/google/rikku/onboard.h new file mode 100644 index 0000000..2711162 --- /dev/null +++ b/src/mainboard/google/rikku/onboard.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#ifndef __ACPI__ +void lan_init(void); +#endif + +/* defines for programming the MAC address */ +#define RIKKU_NIC_VENDOR_ID 0x10EC +#define RIKKU_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define RIKKU_NIC_LED_MODE 0x00 + +/* NIC wake is GPIO 8 */ +#define RIKKU_NIC_WAKE_GPIO 8 + +/* WLAN wake is GPIO 10 */ +#define RIKKU_WLAN_WAKE_GPIO 10 + +/* IT8772F defs */ +#define IT8772F_BASE 0x2e +#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) +#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) +#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) + +#endif diff --git a/src/mainboard/google/rikku/pei_data.c b/src/mainboard/google/rikku/pei_data.c new file mode 100644 index 0000000..4eeabbe --- /dev/null +++ b/src/mainboard/google/rikku/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/rikku/romstage.c b/src/mainboard/google/rikku/romstage.c new file mode 100644 index 0000000..5f06ed9 --- /dev/null +++ b/src/mainboard/google/rikku/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> +#include <mainboard/google/rikku/spd/spd.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +#include "gpio.h" +#include "onboard.h" + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data pei_data; + + post_code(0x32); + + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + + /* Fill out PEI DATA */ + memset(&pei_data, 0, sizeof(pei_data)); + mainboard_fill_pei_data(&pei_data); + mainboard_fill_spd_data(&pei_data); + rp->pei_data = &pei_data; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(rp); +} + +void mainboard_pre_console_init(void) +{ + /* Early SuperIO setup */ + ite_kill_watchdog(IT8772F_GPIO_DEV); + it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On GPIO10.LED */ + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, + 0x01 /* output */, 0x01 /* 1=Simple IO function */, + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + +} diff --git a/src/mainboard/google/rikku/smihandler.c b/src/mainboard/google/rikku/smihandler.c new file mode 100644 index 0000000..c0b8186 --- /dev/null +++ b/src/mainboard/google/rikku/smihandler.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <elog.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <superio/ite/it8772f/it8772f.h> +#include "onboard.h" + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + return 1; +} + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x01 /* polarity */, 0x01 /* 1=pullup */, + 0x01 /* output */, 0x00, /* 0=Alternate function */ + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + case 5: + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, + 0x01 /* output */, 0x01 /* 1=Simple IO function */, + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + default: + break; + } + return; +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + } + return 0; +} diff --git a/src/mainboard/google/rikku/spd/Makefile.inc b/src/mainboard/google/rikku/spd/Makefile.inc new file mode 100644 index 0000000..90f22d8 --- /dev/null +++ b/src/mainboard/google/rikku/spd/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2015 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c diff --git a/src/mainboard/google/rikku/spd/spd.c b/src/mainboard/google/rikku/spd/spd.c new file mode 100644 index 0000000..74879f2 --- /dev/null +++ b/src/mainboard/google/rikku/spd/spd.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <mainboard/google/rikku/spd/spd.h> + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0x00; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0x00; + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + // Enable 2x refresh mode + pei_data->ddr_refresh_2x = 1; + pei_data->dq_pins_interleaved = 1; +} diff --git a/src/mainboard/google/rikku/spd/spd.h b/src/mainboard/google/rikku/spd/spd.h new file mode 100644 index 0000000..e48d93f --- /dev/null +++ b/src/mainboard/google/rikku/spd/spd.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif diff --git a/src/mainboard/google/rikku/thermal.h b/src/mainboard/google/rikku/thermal.h new file mode 100644 index 0000000..92e9b98 --- /dev/null +++ b/src/mainboard/google/rikku/thermal.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x84 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 42 +#define FAN3_THRESHOLD_ON 47 +#define FAN3_PWM 0xa5 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 54 +#define FAN2_THRESHOLD_ON 59 +#define FAN2_PWM 0xb2 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 66 +#define FAN1_THRESHOLD_ON 71 +#define FAN1_PWM 0xc9 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 78 +#define FAN0_THRESHOLD_ON 83 +#define FAN0_PWM 0xd8 + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif

1 0

Patch set updated for coreboot: IT8772F: Add switch to enable HWM(Hardware Monitor)
by Matt DeVillier 27 Dec '15

27 Dec '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12798 -gerrit commit d30dbfc858b0f8e4b8c82068fe13bfebd0704287 Author: Ted Kuo <tedkuo(a)ami.com.tw> Date: Wed Mar 18 10:42:22 2015 +0800 IT8772F: Add switch to enable HWM(Hardware Monitor) Setup External Temperature to read via thermal diode/resistor into TMPINx register by setting thermal_mode switch. BUG=none TEST=Compiled, verified Signed-off-by: Ted Kuo <tedkuo(a)ami.com.tw> Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034 Reviewed-on: https://chromium-review.googlesource.com/260545 Reviewed-by: Shawn N <shawnn(a)chromium.org> Commit-Queue: Ted Kuo <tedkuo(a)ami.com.tw> Tested-by: Ted Kuo <tedkuo(a)ami.com.tw> (cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a) Reviewed-on: https://chromium-review.googlesource.com/262340 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/superio/ite/it8772f/chip.h | 7 +++++++ src/superio/ite/it8772f/it8772f.h | 8 +++++++ src/superio/ite/it8772f/superio.c | 44 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index 78ded22..0d80fb8 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -18,6 +18,7 @@ #define SUPERIO_ITE_IT8772F_CHIP_H #include <device/device.h> +#include "it8772f.h" struct superio_ite_it8772f_config { /* GPIO SimpleIO register values via devicetree.cb */ @@ -37,6 +38,12 @@ struct superio_ite_it8772f_config { u8 peci_tmpin; /* + * Enable thermal mode on tmpinx. + */ + enum thermal_mode tmpin1_mode; + enum thermal_mode tmpin2_mode; + + /* * Enable a FAN for sofware control. */ u8 fan1_enable; diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 8e82bef..2031fff 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -17,6 +17,13 @@ #ifndef SUPERIO_ITE_IT8772F_H #define SUPERIO_ITE_IT8772F_H +/* Supported thermal mode on TMPINx */ +enum thermal_mode { + THERMAL_MODE_DISABLED = 0, + THERMAL_DIODE, + THERMAL_RESISTOR, +}; + #define IT8772F_FDC 0x00 /* Floppy disk controller */ #define IT8772F_SP1 0x01 /* Com1 */ #define IT8772F_EC 0x04 /* Environment controller */ @@ -26,6 +33,7 @@ #define IT8772F_IR 0x0a /* Consumer IR */ /* Environmental Controller interface */ +#define IT8772F_CONFIGURATION 0x00 #define IT8772F_INTERFACE_SELECT 0x0a #define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) #define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 6c6a503..09684ef 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <console/console.h> #include <pc80/keyboard.h> #include <arch/io.h> #include <delay.h> @@ -97,6 +98,43 @@ static void it8772f_enable_peci(struct resource *res, int tmpin) } /* + * Setup External Temperature to read via thermal diode/resistor + * into TMPINx register + */ +static void it8772f_enable_tmpin(struct resource *res, int tmpin, + enum thermal_mode mode) +{ + u8 reg; + + if (tmpin != 1 && tmpin != 2) + return; + + reg = it8772f_envc_read(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE); + + switch (mode) { + case THERMAL_DIODE: + /* Thermal Diode Mode */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + reg | tmpin); + break; + case THERMAL_RESISTOR: + /* Thermal Resistor Mode */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + reg | (tmpin << 3)); + break; + default: + printk(BIOS_ERR, "Unsupported thermal mode 0x%x on TMPIN%d\n", + mode, tmpin); + return; + } + + reg = it8772f_envc_read(res, IT8772F_CONFIGURATION); + + /* Enable the startup of monitoring operation */ + it8772f_envc_write(res, IT8772F_CONFIGURATION, reg | 0x01); +} + +/* * Setup a FAN PWM interface for software control */ static void it8772f_enable_fan(struct resource *res, int fan) @@ -160,6 +198,12 @@ static void it8772f_init(struct device *dev) /* Enable PECI if configured */ it8772f_enable_peci(res, conf->peci_tmpin); + /* Enable HWM if configured */ + if (conf->tmpin1_mode != THERMAL_MODE_DISABLED) + it8772f_enable_tmpin(res, 1, conf->tmpin1_mode); + if (conf->tmpin2_mode != THERMAL_MODE_DISABLED) + it8772f_enable_tmpin(res, 2, conf->tmpin2_mode); + /* Enable FANx if configured */ if (conf->fan1_enable) it8772f_enable_fan(res, 1);

1 0

Patch set updated for coreboot: southbridge/intel/i82801gx: Add option to skip MADT irq override
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12795 -gerrit commit df1b26f26c49077c3c60b3105ec6a2cdcf88ab8b Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Dec 23 16:54:29 2015 +1100 southbridge/intel/i82801gx: Add option to skip MADT irq override Provides Kconfig option IRQ9_MADT_OVERRIDE_OFF to skip overriding IRQ9 in MADT. Required on GA-G41M-ES2L mainboard. Change-Id: I865ad79c7c89f6eaf91653fbda5762542702274c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/southbridge/intel/i82801gx/Kconfig | 7 +++++++ src/southbridge/intel/i82801gx/lpc.c | 8 ++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index c435b99..9a09ab4 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -25,6 +25,13 @@ config SOUTHBRIDGE_INTEL_I82801GX if SOUTHBRIDGE_INTEL_I82801GX +config IRQ9_MADT_OVERRIDE_OFF + bool + default n + help + When selected, prevents ACPI from + overriding IRQ9 in MADT + config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4e9711c..5fe588d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -474,9 +474,13 @@ unsigned long acpi_fill_madt(unsigned long current) /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + if (!IS_ENABLED(CONFIG_IRQ9_MADT_OVERRIDE_OFF)) { + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *) current, + 0, 9, 9, MP_IRQ_POLARITY_HIGH + | MP_IRQ_TRIGGER_LEVEL); + } return current; }

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Patch set updated for coreboot: northbridge/intel/x4x: Native raminit
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11307 -gerrit commit e2085e1c1cd664beb0be5a1de3e31049d203d39f Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Aug 20 00:37:05 2015 +1000 northbridge/intel/x4x: Native raminit Passes memtest86+ with either one or two sticks of 2GB ram but memory map needs a hole at 0xa0000000 to 0xc0000000 Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit.c | 495 +++++++ src/northbridge/intel/x4x/raminit_ddr2.c | 2081 ++++++++++++++++++++++++++++++ 2 files changed, 2576 insertions(+) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c new file mode 100644 index 0000000..c783352 --- /dev/null +++ b/src/northbridge/intel/x4x/raminit.c @@ -0,0 +1,495 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <delay.h> +#include <halt.h> +#include <lib.h> +#include <northbridge/intel/x4x/x4x.h> +#include <pc80/mc146818rtc.h> +#include <spd.h> +#include <string.h> +#include "debug.h" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void sdram_read_spds(sysinfo_t *s) +{ + u8 i, j, chan; + int status = 0; + FOR_EACH_DIMM(i) { + for (j = 0; j < 64; j++) { + status = spd_read_byte(s->spd_map[i], j); + if (status < 0) { + s->dimms[i].card_type = 0; + break; + } + s->dimms[i].spd_data[j] = (u8) status; + PRINTK_DEBUG("%02x ", (u8) status); + if (j % 16 == 15) + PRINTK_DEBUG("\n"); + if (j == 62) + s->dimms[i].card_type = ((u8) status) & 0x1f; + } + PRINTK_DEBUG("\n"); + } + + s->spd_type = 0; + int fail = 1; + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + switch (s->dimms[i].spd_data[2]) { + case 0x8: + if (s->spd_type == 0) { + s->spd_type = DDR2; + } else if (s->spd_type == DDR3) { + die("DIMM type mismatch\n"); + } + break; + case 0xb: + default: + if (s->spd_type == 0) { + s->spd_type = DDR3; + } else if (s->spd_type == DDR2) { + die("DIMM type mismatch\n"); + } + break; + } + } + if (s->spd_type == DDR3) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x0f) + 1; + s->dimms[i].ranks = ((s->dimms[i].spd_data[7] >> 3) & 0x7) + 1; + s->dimms[i].chip_capacity = (s->dimms[i].spd_data[4] & 0xf); + s->dimms[i].banks = 8; + s->dimms[i].rows = ((s->dimms[i].spd_data[5] >> 3) & 0x7) + 12; + s->dimms[i].cols = (s->dimms[i].spd_data[5] & 0x7) + 9; + s->dimms[i].cas_latencies = 0xfe; + s->dimms[i].cas_latencies &= (s->dimms[i].spd_data[14] << 1); + if (s->dimms[i].cas_latencies == 0) + s->dimms[i].cas_latencies = 0x40; + s->dimms[i].tAAmin = s->dimms[i].spd_data[16]; + s->dimms[i].tCKmin = s->dimms[i].spd_data[12]; + s->dimms[i].width = s->dimms[i].spd_data[7] & 0x7; + s->dimms[i].page_size = s->dimms[i].width * (1 << s->dimms[i].cols); // Bytes + s->dimms[i].tRAS = ((s->dimms[i].spd_data[21] & 0xf) << 8) | + s->dimms[i].spd_data[22]; + s->dimms[i].tRP = s->dimms[i].spd_data[20]; + s->dimms[i].tRCD = s->dimms[i].spd_data[18]; + s->dimms[i].tWR = s->dimms[i].spd_data[17]; + fail = 0; + } + } else if (s->spd_type == DDR2) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + s->dimms[i].sides = (s->dimms[i].spd_data[5] & 0x7) + 1; + s->dimms[i].banks = (s->dimms[i].spd_data[17] >> 2) - 1; + s->dimms[i].chip_capacity = s->dimms[i].banks; + s->dimms[i].rows = s->dimms[i].spd_data[3];// - 12; + s->dimms[i].cols = s->dimms[i].spd_data[4];// - 9; + s->dimms[i].cas_latencies = 0x78; + s->dimms[i].cas_latencies &= s->dimms[i].spd_data[18]; + if (s->dimms[i].cas_latencies == 0) + s->dimms[i].cas_latencies = 7; + s->dimms[i].tAAmin = s->dimms[i].spd_data[26]; + s->dimms[i].tCKmin = s->dimms[i].spd_data[25]; + s->dimms[i].width = (s->dimms[i].spd_data[13] >> 3) - 1; + s->dimms[i].page_size = (s->dimms[i].width+1) * (1 << s->dimms[i].cols); // Bytes + s->dimms[i].tRAS = s->dimms[i].spd_data[30]; + s->dimms[i].tRP = s->dimms[i].spd_data[27]; + s->dimms[i].tRCD = s->dimms[i].spd_data[29]; + s->dimms[i].tWR = s->dimms[i].spd_data[36]; + s->dimms[i].ranks = s->dimms[i].sides; // XXX + + PRINTK_DEBUG("DIMM %d\n", i); + PRINTK_DEBUG(" Sides : %d\n", s->dimms[i].sides); + PRINTK_DEBUG(" Banks : %d\n", s->dimms[i].banks); + PRINTK_DEBUG(" Ranks : %d\n", s->dimms[i].ranks); + PRINTK_DEBUG(" Rows : %d\n", s->dimms[i].rows); + PRINTK_DEBUG(" Cols : %d\n", s->dimms[i].cols); + PRINTK_DEBUG(" Page size : %d\n", s->dimms[i].page_size); + PRINTK_DEBUG(" Width : %d\n", (s->dimms[i].width+1)*8); + fail = 0; + } + } + if (fail) { + die("No memory dimms, halt\n"); + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, chan) { + if (s->dimms[chan>>1].sides == 0) { + // NC + if (s->dimms[(chan>>1) + 1].sides == 0) { + // NC/NC + s->dimm_config[chan] = 0; + } else if (s->dimms[(chan>>1) + 1].sides == 1) { + // NC/SS + if (s->dimms[(chan>>1) + 1].width == 0) { + // NC/8SS + s->dimm_config[chan] = 4; + } else { + // NC/16SS + s->dimm_config[chan] = 12; + } + } else { + // NC/DS + if (s->dimms[(chan>>1) + 1].width == 0) { + // NC/8DS + s->dimm_config[chan] = 8; + } else { + // NOT SUPPORTED + die("16DS Not supported\n"); + } + } + } else if (s->dimms[chan>>1].sides == 1) { + // SS + if (s->dimms[(chan>>1) + 1].sides == 0) { + // SS/NC + if (s->dimms[chan>>1].width == 0) { + // 8SS/NC + s->dimm_config[chan] = 1; + } else { + // 16SS/NC + s->dimm_config[chan] = 3; + } + } else if (s->dimms[(chan>>1) + 1].sides == 1) { + // SS/SS + if (s->dimms[chan>>1].width == 0) { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 8SS/8SS + s->dimm_config[chan] = 5; + } else { + // 8SS/16SS + s->dimm_config[chan] = 13; + } + } else { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 16SS/8SS + s->dimm_config[chan] = 7; + } else { + // 16SS/16SS + s->dimm_config[chan] = 15; + } + } + } else { + // SS/DS + if (s->dimms[chan>>1].width == 0) { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 8SS/8DS + s->dimm_config[chan] = 9; + } else { + die("16DS not supported\n"); + } + } else { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 16SS/8DS + s->dimm_config[chan] = 11; + } else { + die("16DS not supported\n"); + } + } + } + } else { + // DS + if (s->dimms[(chan>>1) + 1].sides == 0) { + // DS/NC + if (s->dimms[chan>>1].width == 0) { + // 8DS/NC + s->dimm_config[chan] = 2; + } else { + die("16DS not supported\n"); + } + } else if (s->dimms[(chan>>1) + 1].sides == 1) { + // DS/SS + if (s->dimms[chan>>1].width == 0) { + if (s->dimms[(chan>>1) + 1].width == 0) { + // 8DS/8SS + s->dimm_config[chan] = 6; + } else { + // 8DS/16SS + s->dimm_config[chan] = 14; + } + } else { + die("16DS not supported\n"); + } + } else { + // DS/DS + if (s->dimms[chan>>1].width == 0 && s->dimms[(chan>>1)+1].width == 0) { + // 8DS/8DS + s->dimm_config[chan] = 10; + } + } + } + PRINTK_DEBUG(" Config[CH%d] : %d\n", chan, s->dimm_config[chan]); + } +} + +static u8 lsbpos(u8 val) //Forward +{ + u8 i; + for (i = 0; (i < 8) && ((val & (1 << i)) == 0); i++); + return i; +} + +static u8 msbpos(u8 val) //Reverse +{ + u8 i; + for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); + return i; +} + +static void mchinfo_ddr2(sysinfo_t *s) +{ + const u32 eax = cpuid_ext(0x04, 0).eax; + s->cores = ((eax >> 26) & 0x3f) + 1; + printk(BIOS_SPEW, "%d CPU cores\n", s->cores); + + u32 capid = pci_read_config16(PCI_DEV(0,0,0), 0xe8); + if (!(capid & (1<<(79-64)))) { + printk(BIOS_SPEW, "iTPM enabled\n"); + } + + capid = pci_read_config32(PCI_DEV(0, 0, 0), 0xe4); + if (!(capid & (1<<(57-32)))) { + printk(BIOS_SPEW, "ME enabled\n"); + } + + if (!(capid & (1<<(56-32)))) { + printk(BIOS_SPEW, "AMT enabled\n"); + } + + s->max_ddr2_mhz = (capid & (1<<(53-32)))?667:800; + printk(BIOS_SPEW, "Capable of DDR2 of %d MHz or lower\n", s->max_ddr2_mhz); + + if (!(capid & (1<<(48-32)))) { + printk(BIOS_SPEW, "VT-d enabled\n"); + } +} + +static void sdram_detect_ram_speed(sysinfo_t *s) +{ + u8 i; + u8 commoncas = 0; + u8 cas; + u8 lowcas; + u8 highcas; + u8 maxfreq; + u8 freq = 0; + + // Find max FSB speed + switch (MCHBAR32(0xc00) & 0x7) { + case 0x0: + s->max_fsb = FSB_CLOCK_1066MHz; + break; + case 0x2: + s->max_fsb = FSB_CLOCK_800MHz; + break; + case 0x4: + s->max_fsb = FSB_CLOCK_1333MHz; + break; + default: + die("Can't find FSB\n"); + break; + } + + // Find RAM speed + maxfreq = (u8) ((pci_read_config16(PCI_DEV(0,0,0), 0xea) >> 4) & 0x3f); + if (s->spd_type == DDR2) { + + // Limit frequency for MCH + maxfreq &= 0x7; + freq = MEM_CLOCK_800MHz; + if (maxfreq) { + freq = maxfreq; + } + if (freq > MEM_CLOCK_800MHz) { + freq = MEM_CLOCK_800MHz; + } + + // Detect a common CAS latency + commoncas = 0xff; + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + commoncas &= s->dimms[i].spd_data[18]; + } + if (commoncas == 0) { + die("No common CAS among dimms\n"); + } + + // Start with fastest common CAS + cas = 0; + highcas = msbpos(commoncas); + lowcas = lsbpos(commoncas); + + while (cas == 0 && highcas >= lowcas) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + switch (freq) { + case MEM_CLOCK_800MHz: + if ((s->dimms[i].spd_data[9] > 0x25) || + (s->dimms[i].spd_data[10] > 0x40)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + case MEM_CLOCK_667MHz: + default: + if ((s->dimms[i].spd_data[9] > 0x30) || + (s->dimms[i].spd_data[10] > 0x45)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + } + } + } + if (highcas < lowcas) { + // Timings not supported by MCH, lower the frequency + freq--; + cas = 0; + highcas = msbpos(commoncas); + lowcas = lsbpos(commoncas); + while (cas == 0 && highcas >= lowcas) { + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + switch (freq) { + case MEM_CLOCK_800MHz: + if ((s->dimms[i].spd_data[23] > 0x25) || + (s->dimms[i].spd_data[24] > 0x40)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + case MEM_CLOCK_667MHz: + default: + if ((s->dimms[i].spd_data[23] > 0x30) || + (s->dimms[i].spd_data[24] > 0x45)) { + // CAS too fast, lower it + highcas--; + break; + } else { + cas = highcas; + } + break; + } + } + } + } + s->selected_timings.mem_clock = freq; + s->selected_timings.CAS = cas; + + } else { // DDR3 + // Limit frequency for MCH + maxfreq >>= 3; + freq = MEM_CLOCK_1333MHz; + if (maxfreq) { + freq = maxfreq + 2; + } + if (freq > MEM_CLOCK_1333MHz) { + freq = MEM_CLOCK_1333MHz; + } + + // Limit DDR speed to FSB speed + switch (s->max_fsb) { + case FSB_CLOCK_800MHz: + if (freq > MEM_CLOCK_800MHz) { + freq = MEM_CLOCK_800MHz; + } + break; + case FSB_CLOCK_1066MHz: + if (freq > MEM_CLOCK_1066MHz) { + freq = MEM_CLOCK_1066MHz; + } + break; + case FSB_CLOCK_1333MHz: + if (freq > MEM_CLOCK_1333MHz) { + freq = MEM_CLOCK_1333MHz; + } + break; + default: + die("Invalid FSB\n"); + break; + } + + // TODO: CAS detection for DDR3 + } +} + +/** + * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 + */ +void sdram_initialize(int boot_path, const u8 *spd_map) +{ + sysinfo_t sysinfo; + u8 reg8; + + PRINTK_DEBUG("Setting up RAM controller.\n"); + + pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff); + + memset(&sysinfo, 0, sizeof(sysinfo)); + + sysinfo.boot_path = boot_path; + sysinfo.spd_map[0] = spd_map[0]; + sysinfo.spd_map[1] = spd_map[1]; + sysinfo.spd_map[2] = spd_map[2]; + sysinfo.spd_map[3] = spd_map[3]; + + /* Detect dimms per channel */ + sysinfo.dimms_per_ch = 2; + reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xe9); + if (reg8 & 0x10) { + sysinfo.dimms_per_ch = 1; + } + PRINTK_DEBUG("Dimms per channel: %d\n", sysinfo.dimms_per_ch); + + mchinfo_ddr2(&sysinfo); + + sdram_read_spds(&sysinfo); + + /* Choose Common Frequency */ + sdram_detect_ram_speed(&sysinfo); + + switch (sysinfo.spd_type) { + case DDR2: + raminit_ddr2(&sysinfo); + break; + case DDR3: + // FIXME Add: raminit_ddr3(&sysinfo); + break; + default: + die("Unknown DDR type\n"); + break; + } + + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, reg8 & ~0x80); + + reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf4); + pci_write_config8(PCI_DEV(0,0,0), 0xf4, reg8 | 1); + printk(BIOS_DEBUG, "RAM initialization finished.\n"); +} diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c new file mode 100644 index 0000000..0cdd9d5 --- /dev/null +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -0,0 +1,2081 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <commonlib/helpers.h> +#include <delay.h> +#include "x4x.h" +#include "debug.h" + +#define barrier() __asm__ __volatile__("": : :"memory") + +static u32 fsb2mhz(u32 speed) +{ + return (speed * 267) + 800; +} + +static u32 ddr2mhz(u32 speed) +{ + u32 mhz; + mhz = (speed == 2) ? 667 : + (speed == 3) ? 800 : + (speed == 4) ? 1067 : + (speed == 5) ? 1333 : + 0; + return mhz; +} + +static u8 msbpos(u8 val) //Reverse +{ + u8 i; + for (i = 7; (i >= 0) && ((val & (1 << i)) == 0); i--); + return i; +} + +static void sdram_detect_smallest_params2(sysinfo_t *s) +{ + u16 mult[6] = { + 5000, // 400 + 3750, // 533 + 3000, // 667 + 2500, // 800 + 1875, // 1066 + 1500, // 1333 + }; + + u8 i; + u32 tmp; + u32 maxtras = 0; + u32 maxtrp = 0; + u32 maxtrcd = 0; + u32 maxtwr = 0; + u32 maxtrfc = 0; + u32 maxtwtr = 0; + u32 maxtrrd = 0; + u32 maxtrtp = 0; + + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); + maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); + maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); + maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); + maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + + (s->dimms[i].spd_data[40] & 0xf)); + maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); + maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); + maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); + } + for (i = 9; i < 24; i++) { // 16 + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtras) { + s->selected_timings.tRAS = i; + break; + } + } + for (i = 3; i < 10; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtrp) { + s->selected_timings.tRP = i; + break; + } + } + for (i = 3; i < 10; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtrcd) { + s->selected_timings.tRCD = i; + break; + } + } + for (i = 3; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtwr) { + s->selected_timings.tWR = i; + break; + } + } + for (i = 15; i < 78; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtrfc) { + s->selected_timings.tRFC = ((i + 16) & 0xfe) - 15; + break; + } + } + for (i = 4; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtwtr) { + s->selected_timings.tWTR = i; + break; + } + } + for (i = 2; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtrrd) { + s->selected_timings.tRRD = i; + break; + } + } + for (i = 4; i < 15; i++) { + tmp = mult[s->selected_timings.mem_clock] * i; + if (tmp >= maxtrtp) { + s->selected_timings.tRTP = i; + break; + } + } + + s->selected_timings.fsb_clock = s->max_fsb; + + PRINTK_DEBUG("Selected timings:\n"); + PRINTK_DEBUG(" FSB: %dMHz\n", fsb2mhz(s->selected_timings.fsb_clock)); + PRINTK_DEBUG(" DDR: %dMHz\n", ddr2mhz(s->selected_timings.mem_clock)); + + PRINTK_DEBUG(" CAS: %d\n", s->selected_timings.CAS); + PRINTK_DEBUG(" tRAS: %d\n", s->selected_timings.tRAS); + PRINTK_DEBUG(" tRP: %d\n", s->selected_timings.tRP); + PRINTK_DEBUG(" tRCD: %d\n", s->selected_timings.tRCD); + PRINTK_DEBUG(" tWR: %d\n", s->selected_timings.tWR); + PRINTK_DEBUG(" tRFC: %d\n", s->selected_timings.tRFC); + PRINTK_DEBUG(" tWTR: %d\n", s->selected_timings.tWTR); + PRINTK_DEBUG(" tRRD: %d\n", s->selected_timings.tRRD); + PRINTK_DEBUG(" tRTP: %d\n", s->selected_timings.tRTP); +} + +static void clkcross_ddr2(sysinfo_t *s) +{ + u32 c04, c50, c54, x6d8, x6dc, x6e8, x6ec, x6f8, x6fc, x700, x704, x708, x70c; + + MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); + + if ((s->selected_timings.fsb_clock == FSB_CLOCK_800MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_667MHz)) { + c04 = 0x1f1f1f1f; + c50 = 0x1a07070b; + c54 = 0x0; + x6d8 = 0x10000000; + x6dc = 0x20010208; + x6e8 = 0x04080000; + x6ec = 0x10010002; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x02000000; + x704 = 0x04000100; + x708 = 0x08000000; + x70c = 0x10200204; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_800MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_800MHz)) { + c04 = 0xffffffff; + c50 = 0x05030305; + c54 = 0x0000ffff; + x6d8 = 0x0; + x6dc = 0x08010204; + x6e8 = 0x0; + x6ec = 0x08010204; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x00020001; + x708 = 0x0; + x70c = 0x04080102; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1066MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_667MHz)) { + c04 = 0x6d5b1f1f; + c50 = 0x0f0f0f0f; + c54 = 0x0; + x6d8 = 0x20000000; + x6dc = 0x80020410; + x6e8 = 0x02040008; + x6ec = 0x10000100; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x04000000; + x704 = 0x08000102; + x708 = 0x20000000; + x70c = 0x40010208; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1066MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_800MHz)) { + c04 = 0x07070707; + c50 = 0x06030303; + c54 = 0x0; + x6d8 = 0x0; + x6dc = 0x08010200; + x6e8 = 0x0; + x6ec = 0x04000102; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x00020001; + x708 = 0x0; + x70c = 0x02040801; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1066MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_1066MHz)) { + c04 = 0xffffffff; + c50 = 0x05030305; + c54 = 0x0000ffff; + x6d8 = 0x0; + x6dc = 0x04080102; + x6e8 = 0x0; + x6ec = 0x08010204; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x00020001; + x708 = 0x0; + x70c = 0x02040801; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_667MHz)) { + c04 = 0x05050303; + c50 = 0xffffffff; + c54 = 0xffff0000; + x6d8 = 0x0; + x6dc = 0x08020000; + x6e8 = 0x0; + x6ec = 0x00020001; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x08010204; + x708 = 0x0; + x70c = 0x04010000; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_800MHz)) { + c04 = 0x0d0b0707; + c50 = 0x3e1f1f2f; + c54 = 0x01010000; + x6d8 = 0x0; + x6dc = 0x10020400; + x6e8 = 0x02000000; + x6ec = 0x00040100; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x04080000; + x704 = 0x00100102; + x708 = 0x0; + x70c = 0x08100200; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_1066MHz)) { + c04 = 0x0f0f0f0f; + c50 = 0x5b1f1f6d; + c54 = 0x0; + x6d8 = 0x0; + x6dc = 0x08010204; + x6e8 = 0x04000000; + x6ec = 0x00080102; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x02000408; + x704 = 0x00100001; + x708 = 0x0; + x70c = 0x04080102; + } else if ((s->selected_timings.fsb_clock == FSB_CLOCK_1333MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_1333MHz)) { + c04 = 0xffffffff; + c50 = 0x05030305; + c54 = 0x0000ffff; + x6d8 = 0x0; + x6dc = 0x04080102; + x6e8 = 0x0; + x6ec = 0x04080102; + x6f8 = 0x0; + x6fc = 0x0; + x700 = 0x0; + x704 = 0x0; + x708 = 0x0; + x70c = 0x02040801; + } else { + die("Unsupported DDR/FSB configuration\n"); + } + + MCHBAR32(0xc04) = c04; + MCHBAR32(0xc50) = c50; + MCHBAR32(0xc54) = c54; + MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7); + + MCHBAR32(0x6d8) = x6d8; + MCHBAR32(0x6e0) = x6d8; + MCHBAR32(0x6dc) = x6dc; + MCHBAR32(0x6e4) = x6dc; + MCHBAR32(0x6e8) = x6e8; + MCHBAR32(0x6f0) = x6e8; + MCHBAR32(0x6ec) = x6ec; + MCHBAR32(0x6f4) = x6ec; + MCHBAR32(0x6f8) = x6f8; + MCHBAR32(0x6fc) = x6fc; + MCHBAR32(0x708) = x708; + MCHBAR32(0x70c) = x70c; +} + +static void checkreset_ddr2(sysinfo_t *s) +{ + u8 pmcon2; + u8 reset = 0; + +// MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; + + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + if (!(pmcon2 & 0x80)) { + pmcon2 |= 0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + reset = 1; + + /* do magic 0xf0 thing. */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + } + if (reset) { + PRINTK_DEBUG("Reset...\n"); + outb(0xe, 0xcf9); + asm ("hlt"); + } + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); +} + +static void setioclk_ddr2(sysinfo_t *s) +{ + MCHBAR32(0x1bc) = 0x08060402; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x100; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x20; + MCHBAR16(0x1c0) = MCHBAR16(0x1c0) & ~1; + switch (s->selected_timings.mem_clock) { + default: + case MEM_CLOCK_800MHz: + case MEM_CLOCK_1066MHz: + MCHBAR8(0x5d9) = (MCHBAR8(0x5d9) & ~0x2) | 0x2; + MCHBAR8(0x9d9) = (MCHBAR8(0x9d9) & ~0x2) | 0x2; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xc0; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xe0; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xa0; + break; + case MEM_CLOCK_667MHz: + case MEM_CLOCK_1333MHz: + MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2; + MCHBAR8(0x9d9) = MCHBAR8(0x9d9) & ~0x2; + MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0x40; + break; + } + MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31); + MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31); +} + +static void launch_ddr2(sysinfo_t *s) +{ + u8 i; + u32 launch1 = 0x58001117; + u32 launch2 = 0; + u32 launch3 = 0; + + if (s->selected_timings.CAS == 5) { + launch2 = 0x00220201; + } else if ((s->selected_timings.mem_clock == MEM_CLOCK_800MHz) && + (s->selected_timings.CAS == 6)) { + launch2 = 0x00230302; + } else { + die("Unsupported CAS & Frequency combination detected\n"); + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR32(0x400*i + 0x220) = launch1; + MCHBAR32(0x400*i + 0x224) = launch2; + MCHBAR32(0x400*i + 0x21c) = launch3; + MCHBAR32(0x400*i + 0x248) = MCHBAR32(0x400*i + 0x248) | (1 << 23); + } + + MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000; + MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0; + MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc; +} + +static void clkset0(u8 ch, u8 setting[5]) +{ + MCHBAR16(0x400*ch + 0x5a0) = (MCHBAR16(0x400*ch + 0x5a0) & ~0xc440) | + (setting[4] << 14) | + (setting[3] << 6) | + (setting[2] << 10); + MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0xf) | + setting[0]; +} + +static void clkset1(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x5a0) = (MCHBAR32(0x400*ch + 0x5a0) & ~0x30880) | + (setting[4] << 16) | + (setting[3] << 7) | + (setting[2] << 11); + MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0xf) | + setting[0]; +} + +static void ctrlset0(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x3300000) | + (setting[4] << 24) | + (setting[3] << 20) | + (setting[2] << 21); + MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0xf) | + setting[0]; +} + +static void ctrlset1(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x18c00000) | + (setting[4] << 27) | + (setting[3] << 22) | + (setting[2] << 23); + MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0xf) | + setting[0]; +} + +static void ctrlset2(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | + (setting[4] << 14) | + (setting[3] << 12) | + (setting[2] << 13); + MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0xf) | + setting[0]; +} + +static void ctrlset3(u8 ch, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | + (setting[4] << 10) | + (setting[3] << 8) | + (setting[2] << 9); + MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0xf) | + setting[0]; +} + +static void cmdset(u8 ch, u8 setting[5]) +{ + MCHBAR8(0x400*ch + 0x598) = (MCHBAR8(0x400*ch + 0x598) & ~0x30) | + (setting[4] << 4); + MCHBAR8(0x400*ch + 0x594) = (MCHBAR8(0x400*ch + 0x594) & ~0x60) | + (setting[3] << 5) | + (setting[2] << 6); + MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0xf) | + setting[0]; +} + +static void dqsset(u8 ch, u8 lane, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x5fc) = MCHBAR32(0x400*ch + 0x5fc) & ~(2 << (lane*4)); + + MCHBAR32(0x400*ch + 0x5b4) = (MCHBAR32(0x400*ch + 0x5b4) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5b8) = (MCHBAR32(0x400*ch + 0x5b8) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5bc) = (MCHBAR32(0x400*ch + 0x5bc) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5c0) = (MCHBAR32(0x400*ch + 0x5c0) & ~(0x201 << lane)) | + (setting[2] << (9 + lane)) | + (setting[3] << lane); + + MCHBAR32(0x400*ch + 0x5c8) = (MCHBAR32(0x400*ch + 0x5c8) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + MCHBAR32(0x400*ch + 0x5cc) = (MCHBAR32(0x400*ch + 0x5cc) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + MCHBAR32(0x400*ch + 0x5d0) = (MCHBAR32(0x400*ch + 0x5d0) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + MCHBAR32(0x400*ch + 0x5d4) = (MCHBAR32(0x400*ch + 0x5d4) & ~(0x3 << (16+lane*2))) | + (setting[4] << (16+lane*2)); + + MCHBAR8(0x400*ch + 0x520 + lane*4) = (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x520 + lane*4) = (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x521 + lane*4) = (MCHBAR8(0x400*ch + 0x521 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x521 + lane*4) = (MCHBAR8(0x400*ch + 0x521 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x522 + lane*4) = (MCHBAR8(0x400*ch + 0x522 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x522 + lane*4) = (MCHBAR8(0x400*ch + 0x522 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x523 + lane*4) = (MCHBAR8(0x400*ch + 0x523 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x523 + lane*4) = (MCHBAR8(0x400*ch + 0x523 + lane*4) & ~0xf) | + setting[0]; +} + +static void dqset(u8 ch, u8 lane, u8 setting[5]) +{ + MCHBAR32(0x400*ch + 0x5fc) = MCHBAR32(0x400*ch + 0x5fc) & ~(1 << (lane*4)); + + MCHBAR32(0x400*ch + 0x5a4) = (MCHBAR32(0x400*ch + 0x5a4) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5a8) = (MCHBAR32(0x400*ch + 0x5a8) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5ac) = (MCHBAR32(0x400*ch + 0x5ac) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + MCHBAR32(0x400*ch + 0x5b0) = (MCHBAR32(0x400*ch + 0x5b0) & ~(0x201 << lane)) | + (setting[2] << (9+lane)) | + (setting[3] << lane); + + MCHBAR32(0x400*ch + 0x5c8) = (MCHBAR32(0x400*ch + 0x5c8) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + MCHBAR32(0x400*ch + 0x5cc) = (MCHBAR32(0x400*ch + 0x5cc) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + MCHBAR32(0x400*ch + 0x5d0) = (MCHBAR32(0x400*ch + 0x5d0) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + MCHBAR32(0x400*ch + 0x5d4) = (MCHBAR32(0x400*ch + 0x5d4) & ~(0x3 << (lane*2))) | + (setting[4] << (2*lane)); + + MCHBAR8(0x400*ch + 0x500 + lane*4) = (MCHBAR8(0x400*ch + 0x500 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x500 + lane*4) = (MCHBAR8(0x400*ch + 0x500 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x501 + lane*4) = (MCHBAR8(0x400*ch + 0x501 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x501 + lane*4) = (MCHBAR8(0x400*ch + 0x501 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x502 + lane*4) = (MCHBAR8(0x400*ch + 0x502 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x502 + lane*4) = (MCHBAR8(0x400*ch + 0x502 + lane*4) & ~0xf) | + setting[0]; + MCHBAR8(0x400*ch + 0x503 + lane*4) = (MCHBAR8(0x400*ch + 0x503 + lane*4) & ~0x70) | + (setting[1] << 4); + MCHBAR8(0x400*ch + 0x503 + lane*4) = (MCHBAR8(0x400*ch + 0x503 + lane*4) & ~0xf) | + setting[0]; +} + +static void timings_ddr2(sysinfo_t *s) +{ + u8 i; + u8 twl, ta1, ta2, ta3, ta4; + u8 reg8; + u8 flag1 = 0; + u8 flag2 = 0; + u16 reg16; + u32 reg32; + u16 ddr, fsb; + u8 trpmod = 0; + u8 bankmod = 1; + u8 pagemod = 0; + + u16 fsb2ps[3] = { + 5000, // 800 + 3750, // 1067 + 3000 // 1333 + }; + + u16 ddr2ps[6] = { + 5000, // 400 + 3750, // 533 + 3000, // 667 + 2500, // 800 + 1875, // 1067 + 1500 // 1333 + }; + + u16 lut1[6] = { + 0, + 0, + 2600, + 3120, + 4171, + 5200 + }; + + ta1 = 6; + ta2 = 6; + ta3 = 5; + ta4 = 8; + + twl = s->selected_timings.CAS - 1; + + FOR_EACH_POPULATED_DIMM(s->dimms, i) { + if (s->dimms[i].banks == 1) { // 8 banks + trpmod = 1; + bankmod = 0; + } + if (s->dimms[i].page_size == 2048) { + pagemod = 1; + } + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR8(0x400*i + 0x2f6) = MCHBAR8(0x400*i + 0x2f6) | 0x3; + MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2; + MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0) | (twl << 4); + MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) | + s->selected_timings.CAS; + MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) | + ((s->selected_timings.CAS + 9) << 8); + + reg16 = (s->selected_timings.tRAS << 11) | + ((twl + 4 + s->selected_timings.tWR) << 6) | + ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; + MCHBAR16(0x400*i + 0x250) = reg16; + + reg32 = (bankmod << 21) | + (s->selected_timings.tRRD << 17) | + (s->selected_timings.tRP << 13) | + ((s->selected_timings.tRP + trpmod) << 9) | + s->selected_timings.tRFC; + reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; + if (bankmod) { + switch (s->selected_timings.mem_clock) { + default: + case MEM_CLOCK_667MHz: + if (reg8) { + if (pagemod) { + reg32 |= 16 << 22; + } else { + reg32 |= 12 << 22; + } + } else { + if (pagemod) { + reg32 |= 18 << 22; + } else { + reg32 |= 14 << 22; + } + } + break; + case MEM_CLOCK_800MHz: + if (reg8) { + if (pagemod) { + reg32 |= 18 << 22; + } else { + reg32 |= 14 << 22; + } + } else { + if (pagemod) { + reg32 |= 20 << 22; + } else { + reg32 |= 16 << 22; + } + } + break; + } + } + MCHBAR32(0x400*i + 0x252) = reg32; + + MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) | + (0x4 << 8) | (ta2 << 4) | ta4; + + MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) | + ((twl + 4 + s->selected_timings.tWTR) << 12) | + (ta3 << 8) | (4 << 4) | ta1; + + MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | + s->selected_timings.tRFC; + + MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1); + MCHBAR8(0x400*i + 0x264) = 0xff; + MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) | + s->selected_timings.tRAS; + MCHBAR16(0x400*i + 0x244) = 0x2310; + + switch (s->selected_timings.mem_clock) { + case MEM_CLOCK_667MHz: + reg8 = 0; + break; + default: + reg8 = 1; + break; + } + + MCHBAR8(0x400*i + 0x246) = (MCHBAR8(0x400*i + 0x246) & ~0x1f) | + (reg8 << 2) | 1; + + fsb = fsb2ps[s->selected_timings.fsb_clock]; + ddr = ddr2ps[s->selected_timings.mem_clock]; + reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); + reg32 = (u32)((reg32 / fsb) << 8); + reg32 |= 0x0e000000; + if ((fsb2mhz(s->selected_timings.fsb_clock) / + ddr2mhz(s->selected_timings.mem_clock)) > 2) { + reg32 |= 1 << 24; + } + MCHBAR32(0x400*i + 0x248) = (MCHBAR32(0x400*i + 0x248) & ~0x0f001f00) | + reg32; + + if (twl > 2) { + flag1 = 1; + } + if (s->selected_timings.mem_clock >= MEM_CLOCK_800MHz) { + flag2 = 1; + } + reg16 = (u8)(twl - 1 - flag1 - flag2); + reg16 |= reg16 << 4; + if (s->selected_timings.mem_clock == MEM_CLOCK_1333MHz) { + if (reg16) { + reg16--; + } + } + reg16 |= flag1 << 8; + reg16 |= flag2 << 9; + MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x1ff) | reg16; + MCHBAR16(0x400*i + 0x25e) = 0x15a5; + MCHBAR32(0x400*i + 0x265) = MCHBAR32(0x400*i + 0x265) & ~0x1f; + MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0x000fffff) | + (0x3f << 14) | lut1[s->selected_timings.mem_clock]; + MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) | 1; + MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3; + + reg16 = 0; + switch (s->selected_timings.mem_clock) { + default: + case MEM_CLOCK_667MHz: + reg16 = 0x99; + break; + case MEM_CLOCK_800MHz: + if (s->selected_timings.CAS == 5) { + reg16 = 0x19a; + } else if (s->selected_timings.CAS == 6) { + reg16 = 0x9a; + } + break; + } + reg16 &= 0x7; + reg16 += twl + 9; + reg16 <<= 10; + MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x7c00) | reg16; + MCHBAR8(0x400*i + 0x267) = (MCHBAR8(0x400*i + 0x267) & ~0x3f) | 0x13; + MCHBAR8(0x400*i + 0x268) = (MCHBAR8(0x400*i + 0x268) & ~0xff) | 0x4a; + + reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; + reg16 += 2 << 12; + reg16 |= (0x15 << 6) | 0x1f; + MCHBAR16(0x400*i + 0x26d) = (MCHBAR16(0x400*i + 0x26d) & ~0x7fff) | reg16; + + reg32 = (1 << 25) | (6 << 27); + MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0xfa300000) | reg32; + MCHBAR8(0x400*i + 0x271) = MCHBAR8(0x400*i + 0x271) & ~0x80; + MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) & ~0x6; + } // END EACH POPULATED CHANNEL + + reg16 = 0x1f << 5; + reg16 |= 0xe << 10; + MCHBAR16(0x125) = (MCHBAR16(0x125) & ~0x3fe0) | reg16; + MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540; + MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f; + MCHBAR8(0x12c) = MCHBAR8(0x12c) | 0xa0; + MCHBAR32(0x241) = (MCHBAR32(0x241) & ~0x1ffff) | 0x11; + MCHBAR32(0x641) = (MCHBAR32(0x641) & ~0x1ffff) | 0x11; + MCHBAR8(0x246) = MCHBAR8(0x246) & ~0x10; + MCHBAR8(0x646) = MCHBAR8(0x646) & ~0x10; + MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; + reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); + MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4); + reg8 = (u8)((MCHBAR32(0x258) & ~0x1e0000) >> 17); + MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; + MCHBAR8(0x12f) = 0x4c; + reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); + MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32; + MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2; +} + +static void dll_ddr2(sysinfo_t *s) +{ + u8 i, j, r, reg8, clk, async; + u16 reg16 = 0; + u32 reg32 = 0; + u8 lane; + + MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04; + MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8; + MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f; + MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x8020) | 0x100; + MCHBAR8(0x194) = (MCHBAR8(0x194) & ~0x77) | 0x33; + switch (s->selected_timings.mem_clock) { + default: + case MEM_CLOCK_667MHz: + reg16 = (0xa << 9) | 0xa; + break; + case MEM_CLOCK_800MHz: + reg16 = (0x9 << 9) | 0x9; + break; + } + MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16; + MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010; + udelay(1); + MCHBAR16(0x198) = MCHBAR16(0x198) & ~0x100; + + MCHBAR16(0x1c8) = (MCHBAR16(0x1c8) & ~0x1f) | 0xd; + + udelay(1); + MCHBAR8(0x190) = MCHBAR8(0x190) & ~1; + udelay(1); // 533ns + MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x11554000; + udelay(1); + MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x1455; + udelay(1); + MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x1c; + MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x1c; + udelay(1); // 533ns + MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x3; + MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x3; + udelay(1); // 533ns + + // ME related + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803; + + MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0; + + FOR_EACH_CHANNEL(i) { + reg16 = 0; + MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000; + + reg32 = 0; + FOR_EACH_RANK_IN_CHANNEL(r) if (!RANK_IS_POPULATED(s->dimms, i, r)) { + reg32 |= 0x111 << r; + } + MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32; + MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1; + + if (!CHANNEL_IS_POPULATED(s->dimms, i)) { + PRINTK_DEBUG("No dimms in channel %d\n", i); + reg8 = 0x3f; + } else if(ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { + PRINTK_DEBUG("DimmA populated only in channel %d\n", i); + reg8 = 0x38; + } else if(ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { + PRINTK_DEBUG("DimmB populated only in channel %d\n", i); + reg8 = 0x7; + } else if(BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { + PRINTK_DEBUG("Both dimms populated in channel %d\n", i); + reg8 = 0; + } else { + die("Unhandled case\n"); + } + + //reg8 = 0x00; // FIXME dont switch on all clocks anyway + + MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) | + ((u32)(reg8 << 24)); + } // END EACH CHANNEL + + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + + // Update DLL timing + MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80; + MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40; + MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400; + + u8 dll_setting_667[23][5] = { + // tap pi db delay + {13, 0, 1,0, 0}, + {4, 1, 0,0, 0}, + {13, 0, 1,0, 0}, + {4, 5, 0,0, 0}, + {4, 1, 0,0, 0}, + {4, 1, 0,0, 0}, + {4, 1, 0,0, 0}, + {1, 5, 1,1, 1}, + {1, 6, 1,1, 1}, + {2, 0, 1,1, 1}, + {2, 1, 1,1, 1}, + {2, 1, 1,1, 1}, + {14, 6, 1,0, 0}, + {14, 3, 1,0, 0}, + {14, 0, 1,0, 0}, + {9, 0, 0,0, 1}, + {9, 1, 0,0, 1}, + {9, 2, 0,0, 1}, + {9, 2, 0,0, 1}, + {9, 1, 0,0, 1}, + {6, 4, 0,0, 1}, + {6, 2, 0,0, 1}, + {5, 4, 0,0, 1} + }; + + u8 dll_setting_800[23][5] = { + // tap pi db delay + {11, 5, 1,0, 0}, + {0, 5, 1,1, 0}, + {11, 5, 1,0, 0}, + {1, 4, 1,1, 0}, + {0, 5, 1,1, 0}, + {0, 5, 1,1, 0}, + {0, 5, 1,1, 0}, + {2, 5, 1,1, 1}, + {2, 6, 1,1, 1}, + {3, 0, 1,1, 1}, + {3, 0, 1,1, 1}, + {3, 3, 1,1, 1}, + {2, 0, 1,1, 1}, + {1, 3, 1,1, 1}, + {0, 3, 1,1, 1}, + {9, 3, 0,0, 1}, + {9, 4, 0,0, 1}, + {9, 5, 0,0, 1}, + {9, 6, 0,0, 1}, + {10, 0, 0,0, 1}, + {8, 1, 0,0, 1}, + {7, 5, 0,0, 1}, + {6, 2, 0,0, 1} + }; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc; + MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc; + MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70; + MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555; + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { + clkset0(i, &dll_setting_667[CLKSET0][0]); + clkset1(i, &dll_setting_667[CLKSET1][0]); + ctrlset0(i, &dll_setting_667[CTRL0][0]); + ctrlset1(i, &dll_setting_667[CTRL1][0]); + ctrlset2(i, &dll_setting_667[CTRL2][0]); + ctrlset3(i, &dll_setting_667[CTRL3][0]); + cmdset(i, &dll_setting_667[CMD][0]); + } else { + clkset0(i, &dll_setting_800[CLKSET0][0]); + clkset1(i, &dll_setting_800[CLKSET1][0]); + ctrlset0(i, &dll_setting_800[CTRL0][0]); + ctrlset1(i, &dll_setting_800[CTRL1][0]); + ctrlset2(i, &dll_setting_800[CTRL2][0]); + ctrlset3(i, &dll_setting_800[CTRL3][0]); + cmdset(i, &dll_setting_800[CMD][0]); + } + } + + // XXX if not async mode + MCHBAR16(0x180) = MCHBAR16(0x180) & ~0x8200; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; + j = 0; + for (i = 0; i < 16; i++) { + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while (MCHBAR8(0x180) & 0x10); + if (MCHBAR32(0x184) == 0xffffffff) { + j++; + if (j >= 2) + break; + + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { + j = 2; + break; + } + } else { + j = 0; + } + } + if (i == 1 || ((i == 0) && s->selected_timings.mem_clock == MEM_CLOCK_667MHz)) { + j = 0; + i++; + for (; i < 16; i++) { + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; + while (MCHBAR8(0x180) & 0x10); + if (MCHBAR32(0x184) == 0) { + i++; + break; + } + } + for (; i < 16; i++) { + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while (MCHBAR8(0x180) & 0x10); + if (MCHBAR32(0x184) == 0xffffffff) { + j++; + if (j >= 2) + break; + } else { + j = 0; + } + } + if (j < 2) { + MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while (MCHBAR8(0x180) & 0x10); + j = 2; + } + } + + if (j < 2) { + MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; + async = 1; + } + + clk = 0x1a; + if (async != 1) { + reg8 = MCHBAR8(0x188) & 0x1e; + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz && + s->selected_timings.fsb_clock == FSB_CLOCK_800MHz) { + clk = 0x10; + } else if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { + clk = 0x10; + } else { + clk = 0x1a; + } + } + MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80; + + if ((s->selected_timings.fsb_clock == FSB_CLOCK_800MHz) && + (s->selected_timings.mem_clock == MEM_CLOCK_667MHz)) { + i = MCHBAR8(0x180) & 0xf; + i = (i + 10) % 14; + MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; + MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; + while(MCHBAR8(0x180) & 0x10); + } + + reg8 = MCHBAR8(0x188) & ~1; + MCHBAR8(0x188) = reg8; + reg8 &= ~0x3e; + reg8 |= clk; + MCHBAR8(0x188) = reg8; + reg8 |= 1; + MCHBAR8(0x188) = reg8; + + if (s->selected_timings.mem_clock == MEM_CLOCK_1333MHz) { + MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1; + } + + // Program DQ/DQS dll settings + reg32 = 0; + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + for (lane = 0; lane < 8; lane++) { + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { + reg32 = 0x06db7777; + } else if (s->selected_timings.mem_clock == MEM_CLOCK_800MHz) { + reg32 = 0x00007777; + } + MCHBAR32(0x400*i + 0x540 + lane*4) = + (MCHBAR32(0x400*i + 0x540 + lane*4) & 0x0fffffff) | + reg32; + } + } + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { + for (lane = 0; lane < 8; lane++) { + dqsset(i, lane, &dll_setting_667[DQS1+lane][0]); + } + for (lane = 0; lane < 8; lane++) { + dqset(i, lane, &dll_setting_667[DQ1+lane][0]); + } + } else { + for (lane = 0; lane < 8; lane++) { + dqsset(i, lane, &dll_setting_800[DQS1+lane][0]); + } + for (lane = 0; lane < 8; lane++) { + dqset(i, lane, &dll_setting_800[DQ1+lane][0]); + } + } + } +} + +static void rcomp_ddr2(sysinfo_t *s) +{ + u8 i, j, k; + u32 x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; + u16 x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; + u32 x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; + u32 x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; + u32 x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; + u32 x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; + u32 x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; + u32 x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; + u32 x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; + u32 x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; + u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; + u8 bit[6] = { 0, 0, 1, 1, 0, 0 }; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + for (j = 0; j < 6; j++) { + if (j == 0) { + MCHBAR32(0x400*i + addr[j]) = + (MCHBAR32(0x400*i + addr[j]) & ~0xff000) | 0xaa000; + MCHBAR16(0x400*i + 0x320) = (MCHBAR16(0x400*i + 0x320) & ~0xffff) | 0x6666; + for (k = 0; k < 8; k++) { + MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) = + (MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; + MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) = + (MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; + } + } else { + MCHBAR16(0x400*i + addr[j]) = (MCHBAR16(0x400*i + addr[j]) & ~0xf000) | 0xa000; + MCHBAR16(0x400*i + addr[j] + 4) = (MCHBAR16(0x400*i + addr[j] + 4) & ~0xffff) | + x378[j]; + MCHBAR32(0x400*i + addr[j] + 0xe) = + (MCHBAR32(0x400*i + addr[j] + 0xe) & ~0x3f3f3f3f) | x382[j]; + MCHBAR32(0x400*i + addr[j] + 0x12) = + (MCHBAR32(0x400*i + addr[j] + 0x12) & ~0x3f3f3f3f) | x386[j]; + MCHBAR32(0x400*i + addr[j] + 0x16) = + (MCHBAR32(0x400*i + addr[j] + 0x16) & ~0x3f3f3f3f) | x38a[j]; + MCHBAR32(0x400*i + addr[j] + 0x1a) = + (MCHBAR32(0x400*i + addr[j] + 0x1a) & ~0x3f3f3f3f) | x38e[j]; + MCHBAR32(0x400*i + addr[j] + 0x1e) = + (MCHBAR32(0x400*i + addr[j] + 0x1e) & ~0x3f3f3f3f) | x392[j]; + MCHBAR32(0x400*i + addr[j] + 0x22) = + (MCHBAR32(0x400*i + addr[j] + 0x22) & ~0x3f3f3f3f) | x396[j]; + MCHBAR32(0x400*i + addr[j] + 0x26) = + (MCHBAR32(0x400*i + addr[j] + 0x26) & ~0x3f3f3f3f) | x39a[j]; + MCHBAR32(0x400*i + addr[j] + 0x2a) = + (MCHBAR32(0x400*i + addr[j] + 0x2a) & ~0x3f3f3f3f) | x39e[j]; + } + MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j]; + } + MCHBAR8(0x400*i + 0x45a) = (MCHBAR8(0x400*i + 0x45a) & ~0x3f) | 0x12; + MCHBAR8(0x400*i + 0x45e) = (MCHBAR8(0x400*i + 0x45e) & ~0x3f) | 0x12; + MCHBAR8(0x400*i + 0x462) = (MCHBAR8(0x400*i + 0x462) & ~0x3f) | 0x12; + MCHBAR8(0x400*i + 0x466) = (MCHBAR8(0x400*i + 0x466) & ~0x3f) | 0x12; + } // END EACH POPULATED CHANNEL + + MCHBAR32(0x134) = (MCHBAR32(0x134) & ~0x63c00) | 0x63c00; + MCHBAR16(0x174) = (MCHBAR16(0x174) & ~0x63ff) | 0x63ff; + MCHBAR16(0x178) = 0x0135; + MCHBAR32(0x130) = (MCHBAR32(0x130) & ~0x7bdffe0) | 0x7a9ffa0; + + if (!CHANNEL_IS_POPULATED(s->dimms, 0)) { + MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 27); + } + if (!CHANNEL_IS_POPULATED(s->dimms, 1)) { + MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 28); + } + + MCHBAR8(0x130) = MCHBAR8(0x130) | 1; +} + +static void odt_ddr2(sysinfo_t *s) +{ + u8 i; + u16 odt[16][2] = { + { 0x0000,0x0000 }, // NC_NC + { 0x0000,0x0001 }, // x8SS_NC + { 0x0000,0x0011 }, // x8DS_NC + { 0x0000,0x0001 }, // x16SS_NC + { 0x0004,0x0000 }, // NC_x8SS + { 0x0101,0x0404 }, // x8SS_x8SS + { 0x0101,0x4444 }, // x8DS_x8SS + { 0x0101,0x0404 }, // x16SS_x8SS + { 0x0044,0x0000 }, // NC_x8DS + { 0x1111,0x0404 }, // x8SS_x8DS + { 0x1111,0x4444 }, // x8DS_x8DS + { 0x1111,0x0404 }, // x16SS_x8DS + { 0x0004,0x0000 }, // NC_x16SS + { 0x0101,0x0404 }, // x8SS_x16SS + { 0x0101,0x4444 }, // x8DS_x16SS + { 0x0101,0x0404 }, // x16SS_x16SS + }; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { + MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1]; + MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0]; + MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b; + MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00; + } +} + +static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val) +{ + u32 addr = (ch << 29) | (r*0x08000000); + volatile u32 rubbish; + + MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd; + MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd; + rubbish = read32((void*)((val<<3) | addr)); + udelay(10); + MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD; + MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD; +} + +static void jedec_ddr2(sysinfo_t *s) +{ + u8 i; + u16 mrsval, ch, r, v; + + u8 odt[16][4] = { + {0x00, 0x00, 0x00, 0x00}, + {0x01, 0x00, 0x00, 0x00}, + {0x01, 0x01, 0x00, 0x00}, + {0x01, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x01, 0x00}, + {0x11, 0x00, 0x11, 0x00}, + {0x11, 0x11, 0x11, 0x00}, + {0x11, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x01, 0x01}, + {0x11, 0x00, 0x11, 0x11}, + {0x11, 0x11, 0x11, 0x11}, + {0x11, 0x00, 0x11, 0x11}, + {0x00, 0x00, 0x01, 0x00}, + {0x11, 0x00, 0x11, 0x00}, + {0x11, 0x11, 0x11, 0x00}, + {0x11, 0x00, 0x11, 0x00} + }; + + u16 jedec[12][2] = { + {NOP_CMD, 0x0}, + {PRECHARGE_CMD, 0x0}, + {EMRS2_CMD, 0x0}, + {EMRS3_CMD, 0x0}, + {EMRS1_CMD, 0x0}, + {MRS_CMD, 0x100}, // DLL Reset + {PRECHARGE_CMD, 0x0}, + {CBR_CMD, 0x0}, + {CBR_CMD, 0x0}, + {MRS_CMD, 0x0}, // DLL out of reset + {EMRS1_CMD, 0x380}, // OCD calib default + {EMRS1_CMD, 0x0} + }; + + mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; + + PRINTK_DEBUG("MRS...\n"); + + udelay(200); + + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + PRINTK_DEBUG("CH%d: Found Rank %d\n", ch, r); + for (i = 0; i < 12; i++) { + v = jedec[i][1]; + switch (jedec[i][0]) { + case EMRS1_CMD: + v |= (odt[s->dimm_config[ch]][r] << 2); + break; + case MRS_CMD: + v |= mrsval; + break; + default: + break; + } + dojedec_ddr2(r + ch*4, ch, jedec[i][0], v); + udelay(1); + //PRINTK_DEBUG("Jedec step %d\n", i); + } + } + PRINTK_DEBUG("MRS done\n"); +} + +static u8 sampledqs(u16 mchloc, u32 addr, u8 hilow, u8 repeat) +{ + u8 dqsmatch = 1; + volatile u32 strobe; + + while (repeat-- > 0) { + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2; + udelay(2); + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; + udelay(2); + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0x2; + udelay(2); + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x2; + udelay(2); + barrier(); + strobe = read32((u32 *)addr); + barrier(); + if (((MCHBAR32(mchloc) & 0x40) >> 6) != hilow) { + dqsmatch = 0; + } + } + return dqsmatch; +} + +static void rcven_ddr2(sysinfo_t *s) +{ + u8 i, reg8, ch, lane; + u32 addr; + u8 tap = 0; + u8 savecc, savemedium, savetap, coarsecommon, medium; + u8 lanecoarse[8] = {0}; + u8 mincoarse = 0xff; + u8 pitap[2][8]; + u16 coarsectrl[2]; + u16 coarsedelay[2]; + u16 mediumphase[2]; + u16 readdelay[2]; + u16 mchbar; + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc; + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + addr = (ch << 29); + for (i = 0; !RANK_IS_POPULATED(s->dimms, ch, i); i++) { + addr += 128*1024*1024; + } + for (lane = 0; lane < 8; lane++) { + PRINTK_DEBUG("Channel %d, Lane %d addr=0x%08x\n", ch, lane, addr); +//trylaneagain: + coarsecommon = (s->selected_timings.CAS - 1); + switch (lane) { + case 0: case 1: medium = 0; break; + case 2: case 3: medium = 1; break; + case 4: case 5: medium = 2; break; + case 6: case 7: medium = 3; break; + default: medium = 0; break; + } + mchbar = 0x400*ch + 0x561 + (lane << 2); + tap = 0; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | + (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & ~(3 << (lane*2))) | + (medium << (lane*2)); + MCHBAR8(0x400*ch + 0x560 + lane*4) = MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf; + MCHBAR8(0x400*ch + 0x560 + lane*4) = MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0x70; + savecc = coarsecommon; + savemedium = medium; + savetap = 0; + + MCHBAR16(0x400*ch + 0x588) = (MCHBAR16(0x400*ch + 0x588) & ~(3 << (lane*2))) | + (1 << (lane*2)); + + PRINTK_VERBOSE("rcven 0.1 coarse=%d\n", coarsecommon); + while (sampledqs(mchbar, addr, 1, 1) == 1) { + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (coarsecommon > 16) { + die("Coarse > 16: DQS tuning failed, halt\n"); + break; + } + } + PRINTK_VERBOSE(" GOT IT (high -> low transition) coarse=%d medium=%d\n", coarsecommon, medium); + + savemedium = medium; + savecc = coarsecommon; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | + (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & ~(3 << (lane*2))) | + (medium << (lane*2)); + } + + PRINTK_VERBOSE("rcven 0.2\n"); + while (sampledqs(mchbar, addr, 0, 1) == 1) { + savemedium = medium; + savecc = coarsecommon; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (coarsecommon > 16) { + die("Coarse DQS tuning 2 failed, halt\n"); + break; + } + } + PRINTK_VERBOSE(" GOT IT (low -> high transition) coarse=%d medium=%d\n", coarsecommon, medium); + + + coarsecommon = savecc; + medium = savemedium; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + + PRINTK_VERBOSE("rcven 0.3\n"); + tap = 0; + while (sampledqs(mchbar, addr, 1, 1) == 0) { + savetap = tap; + tap++; + if (tap > 14) { + break; + } + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | tap; + } + + tap = savetap; + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | tap; + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0x70) | 0x30; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (sampledqs(mchbar, addr, 1, 1) == 0) { + die("Not at DQS high, doh\n"); + } + + PRINTK_VERBOSE("rcven 0.4\n"); + while (sampledqs(mchbar, addr, 1, 1) == 1) { + coarsecommon--; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + if (coarsecommon == 0) { + die("Couldn't find DQS-high 0 indicator, halt\n"); + break; + } + } + PRINTK_VERBOSE(" GOT IT (high -> low transition) coarse=%d medium=%d\n", coarsecommon, medium); + + PRINTK_VERBOSE("rcven 0.5\n"); + while (sampledqs(mchbar, addr, 0, 1) == 1) { + savemedium = medium; + savecc = coarsecommon; + if (medium < 3) { + medium++; + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } else { + medium = 0; + coarsecommon++; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + } + if (coarsecommon > 16) { + die("Coarse DQS tuning 5 failed, halt\n"); + break; + } + } + PRINTK_VERBOSE(" GOT IT (low -> high transition) coarse=%d medium=%d\n", coarsecommon, medium); + + PRINTK_VERBOSE("rcven 0.6\n"); + coarsecommon = savecc; + medium = savemedium; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & + ~0xf0000) | (coarsecommon << 16); + MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & + ~(3 << (lane*2))) | (medium << (lane*2)); + while (sampledqs(mchbar, addr, 1, 1) == 0) { + savetap = tap; + tap++; + if (tap > 14) { + break; + } + MCHBAR8(0x400*ch + 0x560 + lane*4) = + (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf) | tap; + } + tap = savetap; + MCHBAR8(0x400*ch + 0x560 + lane*4) = + (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf) | tap; + MCHBAR8(0x400*ch + 0x560 + lane*4) = + (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0x70) | 0x70; + + pitap[ch][lane] = 0x70 | tap; + + MCHBAR16(0x400*ch + 0x588) = MCHBAR16(0x400*ch + 0x588) & ~(3 << (lane*2)); + lanecoarse[lane] = coarsecommon; + PRINTK_VERBOSE("rcven 0.7\n"); + } // END EACH LANE + + // Find minimum coarse value + for (lane = 0; lane < 8; lane++) { + if (mincoarse > lanecoarse[lane]) { + mincoarse = lanecoarse[lane]; + } + } + + PRINTK_DEBUG("Found min coarse value = %d\n", mincoarse); + + for (lane = 0; lane < 8; lane++) { + reg8 = (lanecoarse[lane] == 0) ? 0 : lanecoarse[lane] - mincoarse; + MCHBAR16(0x400*ch + 0x5fa) = (MCHBAR16(0x400*ch + 0x5fa) & ~(3 << (lane*2))) | + (reg8 << (lane*2)); + } + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | (mincoarse << 16); + coarsectrl[ch] = mincoarse; + coarsedelay[ch] = MCHBAR16(0x400*ch + 0x5fa); + mediumphase[ch] = MCHBAR16(0x400*ch + 0x58c); + readdelay[ch] = MCHBAR16(0x400*ch + 0x588); + } // END EACH POPULATED CHANNEL + +/* Resume support */ + FOR_EACH_CHANNEL(ch) { + for (lane = 0; lane < 8; lane++) { + MCHBAR8(0x400*ch + 0x560 + (lane*4)) = + (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | pitap[ch][lane]; + } + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | + (coarsectrl[ch] << 16); + MCHBAR16(0x400*ch + 0x5fa) = coarsedelay[ch]; + MCHBAR16(0x400*ch + 0x58c) = mediumphase[ch]; + } + PRINTK_DEBUG("End rcven\n"); +} + +static void dradrb_ddr2(sysinfo_t *s) +{ + u8 map, i, ch, r, rankpop0, rankpop1; + u32 c0dra = 0; + u32 c1dra = 0; + u32 c0drb = 0; + u32 c1drb = 0; + u32 dra; + u32 dra0; + u32 dra1; + u16 totalmemorymb; + u16 size, offset; + u8 dratab[2][2][2][4] = { + { + { + {0xff, 0xff, 0xff, 0xff}, + {0xff, 0x00, 0x02, 0xff} + }, + { + {0xff, 0x01, 0xff, 0xff}, + {0xff, 0x03, 0xff, 0xff} + } + }, + { + { + {0xff, 0xff, 0xff, 0xff}, + {0xff, 0x04, 0x06, 0x08} + }, + { + {0xff, 0xff, 0xff, 0xff}, + {0x05, 0x07, 0x09, 0xff} + } + } + }; + + u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; + + // DRA + rankpop0 = 0; + rankpop1 = 0; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { + i = ch << 1; + } else { + i = (ch << 1) + 1; + } + dra = dratab[s->dimms[i].banks] + [s->dimms[i].width] + [s->dimms[i].cols-9] + [s->dimms[i].rows-12]; + if (s->dimms[i].banks == 1) { + dra |= 0x80; + } + if (ch == 0) { + c0dra |= dra << (r*8); + rankpop0 |= 1 << r; + } else { + c1dra |= dra << (r*8); + rankpop1 |= 1 << r; + } + } + MCHBAR32(0x208) = c0dra; + MCHBAR32(0x608) = c1dra; + + MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); + MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0); + + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { + MCHBAR8(0x260) = MCHBAR8(0x260) | 1; + } + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) { + MCHBAR8(0x660) = MCHBAR8(0x660) | 1; + } + + // DRB + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { + i = ch << 1; + } else { + i = (ch << 1) + 1; + } + if (ch == 0) { + dra0 = (c0dra >> (8*r)) & 0x7f; + c0drb = (u16)(c0drb + drbtab[dra0]); + s->dimms[i].rank_capacity_mb = drbtab[dra0] << 6; + MCHBAR16(0x200 + 2*r) = c0drb; + } else { + dra1 = (c1dra >> (8*r)) & 0x7f; + c1drb = (u16)(c1drb + drbtab[dra1]); + s->dimms[i].rank_capacity_mb = drbtab[dra1] << 6; + MCHBAR16(0x600 + 2*r) = c1drb; + } + } + + s->channel_capacity[0] = c0drb << 6; + s->channel_capacity[1] = c1drb << 6; + totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; + PRINTK_DEBUG("Total memory: %d + %d = %dMiB\n", + s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); + + rankpop1 >>= 4; + if (rankpop1) { + MCHBAR16(0x600 + 2*msbpos(rankpop1)) = c0drb + c1drb; + MCHBAR16(0x602 + 2*msbpos(rankpop1)) = c0drb + c1drb; + MCHBAR16(0x604 + 2*msbpos(rankpop1)) = c0drb + c1drb; + MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; + } + + MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; + MCHBAR16(0x104) = 0; + size = s->channel_capacity[0] + s->channel_capacity[1]; + MCHBAR16(0x102) = size; + map = 0; + if (s->channel_capacity[0] == 0) { + map = 0; + } else if (s->channel_capacity[1] == 0) { + map |= 0x20; + } else { + map |= 0x40; + } + map |= 0x18; + if (s->channel_capacity[0] <= s->channel_capacity[1]) { + map |= 0x5; + } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + map |= 0x4; + } + MCHBAR8(0x110) = map; + MCHBAR16(0x10e) = 0; + if (s->channel_capacity[1] != 0) { + offset = 0; + } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + offset = size; + } else { + offset = 0; + } + MCHBAR16(0x108) = offset; + MCHBAR16(0x10a) = 0; +} + +static void mmap_ddr2(sysinfo_t *s) +{ + u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; + u16 ggc; + u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + + ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52); + gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; + gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; + tsegsize = 1; // 1MB TSEG + mmiosize = 0x400; // 1GB MMIO + tom = s->channel_capacity[0] + s->channel_capacity[1]; + tolud = MIN(0x1000 - mmiosize, tom); + touud = tom; + gfxbase = tolud - gfxsize; + gttbase = gfxbase - gttsize; + tsegbase = gttbase - tsegsize; + + pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); + pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); + pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); + pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); + pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); + pci_write_config32(PCI_DEV(0,0,0), 0xac, tsegbase << 20); +} + +static void enhanced_ddr2(sysinfo_t *s) +{ + u8 ch, reg8; + + MCHBAR32(0xfb0) = 0x1000d024; + MCHBAR32(0xfb4) = 0xc842; + MCHBAR32(0xfbc) = 0xf; + MCHBAR32(0xfc4) = 0xfe22244; + MCHBAR8(0x12f) = 0x5c; + MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1; + MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2; + MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0; + MCHBAR32(0xfa8) = 0x30d400; + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; + MCHBAR32(0x400*ch + 0x278) = 0x88141881; + MCHBAR16(0x400*ch + 0x27c) = 0x0041; + MCHBAR8(0x400*ch + 0x292) = 0xf2; + MCHBAR16(0x400*ch + 0x272) = MCHBAR16(0x400*ch + 0x272) | 0x100; + MCHBAR8(0x400*ch + 0x243) = (MCHBAR8(0x400*ch + 0x243) & ~0x2) | 1; + MCHBAR32(0x400*ch + 0x288) = 0x8040200; + MCHBAR32(0x400*ch + 0x28c) = 0xff402010; + MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; + } + + reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); + pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 | 1); + MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2; + MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | 0x219100c2; + MCHBAR32(0x2c) = 0x44a53; + MCHBAR32(0x30) = 0x1f5a86; + MCHBAR32(0x34) = 0x1902810; + MCHBAR32(0x38) = 0xf7000000; + MCHBAR32(0x3c) = 0x23014410; + MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | 0x8f038000; + MCHBAR32(0x20) = 0x33001; + pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1); +} + +static void power_ddr2(sysinfo_t *s) +{ + u32 reg1, reg2, reg3, reg4, clkgate, x592; + u8 lane, ch; + u8 twl = 0; + u16 x264, x23c; + + twl = s->selected_timings.CAS - 1; + x264 = 0x78; + switch (s->selected_timings.mem_clock) { + default: + case MEM_CLOCK_667MHz: + reg1 = 0x99; + reg2 = 0x1048a9; + clkgate = 0x230000; + x23c = 0x7a89; + break; + case MEM_CLOCK_800MHz: + if (s->selected_timings.CAS == 5) { + reg1 = 0x19a; + reg2 = 0x1048aa; + } else { + reg1 = 0x9a; + reg2 = 0x2158aa; + x264 = 0x89; + } + clkgate = 0x280000; + x23c = 0x7b89; + break; + } + reg3 = 0x232; + reg4 = 0x2864; + + if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) { + MCHBAR32(0x14) = 0x0010461f; + } else { + MCHBAR32(0x14) = 0x0010691f; + } + MCHBAR32(0x18) = 0xdf6437f7; + MCHBAR32(0x1c) = 0x0; + MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x30000000; + MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000; + MCHBAR16(0x115) = (u16) reg1; + MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2; + MCHBAR8(0x124) = 0x7; + MCHBAR16(0x12a) = (MCHBAR16(0x12a) & 0) | 0x80; + MCHBAR8(0x12c) = (MCHBAR8(0x12c) & 0) | 0xa0; + MCHBAR16(0x174) = MCHBAR16(0x174) & ~(1 << 15); + MCHBAR16(0x188) = (MCHBAR16(0x188) & ~0x1f00) | 0x1f00; + MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x8; + MCHBAR8(0x192) = (MCHBAR8(0x192) & ~1) | 1; + MCHBAR8(0x193) = (MCHBAR8(0x193) & ~0xf) | 0xf; + MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x480) | 0x80; + MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x1fff) | 0x3f; // | clockgatingiii + MCHBAR32(0x6d1) = (MCHBAR32(0x6d1) & ~0xff03ff) | 0x100 | clkgate; + MCHBAR8(0x212) = (MCHBAR8(0x212) & ~0x7f) | 0x7f; + MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xffff0) | 0xcc5f0; + MCHBAR8(0x2c4) = (MCHBAR8(0x2c4) & ~0x70) | 0x70; + MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0xffffff) | 0xff2831; // | clockgatingi + MCHBAR32(0x2d4) = 0x40453600; + MCHBAR32(0x300) = 0xc0b0a08; + MCHBAR32(0x304) = 0x6040201; + MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405; + MCHBAR16(0x610) = 0x232; + MCHBAR16(0x612) = 0x2864; + MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000; + MCHBAR32(0xae4) = 0; + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; + MCHBAR32(0xf00) = 0x393a3b3c; + MCHBAR32(0xf04) = 0x3d3e3f40; + MCHBAR32(0xf08) = 0x393a3b3c; + MCHBAR32(0xf0c) = 0x3d3e3f40; + MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0xfff00001; + MCHBAR32(0xf48) = 0xfff0ffe0; + MCHBAR32(0xf4c) = 0xffc0ff00; + MCHBAR32(0xf50) = 0xfc00f000; + MCHBAR32(0xf54) = 0xc0008000; + MCHBAR32(0xf6c) = (MCHBAR32(0xf6c) & ~0xffff0000) | 0xffff0000; + MCHBAR32(0xfac) = MCHBAR32(0xfac) & ~0x80000000; + MCHBAR32(0xfb8) = MCHBAR32(0xfb8) & ~0xff000000; + MCHBAR32(0xfbc) = (MCHBAR32(0xfbc) & ~0x7f800) | 0xf000; + MCHBAR32(0x1104) = 0x3003232; + MCHBAR32(0x1108) = 0x74; + if (s->selected_timings.fsb_clock == FSB_CLOCK_800MHz) { + MCHBAR32(0x110c) = 0xaa; + } else { + MCHBAR32(0x110c) = 0x100; + } + MCHBAR32(0x1110) = 0x10810350 & ~0x78; + MCHBAR32(0x1114) = 0; + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { + twl = 5; + } else { + twl = 6; + } + x592 = 0xff; + if (pci_read_config8(PCI_DEV(0,0,0), 0x8) < 3) { + x592 = ~0x4; + } + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR8(0x400*ch + 0x239) = twl + 15; + MCHBAR16(0x400*ch + 0x23c) = x23c; + MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0x706033) | 0x406033; + MCHBAR32(0x400*ch + 0x260) = (MCHBAR32(0x400*ch + 0x260) & ~(1 << 16)) | (1 << 16); + MCHBAR8(0x400*ch + 0x264) = x264; + MCHBAR8(0x400*ch + 0x592) = (MCHBAR8(0x400*ch + 0x592) & ~0x3f) | (0x3c & x592); + MCHBAR8(0x400*ch + 0x593) = (MCHBAR8(0x400*ch + 0x593) & ~0x1f) | 0x1e; + } + + for (lane = 0; lane < 8; lane++) { + MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3); + } +} + +void raminit_ddr2(sysinfo_t *s) +{ + u8 ch; + u8 r, bank; + u32 reg32; + + // Select timings based on SPD info + sdram_detect_smallest_params2(s); + + // Reset if required + checkreset_ddr2(s); + + // Clear self refresh + MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; + + // Clear host clk gate reg + MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; + + // Select DDR2 + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + + // Set freq + MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | + (s->selected_timings.mem_clock << 4) | (1 << 10); + + // Overwrite freq if chipset rejects it + s->selected_timings.mem_clock = (MCHBAR8(0xc00) & 0x70) >> 4; + if (s->selected_timings.mem_clock > (s->max_fsb + 3)) { + die("Error: DDR is faster than FSB, halt\n"); + } + + udelay(250000); + + // Program clock crossing + clkcross_ddr2(s); + PRINTK_DEBUG("Done clk crossing\n"); + + // DDR2 IO + setioclk_ddr2(s); + PRINTK_DEBUG("Done I/O clk\n"); + + // Grant to launch + launch_ddr2(s); + PRINTK_DEBUG("Done launch\n"); + + // Program DDR2 timings + timings_ddr2(s); + PRINTK_DEBUG("Done timings\n"); + + // Program DLL + dll_ddr2(s); + + // RCOMP + rcomp_ddr2(s); + PRINTK_DEBUG("RCOMP\n"); + + // ODT + odt_ddr2(s); + PRINTK_DEBUG("Done ODT\n"); + + // RCOMP update + while ((MCHBAR8(0x130) & 1) != 0 ); + PRINTK_DEBUG("Done RCOMP update\n"); + + // Set defaults + MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; + MCHBAR32(0x660) = (MCHBAR32(0x660) & ~1) | 0xf00000; + MCHBAR32(0x208) = 0x01010101; + MCHBAR32(0x608) = 0x01010101; + MCHBAR32(0x200) = 0x00040002; + MCHBAR32(0x204) = 0x00080006; + MCHBAR32(0x600) = 0x00040002; + MCHBAR32(0x604) = 0x00100006; + MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; + MCHBAR32(0x104) = 0; + MCHBAR16(0x102) = 0x400; + MCHBAR8(0x100) = (2 << 5) | (3 << 3); + MCHBAR16(0x10e) = 0; + MCHBAR32(0x108) = 0; + pci_write_config16(PCI_DEV(0,0,0), 0xb0, 0x4000); + pci_write_config16(PCI_DEV(0,0,0), 0xa0, 0x0010); + pci_write_config16(PCI_DEV(0,0,0), 0xa2, 0x0400); + pci_write_config32(PCI_DEV(0,0,0), 0xa4, 0x40000000); + pci_write_config32(PCI_DEV(0,0,0), 0xa8, 0x40000000); + pci_write_config32(PCI_DEV(0,0,0), 0xac, 0x40000000); + + // IOBUFACT + if (CHANNEL_IS_POPULATED(s->dimms, 0)) { + MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x7; + } + if (CHANNEL_IS_POPULATED(s->dimms, 1)) { + if (pci_read_config8(PCI_DEV(0,0,0), 0x8) < 2) { + MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; + MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 1; + } + MCHBAR8(0x9dd) = (MCHBAR8(0x9dd) & ~0x3f) | 0x3f; + MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7; + } + + // Pre jedec + MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR32(0x400*ch + 0x260) = MCHBAR32(0x400*ch + 0x260) | (1 << 27); + } + MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf000) | 0xf000; + MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf00) | 0xf00; + PRINTK_DEBUG("Done pre-jedec\n"); + + // JEDEC reset + jedec_ddr2(s); + + PRINTK_DEBUG("Done jedec steps\n"); + + // After JEDEC reset + MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + if (s->selected_timings.mem_clock == MEM_CLOCK_667MHz) { + reg32 = (2 << 18) | (3 << 13) | (5 << 8); + } else { + reg32 = (2 << 18) | (3 << 13) | (4 << 8); + } + MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32; + MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80; + MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; + MCHBAR32(0x400*ch + 0x278) = 0x88141881; + MCHBAR16(0x400*ch + 0x27c) = 0x41; + MCHBAR8(0x400*ch + 0x292) = 0xf2; + MCHBAR8(0x400*ch + 0x271) = (MCHBAR8(0x400*ch + 0x271) & ~0xe) | 0xe; + } + MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x8; + MCHBAR8(0x2c3) = MCHBAR8(0x2c3) | 0x40; + MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x4; + + PRINTK_DEBUG("Done post-jedec\n"); + + // Set DDR2 init complete + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000; + } + + // Receive enable + rcven_ddr2(s); + PRINTK_DEBUG("Done rcven\n"); + + // Finish rcven + FOR_EACH_CHANNEL(ch) { + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) & ~0xe; + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x2; + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x4; + MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x8; + } + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; + MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; + + // Dummy writes / reads + volatile u32 data; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + for (bank = 0; bank < 4; bank++) { + reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); + write32((u32 *)reg32, 0xffffffff); + data = read32((u32 *)reg32); + PRINTK_DEBUG("Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); + write32((u32 *)reg32, 0x00000000); + data = read32((u32 *)reg32); + PRINTK_DEBUG("Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); + } + } + PRINTK_DEBUG("Done dummy reads\n"); + + // XXX tRD + + // XXX Write training + + // XXX Read training + + // DRADRB + dradrb_ddr2(s); + PRINTK_DEBUG("Done DRADRB\n"); + + // Memory map + mmap_ddr2(s); + PRINTK_DEBUG("Done memory map\n"); + + // Enhanced mode + enhanced_ddr2(s); + PRINTK_DEBUG("Done enhanced mode\n"); + + // Periodic RCOMP + MCHBAR16(0x160) = (MCHBAR16(0x160) & ~0xfff) | 0x999; + MCHBAR16(0x1b4) = MCHBAR16(0x1b4) | 0x3000; + MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82; + PRINTK_DEBUG("Done PRCOMP\n"); + + // Power settings + power_ddr2(s); + PRINTK_DEBUG("Done power settings\n"); + + // ME related + //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); + + PRINTK_DEBUG("Done ddr2\n"); +}

1 0

Patch set updated for coreboot: gigabyte/ga-g41m-es2l: Add mainboard
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11306 -gerrit commit 9ccbd66c751eaafb669f226f9f7f307d259de809 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Aug 19 15:23:32 2015 +1000 gigabyte/ga-g41m-es2l: Add mainboard Board uses x4x native raminit Board boots into Debian 8 with full graphics VGA: - VGA native init works in grub with analog connector - Fails to boot with both channels of ram populated Change-Id: I7417813456817529b8cbaace45cefe47467d0a82 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 44 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name | 2 + src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 1 + src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 34 +++++ .../gigabyte/ga-g41m-es2l/acpi/platform.asl | 28 ++++ .../gigabyte/ga-g41m-es2l/acpi/superio.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 66 +++++++++ src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c | 42 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt | 5 + src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 37 +++++ src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 120 +++++++++++++++ src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 41 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 7 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 163 +++++++++++++++++++++ 15 files changed, 592 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig new file mode 100644 index 0000000..6a31977 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -0,0 +1,44 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_GIGABYTE_GA_G41M_ES2L + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_ITE_IT8718F + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + select IRQ9_MADT_OVERRIDE_OFF + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MAINBOARD_DIR + string + default "gigabyte/ga-g41m-es2l" + +config MAINBOARD_PART_NUMBER + string + default "GA-G41M-ES2L" + +endif # BOARD_GIGABYTE_GA_G41M_ES2L diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name new file mode 100644 index 0000000..e685ce1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_G41M_ES2L + bool "GA-G41M-ES2L" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..0a69f3d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x001effff, 0, 0, 17}, + Package() { 0x001effff, 1, 0, 20}, + Package() { 0x001effff, 2, 0, 16}, + Package() { 0x001effff, 3, 0, 16}, + }) +} Else { + Return (Package() { + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x001effff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x001effff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..fdfe73d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 22 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + Package() { 0x001dffff, 0, 0, 23 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 0, 0, 18 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c new file mode 100644 index 0000000..d9d8032 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->lptp = 0; /* LPT port */ + gnvs->fdcp = 0; /* Floppy Disk Controller */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt new file mode 100644 index 0000000..44ed73a --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c new file mode 100644 index 0000000..dbac2ed --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +static acpi_cstate_t cst_entries[] = { + { + /* acpi C1 / cpu C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } + }, + { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb new file mode 100644 index 0000000..6d85337 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -0,0 +1,120 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + register "slfm" = "1" + register "c5" = "1" + register "c6" = "1" + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 1.0 off end # PCI Bridge to Management Engine + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1458 0xd000 + end + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_legacy_combined" = "0x1" + register "ide_enable_primary" = "0x1" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x0" + register "sata_ports_implemented" = "0x3" + register "gpe0_en" = "0x40" + + device pci 1b.0 on # Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on # PCIe 2 (NIC) + device pci 00.0 on # PCI 10ec:8168 + subsystemid 0x1458 0xe000 + end + end + device pci 1c.2 on end # PCIe 3 + device pci 1c.3 on end # PCIe 4 + device pci 1d.0 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.1 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.2 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.3 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.7 on # USB + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0 + io 0x62 = 0x000 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMbus + subsystemid 0x1458 0x5001 + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl new file mode 100644 index 0000000..5f64d1e --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c new file mode 100644 index 0000000..072a306 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -0,0 +1,7 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c new file mode 100644 index 0000000..6bae128 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <superio/ite/it8718f/it8718f.h> +#include <superio/ite/common/ite.h> +#include <lib.h> +#include <cpu/intel/romstage.h> +#include <arch/stages.h> +#include <cbmem.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000e7, DEFAULT_GPIOBASE + 0x30); + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); + outl(0x00000083, DEFAULT_GPIOBASE + 0x38); + + /* Set default power management registers */ + pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); + outw(0x0011, DEFAULT_PMBASE + 0x00); + outw(0x0120, DEFAULT_PMBASE + 0x02); + outl(0x00001c01, DEFAULT_PMBASE + 0x04); + outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); + outl(0x000000a0, DEFAULT_PMBASE + 0x10); + outl(0xc5000000, DEFAULT_PMBASE + 0x28); + outl(0x00000040, DEFAULT_PMBASE + 0x2c); + outw(0x13e0, DEFAULT_PMBASE + 0x44); + outw(0x003f, DEFAULT_PMBASE + 0x60); + outw(0x0800, DEFAULT_PMBASE + 0x68); + outw(0x0008, DEFAULT_PMBASE + 0x6a); + outw(0x003f, DEFAULT_PMBASE + 0x72); + + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xc7); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x04); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x52); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x00); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + + /* IRQ routing */ + RCBA32(0x3100) = 0x00002210; + RCBA32(0x3104) = 0x00002100; + RCBA32(0x3108) = 0x10004321; + RCBA32(0x310c) = 0x00214321; + RCBA32(0x3110) = 0x00000001; + RCBA32(0x3140) = 0x00410032; + RCBA32(0x3144) = 0x32100237; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich7_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +void main(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + + /* Disable watchdog timer and route port 80 to LPC */ + RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + ich7_enable_lpc(); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + printk(BIOS_DEBUG, "Initializing memory\n"); + sdram_initialize(0, spd_addrmap); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); +}

1 0

Patch set updated for coreboot: northbridge/intel/x4x: Intel 4-series northbridge support
by Damien Zammit 27 Dec '15

27 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11305 -gerrit commit 73eaf96a801339490110247f34044055c6a118be Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Aug 19 15:16:59 2015 +1000 northbridge/intel/x4x: Intel 4-series northbridge support Boots to console on Gigabyte GA-G41M-ES2L Ram initialization *not* included in this patch VGA native init works on analog connector Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/Kconfig | 1 + src/northbridge/intel/x4x/Kconfig | 39 +++ src/northbridge/intel/x4x/Makefile.inc | 29 +++ src/northbridge/intel/x4x/acpi.c | 84 ++++++ src/northbridge/intel/x4x/acpi/hostbridge.asl | 234 +++++++++++++++++ src/northbridge/intel/x4x/acpi/peg.asl | 42 +++ src/northbridge/intel/x4x/acpi/x4x.asl | 49 ++++ src/northbridge/intel/x4x/bootblock.c | 32 +++ src/northbridge/intel/x4x/chip.h | 26 ++ src/northbridge/intel/x4x/debug.h | 28 ++ src/northbridge/intel/x4x/early_init.c | 58 +++++ src/northbridge/intel/x4x/gma.c | 286 ++++++++++++++++++++ src/northbridge/intel/x4x/northbridge.c | 268 +++++++++++++++++++ src/northbridge/intel/x4x/ram_calc.c | 49 ++++ src/northbridge/intel/x4x/x4x.h | 360 ++++++++++++++++++++++++++ 15 files changed, 1585 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 38cf855..c30702f 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -358,6 +358,7 @@ source "src/mainboard/Kconfig" config CBFS_SIZE hex "Size of CBFS filesystem in ROM" default 0x100000 if HAVE_INTEL_FIRMWARE || \ + NORTHBRIDGE_INTEL_X4X || \ NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_SANDYBRIDGE_MRC || \ NORTHBRIDGE_INTEL_IVYBRIDGE_MRC || NORTHBRIDGE_INTEL_IVYBRIDGE || \ NORTHBRIDGE_INTEL_SANDYBRIDGE || \ diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig new file mode 100644 index 0000000..c330fd5 --- /dev/null +++ b/src/northbridge/intel/x4x/Kconfig @@ -0,0 +1,39 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config NORTHBRIDGE_INTEL_X4X + bool + +if NORTHBRIDGE_INTEL_X4X + +config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy + def_bool y + select HAVE_DEBUG_RAM_SETUP + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT + select VGA + select INTEL_GMA_ACPI + select LATE_CBMEM_INIT + +config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/x4x/bootblock.c" + +config VGA_BIOS_ID + string + default "8086,2e32" + +endif diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc new file mode 100644 index 0000000..34d9b0f --- /dev/null +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -0,0 +1,29 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 secunet Security Networks AG +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) + +romstage-y += early_init.c +romstage-y += raminit.c +romstage-y += raminit_ddr2.c +romstage-y += ram_calc.c + +ramstage-y += acpi.c +ramstage-y += ram_calc.c +ramstage-y += gma.c +ramstage-y += northbridge.c + +endif diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c new file mode 100644 index 0000000..60192f5 --- /dev/null +++ b/src/northbridge/intel/x4x/acpi.c @@ -0,0 +1,84 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cbmem.h> +#include <arch/acpigen.h> +#include <cpu/cpu.h> +#include "x4x.h" + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + u32 pciexbar = 0; + u32 pciexbar_reg; + int max_buses; + + dev = dev_find_slot(0, PCI_DEVFN(0,0)); + if (!dev) + return current; + + pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); + + // MMCFG not supported or not enabled. + if (!(pciexbar_reg & 1)) + return current; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: // 256MB + pciexbar = pciexbar_reg & 0xf0000000; + max_buses = 256; + break; + case 1: // 128M + pciexbar = pciexbar_reg & 0xf8000000; + max_buses = 128; + break; + case 2: // 64M + pciexbar = pciexbar_reg & 0xfc000000; + max_buses = 64; + break; + default: // RSVD + return current; + } + + if (!pciexbar) + return current; + + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, + pciexbar, 0x0, 0x0, max_buses - 1); + + return current; +} + +unsigned long northbridge_write_acpi_tables(device_t device, + unsigned long start, + struct acpi_rsdp *rsdp) +{ + unsigned long current; + current = acpi_align_current(start); + + printk(BIOS_DEBUG, "current = %lx\n", current); + + return current; +} diff --git a/src/northbridge/intel/x4x/acpi/hostbridge.asl b/src/northbridge/intel/x4x/acpi/hostbridge.asl new file mode 100644 index 0000000..530fdfa --- /dev/null +++ b/src/northbridge/intel/x4x/acpi/hostbridge.asl @@ -0,0 +1,234 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/ioapic.h> + +Name(_HID,EISAID("PNP0A08")) // PCIe +Name(_CID,EISAID("PNP0A03")) // PCI + +Name(_ADR, 0) +Name(_BBN, 0) + +Device (MCHC) +{ + Name(_ADR, 0x00000000) // 0:0.0 + + OperationRegion(MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset (0x40), // EPBAR + EPEN, 1, // Enable + , 11, // + EPBR, 24, // EPBAR + + Offset (0x48), // MCHBAR + MHEN, 1, // Enable + , 13, // + MHBR, 22, // MCHBAR + + Offset (0x60), // PCIe BAR + PXEN, 1, // Enable + PXSZ, 2, // BAR size + , 23, // + PXBR, 10, // PCIe BAR + + Offset (0x68), // DMIBAR + DMEN, 1, // Enable + , 11, // + DMBR, 24, // DMIBAR + + // ... + + Offset (0x90), // PAM0 + , 4, + PM0H, 2, + , 2, + Offset (0x91), // PAM1 + PM1L, 2, + , 2, + PM1H, 2, + , 2, + Offset (0x92), // PAM2 + PM2L, 2, + , 2, + PM2H, 2, + , 2, + Offset (0x93), // PAM3 + PM3L, 2, + , 2, + PM3H, 2, + , 2, + Offset (0x94), // PAM4 + PM4L, 2, + , 2, + PM4H, 2, + , 2, + Offset (0x95), // PAM5 + PM5L, 2, + , 2, + PM5H, 2, + , 2, + Offset (0x96), // PAM6 + PM6L, 2, + , 2, + PM6H, 2, + , 2, + + Offset (0xa0), // Top of Used Memory + TOM, 8, + + Offset (0xb0), // Top of Low Used Memory + , 4, + TLUD, 12, + } + +} + +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-0xfebfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0xfebfffff, 0x00000000, + IO_APIC_ADDR,,, PM01) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) + +// Current Resource Settings + +Method (_CRS, 0, Serialized) +{ + // Find PCI resource area in MCRS + CreateDwordField(MCRS, ^PM01._MIN, PMIN) + CreateDwordField(MCRS, ^PM01._MAX, PMAX) + CreateDwordField(MCRS, ^PM01._LEN, PLEN) + + // Fix up PCI memory region: + // Enter actual TOLUD. The TOLUD register contains bits 20-31 of + // the top of memory address. + ShiftLeft (^MCHC.TLUD, 20, PMIN) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + Return (MCRS) +} + +/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ +#include "acpi/x4x_pci_irqs.asl" diff --git a/src/northbridge/intel/x4x/acpi/peg.asl b/src/northbridge/intel/x4x/acpi/peg.asl new file mode 100644 index 0000000..f2314c2 --- /dev/null +++ b/src/northbridge/intel/x4x/acpi/peg.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEGP) +{ + Name (_ADR, 0x00010000) + + // PCI Interrupt Routing. + Method (_PRT) + { + If (PICM) { + Return (Package() { + Package() { 0x0001ffff, 0, 0, 16 }, + Package() { 0x0001ffff, 1, 0, 17 }, + Package() { 0x0001ffff, 2, 0, 18 }, + Package() { 0x0001ffff, 3, 0, 19 }, + }) + } Else { + Return (Package() { + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + }) + } + + } +} diff --git a/src/northbridge/intel/x4x/acpi/x4x.asl b/src/northbridge/intel/x4x/acpi/x4x.asl new file mode 100644 index 0000000..2b9435a --- /dev/null +++ b/src/northbridge/intel/x4x/acpi/x4x.asl @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "hostbridge.asl" +#include "../x4x.h" + +/* PCI Device Resource Consumption */ +Device (PDRC) +{ + Name (_HID, EISAID("PNP0C02")) + Name (_UID, 1) + + Name (PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, 0xfed1c000, 0x00004000) // RCBA + Memory32Fixed(ReadWrite, DEFAULT_MCHBAR, 0x00004000) + Memory32Fixed(ReadWrite, DEFAULT_DMIBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_EPBAR, 0x00001000) + Memory32Fixed(ReadWrite, DEFAULT_PCIEXBAR, 0x04000000) + Memory32Fixed(ReadWrite, 0xfed20000, 0x00020000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed40000, 0x00005000) // Misc ICH + Memory32Fixed(ReadWrite, 0xfed45000, 0x0004b000) // Misc ICH + }) + + // Current Resource Settings + Method (_CRS, 0, Serialized) + { + Return(PDRS) + } +} + +// PCIe graphics port 0:1.0 +#include "peg.asl" + +// Integrated graphics 0:2.0 +#include <drivers/intel/gma/acpi/non-pch.asl> diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c new file mode 100644 index 0000000..adcaa89 --- /dev/null +++ b/src/northbridge/intel/x4x/bootblock.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +#define D0F0_PCIEXBAR_LO 0x60 +#define TPMBASE 0xfed40000 +#define TPM32(x) *((volatile u32 *)(TPMBASE + x)) + +static void bootblock_northbridge_init(void) +{ + uint32_t reg32; + + /* Disable LaGrande Technology (LT) */ + reg32 = TPM32(0); + + reg32 = CONFIG_MMCONF_BASE_ADDRESS | (2 << 1) | 1; + pci_io_write_config32(PCI_DEV(0,0,0), D0F0_PCIEXBAR_LO, reg32); +} diff --git a/src/northbridge/intel/x4x/chip.h b/src/northbridge/intel/x4x/chip.h new file mode 100644 index 0000000..1fb54cc --- /dev/null +++ b/src/northbridge/intel/x4x/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NORTHBRIDGE_INTEL_X4X_CHIP_H +#define NORTHBRIDGE_INTEL_X4X_CHIP_H + +#include <drivers/intel/gma/i915.h> + +struct northbridge_intel_x4x_config { + struct i915_gpu_controller_info gfx; +}; + +#endif diff --git a/src/northbridge/intel/x4x/debug.h b/src/northbridge/intel/x4x/debug.h new file mode 100644 index 0000000..c5d3cf4 --- /dev/null +++ b/src/northbridge/intel/x4x/debug.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Debugging macros. */ +#if 1 +#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) +#else +#define PRINTK_DEBUG(x...) +#endif + +#if 0 +#define PRINTK_VERBOSE(x...) printk(BIOS_DEBUG, x) +#else +#define PRINTK_VERBOSE(x...) +#endif diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c new file mode 100644 index 0000000..1d43e0a --- /dev/null +++ b/src/northbridge/intel/x4x/early_init.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include "x4x.h" + +void x4x_early_init(void) +{ + u16 reg16; + + const device_t d0f0 = PCI_DEV(0, 0, 0); + + /* Setup MCHBAR. */ + pci_write_config32(d0f0, D0F0_MCHBAR_LO, (uintptr_t)DEFAULT_MCHBAR | 1); + + /* Setup DMIBAR. */ + pci_write_config32(d0f0, D0F0_DMIBAR_LO, (uintptr_t)DEFAULT_DMIBAR | 1); + + /* Setup EPBAR. */ + pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); + + /* Setup PMBASE */ + pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); + + /* Setup HECIBAR */ + pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR); + reg16 = pci_read_config16(PCI_DEV(0,3,0), 0x4); + pci_write_config16(PCI_DEV(0,3,0), 0x4, reg16 | 0x6); + + /* Set C0000-FFFFF to access RAM on both reads and writes */ + pci_write_config8(d0f0, D0F0_PAM(0), 0x30); + pci_write_config8(d0f0, D0F0_PAM(1), 0x33); + pci_write_config8(d0f0, D0F0_PAM(2), 0x33); + pci_write_config8(d0f0, D0F0_PAM(3), 0x33); + pci_write_config8(d0f0, D0F0_PAM(4), 0x33); + pci_write_config8(d0f0, D0F0_PAM(5), 0x33); + pci_write_config8(d0f0, D0F0_PAM(6), 0x33); + + /* Enable internal GFX */ + pci_write_config16(d0f0, D0F0_GGC, 0x0170); + + reg16 = pci_read_config16(d0f0, D0F0_DEVEN); + pci_write_config16(d0f0, D0F0_DEVEN, reg16 | 0x8); +} diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c new file mode 100644 index 0000000..7891229 --- /dev/null +++ b/src/northbridge/intel/x4x/gma.c @@ -0,0 +1,286 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Chromium OS Authors + * Copyright (C) 2013 Vladimir Serbinenko + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <delay.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <device/pci_ops.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <kconfig.h> + +#include "drivers/intel/gma/i915_reg.h" +#include "chip.h" +#include "x4x.h" +#include <drivers/intel/gma/intel_bios.h> +#include <drivers/intel/gma/i915.h> +#include <pc80/vga.h> +#include <pc80/vga_io.h> + +static struct resource *gtt_res = NULL; + +void gtt_write(u32 reg, u32 data) +{ + write32(res2mmio(gtt_res, reg, 0), data); +} + +static void intel_gma_init(const struct northbridge_intel_x4x_config *info, + u8 *mmio, u32 physbase, u16 piobase, u32 lfb) +{ + + int i; + u32 hactive, vactive; + vga_gr_write(0x18, 0); + + /* Setup GTT. */ + for (i = 0; i < 0x2000; i++) + { + outl((i << 2) | 1, piobase); + outl(physbase + (i << 12) + 1, piobase + 4); + } + + write32(mmio + VGA0, 0x31108); + write32(mmio + VGA1, 0x31406); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + 0x7041c, 0x0); + write32(mmio + DPLL_MD(0), 0x3); + write32(mmio + DPLL_MD(1), 0x3); + + vga_misc_write(0x67); + + const u8 cr[] = { 0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f, + 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00, + 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3, + 0xff + }; + vga_cr_write(0x11, 0); + + for (i = 0; i <= 0x18; i++) + vga_cr_write(i, cr[i]); + + /* Disable screen memory to prevent garbage from appearing. */ + vga_sr_write(1, vga_sr_read(1) | 0x20); + + hactive = 640; + vactive = 400; + + vga_textmode_init(); + + mdelay(1); + write32(mmio + FP0(0), 0x31108); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + mdelay(1); + write32(mmio + DPLL(0), + DPLL_VCO_ENABLE | DPLLB_MODE_DAC_SERIAL + | DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 + | 0x10601 + ); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + HTOTAL(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HBLANK(0), + ((hactive - 1) << 16) + | (hactive - 1)); + write32(mmio + HSYNC(0), + ((hactive - 1) << 16) + | (hactive - 1)); + + write32(mmio + VTOTAL(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VBLANK(0), ((vactive - 1) << 16) + | (vactive - 1)); + write32(mmio + VSYNC(0), + ((vactive - 1) << 16) + | (vactive - 1)); + + write32(mmio + PIPECONF(0), PIPECONF_DISABLE); + + write32(mmio + PF_WIN_POS(0), 0); + + write32(mmio + PIPESRC(0), (639 << 16) | 399); + write32(mmio + PF_CTL(0),PF_ENABLE | PF_FILTER_MED_3x3); + write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); + write32(mmio + PFIT_CONTROL, 0xa0000000); + + mdelay(1); + + write32(mmio + 0x000f000c, 0x00002040); + mdelay(1); + write32(mmio + 0x000f000c, 0x00002050); + write32(mmio + 0x00060100, 0x00044000); + mdelay(1); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + + write32(mmio + VGACNTRL, 0x0); + write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); + mdelay(1); + + write32(mmio + ADPA, ADPA_DAC_ENABLE + | ADPA_PIPE_A_SELECT + | ADPA_CRT_HOTPLUG_MONITOR_COLOR + | ADPA_CRT_HOTPLUG_ENABLE + | ADPA_USE_VGA_HVPOLARITY + | ADPA_VSYNC_CNTL_ENABLE + | ADPA_HSYNC_CNTL_ENABLE + | ADPA_DPMS_ON + ); + + write32(mmio + PP_CONTROL, PANEL_POWER_ON); + + /* Enable screen memory. */ + vga_sr_write(1, vga_sr_read(1) & ~0x20); + + /* Clear interrupts. */ + write32(mmio + DEIIR, 0xffffffff); + write32(mmio + SDEIIR, 0xffffffff); +} + +static void gma_func0_init(struct device *dev) +{ + u32 reg32; + + /* IGD needs to be Bus Master */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; + pci_write_config32(dev, PCI_COMMAND, reg32); + + /* Init graphics power management */ + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + + struct northbridge_intel_x4x_config *conf = dev->chip_info; + + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); + } else { + u32 physbase; + struct resource *lfb_res; + struct resource *pio_res; + + lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); + + physbase = pci_read_config32(dev, 0x5c) & ~0xf; + + if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base + && lfb_res && lfb_res->base) { + printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, + pio_res->base, lfb_res->base); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); + } + + /* Post VBIOS init */ + /* Enable Backlight */ + gtt_write(BLC_PWM_CTL2, (1 << 31)); + if (conf->gfx.backlight == 0) + gtt_write(BLC_PWM_CTL, 0x06100610); + else + gtt_write(BLC_PWM_CTL, conf->gfx.backlight); +} + +static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) +{ + if (!vendor || !device) { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + pci_read_config32(dev, PCI_VENDOR_ID)); + } else { + pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, + ((device & 0xffff) << 16) | (vendor & + 0xffff)); + } +} + +const struct i915_gpu_controller_info * +intel_gma_get_controller_info(void) +{ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x2,0)); + if (!dev) { + return NULL; + } + struct northbridge_intel_x4x_config *chip = dev->chip_info; + return &chip->gfx; +} + +static void gma_ssdt(device_t device) +{ + const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); + if (!gfx) { + return; + } + + drivers_intel_gma_displays_ssdt_generate(gfx); +} + +static struct pci_operations gma_pci_ops = { + .set_subsystem = gma_set_subsystem, +}; + +static struct device_operations gma_func0_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = gma_ssdt, + .init = gma_func0_init, + .scan_bus = 0, + .enable = 0, + .ops_pci = &gma_pci_ops, +}; + +static const unsigned short pci_device_ids[] = +{ + 0x2e32, 0 +}; + +static const struct pci_driver gma __pci_driver = { + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c new file mode 100644 index 0000000..716844b --- /dev/null +++ b/src/northbridge/intel/x4x/northbridge.c @@ -0,0 +1,268 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/hypertransport.h> +#include <stdlib.h> +#include <string.h> +#include <cpu/cpu.h> +#include <boot/tables.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "chip.h" +#include "x4x.h" +#include "arch/acpi.h" + +/* Reserve segments A and B: + * + * 0xa0000 - 0xbffff: legacy VGA + */ +static const int legacy_hole_base_k = 0xa0000 / 1024; +static const int legacy_hole_size_k = 128; + +static int decode_pcie_bar(u32 *const base, u32 *const len) +{ + *base = 0; + *len = 0; + + const device_t dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!dev) + return 0; + + const u32 pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); + + if (!(pciexbar_reg & (1 << 0))) + return 0; + + switch ((pciexbar_reg >> 1) & 3) { + case 0: /* 256MB */ + *base = pciexbar_reg & (0x0f << 28); + *len = 256 * 1024 * 1024; + return 1; + case 1: /* 128M */ + *base = pciexbar_reg & (0x1f << 27); + *len = 128 * 1024 * 1024; + return 1; + case 2: /* 64M */ + *base = pciexbar_reg & (0x3f << 26); + *len = 64 * 1024 * 1024; + return 1; + } + + return 0; +} + +static void mch_domain_read_resources(device_t dev) +{ + u64 tom, touud; + u32 tomk, tsegk, tolud, usable_tomk; + u32 pcie_config_base, pcie_config_size; + u32 uma_sizek = 0; + + /* 1024KiB TSEG */ + tsegk = 1 << 10; + + pci_domain_read_resources(dev); + + /* Top of Upper Usable DRAM, including remap */ + touud = pci_read_config16(dev, D0F0_TOUUD); + touud <<= 20; + + /* Top of Lower Usable DRAM */ + tolud = pci_read_config16(dev, D0F0_TOLUD) & 0xfff0; + tolud <<= 16; + + /* Top of Memory - does not account for any UMA */ + tom = pci_read_config16(dev, D0F0_TOM) & 0x01ff; + tom <<= 26; + + printk(BIOS_DEBUG, "TOUUD 0x%llx TOLUD 0x%08x TOM 0x%llx\n", + touud, tolud, tom); + + tomk = tolud >> 10; + + /* Graphics memory comes next */ + const u16 ggc = pci_read_config16(dev, D0F0_GGC); + printk(BIOS_DEBUG, "IGD decoded, subtracting "); + + /* Graphics memory */ + const u32 gms_sizek = decode_igd_memory_size((ggc >> 4) & 0xf); + printk(BIOS_DEBUG, "%uM UMA", gms_sizek >> 10); + + /* GTT Graphics Stolen Memory Size (GGMS) */ + const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); + printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); + + uma_sizek = gms_sizek + gsm_sizek + tsegk; + usable_tomk = tomk - uma_sizek; + + printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); + + /* Report the memory regions */ + ram_resource(dev, 3, 0, legacy_hole_base_k); + ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, + (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); + + /* + * If >= 4GB installed then memory from TOLUD to 4GB + * is remapped above TOM, TOUUD will account for both + */ + touud >>= 10; /* Convert to KB */ + if (touud > 4096 * 1024) { + ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", + (touud >> 10) - 4096); + } + + printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " + "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, 6, usable_tomk, uma_sizek, IORESOURCE_RESERVE); + + /* Some strange hole, reserve it */ + fixed_mem_resource(dev, 7, usable_tomk - (0x02000000 >> 10), 0x02000000 >> 10, IORESOURCE_RESERVE); + + if (decode_pcie_bar(&pcie_config_base, &pcie_config_size)) { + printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " + "size=0x%x\n", pcie_config_base, pcie_config_size); + fixed_mem_resource(dev, 8, pcie_config_base >> 10, + pcie_config_size >> 10, IORESOURCE_RESERVE); + } +} + +static void mch_domain_set_resources(device_t dev) +{ + struct resource *resource; + int i; + + for (i = 3; i < 9; ++i) { + /* Report read resources. */ + resource = probe_resource(dev, i); + if (resource) + report_resource_stored(dev, resource, ""); + } + + assign_resources(dev->link_list); +} + +static void mch_domain_init(device_t dev) +{ + u32 reg32; + + /* Enable SERR */ + reg32 = pci_read_config32(dev, PCI_COMMAND); + reg32 |= PCI_COMMAND_SERR; + pci_write_config32(dev, PCI_COMMAND, reg32); +} + +static struct device_operations pci_domain_ops = { + .read_resources = mch_domain_read_resources, + .set_resources = mch_domain_set_resources, + .enable_resources = NULL, + .init = mch_domain_init, + .scan_bus = pci_domain_scan_bus, + .ops_pci_bus = pci_bus_default_ops, + .write_acpi_tables = northbridge_write_acpi_tables, + .acpi_fill_ssdt_generator = generate_cpu_entries, +}; + + +static void cpu_bus_init(device_t dev) +{ + initialize_cpus(dev->link_list); +} + +static struct device_operations cpu_bus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, + .init = cpu_bus_init, + .scan_bus = 0, +}; + + +static void enable_dev(device_t dev) +{ + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; +#if CONFIG_HAVE_ACPI_RESUME + switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { + case SKPAD_NORMAL_BOOT_MAGIC: + printk(BIOS_DEBUG, "Normal boot.\n"); + acpi_slp_type=0; + break; + case SKPAD_ACPI_S3_MAGIC: + printk(BIOS_DEBUG, "S3 Resume.\n"); + acpi_slp_type=3; + break; + default: + printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); + acpi_slp_type=0; + break; + } +#endif + } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } +} + +static void x4x_init(void *const chip_info) +{ + int dev, fn, bit_base; + + struct device *const d0f0 = dev_find_slot(0, 0); + + /* Hide internal functions based on devicetree info. */ + for (dev = 3; dev > 0; --dev) { + switch (dev) { + case 3: /* ME */ + fn = 3; + bit_base = 6; + break; + case 2: /* IGD */ + fn = 1; + bit_base = 3; + break; + case 1: /* PEG */ + fn = 0; + bit_base = 1; + break; + } + for (; fn >= 0; --fn) { + const struct device *const d = + dev_find_slot(0, PCI_DEVFN(dev, fn)); + if (!d || d->enabled) continue; + const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + pci_write_config32(d0f0, D0F0_DEVEN, + deven & ~(1 << (bit_base + fn))); + } + } + + const u32 deven = pci_read_config32(d0f0, D0F0_DEVEN); + if (!(deven & (0xf << 6))) + pci_write_config32(d0f0, D0F0_DEVEN, deven & ~(1 << 14)); +} + +struct chip_operations northbridge_intel_x4x_ops = { + CHIP_NAME("Intel 4-Series Northbridge") + .enable_dev = enable_dev, + .init = x4x_init, +}; diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c new file mode 100644 index 0000000..b89240e --- /dev/null +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <console/console.h> +#include <cbmem.h> +#include "x4x.h" + +/** Decodes used Graphics Mode Select (GMS) to kilobytes. */ +u32 decode_igd_memory_size(const u32 gms) +{ + const u16 ggc2uma[] = { 0, 0, 0, 0, 0, + 32, 48, 64, 128, 256, 96, 160, 224, 352 }; + + if (gms > ARRAY_SIZE(ggc2uma)) + die("Bad Graphics Mode Select (GMS) setting.\n"); + + return ggc2uma[gms] << 10; +} + +/** Decodes used GTT Graphics Memory Size (GGMS) to kilobytes. */ +u32 decode_igd_gtt_size(const u32 gsm) +{ + const u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; + + if (gsm > ARRAY_SIZE(ggc2gtt)) + die("Bad GTT Graphics Memory Size (GGMS) setting.\n"); + + return ggc2gtt[gsm] << 10; +} diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h new file mode 100644 index 0000000..f8f1bda --- /dev/null +++ b/src/northbridge/intel/x4x/x4x.h @@ -0,0 +1,360 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * 2012 secunet Security Networks AG + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __NORTHBRIDGE_INTEL_X4X_X4X_H__ +#define __NORTHBRIDGE_INTEL_X4X_X4X_H__ + +#include "southbridge/intel/i82801gx/i82801gx.h" + +#ifndef __ACPI__ + +#include <rules.h> +#include <stdint.h> + +typedef enum { + FSB_CLOCK_800MHz = 0, + FSB_CLOCK_1066MHz = 1, + FSB_CLOCK_1333MHz = 2, +} fsb_clock_t; + +typedef enum { + MEM_CLOCK_400MHz = 0, + MEM_CLOCK_533MHz = 1, + MEM_CLOCK_667MHz = 2, + MEM_CLOCK_800MHz = 3, + MEM_CLOCK_1066MHz = 4, + MEM_CLOCK_1333MHz = 5, +} mem_clock_t; + +typedef enum { + DDR2 = 2, + DDR3 = 3, +} ddr_t; + +typedef enum { /* as in DDR3 spd */ + CHIP_WIDTH_x4 = 0, + CHIP_WIDTH_x8 = 1, + CHIP_WIDTH_x16 = 2, + CHIP_WIDTH_x32 = 3, +} chip_width_t; + +typedef enum { /* as in DDR3 spd */ + CHIP_CAP_256M = 0, + CHIP_CAP_512M = 1, + CHIP_CAP_1G = 2, + CHIP_CAP_2G = 3, + CHIP_CAP_4G = 4, + CHIP_CAP_8G = 5, + CHIP_CAP_16G = 6, +} chip_capacity_t; + +typedef struct { + unsigned int CAS; + fsb_clock_t fsb_clock; + mem_clock_t mem_clock; + unsigned int tRAS; + unsigned int tRP; + unsigned int tRCD; + unsigned int tWR; + unsigned int tRFC; + unsigned int tWTR; + unsigned int tRRD; + unsigned int tRTP; +} timings_t; + +typedef struct { + unsigned int card_type; /* 0x0: unpopulated, + 0xa - 0xf: raw card type A - F */ + chip_width_t width; + chip_capacity_t chip_capacity; + unsigned int page_size; /* of whole DIMM in Bytes (4096 or 8192) */ + unsigned int sides; + unsigned int banks; + unsigned int ranks; + unsigned int rows; + unsigned int cols; + unsigned int cas_latencies; + unsigned int tAAmin; + unsigned int tCKmin; + unsigned int tWR; + unsigned int tRP; + unsigned int tRCD; + unsigned int tRAS; + unsigned int rank_capacity_mb; /* per rank in Mega Bytes */ + u8 spd_data[256]; +} dimminfo_t; + +/* The setup is up to two DIMMs per channel */ +typedef struct { + int txt_enabled; + int cores; + int boot_path; + int max_ddr2_mhz; + int max_ddr3_mt; + fsb_clock_t max_fsb; + int max_fsb_mhz; + int max_render_mhz; + int enable_igd; + int enable_peg; + u16 ggc; + + int dimm_config[2]; + int dimms_per_ch; + int spd_type; + int channel_capacity[2]; + timings_t selected_timings; + dimminfo_t dimms[4]; + u8 spd_map[4]; +} sysinfo_t; + +typedef enum { + CLKSET0 = 0, + CTRL0, + CLKSET1, + CMD, + CTRL1, + CTRL2, + CTRL3, + DQS1, + DQS2, + DQS3, + DQS4, + DQS5, + DQS6, + DQS7, + DQS8, + DQ1, + DQ2, + DQ3, + DQ4, + DQ5, + DQ6, + DQ7, + DQ8 +} DDR2_Signals; + +#define NOP_CMD 0x2 +#define PRECHARGE_CMD 0x4 +#define MRS_CMD 0x6 +#define EMRS_CMD 0x8 +#define EMRS1_CMD (EMRS_CMD | 0x10) +#define EMRS2_CMD (EMRS_CMD | 0x20) +#define EMRS3_CMD (EMRS_CMD | 0x30) +#define ZQCAL_CMD 0xa +#define CBR_CMD 0xc +#define NORMALOP_CMD 0xe + +#define TOTAL_CHANNELS 2 +#define TOTAL_DIMMS 4 + +#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) +#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) +#define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) +#define ONLY_DIMMB_IS_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3) && \ + !DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2))) +#define BOTH_DIMMS_ARE_POPULATED(dimms, ch) ( \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ + (DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3)))) +#define FOR_EACH_DIMM(idx) \ + for (idx = 0; idx < TOTAL_DIMMS; ++idx) +#define FOR_EACH_POPULATED_DIMM(dimms, idx) \ + FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) +#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf)) +#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define FOR_EACH_CHANNEL(idx) \ + for (idx = 0; idx < TOTAL_CHANNELS; ++idx) +#define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ + FOR_EACH_CHANNEL(idx) IF_CHANNEL_POPULATED(dimms, idx) + +#define RANKS_PER_CHANNEL 4 +#define RANK_IS_POPULATED(dimms, ch, r) \ + ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ + (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define IF_RANK_POPULATED(dimms, ch, r) \ + if ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ + (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) +#define FOR_EACH_RANK_IN_CHANNEL(r) \ + for (r = 0; r < RANKS_PER_CHANNEL; ++r) +#define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ + FOR_EACH_RANK_IN_CHANNEL(r) IF_RANK_POPULATED(dimms, ch, r) +#define FOR_EACH_RANK(ch, r) \ + FOR_EACH_CHANNEL(ch) FOR_EACH_RANK_IN_CHANNEL(r) +#define FOR_EACH_POPULATED_RANK(dimms, ch, r) \ + FOR_EACH_RANK(ch, r) IF_RANK_POPULATED(dimms, ch, r) + +#define DDR3_MAX_CAS 18 + +enum { + VCO_2666 = 4, + VCO_3200 = 0, + VCO_4000 = 1, + VCO_5333 = 2, +}; + +#endif + +/* Offsets of read/write training results in CMOS. + They will be restored upon S3 resumes. */ +#define CMOS_READ_TRAINING 0x80 /* 16 bytes */ +#define CMOS_WRITE_TRAINING 0x90 /* 16 bytes + (could be reduced to 10 bytes) */ + + +#ifndef __ACPI__ +#define DEFAULT_MCHBAR ((u8 *)0xfed14000) +#define DEFAULT_DMIBAR ((u8 *)0xfed18000) +#else +#define DEFAULT_MCHBAR 0xfed14000 +#define DEFAULT_DMIBAR 0xfed18000 +#endif +#define DEFAULT_EPBAR 0xfed19000 +#define DEFAULT_HECIBAR 0xfed10000 + + /* 4 KB per PCIe device */ +#define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS + +/* + * D0:F0 + */ +#define D0F0_EPBAR_LO 0x40 +#define D0F0_EPBAR_HI 0x44 +#define D0F0_MCHBAR_LO 0x48 +#define D0F0_MCHBAR_HI 0x4c +#define D0F0_GGC 0x52 +#define D0F0_DEVEN 0x54 +#define D0F0_PCIEXBAR_LO 0x60 +#define D0F0_PCIEXBAR_HI 0x64 +#define D0F0_DMIBAR_LO 0x68 +#define D0F0_DMIBAR_HI 0x6c +#define D0F0_PMBASE 0x78 +#define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ +#define D0F0_REMAPBASE 0x98 +#define D0F0_REMAPLIMIT 0x9a +#define D0F0_SMRAM 0x9d +#define D0F0_ESMRAMC 0x9e +#define D0F0_TOM 0xa0 +#define D0F0_TOUUD 0xa2 +#define D0F0_TOLUD 0xb0 +#define D0F0_GBSM 0xa4 +#define D0F0_BGSM 0xa8 +#define D0F0_TSEG 0xac +#define D0F0_SKPD 0xdc /* Scratchpad Data */ +#define D0F0_CAPID0 0xe0 + +/* + * D1:F0 PEG + */ +#define PEG_CAP 0xa2 +#define SLOTCAP 0xb4 +#define PEGLC 0xec +#define D1F0_VCCAP 0x104 +#define D1F0_VC0RCTL 0x114 + +/* + * Graphics frequencies + */ +#define GCFGC_PCIDEV PCI_DEV(0, 2, 0) +#define GCFGC_OFFSET 0xf0 +#define GCFGC_CR_SHIFT 0 +#define GCFGC_CR_MASK (0xf << GCFGC_CR_SHIFT) +#define GCFGC_CS_SHIFT 8 +#define GCFGC_CS_MASK (0xf << GCFGC_CS_SHIFT) +#define GCFGC_CD_SHIFT 12 +#define GCFGC_CD_MASK (0x1 << GCFGC_CD_SHIFT) +#define GCFGC_UPDATE_SHIFT 5 +#define GCFGC_UPDATE (0x1 << GCFGC_UPDATE_SHIFT) + +/* + * MCHBAR + */ + +#define MCHBAR8(x) *((volatile u8 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR16(x) *((volatile u16 *)(DEFAULT_MCHBAR + x)) +#define MCHBAR32(x) *((volatile u32 *)(DEFAULT_MCHBAR + x)) + +#define PMSTS_MCHBAR 0x0f14 /* Self refresh channel status */ +#define PMSTS_WARM_RESET (1 << 1) +#define PMSTS_BOTH_SELFREFRESH (1 << 0) + +#define CLKCFG_MCHBAR 0x0c00 +#define CLKCFG_FSBCLK_SHIFT 0 +#define CLKCFG_FSBCLK_MASK (7 << CLKCFG_FSBCLK_SHIFT) +#define CLKCFG_MEMCLK_SHIFT 4 +#define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) +#define CLKCFG_UPDATE (1 << 12) + +#define SSKPD_MCHBAR 0x0c1c +#define SSKPD_CLK_SHIFT 0 +#define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT) + +/* + * DMIBAR + */ + +#define DMIBAR8(x) *((volatile u8 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR16(x) *((volatile u16 *)(DEFAULT_DMIBAR + x)) +#define DMIBAR32(x) *((volatile u32 *)(DEFAULT_DMIBAR + x)) + +#define DMIVC0RCTL 0x14 +#define DMIVC1RCTL 0x20 +#define DMIVC1RSTS 0x26 +#define DMIESD 0x44 +#define DMILE1D 0x50 +#define DMILE1A 0x58 +#define DMILE2D 0x60 +#define DMILE2A 0x68 + + +/* + * EPBAR + */ + +#define EPBAR8(x) *((volatile u8 *)(DEFAULT_EPBAR + x)) +#define EPBAR16(x) *((volatile u16 *)(DEFAULT_EPBAR + x)) +#define EPBAR32(x) *((volatile u32 *)(DEFAULT_EPBAR + x)) + +#define EPESD 0x44 +#define EPLE1D 0x50 +#define EPLE1A 0x58 +#define EPLE2D 0x60 + + +#ifndef __ACPI__ +void x4x_early_init(void); +u32 decode_igd_memory_size(u32 gms); +u32 decode_igd_gtt_size(u32 gsm); +void init_igd(const sysinfo_t *const); +void igd_compute_ggc(sysinfo_t *const sysinfo); +int raminit_read_vco_index(void); +void sdram_initialize(int boot_path, const u8 *spd_map); +void raminit_ddr2(sysinfo_t *); + + +#if ENV_RAMSTAGE +#include <device/device.h> + +struct acpi_rsdp; +unsigned long northbridge_write_acpi_tables(device_t device, unsigned long start, struct acpi_rsdp *rsdp); +#endif + + +#endif /* !__ACPI__ */ +#endif

1 0

Patch set updated for coreboot: google/guado: initial upstream migration
by Matt DeVillier 27 Dec '15

27 Dec '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12800 -gerrit commit dce1369a1217736f87e58cb1613de1d7fa4239db Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Tue Nov 3 23:20:10 2015 -0600 google/guado: initial upstream migration Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream, using google/auron and google/panther as refs. TEST=built and booted guado with full functionality Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702 Tested-by: Matt DeVillier <matt.devillier(a)gmail.com> Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/guado/Kconfig | 64 ++++ src/mainboard/google/guado/Kconfig.name | 2 + src/mainboard/google/guado/Makefile.inc | 24 ++ src/mainboard/google/guado/acpi/chromeos.asl | 19 ++ src/mainboard/google/guado/acpi/ec.asl | 0 .../google/guado/acpi/haswell_pci_irqs.asl | 83 +++++ src/mainboard/google/guado/acpi/mainboard.asl | 69 +++++ src/mainboard/google/guado/acpi/platform.asl | 71 +++++ src/mainboard/google/guado/acpi/superio.asl | 32 ++ src/mainboard/google/guado/acpi/thermal.asl | 340 +++++++++++++++++++++ src/mainboard/google/guado/acpi/video.asl | 39 +++ src/mainboard/google/guado/acpi_tables.c | 66 ++++ src/mainboard/google/guado/board_info.txt | 7 + src/mainboard/google/guado/chromeos.c | 101 ++++++ src/mainboard/google/guado/cmos.layout | 135 ++++++++ src/mainboard/google/guado/devicetree.cb | 122 ++++++++ src/mainboard/google/guado/dsdt.asl | 57 ++++ src/mainboard/google/guado/fadt.c | 154 ++++++++++ src/mainboard/google/guado/gpio.h | 120 ++++++++ src/mainboard/google/guado/hda_verb.c | 109 +++++++ src/mainboard/google/guado/lan.c | 191 ++++++++++++ src/mainboard/google/guado/mainboard.c | 54 ++++ src/mainboard/google/guado/onboard.h | 42 +++ src/mainboard/google/guado/pei_data.c | 59 ++++ src/mainboard/google/guado/romstage.c | 64 ++++ src/mainboard/google/guado/smihandler.c | 89 ++++++ src/mainboard/google/guado/spd/Makefile.inc | 16 + src/mainboard/google/guado/spd/spd.c | 37 +++ src/mainboard/google/guado/spd/spd.h | 22 ++ src/mainboard/google/guado/thermal.h | 55 ++++ 30 files changed, 2243 insertions(+) diff --git a/src/mainboard/google/guado/Kconfig b/src/mainboard/google/guado/Kconfig new file mode 100644 index 0000000..975d9a6 --- /dev/null +++ b/src/mainboard/google/guado/Kconfig @@ -0,0 +1,64 @@ +if BOARD_GOOGLE_GUADO + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SOC_INTEL_BROADWELL + select BOARD_ROMSIZE_KB_8192 + select SUPERIO_ITE_IT8772F + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_ACPI_RESUME + select MMCONF_SUPPORT + select HAVE_SMI_HANDLER + select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_LPC_TPM + +config CHROMEOS + select CHROMEOS_VBNV_CMOS + select CHROMEOS_RAMOOPS_DYNAMIC + select VIRTUAL_DEV_SWITCH + select PHYSICAL_REC_SWITCH + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x2 + +config VBOOT_REFCODE_INDEX + hex + default 0x3 + +config MAINBOARD_DIR + string + default google/guado + +config MAINBOARD_PART_NUMBER + string + default "Guado" + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config VGA_BIOS_FILE + string + default "pci8086,0166.rom" + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + + +config MAINBOARD_FAMILY + string + depends on GENERATE_SMBIOS_TABLES + default "Google_Guado" + +endif diff --git a/src/mainboard/google/guado/Kconfig.name b/src/mainboard/google/guado/Kconfig.name new file mode 100644 index 0000000..e8ae9fd --- /dev/null +++ b/src/mainboard/google/guado/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GOOGLE_GUADO + bool "Guado" diff --git a/src/mainboard/google/guado/Makefile.inc b/src/mainboard/google/guado/Makefile.inc new file mode 100644 index 0000000..0557cc2 --- /dev/null +++ b/src/mainboard/google/guado/Makefile.inc @@ -0,0 +1,24 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-y += spd +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-y += lan.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c + +romstage-y += pei_data.c +ramstage-y += pei_data.c diff --git a/src/mainboard/google/guado/acpi/chromeos.asl b/src/mainboard/google/guado/acpi/chromeos.asl new file mode 100644 index 0000000..492ee6b --- /dev/null +++ b/src/mainboard/google/guado/acpi/chromeos.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Name(OIPG, Package() { + Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button + Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect +}) diff --git a/src/mainboard/google/guado/acpi/ec.asl b/src/mainboard/google/guado/acpi/ec.asl new file mode 100644 index 0000000..e69de29 diff --git a/src/mainboard/google/guado/acpi/haswell_pci_irqs.asl b/src/mainboard/google/guado/acpi/haswell_pci_irqs.asl new file mode 100644 index 0000000..3244365 --- /dev/null +++ b/src/mainboard/google/guado/acpi/haswell_pci_irqs.asl @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for IvyBridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, 0, 16 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 22 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, 0, 18 }, + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 22 }, + Package() { 0x001fffff, 1, 0, 18 }, + Package() { 0x001fffff, 2, 0, 17 }, + Package() { 0x001fffff, 3, 0, 16 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, 0, 20 }, + Package() { 0x0015ffff, 1, 0, 21 }, + Package() { 0x0015ffff, 2, 0, 21 }, + Package() { 0x0015ffff, 3, 0, 21 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, 0, 23 }, + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // Mini-HD Audio 0:3.0 + Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // XHCI 0:14.0 + Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + // Serial IO 0:15.0 + Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, + Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, + // SDIO 0:17.0 + Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + }) + } +} + diff --git a/src/mainboard/google/guado/acpi/mainboard.asl b/src/mainboard/google/guado/acpi/mainboard.asl new file mode 100644 index 0000000..37457fc --- /dev/null +++ b/src/mainboard/google/guado/acpi/mainboard.asl @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <mainboard/google/guado/onboard.h> + +Scope (\_SB) +{ + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} + +/* + * LAN connected to Root Port 3, becomes Root Port 1 after coalesce + */ +Scope (\_SB.PCI0.RP01) +{ + Device (ETH0) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { GUADO_NIC_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (GUADO_NIC_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} + +/* + * WLAN connected to Root Port 4, becomes Root Port 2 after coalesce + */ +Scope (\_SB.PCI0.RP02) +{ + Device (WLAN) + { + Name (_ADR, 0x00000000) + Name (_PRW, Package() { GUADO_WLAN_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (GUADO_WLAN_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + } +} diff --git a/src/mainboard/google/guado/acpi/platform.asl b/src/mainboard/google/guado/acpi/platform.asl new file mode 100644 index 0000000..06de271 --- /dev/null +++ b/src/mainboard/google/guado/acpi/platform.asl @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Initialize thermal defaults */ + \_TZ.THRM._INI () + + Return(Package(){0,0}) +} diff --git a/src/mainboard/google/guado/acpi/superio.asl b/src/mainboard/google/guado/acpi/superio.asl new file mode 100644 index 0000000..a65b3f5 --- /dev/null +++ b/src/mainboard/google/guado/acpi/superio.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Values should match those defined in devicetree.cb */ + +#undef SIO_ENABLE_FDC0 // pnp 2e.0: Disable Floppy Controller +#undef SIO_ENABLE_INFR // pnp 2e.a: Disable Consumer IR + +#undef SIO_ENABLE_PS2K // pnp 2e.5: Disable PS/2 Keyboard +#undef SIO_ENABLE_PS2M // pnp 2e.6: Disable PS/2 Mouse +#define SIO_ENABLE_COM1 // pnp 2e.1: Enable Serial Port 1 +#define SIO_ENABLE_ENVC // pnp 2e.4: Enable Environmental Controller +#define SIO_ENVC_IO0 0x700 // pnp 2e.4: io 0x60 +#define SIO_ENVC_IO1 0x710 // pnp 2e.4: io 0x62 +#define SIO_ENABLE_GPIO // pnp 2e.7: Enable GPIO +#define SIO_GPIO_IO0 0x720 // pnp 2e.7: io 0x60 +#define SIO_GPIO_IO1 0x730 // pnp 2e.7: io 0x60 + +#include "superio/ite/it8772f/acpi/superio.asl" + diff --git a/src/mainboard/google/guado/acpi/thermal.asl b/src/mainboard/google/guado/acpi/thermal.asl new file mode 100644 index 0000000..a173585 --- /dev/null +++ b/src/mainboard/google/guado/acpi/thermal.asl @@ -0,0 +1,340 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../thermal.h" + +// Thermal Zone + +Scope (\_TZ) +{ + ThermalZone (THRM) + { + Name (_TC1, 0x02) + Name (_TC2, 0x05) + + // Thermal zone polling frequency: 10 seconds + Name (_TZP, 100) + + // Thermal sampling period for passive cooling: 2 seconds + Name (_TSP, 20) + + // Convert from Degrees C to 1/10 Kelvin for ACPI + Method (CTOK, 1) { + // 10th of Degrees C + Multiply (Arg0, 10, Local0) + + // Convert to Kelvin + Add (Local0, 2732, Local0) + + Return (Local0) + } + + // Threshold for OS to shutdown + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + // Threshold for passive cooling + Method (_PSV, 0, Serialized) + { + Return (CTOK (\TPSV)) + } + + // Processors used for passive cooling + Method (_PSL, 0, Serialized) + { + Return (\PPKG ()) + } + + // Start fan at state 4 = lowest temp state + Method (_INI) + { + Store (4, \FLVL) + Store (FAN4_PWM, \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + + Method (TCHK, 0, Serialized) + { + // Get CPU Temperature from PECI via SuperIO TMPIN3 + Store (\_SB.PCI0.LPCB.SIO.ENVC.TIN3, Local0) + + // Check for "no reading available + If (LEqual (Local0, 0x80)) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // Check for invalid readings + If (LOr (LEqual (Local0, 255), LEqual (Local0, 0))) { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + + // PECI raw value is an offset from Tj_max + Subtract (255, Local0, Local1) + + // Handle values greater than Tj_max + If (LGreaterEqual (Local1, \TMAX)) { + Return (CTOK (\TMAX)) + } + + // Subtract from Tj_max to get temperature + Subtract (\TMAX, Local1, Local0) + Return (CTOK (Local0)) + } + + Method (_TMP, 0, Serialized) + { + // Get temperature from SuperIO in deci-kelvin + Store (TCHK (), Local0) + + // Critical temperature in deci-kelvin + Store (CTOK (\TMAX), Local1) + + If (LGreaterEqual (Local0, Local1)) { + Store ("CRITICAL TEMPERATURE", Debug) + Store (Local0, Debug) + + // Wait 1 second for SuperIO to re-poll + Sleep (1000) + + // Re-read temperature from SuperIO + Store (TCHK (), Local0) + + Store ("RE-READ TEMPERATURE", Debug) + Store (Local0, Debug) + } + + Return (Local0) + } + + Method (_AC0) { + If (LLessEqual (\FLVL, 0)) { + Return (CTOK (FAN0_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN0_THRESHOLD_ON)) + } + } + + Method (_AC1) { + If (LLessEqual (\FLVL, 1)) { + Return (CTOK (FAN1_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN1_THRESHOLD_ON)) + } + } + + Method (_AC2) { + If (LLessEqual (\FLVL, 2)) { + Return (CTOK (FAN2_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN2_THRESHOLD_ON)) + } + } + + Method (_AC3) { + If (LLessEqual (\FLVL, 3)) { + Return (CTOK (FAN3_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN3_THRESHOLD_ON)) + } + } + + Method (_AC4) { + If (LLessEqual (\FLVL, 4)) { + Return (CTOK (FAN4_THRESHOLD_OFF)) + } Else { + Return (CTOK (FAN4_THRESHOLD_ON)) + } + } + + Name (_AL0, Package () { FAN0 }) + Name (_AL1, Package () { FAN1 }) + Name (_AL2, Package () { FAN2 }) + Name (_AL3, Package () { FAN3 }) + Name (_AL4, Package () { FAN4 }) + + PowerResource (FNP0, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 0)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (0, \FLVL) + Store (FAN0_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP1, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 1)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (1, \FLVL) + Store (FAN1_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP2, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 2)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (2, \FLVL) + Store (FAN2_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP3, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 3)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (3, \FLVL) + Store (FAN3_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + PowerResource (FNP4, 0, 0) + { + Method (_STA) { + If (LLessEqual (\FLVL, 4)) { + Return (One) + } Else { + Return (Zero) + } + } + Method (_ON) { + If (LNot (_STA ())) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + Method (_OFF) { + If (_STA ()) { + Store (4, \FLVL) + Store (FAN4_PWM, + \_SB.PCI0.LPCB.SIO.ENVC.F2PS) + Notify (\_TZ.THRM, 0x81) + } + } + } + + Device (FAN0) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 0) + Name (_PR0, Package () { FNP0 }) + } + + Device (FAN1) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 1) + Name (_PR0, Package () { FNP1 }) + } + + Device (FAN2) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 2) + Name (_PR0, Package () { FNP2 }) + } + + Device (FAN3) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 3) + Name (_PR0, Package () { FNP3 }) + } + + Device (FAN4) + { + Name (_HID, EISAID ("PNP0C0B")) + Name (_UID, 4) + Name (_PR0, Package () { FNP4 }) + } + } +} + diff --git a/src/mainboard/google/guado/acpi/video.asl b/src/mainboard/google/guado/acpi/video.asl new file mode 100644 index 0000000..1405b04 --- /dev/null +++ b/src/mainboard/google/guado/acpi/video.asl @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Brightness write +Method (BRTW, 1, Serialized) +{ + // TODO +} + +// Hot Key Display Switch +Method (HKDS, 1, Serialized) +{ + // TODO +} + +// Lid Switch Display Switch +Method (LSDS, 1, Serialized) +{ + // TODO +} + +// Brightness Notification +Method(BRTN,1,Serialized) +{ + // TODO (no displays defined yet) +} + diff --git a/src/mainboard/google/guado/acpi_tables.c b/src/mainboard/google/guado/acpi_tables.c new file mode 100644 index 0000000..4f75200 --- /dev/null +++ b/src/mainboard/google/guado/acpi_tables.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <soc/acpi.h> +#include <soc/nvs.h> +#include "thermal.h" + + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tmps = TEMPERATURE_SENSOR_ID; + + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; + gnvs->flvl = 1; +} + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + acpi_init_gnvs(gnvs); + + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} diff --git a/src/mainboard/google/guado/board_info.txt b/src/mainboard/google/guado/board_info.txt new file mode 100644 index 0000000..aa7a848 --- /dev/null +++ b/src/mainboard/google/guado/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: Asus +Board name: Chromebox2 +Category: half +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/guado/chromeos.c b/src/mainboard/google/guado/chromeos.c new file mode 100644 index 0000000..094447d --- /dev/null +++ b/src/mainboard/google/guado/chromeos.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <console/console.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/sata.h> + +#define GPIO_SPI_WP 58 +#define GPIO_REC_MODE 12 + +#define FLAG_SPI_WP 0 +#define FLAG_REC_MODE 1 +#define FLAG_DEV_MODE 2 + +#ifndef __PRE_RAM__ +#include <boot/coreboot_tables.h> + +#define GPIO_COUNT 6 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, GPIO_SPI_WP, ACTIVE_HIGH, "write protect", 0); + fill_lb_gpio(gpio++, GPIO_REC_MODE, ACTIVE_LOW, "recovery", + get_recovery_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", + get_developer_mode_switch()); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); +} +#endif + +int get_write_protect_state(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_SPI_WP) & 1; +} + +int get_developer_mode_switch(void) +{ + return 0; +} + +int get_recovery_mode_switch(void) +{ + device_t dev; +#ifdef __PRE_RAM__ + dev = PCI_DEV(0, 0x1f, 2); +#else + dev = dev_find_slot(0, PCI_DEVFN(0x1f, 2)); +#endif + return (pci_read_config32(dev, SATA_SP) >> FLAG_REC_MODE) & 1; +} + +#ifdef __PRE_RAM__ +void save_chromeos_gpios(void) +{ + u32 flags = 0; + + /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ + if (get_gpio(GPIO_SPI_WP)) + flags |= (1 << FLAG_SPI_WP); + + /* Recovery: GPIO12 = RECOVERY_L, active low */ + if (!get_gpio(GPIO_REC_MODE)) + flags |= (1 << FLAG_REC_MODE); + + /* Developer: Virtual */ + + pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); +} +#endif diff --git a/src/mainboard/google/guado/cmos.layout b/src/mainboard/google/guado/cmos.layout new file mode 100644 index 0000000..f862cd6 --- /dev/null +++ b/src/mainboard/google/guado/cmos.layout @@ -0,0 +1,135 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# coreboot config options: bootloader +#Used by ChromeOS: +416 128 r 0 vbnv +#544 440 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/google/guado/devicetree.cb b/src/mainboard/google/guado/devicetree.cb new file mode 100644 index 0000000..4d16ed6 --- /dev/null +++ b/src/mainboard/google/guado/devicetree.cb @@ -0,0 +1,122 @@ +chip soc/intel/broadwell + + # Disable eDP Hotplug + register "gpu_dp_d_hotplug" = "0x00" + + # Enable DisplayPort C Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Enable HDMI Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + + + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # SuperIO range is 0x700-0x73f + register "gen2_dec" = "0x003c0701" + + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000000" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_devslp_disable" = "0x1" + + register "sio_acpi_mode" = "0" + register "sio_i2c0_voltage" = "0" # 3.3V + register "sio_i2c1_voltage" = "0" # 3.3V + + # Force enable ASPM for PCIe Port 4 + register "pcie_port_force_aspm" = "0x10" + + # Enable port coalescing + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 off end # Serial I/O DMA + device pci 15.1 off end # I2C0 + device pci 15.2 off end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 on end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip superio/ite/it8772f + # Skip keyboard init + register "skip_keyboard" = "1" + # Enable PECI on TMPIN3 + register "peci_tmpin" = "3" + # Enable FAN2 + register "fan2_enable" = "1" + + device pnp 2e.0 off end # FDC + device pnp 2e.1 on # Serial Port 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x700 + io 0x62 = 0x710 + irq 0x70 = 0x09 + irq 0xf2 = 0x20 + irq 0xf4 = 0x0 + irq 0xfa = 0x12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x720 + io 0x62 = 0x730 + end + device pnp 2e.5 off + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end # Keyboard + device pnp 2e.6 off + irq 0x70 = 12 + end # Mouse + device pnp 2e.a off end # IR + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal + end +end diff --git a/src/mainboard/google/guado/dsdt.asl b/src/mainboard/google/guado/dsdt.asl new file mode 100644 index 0000000..e078694 --- /dev/null +++ b/src/mainboard/google/guado/dsdt.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <soc/intel/broadwell/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + // CPU + #include <soc/intel/broadwell/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> + } + } + + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific + #include "acpi/chromeos.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> + + // Chipset specific sleep states + #include <soc/intel/broadwell/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/google/guado/fadt.c b/src/mainboard/google/guado/fadt.c new file mode 100644 index 0000000..c377d67 --- /dev/null +++ b/src/mainboard/google/guado/fadt.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <device/pci.h> +#include <soc/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/pch.h> +#include <soc/iomap.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = ACPI_BASE_ADDRESS; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x80; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 32; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 1; + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 0; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = 0; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/google/guado/gpio.h b/src/mainboard/google/guado/gpio.h new file mode 100644 index 0000000..4c167e3 --- /dev/null +++ b/src/mainboard/google/guado/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef GUADO_GPIO_H +#define GUADO_GPIO_H + +#include <soc/gpio.h> + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: LAN_WAKE_L_Q */ + PCH_GPIO_OUT_HIGH, /* 9: PP3300_WLAN_EN */ + PCH_GPIO_ACPI_SCI, /* 10: WLAN_WAKE_L_Q */ + PCH_GPIO_UNUSED, /* 11: SMBALERT */ + PCH_GPIO_INPUT_INVERT, /* 12: RECOVERY_L */ + PCH_GPIO_UNUSED, /* 13: UNUSED */ + PCH_GPIO_UNUSED, /* 14: UNUSED */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 16: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 17: PP3300_VP8_EN */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: NATIVE: CLK_PCIE_REQ2# */ + PCH_GPIO_NATIVE, /* 21: NATIVE: CLK_PCIE_REQ3# */ + PCH_GPIO_NATIVE, /* 22: NATIVE: CLK_PCIE_REQ4# */ + PCH_GPIO_UNUSED, /* 23: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 24: WLAN_OFF_L */ + PCH_GPIO_UNUSED, /* 25: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 26: USB_CTL_1 */ + PCH_GPIO_UNUSED, /* 27: UNUSED */ + PCH_GPIO_OUT_LOW, /* 28: USB_ILIM_SEL */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSPWRACK_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: PCH_ACPRESENT */ + PCH_GPIO_NATIVE, /* 32: NATIVE: CLKRUN# */ + PCH_GPIO_NATIVE, /* 33: NATIVE: DEVSLP0 */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: USB_OC0# */ + PCH_GPIO_NATIVE, /* 41: NATIVE: USB_OC1# */ + PCH_GPIO_NATIVE, /* 42: NATIVE: USB_OC2# */ + PCH_GPIO_NATIVE, /* 43: NATIVE: USB_OC3# */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 45: PP5000_CODEC_EN */ + PCH_GPIO_OUT_HIGH, /* 46: BT_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 47: USB1_PWR_EN */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 49: POWER_LED */ + PCH_GPIO_OUT_HIGH, /* 50: VP8_DISABLE_L */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_UNUSED, /* 52: UNUSED */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 56: USB2_PWR_EN */ + PCH_GPIO_OUT_HIGH, /* 57: USB3_PWR_EN */ + PCH_GPIO_INPUT, /* 58: PCH_SPI_WP_D */ + PCH_GPIO_OUT_HIGH, /* 59: PP3300_LAN_EN */ + PCH_GPIO_NATIVE, /* 60: NATIVE: SMB0ALERT# */ + PCH_GPIO_UNUSED, /* 61: UNUSED */ + PCH_GPIO_UNUSED, /* 62: UNUSED */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 67: UNUSED */ + PCH_GPIO_UNUSED, /* 68: UNUSED */ + PCH_GPIO_UNUSED, /* 69: UNUSED */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_NATIVE, /* 74: NATIVE: SMB_ME1_DAT */ + PCH_GPIO_NATIVE, /* 75: NATIVE: SMB_ME1_CLK */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_NATIVE, /* 81: NATIVE: SPKR */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_UNUSED, /* 83: UNUSED */ + PCH_GPIO_UNUSED, /* 84: UNUSED */ + PCH_GPIO_UNUSED, /* 85: UNUSED */ + PCH_GPIO_UNUSED, /* 86: UNUSED (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_UNUSED, /* 89: UNUSED */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/guado/hda_verb.c b/src/mainboard/google/guado/hda_verb.c new file mode 100644 index 0000000..284015d --- /dev/null +++ b/src/mainboard/google/guado/hda_verb.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 + 0x10ec0283, // Subsystem ID + 0x0000000c, // Number of jacks (NID entries) + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x10ec0283 */ + 0x00172083, + 0x00172102, + 0x001722ec, + 0x00172310, + + /* Pin Widget Verb Table */ + + /* Pin Complex (NID 0x12) DMIC */ + 0x01271cf0, + 0x01271d11, + 0x01271e11, + 0x01271f41, + + /* Pin Complex (NID 0x14) SPKR-OUT PORTD */ + 0x01471cf0, + 0x01471d11, + 0x01471e11, + 0x01471f40, + + /* Pin Complex (NID 0x17) */ + 0x01771cf0, + 0x01771d11, + 0x01771e11, + 0x01771f41, + + /* Pin Complex (NID 0x18) MIC1 PORTB */ + 0x01971c11, // group 1, cap 1 + 0x01971d10, // black, jack detect + 0x01971ea7, // mic in, analog + 0x01971f03, // connector, left panel + + /* Pin Complex (NID 0x19) MIC2 PORTF */ + 0x01871cf0, + 0x01871d11, + 0x01871e11, + 0x01871f41, + + /* Pin Complex (NID 0x1A) LINE1 PORTC */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1B) LINE2 PORTE */ + 0x01a71cf0, + 0x01a71d11, + 0x01a71e11, + 0x01a71f41, + + /* Pin Complex (NID 0x1d) PCBeep */ + 0x01d71c2d, // eapd low on ex-amp, laptop, custom enable + 0x01d71d81, // mute spkr on hpout + 0x01d71e15, // pcbeep en able, checksum + 0x01d71f40, // no physical, internal + + /* Pin Complex (NID 0x1E) SPDIF-OUT */ + 0x01e71cf0, + 0x01e71d11, + 0x01e71e11, + 0x01e71f41, + + /* Pin Complex (NID 0x21) HPOUT PORT-I */ + 0x02171c1f, // group1, + 0x02171d10, // black, jack detect + 0x02171e21, // HPOut, 1/8 stereo + 0x02171f03, // connector, left panel + + /* Undocumented settings from Realtek (needed for beep_gen) */ + /* Widget node 0x20 */ + 0x02050010, + 0x02040c20, + 0x0205001b, + 0x0204081b, +}; + +const u32 pc_beep_verbs[] = { + 0x00170500, /* power up everything (codec, dac, adc, mixers) */ + 0x01470740, /* enable speaker out */ + 0x01470c02, /* set speaker EAPD pin */ + 0x0143b01f, /* unmute speaker */ + 0x00c37100, /* unmute mixer nid 0xc input 1 */ + 0x00b37410, /* unmute mixer nid 0xb beep input and set volume */ +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/guado/lan.c b/src/mainboard/google/guado/lan.c new file mode 100644 index 0000000..041c3f0 --- /dev/null +++ b/src/mainboard/google/guado/lan.c @@ -0,0 +1,191 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <types.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <fmap.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include "onboard.h" + +static unsigned int search(char *p, u8 *a, unsigned int lengthp, + unsigned int lengtha) +{ + int i, j; + + /* Searching */ + for (j = 0; j <= lengtha - lengthp; j++) { + for (i = 0; i < lengthp && p[i] == a[i + j]; i++) ; + if (i >= lengthp) + return j; + } + return lengtha; +} + +static unsigned char get_hex_digit(u8 *offset) +{ + unsigned char retval = 0; + + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } + + return retval; +} + +static int get_mac_address(u32 *high_dword, u32 *low_dword, + u8 *search_address, u32 search_length) +{ + char key[] = "ethernet_mac"; + unsigned int offset; + int i; + + offset = search(key, search_address, sizeof(key) - 1, search_length); + if (offset == search_length) { + printk(BIOS_DEBUG, + "Error: Could not locate '%s' in VPD\n", key); + return 0; + } + printk(BIOS_DEBUG, "Located '%s' in VPD\n", key); + + offset += sizeof(key); /* move to next character */ + *high_dword = 0; + + /* Fetch the MAC address and put the octets in the correct order to + * be programmed. + * + * From RTL8105E_Series_EEPROM-Less_App_Note_1.1 + * If the MAC address is 001122334455h: + * Write 33221100h to I/O register offset 0x00 via double word access + * Write 00005544h to I/O register offset 0x04 via double word access + */ + + for (i = 0; i < 4; i++) { + *high_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *high_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + *low_dword = 0; + for (i = 0; i < 2; i++) { + *low_dword |= (get_hex_digit(search_address + offset) + << (4 + (i * 8))); + *low_dword |= (get_hex_digit(search_address + offset + 1) + << (i * 8)); + offset += 3; + } + + return *high_dword | *low_dword; +} + +static void program_mac_address(u16 io_base) +{ + void *search_address = NULL; + size_t search_length = -1; + + /* Default MAC Address of A0:00:BA:D0:0B:AD */ + u32 high_dword = 0xD0BA00A0; /* high dword of mac address */ + u32 low_dword = 0x0000AD0B; /* low word of mac address as a dword */ + + if (IS_ENABLED(CONFIG_CHROMEOS)) { + struct region_device rdev; + + if (fmap_locate_area_as_rdev("RO_VPD", &rdev) == 0) { + search_address = rdev_mmap_full(&rdev); + + if (search_address != NULL) + search_length = region_device_sz(&rdev); + } + } else { + search_address = cbfs_boot_map_with_leak("vpd.bin", + CBFS_TYPE_RAW, + &search_length); + } + + if (search_address == NULL) + printk(BIOS_ERR, "LAN: VPD not found.\n"); + else + get_mac_address(&high_dword, &low_dword, search_address, + search_length); + + if (io_base) { + printk(BIOS_DEBUG, "Realtek NIC io_base = 0x%04x\n", io_base); + printk(BIOS_DEBUG, "Programming MAC Address\n"); + + /* Disable register protection */ + outb(0xc0, io_base + 0x50); + outl(high_dword, io_base); + outl(low_dword, io_base + 0x04); + outb(0x60, io_base + 54); + /* Enable register protection again */ + outb(0x00, io_base + 0x50); + } +} + +void lan_init(void) +{ + u16 io_base = 0; + struct device *ethernet_dev = NULL; + + /* Get NIC's IO base address */ + ethernet_dev = dev_find_device(GUADO_NIC_VENDOR_ID, + GUADO_NIC_DEVICE_ID, 0); + if (ethernet_dev != NULL) { + io_base = pci_read_config16(ethernet_dev, 0x10) & 0xfffe; + + /* + * Battery life time - LAN PCIe should enter ASPM L1 to save + * power when LAN connection is idle. + * enable CLKREQ: LAN pci config space 0x81h=01 + */ + pci_write_config8(ethernet_dev, 0x81, 0x01); + } + + if (io_base) { + /* Program MAC address based on VPD data */ + program_mac_address(io_base); + + /* + * Program NIC LEDS + * + * RTL8105E Series EEPROM-Less Application Note, + * Section 5.6 LED Mode Configuration + * + * Step1: Write C0h to I/O register 0x50 via byte access to + * disable 'register protection' + * Step2: Write xx001111b to I/O register 0x52 via byte access + * (bit7 is LEDS1 and bit6 is LEDS0) + * Step3: Write 0x00 to I/O register 0x50 via byte access to + * enable 'register protection' + */ + outb(0xc0, io_base + 0x50); /* Disable protection */ + outb((GUADO_NIC_LED_MODE << 6) | 0x0f, io_base + 0x52); + outb(0x00, io_base + 0x50); /* Enable register protection */ + } +} diff --git a/src/mainboard/google/guado/mainboard.c b/src/mainboard/google/guado/mainboard.c new file mode 100644 index 0000000..f400c2fe --- /dev/null +++ b/src/mainboard/google/guado/mainboard.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <smbios.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "onboard.h" + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +static void mainboard_init(device_t dev) +{ + lan_init(); +} + +// mainboard_enable is executed as first thing after +// enumerate_buses(). + +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; + diff --git a/src/mainboard/google/guado/onboard.h b/src/mainboard/google/guado/onboard.h new file mode 100644 index 0000000..783c44a --- /dev/null +++ b/src/mainboard/google/guado/onboard.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#ifndef __ACPI__ +void lan_init(void); +#endif + +/* defines for programming the MAC address */ +#define GUADO_NIC_VENDOR_ID 0x10EC +#define GUADO_NIC_DEVICE_ID 0x8168 + +/* 0x00: White LINK LED and Amber ACTIVE LED */ +#define GUADO_NIC_LED_MODE 0x00 + +/* NIC wake is GPIO 8 */ +#define GUADO_NIC_WAKE_GPIO 8 + +/* WLAN wake is GPIO 10 */ +#define GUADO_WLAN_WAKE_GPIO 10 + +/* IT8772F defs */ +#define IT8772F_BASE 0x2e +#define IT8772F_SERIAL_DEV PNP_DEV(IT8772F_BASE, IT8772F_SP1) +#define IT8772F_GPIO_DEV PNP_DEV(IT8772F_BASE, IT8772F_GPIO) +#define IT8772F_DUMMY_DEV PNP_DEV(IT8772F_BASE, 0) + +#endif diff --git a/src/mainboard/google/guado/pei_data.c b/src/mainboard/google/guado/pei_data.c new file mode 100644 index 0000000..1b5ea51 --- /dev/null +++ b/src/mainboard/google/guado/pei_data.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + pei_data->ec_present = 0; + + /* P0: VP8 */ + pei_data_usb2_port(pei_data, 0, 0x0064, 1, 0, + USB_PORT_MINI_PCIE); + /* P1: Port A, CN22 */ + pei_data_usb2_port(pei_data, 1, 0x0040, 1, 0, + USB_PORT_INTERNAL); + /* P2: Port B, CN23 */ + pei_data_usb2_port(pei_data, 2, 0x0040, 1, 1, + USB_PORT_INTERNAL); + /* P3: WLAN */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_MINI_PCIE); + /* P4: Port C, CN25 */ + pei_data_usb2_port(pei_data, 4, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P5: Port D, CN25 */ + pei_data_usb2_port(pei_data, 5, 0x0040, 1, 2, + USB_PORT_INTERNAL); + /* P6: Card Reader */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: EMPTY */ + pei_data_usb2_port(pei_data, 7, 0x0000, 0, 0, + USB_PORT_SKIP); + + /* P1: CN22 */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: CN23 */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: CN25 */ + pei_data_usb3_port(pei_data, 2, 1, 2, 0); + /* P4: CN25 */ + pei_data_usb3_port(pei_data, 3, 1, 2, 0); +} diff --git a/src/mainboard/google/guado/romstage.c b/src/mainboard/google/guado/romstage.c new file mode 100644 index 0000000..24acc80 --- /dev/null +++ b/src/mainboard/google/guado/romstage.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/pei_wrapper.h> +#include <soc/romstage.h> +#include <mainboard/google/guado/spd/spd.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> +#include "gpio.h" +#include "onboard.h" + + +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data pei_data; + + post_code(0x32); + + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); + + /* Fill out PEI DATA */ + memset(&pei_data, 0, sizeof(pei_data)); + mainboard_fill_pei_data(&pei_data); + mainboard_fill_spd_data(&pei_data); + rp->pei_data = &pei_data; + + /* Call into the real romstage main with this board's attributes. */ + romstage_common(rp); +} + +void mainboard_pre_console_init(void) +{ + /* Early SuperIO setup */ + ite_kill_watchdog(IT8772F_GPIO_DEV); + it8772f_ac_resume_southbridge(IT8772F_DUMMY_DEV); + ite_enable_serial(IT8772F_SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Turn On GPIO10.LED */ + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, + 0x01 /* output */, 0x01 /* 1=Simple IO function */, + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + +} diff --git a/src/mainboard/google/guado/smihandler.c b/src/mainboard/google/guado/smihandler.c new file mode 100644 index 0000000..9fe9dfa --- /dev/null +++ b/src/mainboard/google/guado/smihandler.c @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <elog.h> +#include <ec/google/chromeec/ec.h> +#include <soc/gpio.h> +#include <soc/iomap.h> +#include <soc/nvs.h> +#include <soc/pm.h> +#include <soc/smm.h> +#include <superio/ite/it8772f/it8772f.h> +#include "onboard.h" + + +int mainboard_io_trap_handler(int smif) +{ + switch (smif) { + case 0x99: + printk(BIOS_DEBUG, "Sample\n"); + smm_get_gnvs()->smif = 0; + break; + default: + return 0; + } + + /* On success, the IO Trap Handler returns 0 + * On failure, the IO Trap Handler returns a value != 0 + * + * For now, we force the return value to 0 and log all traps to + * see what's going on. + */ + return 1; +} + +/* gpi_sts is GPIO 47:32 */ +void mainboard_smi_gpi(u32 gpi_sts) +{ +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x01 /* polarity */, 0x01 /* 1=pullup */, + 0x01 /* output */, 0x00, /* 0=Alternate function */ + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + case 5: + it8772f_gpio_led(IT8772F_GPIO_DEV, 1 /* set */, 0x01 /* select */, + 0x00 /* polarity: non-inverting */, 0x00 /* 0=pulldown */, + 0x01 /* output */, 0x01 /* 1=Simple IO function */, + SIO_GPIO_BLINK_GPIO10, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); + break; + default: + break; + } + return; +} + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_ACPI_ENABLE: + break; + case APM_CNT_ACPI_DISABLE: + break; + } + return 0; +} diff --git a/src/mainboard/google/guado/spd/Makefile.inc b/src/mainboard/google/guado/spd/Makefile.inc new file mode 100644 index 0000000..275d983 --- /dev/null +++ b/src/mainboard/google/guado/spd/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c diff --git a/src/mainboard/google/guado/spd/spd.c b/src/mainboard/google/guado/spd/spd.c new file mode 100644 index 0000000..bfbebf5 --- /dev/null +++ b/src/mainboard/google/guado/spd/spd.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <soc/gpio.h> +#include <soc/pei_data.h> +#include <soc/romstage.h> +#include <mainboard/google/guado/spd/spd.h> + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + pei_data->spd_addresses[0] = 0xa0; + pei_data->spd_addresses[1] = 0x00; + pei_data->spd_addresses[2] = 0xa4; + pei_data->spd_addresses[3] = 0x00; + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + // Enable 2x refresh mode + pei_data->ddr_refresh_2x = 1; + pei_data->dq_pins_interleaved = 1; +} diff --git a/src/mainboard/google/guado/spd/spd.h b/src/mainboard/google/guado/spd/spd.h new file mode 100644 index 0000000..02709cd --- /dev/null +++ b/src/mainboard/google/guado/spd/spd.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif diff --git a/src/mainboard/google/guado/thermal.h b/src/mainboard/google/guado/thermal.h new file mode 100644 index 0000000..685b988 --- /dev/null +++ b/src/mainboard/google/guado/thermal.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +#define TEMPERATURE_SENSOR_ID 0 /* PECI */ + +/* Fan is OFF */ +#define FAN4_THRESHOLD_OFF 0 +#define FAN4_THRESHOLD_ON 0 +#define FAN4_PWM 0x00 + +/* Fan is at LOW speed */ +#define FAN3_THRESHOLD_OFF 40 +#define FAN3_THRESHOLD_ON 50 +#define FAN3_PWM 0x55 + +/* Fan is at MEDIUM speed */ +#define FAN2_THRESHOLD_OFF 55 +#define FAN2_THRESHOLD_ON 67 +#define FAN2_PWM 0xa6 + +/* Fan is at HIGH speed */ +#define FAN1_THRESHOLD_OFF 65 +#define FAN1_THRESHOLD_ON 70 +#define FAN1_PWM 0xc0 + +/* Fan is at FULL speed */ +#define FAN0_THRESHOLD_OFF 90 +#define FAN0_THRESHOLD_ON 100 +#define FAN0_PWM 0xff + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif

1 0

Patch set updated for coreboot: IT8772F: Add switch to enable HWM(Hardware Monitor)
by Matt DeVillier 27 Dec '15

27 Dec '15

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12798 -gerrit commit 3d8c2f806433f17c04da5fab7aa02b6f3e363010 Author: Ted Kuo <tedkuo(a)ami.com.tw> Date: Wed Mar 18 10:42:22 2015 +0800 IT8772F: Add switch to enable HWM(Hardware Monitor) Setup External Temperature to read via thermal diode/resistor into TMPINx register by setting thermal_mode switch. BUG=none TEST=Compiled, verified Signed-off-by: Ted Kuo <tedkuo(a)ami.com.tw> Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034 Reviewed-on: https://chromium-review.googlesource.com/260545 Reviewed-by: Shawn N <shawnn(a)chromium.org> Commit-Queue: Ted Kuo <tedkuo(a)ami.com.tw> Tested-by: Ted Kuo <tedkuo(a)ami.com.tw> (cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a) Reviewed-on: https://chromium-review.googlesource.com/262340 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/superio/ite/it8772f/chip.h | 7 +++++++ src/superio/ite/it8772f/it8772f.h | 8 +++++++ src/superio/ite/it8772f/superio.c | 44 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/src/superio/ite/it8772f/chip.h b/src/superio/ite/it8772f/chip.h index 78ded22..0d80fb8 100644 --- a/src/superio/ite/it8772f/chip.h +++ b/src/superio/ite/it8772f/chip.h @@ -18,6 +18,7 @@ #define SUPERIO_ITE_IT8772F_CHIP_H #include <device/device.h> +#include "it8772f.h" struct superio_ite_it8772f_config { /* GPIO SimpleIO register values via devicetree.cb */ @@ -37,6 +38,12 @@ struct superio_ite_it8772f_config { u8 peci_tmpin; /* + * Enable thermal mode on tmpinx. + */ + enum thermal_mode tmpin1_mode; + enum thermal_mode tmpin2_mode; + + /* * Enable a FAN for sofware control. */ u8 fan1_enable; diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 2c6c44b..209db25 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -17,6 +17,13 @@ #ifndef SUPERIO_ITE_IT8772F_H #define SUPERIO_ITE_IT8772F_H +/* Supported thermal mode on TMPINx */ +enum thermal_mode { + THERMAL_MODE_DISABLED = 0, + THERMAL_DIODE, + THERMAL_RESISTOR, +}; + #define IT8772F_BASE 0x2e #define IT8772F_FDC 0x00 /* Floppy disk controller */ @@ -28,6 +35,7 @@ #define IT8772F_IR 0x0a /* Consumer IR */ /* Environmental Controller interface */ +#define IT8772F_CONFIGURATION 0x00 #define IT8772F_INTERFACE_SELECT 0x0a #define IT8772F_INTERFACE_PSEUDO_EOC (1 << 7) #define IT8772F_INTERFACE_SMB_ENABLE (1 << 6) diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 6c6a503..09684ef 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -16,6 +16,7 @@ #include <device/device.h> #include <device/pnp.h> +#include <console/console.h> #include <pc80/keyboard.h> #include <arch/io.h> #include <delay.h> @@ -97,6 +98,43 @@ static void it8772f_enable_peci(struct resource *res, int tmpin) } /* + * Setup External Temperature to read via thermal diode/resistor + * into TMPINx register + */ +static void it8772f_enable_tmpin(struct resource *res, int tmpin, + enum thermal_mode mode) +{ + u8 reg; + + if (tmpin != 1 && tmpin != 2) + return; + + reg = it8772f_envc_read(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE); + + switch (mode) { + case THERMAL_DIODE: + /* Thermal Diode Mode */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + reg | tmpin); + break; + case THERMAL_RESISTOR: + /* Thermal Resistor Mode */ + it8772f_envc_write(res, IT8772F_ADC_TEMP_CHANNEL_ENABLE, + reg | (tmpin << 3)); + break; + default: + printk(BIOS_ERR, "Unsupported thermal mode 0x%x on TMPIN%d\n", + mode, tmpin); + return; + } + + reg = it8772f_envc_read(res, IT8772F_CONFIGURATION); + + /* Enable the startup of monitoring operation */ + it8772f_envc_write(res, IT8772F_CONFIGURATION, reg | 0x01); +} + +/* * Setup a FAN PWM interface for software control */ static void it8772f_enable_fan(struct resource *res, int fan) @@ -160,6 +198,12 @@ static void it8772f_init(struct device *dev) /* Enable PECI if configured */ it8772f_enable_peci(res, conf->peci_tmpin); + /* Enable HWM if configured */ + if (conf->tmpin1_mode != THERMAL_MODE_DISABLED) + it8772f_enable_tmpin(res, 1, conf->tmpin1_mode); + if (conf->tmpin2_mode != THERMAL_MODE_DISABLED) + it8772f_enable_tmpin(res, 2, conf->tmpin2_mode); + /* Enable FANx if configured */ if (conf->fan1_enable) it8772f_enable_fan(res, 1);

1 0

New patch to review for coreboot: Makefile.inc: Fmaptool build fixes
by Martin Roth 27 Dec '15

27 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12806 -gerrit commit 4abefc8320bf5cb0c56bde0a015a5b64a6896b3b Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Dec 26 17:02:41 2015 -0700 Makefile.inc: Fmaptool build fixes - make sure CONFIG_CBFS_SIZE is lowercase for fmaptool. - Regenerate the fmap.fmd file when config.h changes. - Print the fmaptool step when doing the build. Change-Id: Ib518ed469d9e39eb41c81f7b19480c7789067d2d Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- Makefile.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 345a28a..06dea87 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -659,7 +659,7 @@ FMAP_ROM_SIZE := $(CONFIG_ROM_SIZE) # entire "BIOS" region (everything directly of concern to the host system) # relative to ROM_BASE FMAP_BIOS_BASE := $(call int-subtract, $(CONFIG_ROM_SIZE) $(CONFIG_CBFS_SIZE)) -FMAP_BIOS_SIZE := $(CONFIG_CBFS_SIZE) +FMAP_BIOS_SIZE := $(shell echo $(CONFIG_CBFS_SIZE) | tr A-F a-f) # position and size of flashmap, relative to BIOS_BASE FMAP_FMAP_BASE := 0 FMAP_FMAP_SIZE := 0x100 @@ -683,7 +683,7 @@ FMAP_CBFS_BASE := $(call int-add,$(FMAP_FMAP_BASE) $(FMAP_FMAP_SIZE)) FMAP_CBFS_SIZE := $(call int-subtract,$(FMAP_BIOS_SIZE) $(FMAP_CBFS_BASE)) endif -$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) +$(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(obj)/config.h sed -e "s,##ROM_BASE##,$(FMAP_ROM_ADDR)," \ -e "s,##ROM_SIZE##,$(FMAP_ROM_SIZE)," \ -e "s,##BIOS_BASE##,$(FMAP_BIOS_BASE)," \ @@ -695,7 +695,7 @@ $(obj)/fmap.fmd: $(top)/Makefile.inc $(DEFAULT_FLASHMAP) $(DEFAULT_FLASHMAP) > $@.tmp mv $@.tmp $@ else -$(obj)/fmap.fmd: $(CONFIG_FMDFILE) +$(obj)/fmap.fmd: $(CONFIG_FMDFILE) $(obj)/config.h cp $< $@ endif @@ -703,6 +703,7 @@ endif $(obj)/fmap.h: $(obj)/fmap.fmap $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/fmap.h $< $@" $(FMAPTOOL) -h $(obj)/fmap.h $< $@ $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap

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New patch to review for coreboot: Kconfig: move fmap description file prompt into general setup
by Martin Roth 27 Dec '15

27 Dec '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12805 -gerrit commit 77d7408df61927dea0957cb8e88c42de0dc428a4 Author: Martin Roth <gaumless(a)gmail.com> Date: Sat Dec 26 16:51:16 2015 -0700 Kconfig: move fmap description file prompt into general setup Split up the prompt and setting the default so that the prompt can go in the general setup menu but still have the default set in the mainboard Kconfig files. Change-Id: I52fba5ced869d51d10065f8c9ebd258d3a1d4156 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/Kconfig | 21 +++++++++++++-------- 1 file changed, 13 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 38cf855..6069d42 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -347,6 +347,14 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. +# default is set at the end of the file so it can be overriden in the maiboards +config FMDFILE + string "fmap description file in fmd format" + help + The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, + but in some cases more complex setups are required. + When an fmd is specified, it overrides the default format. + endmenu source "src/acpi/Kconfig" @@ -376,14 +384,6 @@ config CBFS_SIZE endmenu -config FMDFILE - string "fmap description file in fmd format" - default "" - help - The build system creates a default FMAP from ROM_SIZE and CBFS_SIZE, - but in some cases more complex setups are required. - When an fmd is specified, it overrides the default format. - config SYSTEM_TYPE_LAPTOP default n bool @@ -1153,3 +1153,8 @@ config MAX_REBOOT_CNT Internal option that sets the maximum number of bootblock executions allowed with the normal image enabled before assuming the normal image is defective and switching to the fallback image. + +# Set defaults at the end so that the prompts can go where we want them +config FMDFILE + string + default ""

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coreboot-gerrit December 2015