coreboot-gerrit December 2015

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Patch set updated for coreboot: commonlib: Add function to hash contents of a CBFS region.
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12786 -gerrit commit 75cd065dfd47f6a3adfd8aaf982533447804c06e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 15 15:57:11 2015 -0600 commonlib: Add function to hash contents of a CBFS region. Provide a common routine to hash the contents of a cbfs region. The cbfs region is hashed in the following order: 1. potential cbfs header at offset 0 2. potential cbfs header retlative offset at cbfs size - 4 3. For each file the metadata of the file. 4. For each non-empty file the data of the file. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized in chromeos cros_bundle_firmware as well as at runtime during vboot verification on glados. Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- Makefile.inc | 2 + src/commonlib/cbfs.c | 158 +++++++++++++++++++++++++++- src/commonlib/include/commonlib/cbfs.h | 12 +++ src/vendorcode/amd/pi/Makefile.inc | 1 + src/vendorcode/google/chromeos/Makefile.inc | 2 - 5 files changed, 168 insertions(+), 7 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 345a28a..18cc23e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -301,6 +301,8 @@ endif CPPFLAGS_common := -Isrc -Isrc/include -Isrc/commonlib/include -I$(obj) CPPFLAGS_common += -Isrc/device/oprom/include +VB_SOURCE ?= 3rdparty/vboot +CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include CPPFLAGS_common += -include $(src)/include/kconfig.h CFLAGS_common += -pipe -g -nostdinc diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c index 06d31ed..56faf28 100644 --- a/src/commonlib/cbfs.c +++ b/src/commonlib/cbfs.c @@ -108,6 +108,19 @@ int cbfs_for_each_file(const struct region_device *cbfs, return -1; } +static int cbfsf_file_type(struct cbfsf *fh, uint32_t *ftype) +{ + const size_t sz = sizeof(*ftype); + + if (rdev_readat(&fh->metadata, ftype, + offsetof(struct cbfs_file, type), sz) != sz) + return -1; + + *ftype = read_be32(ftype); + + return 0; +} + int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, const char *name, uint32_t *type) { @@ -148,13 +161,9 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, if (type != NULL) { uint32_t ftype; - if (rdev_readat(&fh->metadata, &ftype, - offsetof(struct cbfs_file, type), - sizeof(ftype)) != sizeof(ftype)) + if (cbfsf_file_type(fh, &ftype)) break; - ftype = read_be32(&ftype); - if (*type != ftype) { DEBUG(" Unmatched type %x at %zx\n", ftype, rdev_relative_offset(cbfs, @@ -174,3 +183,142 @@ int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, LOG("'%s' not found.\n", name); return -1; } + +static int cbfs_extend_hash_buffer(struct vb2_digest_context *ctx, + void *buf, size_t sz) +{ + return vb2_digest_extend(ctx, buf, sz); +} + +static int cbfs_extend_hash(struct vb2_digest_context *ctx, + const struct region_device *rdev) +{ + uint8_t buffer[1024]; + size_t sz_left; + size_t offset; + + sz_left = region_device_sz(rdev); + offset = 0; + + while (sz_left) { + int rv; + size_t block_sz = MIN(sz_left, sizeof(buffer)); + + if (rdev_readat(rdev, buffer, offset, block_sz) != block_sz) + return VB2_ERROR_UNKNOWN; + + rv = cbfs_extend_hash_buffer(ctx, buffer, block_sz); + + if (rv) + return rv; + + sz_left -= block_sz; + offset += block_sz; + } + + return VB2_SUCCESS; +} + +/* Include offsets of child regions within the parent into the hash. */ +static int cbfs_extend_hash_with_offset(struct vb2_digest_context *ctx, + const struct region_device *p, + const struct region_device *c) +{ + int32_t soffset; + int rv; + + soffset = rdev_relative_offset(p, c); + + if (soffset < 0) + return VB2_ERROR_UNKNOWN; + + /* All offsets in big endian format. */ + write_be32(&soffset, soffset); + + rv = cbfs_extend_hash_buffer(ctx, &soffset, sizeof(soffset)); + + if (rv) + return rv; + + return cbfs_extend_hash(ctx, c); +} + +/* Hash in the potential CBFS header sitting at the beginning of the CBFS + * region as well as relative offset at the end. */ +static int cbfs_extend_hash_master_header(struct vb2_digest_context *ctx, + const struct region_device *cbfs) +{ + struct region_device rdev; + int rv; + + if (rdev_chain(&rdev, cbfs, 0, sizeof(struct cbfs_header))) + return VB2_ERROR_UNKNOWN; + + rv = cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); + + if (rv) + return rv; + + /* Include potential relative offset at end of region. */ + if (rdev_chain(&rdev, cbfs, region_device_sz(cbfs) - sizeof(int32_t), + sizeof(int32_t))) + return VB2_ERROR_UNKNOWN; + + return cbfs_extend_hash_with_offset(ctx, cbfs, &rdev); +} + +int cbfs_vb2_hash_contents(const struct region_device *cbfs, + enum vb2_hash_algorithm hash_alg, void *digest, + size_t digest_sz) +{ + struct vb2_digest_context ctx; + int rv; + struct cbfsf f; + struct cbfsf *prev; + struct cbfsf *fh; + + rv = vb2_digest_init(&ctx, hash_alg); + + if (rv) + return rv; + + rv = cbfs_extend_hash_master_header(&ctx, cbfs); + if (rv) + return rv; + + prev = NULL; + fh = &f; + + while (1) { + uint32_t ftype; + + rv = cbfs_for_each_file(cbfs, prev, fh); + prev = fh; + + if (rv < 0) + return VB2_ERROR_UNKNOWN; + + /* End of CBFS. */ + if (rv > 0) + break; + + rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->metadata); + + if (rv) + return rv; + + /* Include data contents in hash if file is non-empty. */ + if (cbfsf_file_type(fh, &ftype)) + return VB2_ERROR_UNKNOWN; + + if (ftype == CBFS_TYPE_DELETED || ftype == CBFS_TYPE_DELETED2) + continue; + + rv = cbfs_extend_hash_with_offset(&ctx, cbfs, &fh->data); + + if (rv) + return rv; + } + + return vb2_digest_finalize(&ctx, digest, digest_sz); +} diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h index b0a468c..e1019c6 100644 --- a/src/commonlib/include/commonlib/cbfs.h +++ b/src/commonlib/include/commonlib/cbfs.h @@ -18,6 +18,9 @@ #include <commonlib/cbfs_serialized.h> #include <commonlib/region.h> +/* TODO: remove me! This is for vboot_handoff.c's benefit. */ +#define NEED_VB20_INTERNALS +#include <vb2_api.h> /* Object representing cbfs files. */ struct cbfsf { @@ -52,4 +55,13 @@ static inline void cbfs_file_metadata(struct region_device *metadata, int cbfs_for_each_file(const struct region_device *cbfs, const struct cbfsf *prev, struct cbfsf *fh); +/* + * Perform the vb2 hash over the CBFS region skipping empty file contents. + * Caller is responsiblef or providing the hash algorithm as well as storage + * for the final digest. Return 0 on success or non-zero on error. + */ +int cbfs_vb2_hash_contents(const struct region_device *cbfs, + enum vb2_hash_algorithm hash_alg, void *digest, + size_t digest_sz); + #endif diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index bb383b9..79d6171 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -62,6 +62,7 @@ AGESA_INC += -I$(src)/southbridge/amd/pi/hudson AGESA_INC += -I$(src)/arch/x86/include AGESA_INC += -I$(src)/include AGESA_INC += -I$(src)/commonlib/include +AGESA_INC += -I$(VB_SOURCE)/firmware/include AGESA_CFLAGS += -march=amdfam10 -mno-3dnow -fno-zero-initialized-in-bss -fno-strict-aliasing CFLAGS_x86_32 += $(AGESA_CFLAGS) diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index ef84798..00fcd2f 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -49,6 +49,4 @@ else CFLAGS_common += -DMOCK_TPM=0 endif -VB_SOURCE ?= 3rdparty/vboot subdirs-$(CONFIG_VBOOT_VERIFY_FIRMWARE) += vboot2 -CPPFLAGS_common += -I$(VB_SOURCE)/firmware/include

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Patch set updated for coreboot: cbfstool: Use buffer over offset/size pair for cbfs_copy_instance
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12787 -gerrit commit 748bfeaf1ce71ab14366e77d338a2e00fd1c5f08 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 20 19:22:50 2015 +0100 cbfstool: Use buffer over offset/size pair for cbfs_copy_instance This allows adding support for FMAP based cbfstool copy more easily. BUG=chromium:445938 BRANCH=tot TEST=bundle_firmware still works Change-Id: I72e7bc4da7d27853e324400f76f86136e3d8726e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/cbfstool/cbfs_image.c | 41 +++++++++++++---------------------------- util/cbfstool/cbfs_image.h | 3 +-- util/cbfstool/cbfstool.c | 33 ++++++++++++++++++++------------- 3 files changed, 34 insertions(+), 43 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 1cfe90d..25aafe9 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -387,8 +387,7 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in, return 1; } -int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, - size_t copy_size) +int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst) { assert(image); if (!cbfs_is_legacy_cbfs(image)) @@ -399,37 +398,23 @@ int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, size_t align, entry_offset; ssize_t last_entry_size; - size_t cbfs_offset, cbfs_end; - size_t copy_end = copy_offset + copy_size; + size_t copy_end = buffer_size(dst); align = image->header.align; - cbfs_offset = image->header.offset; - cbfs_end = image->header.romsize; - - if (copy_end > image->buffer.size) { - ERROR("Copy offset out of range: [%zx:%zx)\n", - copy_offset, copy_end); - return 1; - } - - /* Range check requested copy region with source cbfs. */ - if ((copy_offset >= cbfs_offset && copy_offset < cbfs_end) || - (copy_end >= cbfs_offset && copy_end <= cbfs_end)) { - ERROR("New image would overlap old one.\n"); - return 1; - } - /* This will work, let's create a copy. */ - copy_header = (struct cbfs_header *)(image->buffer.data + copy_offset); + copy_header = (struct cbfs_header *)buffer_get(dst); cbfs_put_header(copy_header, &image->header); copy_header->bootblocksize = 0; - /* Romsize is a misnomer. It's the absolute limit of cbfs content.*/ - copy_header->romsize = htonl(copy_end); - entry_offset = align_up(copy_offset + sizeof(*copy_header), align); - copy_header->offset = htonl(entry_offset); - dst_entry = (struct cbfs_file *)(image->buffer.data + entry_offset); + /* FIXME: romsize and offset have a full-flash interpretation even + * though they don't need to and should be region-relative (where + * region is sufficiently specified by the master header pointer. + * But that's for a later change. */ + copy_header->romsize = htonl(dst->offset + buffer_size(dst)); + entry_offset = align_up(sizeof(*copy_header), align); + copy_header->offset = htonl(dst->offset + entry_offset); + dst_entry = (struct cbfs_file *)(buffer_get(dst) + entry_offset); /* Copy non-empty files */ for (src_entry = cbfs_find_first_entry(image); @@ -446,7 +431,7 @@ int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, dst_entry = (struct cbfs_file *)( (uintptr_t)dst_entry + align_up(entry_size, align)); - if ((size_t)((char *)dst_entry - image->buffer.data) >= + if ((size_t)((void *)dst_entry - buffer_get(dst)) >= copy_end) { ERROR("Ran out of room in copy region.\n"); return 1; @@ -454,7 +439,7 @@ int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, } /* Last entry size is all the room above it. */ - last_entry_size = copy_end - ((char *)dst_entry - image->buffer.data) + last_entry_size = copy_end - ((void *)dst_entry - buffer_get(dst)) - cbfs_calculate_file_header_size(""); if (last_entry_size < 0) diff --git a/util/cbfstool/cbfs_image.h b/util/cbfstool/cbfs_image.h index 195494c..00adcc8 100644 --- a/util/cbfstool/cbfs_image.h +++ b/util/cbfstool/cbfs_image.h @@ -74,8 +74,7 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in, /* Create a duplicate CBFS image. Returns 0 on success, otherwise non-zero. * Will not succeed on new-style images without a master header. */ -int cbfs_copy_instance(struct cbfs_image *image, size_t copy_offset, - size_t copy_size); +int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst); /* Releases the CBFS image. Returns 0 on success, otherwise non-zero. */ int cbfs_image_delete(struct cbfs_image *image); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 2529296..c9a9564 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -917,27 +917,34 @@ static int cbfs_update_fit(void) static int cbfs_copy(void) { - if (!param.copyoffset_assigned) { - ERROR("You need to specify -D/--copy-offset.\n"); - return 1; - } - - if (!param.size) { - ERROR("You need to specify -s/--size.\n"); - return 1; - } + /* always a valid source region */ + struct cbfs_image src_image; - struct cbfs_image image; - if (cbfs_image_from_buffer(&image, param.image_region, + if (cbfs_image_from_buffer(&src_image, param.image_region, param.headeroffset)) return 1; - if (!cbfs_is_legacy_cbfs(&image)) { + struct buffer dst_buffer; + + if (cbfs_is_legacy_cbfs(&src_image)) { + if (!param.copyoffset_assigned) { + ERROR("You need to specify -D/--copy-offset.\n"); + return 1; + } + + if (!param.size) { + ERROR("You need to specify -s/--size.\n"); + return 1; + } + + buffer_splice(&dst_buffer, param.image_region, + param.copyoffset, param.size); + } else { ERROR("This operation is only valid on legacy images having CBFS master headers\n"); return 1; } - return cbfs_copy_instance(&image, param.copyoffset, param.size); + return cbfs_copy_instance(&src_image, &dst_buffer); } static const struct command commands[] = {

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Patch set updated for coreboot: cbfstool: Adapt "cbfstool copy" to only use fmap regions.
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12788 -gerrit commit fa7d72307cc40b9c08daa77ce6000d80d0525f51 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 20 21:48:18 2015 +0100 cbfstool: Adapt "cbfstool copy" to only use fmap regions. These need to go together, so the commit became a bit larger than typial. - Add an option -R for the copy source fmap region. Use: cbfstool copy -r target-region -R source-region. - Don't generate a CBFS master header because for fmap regions, we assume that the region starts with a file header. Use cbfstool add-master-header to add it afterwards, if necessary. - Don't copy files of type "cbfs master header" (which are what cbfstool add-master-header creates) - Leave room for the master header pointer - Remove -D command line option as it's no longer used. BUG=chromium:445938 BRANCH=none TEST=Manual test on image and integration test w/ bundle_firmware changes. CQ-DEPEND=CL:313770,CL:313771 Change-Id: I2a11cda42caee96aa763f162b5f3bc11bb7992f9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Signed-off-by: Patrick Georgi <adurbin(a)chromium.org> --- util/cbfstool/cbfs_image.c | 29 ++++++++------------------ util/cbfstool/cbfstool.c | 52 ++++++++++++++++++---------------------------- 2 files changed, 29 insertions(+), 52 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 25aafe9..3820c40 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -390,31 +390,16 @@ int cbfs_image_from_buffer(struct cbfs_image *out, struct buffer *in, int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst) { assert(image); - if (!cbfs_is_legacy_cbfs(image)) - return -1; struct cbfs_file *src_entry, *dst_entry; - struct cbfs_header *copy_header; - size_t align, entry_offset; + size_t align; ssize_t last_entry_size; size_t copy_end = buffer_size(dst); - align = image->header.align; - - /* This will work, let's create a copy. */ - copy_header = (struct cbfs_header *)buffer_get(dst); - cbfs_put_header(copy_header, &image->header); + align = CBFS_ENTRY_ALIGNMENT; - copy_header->bootblocksize = 0; - /* FIXME: romsize and offset have a full-flash interpretation even - * though they don't need to and should be region-relative (where - * region is sufficiently specified by the master header pointer. - * But that's for a later change. */ - copy_header->romsize = htonl(dst->offset + buffer_size(dst)); - entry_offset = align_up(sizeof(*copy_header), align); - copy_header->offset = htonl(dst->offset + entry_offset); - dst_entry = (struct cbfs_file *)(buffer_get(dst) + entry_offset); + dst_entry = (struct cbfs_file *)buffer_get(dst); /* Copy non-empty files */ for (src_entry = cbfs_find_first_entry(image); @@ -423,6 +408,7 @@ int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst) size_t entry_size; if ((src_entry->type == htonl(CBFS_COMPONENT_NULL)) || + (src_entry->type == htonl(CBFS_COMPONENT_CBFSHEADER)) || (src_entry->type == htonl(CBFS_COMPONENT_DELETED))) continue; @@ -438,9 +424,12 @@ int cbfs_copy_instance(struct cbfs_image *image, struct buffer *dst) } } - /* Last entry size is all the room above it. */ + /* Last entry size is all the room above it, except for top 4 bytes + * which may be used by the master header pointer. This messes with + * the ability to stash something "top-aligned" into the region, but + * keeps things simpler. */ last_entry_size = copy_end - ((void *)dst_entry - buffer_get(dst)) - - cbfs_calculate_file_header_size(""); + - cbfs_calculate_file_header_size("") - sizeof(int32_t); if (last_entry_size < 0) WARN("No room to create the last entry!\n") diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index c9a9564..f00aa30 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -49,6 +49,7 @@ static struct param { const char *filename; const char *fmap; const char *region_name; + const char *source_region; const char *bootblock; const char *ignore_section; uint64_t u64val; @@ -56,8 +57,6 @@ static struct param { uint32_t baseaddress; uint32_t baseaddress_assigned; uint32_t loadaddress; - uint32_t copyoffset; - uint32_t copyoffset_assigned; uint32_t headeroffset; uint32_t headeroffset_assigned; uint32_t entrypoint; @@ -917,34 +916,25 @@ static int cbfs_update_fit(void) static int cbfs_copy(void) { - /* always a valid source region */ struct cbfs_image src_image; + struct buffer src_buf; - if (cbfs_image_from_buffer(&src_image, param.image_region, - param.headeroffset)) + if (!param.source_region) { + ERROR("You need to specify -R/--source-region.\n"); return 1; + } - struct buffer dst_buffer; - - if (cbfs_is_legacy_cbfs(&src_image)) { - if (!param.copyoffset_assigned) { - ERROR("You need to specify -D/--copy-offset.\n"); - return 1; - } - - if (!param.size) { - ERROR("You need to specify -s/--size.\n"); - return 1; - } - - buffer_splice(&dst_buffer, param.image_region, - param.copyoffset, param.size); - } else { - ERROR("This operation is only valid on legacy images having CBFS master headers\n"); + /* Obtain the source region and convert it to a cbfs_image. */ + if (!partitioned_file_read_region(&src_buf, param.image_file, + param.source_region)) { + ERROR("Region not found in image: %s\n", param.source_region); return 1; } - return cbfs_copy_instance(&src_image, &dst_buffer); + if (cbfs_image_from_buffer(&src_image, &src_buf, param.headeroffset)) + return 1; + + return cbfs_copy_instance(&src_image, param.image_region); } static const struct command commands[] = { @@ -955,7 +945,7 @@ static const struct command commands[] = { {"add-stage", "a:H:r:f:n:t:c:b:P:S:yvA:h?", cbfs_add_stage, true, true}, {"add-int", "H:r:i:n:b:vh?", cbfs_add_integer, true, true}, {"add-master-header", "H:r:vh?", cbfs_add_master_header, true, true}, - {"copy", "H:D:s:h?", cbfs_copy, true, true}, + {"copy", "r:R:h?", cbfs_copy, true, true}, {"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true}, {"extract", "H:r:m:n:f:vh?", cbfs_extract, true, false}, {"layout", "wvh?", cbfs_layout, false, false}, @@ -972,7 +962,6 @@ static struct option long_options[] = { {"bootblock", required_argument, 0, 'B' }, {"cmdline", required_argument, 0, 'C' }, {"compression", required_argument, 0, 'c' }, - {"copy-offset", required_argument, 0, 'D' }, {"empty-fits", required_argument, 0, 'x' }, {"entry-point", required_argument, 0, 'e' }, {"file", required_argument, 0, 'f' }, @@ -980,6 +969,7 @@ static struct option long_options[] = { {"fill-upward", no_argument, 0, 'u' }, {"flashmap", required_argument, 0, 'M' }, {"fmap-regions", required_argument, 0, 'r' }, + {"source-region", required_argument, 0, 'R' }, {"hash-algorithm",required_argument, 0, 'A' }, {"header-offset", required_argument, 0, 'H' }, {"help", no_argument, 0, 'h' }, @@ -1085,9 +1075,8 @@ static void usage(char *name) "Add a legacy CBFS master header\n" " remove [-r image,regions] -n NAME " "Remove a component\n" - " copy -D new_header_offset -s region size \\\n" - " [-H source header offset] " - "Create a copy (duplicate) cbfs instance*\n" + " copy -r image,regions -R source-region " + "Create a copy (duplicate) cbfs instance in fmap\n" " create -m ARCH -s size [-b bootblock offset] \\\n" " [-o CBFS offset] [-H header offset] [-B bootblock] " "Create a legacy ROM file with CBFS master header*\n" @@ -1216,6 +1205,9 @@ int main(int argc, char **argv) case 'r': param.region_name = optarg; break; + case 'R': + param.source_region = optarg; + break; case 'b': param.baseaddress = strtoul(optarg, NULL, 0); // baseaddress may be zero on non-x86, so we @@ -1246,10 +1238,6 @@ int main(int argc, char **argv) optarg, NULL, 0); param.headeroffset_assigned = 1; break; - case 'D': - param.copyoffset = strtoul(optarg, NULL, 0); - param.copyoffset_assigned = 1; - break; case 'a': param.alignment = strtoul(optarg, NULL, 0); break;

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Patch set updated for coreboot: cbfstool: keep cbfs master header pointer
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12789 -gerrit commit 6d518345aa4d1a48d90e47c0af1a4c99d504a9e7 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Nov 20 23:23:44 2015 +0100 cbfstool: keep cbfs master header pointer Adding new files overwrote the header with the empty file (ie 0xff), so carve out some space. BUG=chromium:445938 BRANCH=none TEST=none Change-Id: I91c292df381c2bac41c6cb9dda74dae99defd81d Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/cbfstool/cbfs_image.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 3820c40..2d7a6f0 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -523,6 +523,11 @@ static int cbfs_add_entry_at(struct cbfs_image *image, } len = addr_next - addr - min_entry_size; + /* keep space for master header pointer */ + if ((void *)entry + min_entry_size + len > buffer_get(&image->buffer) + + buffer_size(&image->buffer) - sizeof(int32_t)) { + len -= sizeof(int32_t); + } cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); if (verbose > 1) cbfs_print_entry_info(image, entry, stderr); return 0;

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Patch set updated for coreboot: cbfstool: Add 'hashcbfs' command to compute hash of CBFS region.
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12790 -gerrit commit 8769588ee017f7323e5e8fabfe38c6680abf00ff Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 15 18:00:30 2015 -0600 cbfstool: Add 'hashcbfs' command to compute hash of CBFS region. For the purposes of maintaining integrity of a CBFS allow one to hash a CBFS over a given region. The hash consists of all file metadata and non-empty file data. The resulting digest is saved to the requested destination region. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Integrated with glados chrome os build. vboot verification works using the same code to generate the hash in the tooling as well as at runtime on the board in question. Change-Id: Ib0d6bf668ffd6618f5f73e1217bdef404074dbfc Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/Makefile.inc | 8 +++++++ util/cbfstool/cbfs_hash.c | 33 ++++++++++++++++++++++++++++ util/cbfstool/cbfstool.c | 54 ++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 95 insertions(+) diff --git a/util/cbfstool/Makefile.inc b/util/cbfstool/Makefile.inc index 9633ca4..8e04411 100644 --- a/util/cbfstool/Makefile.inc +++ b/util/cbfstool/Makefile.inc @@ -2,10 +2,14 @@ cbfsobj := cbfsobj += cbfstool.o cbfsobj += common.o cbfsobj += compress.o +cbfsobj += cbfs.o +cbfsobj += cbfs_hash.o cbfsobj += cbfs_image.o cbfsobj += cbfs-mkstage.o cbfsobj += cbfs-mkpayload.o cbfsobj += elfheaders.o +cbfsobj += mem_pool.o +cbfsobj += region.o cbfsobj += rmodule.o cbfsobj += xdr.o cbfsobj += fit.o @@ -129,6 +133,10 @@ $(objutil)/cbfstool/LzmaEnc.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual # Tolerate vboot warnings $(objutil)/cbfstool/2sha_utility.o: TOOLCFLAGS += -Wno-sign-compare $(objutil)/cbfstool/2sha1.o: TOOLCFLAGS += -Wno-cast-qual +# Tolerate commonlib warnings +$(objutil)/cbfstool/region.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual +$(objutil)/cbfstool/cbfs.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual +$(objutil)/cbfstool/mem_pool.o: TOOLCFLAGS += -Wno-sign-compare -Wno-cast-qual $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_parser.h $(objutil)/cbfstool/fmd.o: $(objutil)/cbfstool/fmd_scanner.h diff --git a/util/cbfstool/cbfs_hash.c b/util/cbfstool/cbfs_hash.c new file mode 100644 index 0000000..332a59b --- /dev/null +++ b/util/cbfstool/cbfs_hash.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <commonlib/cbfs.h> +#include <commonlib/region.h> + +int cbfs_calculate_hash(void *cbfs, size_t cbfs_sz, + enum vb2_hash_algorithm hash_algo, + void *digest, size_t digest_sz); + +int cbfs_calculate_hash(void *cbfs, size_t cbfs_sz, + enum vb2_hash_algorithm hash_algo, + void *digest, size_t digest_sz) +{ + struct mem_region_device mdev; + + mem_region_device_init(&mdev, cbfs, cbfs_sz); + + return cbfs_vb2_hash_contents(&mdev.rdev, + hash_algo, digest, digest_sz); +} diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index f00aa30..2da4071 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -781,6 +781,57 @@ static int cbfs_print(void) return 0; } +/* Forward declared so there aren't type collisions with cbfstool proper + * and commonlib. */ +int cbfs_calculate_hash(void *cbfs, size_t cbfs_sz, + enum vb2_hash_algorithm hash_algo, + void *digest, size_t digest_sz); + +static int cbfs_hash(void) +{ + struct cbfs_image src_image; + struct buffer src_buf; + struct buffer *dst = param.image_region; + + if (param.hash == VB2_HASH_INVALID) { + ERROR("You need to specify -A/--hash-algorithm.\n"); + return 1; + } + + if (!param.source_region) { + ERROR("You need to specify -R/--source-region.\n"); + return 1; + } + + unsigned hash_size = widths_cbfs_hash[param.hash]; + if (hash_size == 0) + return 1; + + if (buffer_size(param.image_region) < hash_size) { + ERROR("Region '%s' size too small.\n", param.region_name) + return 1; + } + + /* Obtain the source region and convert it to a cbfs_image. */ + if (!partitioned_file_read_region(&src_buf, param.image_file, + param.source_region)) { + ERROR("Region not found in image: %s\n", param.source_region); + return 1; + } + + if (cbfs_image_from_buffer(&src_image, &src_buf, param.headeroffset)) + return 1; + + if (cbfs_calculate_hash(buffer_get(&src_image.buffer), + buffer_size(&src_image.buffer), + param.hash, buffer_get(dst), hash_size)) { + ERROR("Hash calculation failed.\n"); + return 1; + } + + return 0; +} + static int cbfs_extract(void) { if (!param.filename) { @@ -947,6 +998,7 @@ static const struct command commands[] = { {"add-master-header", "H:r:vh?", cbfs_add_master_header, true, true}, {"copy", "r:R:h?", cbfs_copy, true, true}, {"create", "M:r:s:B:b:H:o:m:vh?", cbfs_create, true, true}, + {"hashcbfs", "r:R:A:vh?", cbfs_hash, true, true}, {"extract", "H:r:m:n:f:vh?", cbfs_extract, true, false}, {"layout", "wvh?", cbfs_layout, false, false}, {"print", "H:r:vh?", cbfs_print, true, false}, @@ -1090,6 +1142,8 @@ static void usage(char *name) " print [-r image,regions] " "Show the contents of the ROM\n" " extract [-r image,regions] [-m ARCH] -n NAME -f FILE " + " hashcbfs -r image_region -R source-region " + "Hashes CBFS source-region and saves digest\n" "Extracts a raw payload from ROM\n" " write -r image,regions -f file [-u | -d] " "Write file into same-size [or larger] raw region\n"

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Patch set updated for coreboot: commonlib: Add common cbfs parsing logic to coreboot and cbfstool.
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12783 -gerrit commit f007dbd8739ec902abc4717d31be88a37e50c1f1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 15 13:33:51 2015 -0600 commonlib: Add common cbfs parsing logic to coreboot and cbfstool. To continue sharing more code between the tools and coreboot proper provide cbfs parsing logic in commonlib. A cbfs_for_each_file() function was added to allow one to act on each file found within a cbfs. cbfs_locate() was updated to use that logic. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/Makefile.inc | 6 ++ src/commonlib/cbfs.c | 176 +++++++++++++++++++++++++++++++++ src/commonlib/include/commonlib/cbfs.h | 55 +++++++++++ src/include/cbfs.h | 28 +----- src/lib/cbfs.c | 72 -------------- 5 files changed, 238 insertions(+), 99 deletions(-) diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index 929bf8e..19f9ba3 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -10,3 +10,9 @@ ramstage-y += region.c smm-y += region.c ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1_relocate.c + +bootblock-y += cbfs.c +verstage-y += cbfs.c +romstage-y += cbfs.c +ramstage-y += cbfs.c +smm-y += cbfs.c diff --git a/src/commonlib/cbfs.c b/src/commonlib/cbfs.c new file mode 100644 index 0000000..06d31ed --- /dev/null +++ b/src/commonlib/cbfs.c @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <commonlib/cbfs.h> +#include <commonlib/endian.h> +#include <commonlib/helpers.h> +#include <string.h> + +#if !defined(ERROR) +#define ERROR(x...) printk(BIOS_ERR, "CBFS: " x) +#endif +#if !defined(LOG) +#define LOG(x...) printk(BIOS_INFO, "CBFS: " x) +#endif +#if defined(IS_ENABLED) + +#if IS_ENABLED(CONFIG_DEBUG_CBFS) +#define DEBUG(x...) printk(BIOS_SPEW, "CBFS: " x) +#else +#define DEBUG(x...) +#endif + +#elif !defined(DEBUG) +#define DEBUG(x...) +#endif + +static size_t cbfs_next_offset(const struct region_device *cbfs, + const struct cbfsf *f) +{ + size_t offset; + + if (f == NULL) + return 0; + + /* The region_device objects store absolute offets over the whole + * region. Therefore a relative offset needs to be calculated. */ + offset = rdev_relative_offset(cbfs, &f->data); + offset += region_device_sz(&f->data); + + return ALIGN_UP(offset, CBFS_ALIGNMENT); +} + +static int cbfs_end(const struct region_device *cbfs, size_t offset) +{ + if (offset >= region_device_sz(cbfs)) + return 1; + + return 0; +} + +int cbfs_for_each_file(const struct region_device *cbfs, + const struct cbfsf *prev, struct cbfsf *fh) +{ + size_t offset; + + offset = cbfs_next_offset(cbfs, prev); + + /* Try to scan the entire cbfs region looking for file name. */ + while (1) { + struct cbfs_file file; + const size_t fsz = sizeof(file); + + DEBUG("Checking offset %zx\n", offset); + + /* End of region. */ + if (cbfs_end(cbfs, offset)) + return 1; + + /* Can't read file. Nothing else to do but bail out. */ + if (rdev_readat(cbfs, &file, offset, fsz) != fsz) + break; + + if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) { + offset++; + offset = ALIGN_UP(offset, CBFS_ALIGNMENT); + continue; + } + + file.len = read_be32(&file.len); + file.offset = read_be32(&file.offset); + + DEBUG("File @ offset %zx size %x\n", offset, file.len); + + /* Keep track of both the metadata and the data for the file. */ + if (rdev_chain(&fh->metadata, cbfs, offset, file.offset)) + break; + + if (rdev_chain(&fh->data, cbfs, offset + file.offset, file.len)) + break; + + /* Success. */ + return 0; + } + + return -1; +} + +int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, + const char *name, uint32_t *type) +{ + struct cbfsf *prev; + + LOG("Locating '%s'\n", name); + + prev = NULL; + + while (1) { + int ret; + char *fname; + int name_match; + const size_t fsz = sizeof(struct cbfs_file); + + ret = cbfs_for_each_file(cbfs, prev, fh); + prev = fh; + + /* Either failed to read or hit the end of the region. */ + if (ret < 0 || ret > 0) + break; + + fname = rdev_mmap(&fh->metadata, fsz, + region_device_sz(&fh->metadata) - fsz); + + if (fname == NULL) + break; + + name_match = !strcmp(fname, name); + rdev_munmap(&fh->metadata, fname); + + if (!name_match) { + DEBUG(" Unmatched '%s' at %zx\n", fname, + rdev_relative_offset(cbfs, &fh->metadata)); + continue; + } + + if (type != NULL) { + uint32_t ftype; + + if (rdev_readat(&fh->metadata, &ftype, + offsetof(struct cbfs_file, type), + sizeof(ftype)) != sizeof(ftype)) + break; + + ftype = read_be32(&ftype); + + if (*type != ftype) { + DEBUG(" Unmatched type %x at %zx\n", ftype, + rdev_relative_offset(cbfs, + &fh->metadata)); + continue; + } + } + + LOG("Found @ offset %zx size %zx\n", + rdev_relative_offset(cbfs, &fh->metadata), + region_device_sz(&fh->data)); + + /* Success. */ + return 0; + } + + LOG("'%s' not found.\n", name); + return -1; +} diff --git a/src/commonlib/include/commonlib/cbfs.h b/src/commonlib/include/commonlib/cbfs.h new file mode 100644 index 0000000..b0a468c --- /dev/null +++ b/src/commonlib/include/commonlib/cbfs.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _COMMONLIB_CBFS_H_ +#define _COMMONLIB_CBFS_H_ + +#include <commonlib/cbfs_serialized.h> +#include <commonlib/region.h> + +/* Object representing cbfs files. */ +struct cbfsf { + struct region_device metadata; + struct region_device data; +}; + +/* Locate file by name and optional type. Returns 0 on succcess else < 0 on + * error.*/ +int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, + const char *name, uint32_t *type); + +static inline void cbfs_file_data(struct region_device *data, + const struct cbfsf *file) +{ + rdev_chain(data, &file->data, 0, region_device_sz(&file->data)); +} + +static inline void cbfs_file_metadata(struct region_device *metadata, + const struct cbfsf *file) +{ + rdev_chain(metadata, &file->metadata, 0, + region_device_sz(&file->metadata)); +} + +/* + * Provide a handle to each cbfs file within a cbfs. The prev pointer represents + * the previous file (NULL on first invocation). The next object gets filled + * out with the next file. This returns < 0 on error, 0 on finding the next + * file, and > 0 at end of cbfs. + */ +int cbfs_for_each_file(const struct region_device *cbfs, + const struct cbfsf *prev, struct cbfsf *fh); + +#endif diff --git a/src/include/cbfs.h b/src/include/cbfs.h index 7848d6d..0d95387 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -16,19 +16,9 @@ #ifndef _CBFS_H_ #define _CBFS_H_ -#include <commonlib/cbfs_serialized.h> -#include <commonlib/region.h> +#include <commonlib/cbfs.h> #include <program_loading.h> -/* - * CBFS operations consist of the following concepts: - * - region_device for the boot media - * - cbfsd which is a descriptor for representing a cbfs instance - */ - -/* Object representing cbfs files. */ -struct cbfsf; - /*********************************************** * Perform CBFS operations on the boot device. * ***********************************************/ @@ -48,28 +38,12 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size); /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); -/* Locate file by name and optional type. Returns 0 on succcess else < 0 on - * error.*/ -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type); - /***************************************************************** * Support structures and functions. Direct field access should * * only be done by implementers of cbfs regions -- Not the above * * API. * *****************************************************************/ -struct cbfsf { - struct region_device metadata; - struct region_device data; -}; - -static inline void cbfs_file_data(struct region_device *data, - const struct cbfsf *file) -{ - rdev_chain(data, &file->data, 0, region_device_sz(&file->data)); -} - /* The cbfs_props struct describes the properties associated with a CBFS. */ struct cbfs_props { /* CBFS starts at the following offset within the boot region. */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index d68aa39..55a8536 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -68,78 +68,6 @@ void *cbfs_boot_map_with_leak(const char *name, uint32_t type, size_t *size) return rdev_mmap(&fh.data, 0, fsize); } -int cbfs_locate(struct cbfsf *fh, const struct region_device *cbfs, - const char *name, uint32_t *type) -{ - size_t offset = 0; - - LOG("Locating '%s'\n", name); - - /* Try to scan the entire cbfs region looking for file name. */ - while (1) { - struct cbfs_file file; - const size_t fsz = sizeof(file); - char *fname; - int name_match; - size_t datasz; - - DEBUG("Checking offset %zx\n", offset); - - /* Can't read file. Nothing else to do but bail out. */ - if (rdev_readat(cbfs, &file, offset, fsz) != fsz) - break; - - if (memcmp(file.magic, CBFS_FILE_MAGIC, sizeof(file.magic))) { - offset++; - offset = ALIGN_UP(offset, CBFS_ALIGNMENT); - continue; - } - - file.len = ntohl(file.len); - file.type = ntohl(file.type); - file.offset = ntohl(file.offset); - - /* See if names match. */ - fname = rdev_mmap(cbfs, offset + fsz, file.offset - fsz); - - if (fname == NULL) - break; - - name_match = !strcmp(fname, name); - rdev_munmap(cbfs, fname); - - if (!name_match) { - DEBUG(" Unmatched '%s' at %zx\n", fname, offset); - offset += file.offset + file.len; - offset = ALIGN_UP(offset, CBFS_ALIGNMENT); - continue; - } - - if (type != NULL && *type != file.type) { - DEBUG(" Unmatched type %x at %zx\n", file.type, offset); - offset += file.offset + file.len; - offset = ALIGN_UP(offset, CBFS_ALIGNMENT); - continue; - } - - LOG("Found @ offset %zx size %x\n", offset, file.len); - /* File and type match. Keep track of both the metadata and - * the data for the file. */ - if (rdev_chain(&fh->metadata, cbfs, offset, file.offset)) - break; - offset += file.offset; - datasz = file.len; - if (rdev_chain(&fh->data, cbfs, offset, datasz)) - break; - - /* Success. */ - return 0; - } - - LOG("'%s' not found.\n", name); - return -1; -} - static size_t inflate(void *src, void *dst) { if (ENV_BOOTBLOCK || ENV_VERSTAGE)

1 0

Patch set updated for coreboot: commonlib: Add function to compute relative offsets from two region_devices.
by Aaron Durbin 23 Dec '15

23 Dec '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12782 -gerrit commit e1e49bc7ba5480338ab6f5980e38063b42cb3e2e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 15 13:29:41 2015 -0600 commonlib: Add function to compute relative offsets from two region_devices. Provide a helper function which returns the relative offset between 2 region_devices that have a parent-child child relationship. BUG=chrome-os-partner:48412 BUG=chromium:445938 BRANCH=None TEST=Utilized and booted on glados. Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/commonlib/include/commonlib/region.h | 7 +++++++ src/commonlib/region.c | 12 ++++++++++++ 2 files changed, 19 insertions(+) diff --git a/src/commonlib/include/commonlib/region.h b/src/commonlib/include/commonlib/region.h index cc4ee28..35d48ad 100644 --- a/src/commonlib/include/commonlib/region.h +++ b/src/commonlib/include/commonlib/region.h @@ -121,6 +121,13 @@ static inline void *rdev_mmap_full(const struct region_device *rd) return rdev_mmap(rd, 0, region_device_sz(rd)); } +/* + * Compute relative offset of the child (c) w.r.t. the parent (p). Returns < 0 + * when child is not within the parent's region. + */ +ssize_t rdev_relative_offset(const struct region_device *p, + const struct region_device *c); + struct mem_region_device { char *base; struct region_device rdev; diff --git a/src/commonlib/region.c b/src/commonlib/region.c index 8b0b0d9..2cd273a 100644 --- a/src/commonlib/region.c +++ b/src/commonlib/region.c @@ -48,6 +48,18 @@ static const struct region_device *rdev_root(const struct region_device *rdev) return rdev->root; } +ssize_t rdev_relative_offset(const struct region_device *p, + const struct region_device *c) +{ + if (rdev_root(p) != rdev_root(c)) + return -1; + + if (!is_subregion(&p->region, &c->region)) + return -1; + + return region_device_offset(c) - region_device_offset(p); +} + void *rdev_mmap(const struct region_device *rd, size_t offset, size_t size) { const struct region_device *rdev;

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New patch to review for coreboot: southbridge/intel/i82801gx: Add option to skip MADT irq override
by Damien Zammit 23 Dec '15

23 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12795 -gerrit commit eda6b77140513679b4ee8f8cc27a3977a9d66464 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Dec 23 16:54:29 2015 +1100 southbridge/intel/i82801gx: Add option to skip MADT irq override Provides Kconfig option IRQ9_MADT_OVERRIDE_OFF to skip overriding IRQ9 in MADT. Required on GA-G41M-ES2L mainboard. Change-Id: I865ad79c7c89f6eaf91653fbda5762542702274c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/southbridge/intel/i82801gx/Kconfig | 7 +++++++ src/southbridge/intel/i82801gx/lpc.c | 8 ++++++-- 2 files changed, 13 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index c435b99..9a09ab4 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -25,6 +25,13 @@ config SOUTHBRIDGE_INTEL_I82801GX if SOUTHBRIDGE_INTEL_I82801GX +config IRQ9_MADT_OVERRIDE_OFF + bool + default n + help + When selected, prevents ACPI from + overriding IRQ9 in MADT + config EHCI_BAR hex default 0xfef00000 diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 4e9711c..5fe588d 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -474,9 +474,13 @@ unsigned long acpi_fill_madt(unsigned long current) /* INT_SRC_OVR */ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_EDGE); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_POLARITY_HIGH | MP_IRQ_TRIGGER_LEVEL); + if (!IS_ENABLED(CONFIG_IRQ9_MADT_OVERRIDE_OFF)) { + current += acpi_create_madt_irqoverride( + (acpi_madt_irqoverride_t *) current, + 0, 9, 9, MP_IRQ_POLARITY_HIGH + | MP_IRQ_TRIGGER_LEVEL); + } return current; }

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Patch set updated for coreboot: gigabyte/ga-g41m-es2l: Add mainboard
by Damien Zammit 23 Dec '15

23 Dec '15

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11306 -gerrit commit 9eac4a2290ee5f16aa0519494e49b95107dba9c2 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Aug 19 15:23:32 2015 +1000 gigabyte/ga-g41m-es2l: Add mainboard Board uses x4x native raminit Board boots into Debian 8 with full graphics VGA: - VGA native init works in grub with analog connector - Fails to boot with both channels of ram populated Change-Id: I7417813456817529b8cbaace45cefe47467d0a82 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 52 +++++++ src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name | 2 + src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc | 1 + src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 34 +++++ .../gigabyte/ga-g41m-es2l/acpi/platform.asl | 28 ++++ .../gigabyte/ga-g41m-es2l/acpi/superio.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 66 +++++++++ src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c | 42 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt | 5 + src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 37 +++++ src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 113 ++++++++++++++ src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl | 41 ++++++ src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c | 7 + src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 163 +++++++++++++++++++++ 15 files changed, 593 insertions(+) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig new file mode 100644 index 0000000..f2ce664 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -0,0 +1,52 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_GIGABYTE_GA_G41M_ES2L + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_LGA775 + select NORTHBRIDGE_INTEL_X4X + select SOUTHBRIDGE_INTEL_I82801GX + select SUPERIO_ITE_IT8718F + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_1024 + select INTEL_EDID + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_DO_NATIVE_VGA_INIT + select IRQ9_MADT_OVERRIDE_OFF + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +# First 0x100 bytes of rom is protected, +# cant be flashed in-place with external programmer. +# So shrink CBFS to not go there. +config CBFS_SIZE + hex "Size of CBFS filesystem in ROM" + default 0xFFF00 + + +config MAINBOARD_DIR + string + default "gigabyte/ga-g41m-es2l" + +config MAINBOARD_PART_NUMBER + string + default "GA-G41M-ES2L" + +endif # BOARD_GIGABYTE_GA_G41M_ES2L diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name new file mode 100644 index 0000000..e685ce1 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_GIGABYTE_GA_G41M_ES2L + bool "GA-G41M-ES2L" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc new file mode 100644 index 0000000..f9621db --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += cstates.c diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000..0a69f3d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x001effff, 0, 0, 17}, + Package() { 0x001effff, 1, 0, 20}, + Package() { 0x001effff, 2, 0, 16}, + Package() { 0x001effff, 3, 0, 16}, + }) +} Else { + Return (Package() { + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x001effff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x001effff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl new file mode 100644 index 0000000..2997587 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000..fdfe73d --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 22 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + Package() { 0x001dffff, 0, 0, 23 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 0, 0, 18 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c new file mode 100644 index 0000000..d9d8032 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi_tables.c @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <arch/ioapic.h> + +#include "southbridge/intel/i82801gx/nvs.h" + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + + gnvs->pwrs = 1; /* Power state (AC = 1) */ + gnvs->lptp = 0; /* LPT port */ + gnvs->fdcp = 0; /* Floppy Disk Controller */ + gnvs->osys = 2002; /* At least WINXP SP2 (HPET fix) */ + gnvs->apic = 1; /* Enable APIC */ + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->cmap = 0x01; /* Enable COM 1 port */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt new file mode 100644 index 0000000..44ed73a --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/board_info.txt @@ -0,0 +1,5 @@ +Category: desktop +Board URL: +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c new file mode 100644 index 0000000..dbac2ed --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 secunet Security Networks AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <device/device.h> +#include <southbridge/intel/i82801gx/i82801gx.h> + +static acpi_cstate_t cst_entries[] = { + { + /* acpi C1 / cpu C1 */ + 1, 0x01, 1000, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } + }, + { + /* acpi C2 / cpu C2 */ + 2, 0x01, 500, + { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } + }, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb new file mode 100644 index 0000000..8b2044e --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -0,0 +1,113 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +chip northbridge/intel/x4x # Northbridge + device cpu_cluster 0 on # APIC cluster + chip cpu/intel/socket_LGA775 + device lapic 0 on end + end + chip cpu/intel/model_1067x # CPU + device lapic 0xACAC off end + register "slfm" = "1" + register "c5" = "1" + register "c6" = "1" + end + end + device domain 0 on # PCI domain + subsystemid 0x1458 0x5000 inherit + device pci 0.0 on # Host Bridge + subsystemid 0x1458 0x5000 + end + device pci 1.0 off end # PCI Bridge to Management Engine + device pci 2.0 on # Integrated graphics controller + subsystemid 0x1458 0xd000 + end + device pci 2.1 off end # Integrated graphics controller 2 + device pci 3.0 off end # ME + device pci 3.1 off end # ME + chip southbridge/intel/i82801gx # Southbridge + register "pirqa_routing" = "0x0b" + register "pirqb_routing" = "0x0b" + register "pirqc_routing" = "0x0b" + register "pirqd_routing" = "0x0b" + register "pirqe_routing" = "0x0b" + register "pirqf_routing" = "0x0b" + register "pirqg_routing" = "0x0b" + register "pirqh_routing" = "0x0b" + register "ide_legacy_combined" = "0x0" + register "ide_enable_primary" = "0x0" + register "ide_enable_secondary" = "0x0" + register "sata_ahci" = "0x1" + register "gpe0_en" = "0x40" + + device pci 1b.0 on # Audio + subsystemid 0x1458 0xa002 + end + device pci 1c.0 on end # PCIe 1 + device pci 1c.1 on end # PCIe 2 + device pci 1d.0 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.1 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.2 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.3 on # USB + subsystemid 0x1458 0x5004 + end + device pci 1d.7 on # USB + subsystemid 0x1458 0x5006 + end + device pci 1e.0 on end # PCI bridge + device pci 1f.0 on # ISA bridge + subsystemid 0x1458 0x5001 + chip superio/ite/it8718f # Super I/O + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + irq 0x70 = 0 + io 0x62 = 0x000 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + irq 0x70 = 1 + io 0x62 = 0x64 + end + device pnp 2e.6 off end # Mouse + device pnp 2e.7 off end # GPIO + end + end + device pci 1f.1 off end # PATA/IDE + device pci 1f.2 on # SATA + subsystemid 0x1458 0xb005 + end + device pci 1f.3 on # SMbus + subsystemid 0x1458 0x5001 + end + device pci 1f.4 off end + device pci 1f.5 off end + device pci 1f.6 off end + end + end +end diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl new file mode 100644 index 0000000..5f64d1e --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20090419 // OEM revision +) +{ + // global NVS and variables + #include "acpi/platform.asl" + #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/x4x/acpi/x4x.asl> + #include <southbridge/intel/i82801gx/acpi/ich7.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c new file mode 100644 index 0000000..072a306 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/hda_verb.c @@ -0,0 +1,7 @@ +#include <device/azalia_device.h> + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c new file mode 100644 index 0000000..6bae128 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -0,0 +1,163 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <stdlib.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <console/console.h> +#include <southbridge/intel/i82801gx/i82801gx.h> +#include <northbridge/intel/x4x/x4x.h> +#include <cpu/x86/bist.h> +#include <superio/ite/it8718f/it8718f.h> +#include <superio/ite/common/ite.h> +#include <lib.h> +#include <cpu/intel/romstage.h> +#include <arch/stages.h> +#include <cbmem.h> + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +/* Early mainboard specific GPIO setup. + * We should use standard gpio.h eventually + */ + +static void mb_gpio_init(void) +{ + device_t dev; + + /* Southbridge GPIOs. */ + dev = PCI_DEV(0x0, 0x1f, 0x0); + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); + pci_write_config8(dev, GPIO_CNTL, 0x10); + + outl(0x1f15f7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ + outl(0xe2e9ffc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ + outl(0xe0d7fcc3, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x000039ff, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ + outl(0x000000e7, DEFAULT_GPIOBASE + 0x30); + outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); + outl(0x00000083, DEFAULT_GPIOBASE + 0x38); + + /* Set default power management registers */ + pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); + outw(0x0011, DEFAULT_PMBASE + 0x00); + outw(0x0120, DEFAULT_PMBASE + 0x02); + outl(0x00001c01, DEFAULT_PMBASE + 0x04); + outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); + outl(0x000000a0, DEFAULT_PMBASE + 0x10); + outl(0xc5000000, DEFAULT_PMBASE + 0x28); + outl(0x00000040, DEFAULT_PMBASE + 0x2c); + outw(0x13e0, DEFAULT_PMBASE + 0x44); + outw(0x003f, DEFAULT_PMBASE + 0x60); + outw(0x0800, DEFAULT_PMBASE + 0x68); + outw(0x0008, DEFAULT_PMBASE + 0x6a); + outw(0x003f, DEFAULT_PMBASE + 0x72); + + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x00); + ite_reg_write(GPIO_DEV, 0x26, 0xc7); + ite_reg_write(GPIO_DEV, 0x27, 0x80); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x0a); + ite_reg_write(GPIO_DEV, 0x2c, 0x01); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_reg_write(GPIO_DEV, 0x72, 0x00); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc1, 0xc7); + ite_reg_write(GPIO_DEV, 0xc2, 0x80); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xc4, 0x0a); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x04); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xcc, 0x02); + ite_reg_write(GPIO_DEV, 0xf0, 0x10); + ite_reg_write(GPIO_DEV, 0xf1, 0x40); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x52); + + ite_reg_write(EC_DEV, 0xf0, 0x80); + ite_reg_write(EC_DEV, 0xf1, 0x00); + ite_reg_write(EC_DEV, 0xf2, 0x0a); + ite_reg_write(EC_DEV, 0xf3, 0x80); + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + + /* IRQ routing */ + RCBA32(0x3100) = 0x00002210; + RCBA32(0x3104) = 0x00002100; + RCBA32(0x3108) = 0x10004321; + RCBA32(0x310c) = 0x00214321; + RCBA32(0x3110) = 0x00000001; + RCBA32(0x3140) = 0x00410032; + RCBA32(0x3144) = 0x32100237; + + /* Enable IOAPIC */ + RCBA8(0x31ff) = 0x03; + RCBA8(0x31ff); +} + +static void ich7_enable_lpc(void) +{ + /* Disable Serial IRQ */ + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0x00); + /* Decode range */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); + pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); + + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x0291); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x007c); +} + +void main(unsigned long bist) +{ + // ch0 ch1 + const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; + + /* Disable watchdog timer and route port 80 to LPC */ + RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + + /* Set southbridge and Super I/O GPIOs. */ + mb_gpio_init(); + + ich7_enable_lpc(); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + + console_init(); + + report_bist_failure(bist); + enable_smbus(); + + x4x_early_init(); + + printk(BIOS_DEBUG, "Initializing memory\n"); + sdram_initialize(0, spd_addrmap); + quick_ram_check(); + printk(BIOS_DEBUG, "Memory initialized\n"); +}

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New patch to review for coreboot: soc/intel: Add support for EHCI debug
by Duncan Laurie 23 Dec '15

23 Dec '15

Duncan Laurie (dlaurie(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12794 -gerrit commit 608cdd37eb99a8b48f0343519f42b00723362a3e Author: Duncan Laurie <dlaurie(a)google.com> Date: Tue Dec 22 17:15:29 2015 -0800 soc/intel: Add support for EHCI debug This was removed from broadwell in commit 11874 but was never added anywhere that could be used by broadwell. Add it back to the soc/intel/common directory so EHCI debug can work again. Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6 Signed-off-by: Duncan Laurie <dlaurie(a)google.com> --- src/soc/intel/common/Makefile.inc | 3 ++ src/soc/intel/common/usb_debug.c | 59 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index a7218b7..5c69bca 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -15,6 +15,9 @@ ramstage-y += util.c ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += usb_debug.c +ramstage-$(CONFIG_USBDEBUG) += usb_debug.c + # Create and add the MRC cache to the cbfs image ifneq ($(CONFIG_CHROMEOS),y) $(obj)/mrc.cache: $(obj)/config.h diff --git a/src/soc/intel/common/usb_debug.c b/src/soc/intel/common/usb_debug.c new file mode 100644 index 0000000..fffebf0 --- /dev/null +++ b/src/soc/intel/common/usb_debug.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/pci_ehci.h> +#include <device/pci_def.h> + +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + u32 class; + pci_devfn_t dev = PCI_DEV(0, 0x1d, 0); + + class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; + if (class != PCI_EHCI_CLASSCODE) + return 0; + + return dev; +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + /* Hardcoded to physical port 1 */ +} + +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) +{ + u32 tmp32; + + if (!dev) + return; + + /* Set the EHCI BAR address. */ + pci_write_config32(dev, EHCI_BAR_INDEX, base); + + /* Enable access to the EHCI memory space registers. */ + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + + /* Force ownership of hte Debug Port to the EHCI controller. */ + tmp32 = read32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET)); + tmp32 |= (1 << 30); + write32((void *)(base + CONFIG_EHCI_DEBUG_OFFSET), tmp32); +}

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coreboot-gerrit December 2015