coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

1 participants
1544 discussions

Patch set updated for coreboot: Remove dependency for HAS_PRECBMEM_TIMESTAMP_REGION
by Martin Roth 12 Nov '15

12 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11338 -gerrit commit 1e287503a032ddb572ab9c9ecb8e7a3b2cc758fa Author: Martin Roth <martinroth(a)google.com> Date: Mon Aug 24 16:42:31 2015 -0600 Remove dependency for HAS_PRECBMEM_TIMESTAMP_REGION HAS_PRECBMEM_TIMESTAMP_REGION was dependent on COLLECT_TIMESTAMPS, but should be allowed to be selected independently. My thought is that the code may only be used when collecting timestamps, the HAS prefix signifies that this is a platform configuration option. This fix could also be done by adding 'if COLLECT_TIMESTAMPS' everywhere that 'select HAS_PRECBMEM_TIMESTAMP_REGION' is used Change-Id: Iaf4895475c38a855a048dc9b82d4c97e5e3f4e5c Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 3562887..f0aea2b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -188,7 +188,6 @@ config COLLECT_TIMESTAMPS config HAS_PRECBMEM_TIMESTAMP_REGION bool "Timestamp region exists for pre-cbmem timestamps" default y if ARCH_ROMSTAGE_X86_32 && CACHE_AS_RAM - depends on COLLECT_TIMESTAMPS help A separate region is maintained to allow storing of timestamps before cbmem comes up. This is useful for storing timestamps across different

1 0

Patch set updated for coreboot: uart8250mem: Change the delay for uart (Don't merge)
by Zheng Bao 12 Nov '15

12 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12343 -gerrit commit 726a55ecefb3ed161ccae22faa327548e3cf437d Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Nov 13 00:42:49 2015 +0800 uart8250mem: Change the delay for uart (Don't merge) Change-Id: I6131adbe24a0ee6dfd47d00265fd8583ef22ec0d Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/drivers/uart/uart8250mem.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..9cb29f0 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -32,6 +32,12 @@ #define SINGLE_CHAR_TIMEOUT (50 * 1000) #define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT) +static void my_delay(int delay) +{ + while (delay --) + outb(0xaa, 0x80); +} + #if IS_ENABLED(CONFIG_DRIVERS_UART_8250MEM_32) static uint8_t uart8250_read(void *base, uint8_t reg) { @@ -63,7 +69,7 @@ static void uart8250_mem_tx_byte(void *base, unsigned char data) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_tx_byte(base)) - udelay(1); + my_delay(1); uart8250_write(base, UART8250_TBR, data); } @@ -71,7 +77,7 @@ static void uart8250_mem_tx_flush(void *base) { unsigned long int i = FIFO_TIMEOUT; while(i-- && !(uart8250_read(base, UART8250_LSR) & UART8250_LSR_TEMT)) - udelay(1); + my_delay(1); } static int uart8250_mem_can_rx_byte(void *base) @@ -83,7 +89,7 @@ static unsigned char uart8250_mem_rx_byte(void *base) { unsigned long int i = SINGLE_CHAR_TIMEOUT; while(i-- && !uart8250_mem_can_rx_byte(base)) - udelay(1); + my_delay(1); if (i) return uart8250_read(base, UART8250_RBR); else

1 0

Patch set updated for coreboot: AMD/bettong: Add UART support
by Zheng Bao 12 Nov '15

12 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11749 -gerrit commit a0d970712c77a6461f56786b75daf840663967ad Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Fri Nov 13 00:41:45 2015 +0800 AMD/bettong: Add UART support The function delay in uart8250mem.c is not enough for hudson. Need a seprate patch to fix that. Select HUDSON_UART to enable this feature. Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- src/southbridge/amd/agesa/hudson/acpi/uart.asl | 66 ++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/Kconfig | 16 +++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 5 ++ src/southbridge/amd/pi/hudson/early_setup.c | 25 ++++++++++ src/southbridge/amd/pi/hudson/uart.c | 47 ++++++++++++++++++ 5 files changed, 159 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/acpi/uart.asl b/src/southbridge/amd/agesa/hudson/acpi/uart.asl new file mode 100644 index 0000000..9177cb0 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/acpi/uart.asl @@ -0,0 +1,66 @@ + Scope(\_SB.FUR0) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, Zero) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x30, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +/* + Scope(\_SB.FUR1) + { + Device(UART) + { + Name(_HID, "UTK0001") + Name(_CID, "UARTTest") + Name(_UID, One) + Method(_CRS, 0, NotSerialized) + { + Name(RBUF, Buffer(0x22) + { + 0x8E, 0x1D, 0x00, 0x01, 0x00, 0x03, 0x02, 0x35, + 0x00, 0x01, 0x0A, 0x00, 0x00, 0xC2, 0x01, 0x00, + 0x20, 0x00, 0x20, 0x00, 0x00, 0xC0, 0x5C, 0x5F, + 0x53, 0x42, 0x2E, 0x46, 0x55, 0x52, 0x31, 0x00, + 0x79, 0x00 + }) + Return(RBUF) + } + Method(_STA, 0, NotSerialized) + { + If(LEqual(MWTT, Zero)) + { + Return(0x0F) + } + Else + { + Return(Zero) + } + } + } + } +*/ diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index c720791..94a313d 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -227,3 +227,19 @@ config AZ_PIN bit 5,4 - pin 2 bit 7,6 - pin 3 endif + +config HUDSON_UART + bool "UART controller on Kern." + default n + depends on SOUTHBRIDGE_AMD_PI_KERN + select DRIVERS_UART_8250MEM + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + help + There are two UART controllers in Kern. + The UART registers are memory-mapped. UART + controller 0 registers range from FEDC_6000h + to FEDC_6FFFh. UART controller 1 registers + range from FEDC_8000h to FEDC_8FFFh. + + diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 00d150f..2c2458c 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -50,6 +50,11 @@ romstage-y += imc.c ramstage-y += imc.c endif +ifeq ($(CONFIG_HUDSON_UART), y) +romstage-y += uart.c +ramstage-y += uart.c +endif + smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 14ffd8b..e2e13cd 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -18,11 +18,14 @@ #include <stdint.h> #include <arch/io.h> +#include <cpu/x86/msr.h> #include <arch/acpi.h> #include <console/console.h> #include <reset.h> #include <arch/cpu.h> +#include <delay.h> #include <cbmem.h> +#include <Fch/Fch.h> #include "hudson.h" #include "pci_devs.h" @@ -75,6 +78,9 @@ void hudson_lpc_port80(void) { u8 byte; device_t dev; +#if CONFIG_HUDSON_UART + msr_t msr; +#endif /* Enable LPC controller */ outb(0xEC, 0xCD6); @@ -88,6 +94,25 @@ void hudson_lpc_port80(void) byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); + +#if CONFIG_HUDSON_UART + msr = rdmsr(0x1B); + msr.lo |= 1 << 11; + wrmsr(0x1B, msr); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x56 + CONFIG_UART_FOR_CONSOLE * 2, byte); + byte = read8(ACPI_MMIO_BASE + AOAC_BASE + 0x62); + byte |= 1 << 3; + write8(ACPI_MMIO_BASE + AOAC_BASE + 0x62, byte); + write8(ACPI_MMIO_BASE + 0xD00 + 0x89, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8A, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8E, 0); + write8(ACPI_MMIO_BASE + 0xD00 + 0x8F, 0); + + udelay(2000); + write8((void *)0xFEDC6000 + 0x2000 * CONFIG_UART_FOR_CONSOLE + 0x88, 0x01); /* reset UART */ +#endif } void hudson_lpc_decode(void) diff --git a/src/southbridge/amd/pi/hudson/uart.c b/src/southbridge/amd/pi/hudson/uart.c new file mode 100644 index 0000000..ba35fbf --- /dev/null +++ b/src/southbridge/amd/pi/hudson/uart.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + + +#include <boot/coreboot_tables.h> +#include <console/console.h> /* for __console definition */ +#include <console/uart.h> +#include <drivers/uart/uart8250reg.h> + +#define ACPI_MMIO_BASE 0xFED80000 +#define AOAC_BASE 0x1E00 +uintptr_t uart_platform_base(int idx) +{ + return (uintptr_t)(0xFEDC6000 + 0x2000 * (idx & 1)); +} + +unsigned int uart_platform_refclk(void) +{ + return 48000000; +} + +#ifdef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); + serial.baud = default_baudrate(); + serial.regwidth = 4; + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif

1 0

New patch to review for coreboot: amdfwtool: Add amdfwtool to combine AMD firmware
by Zheng Bao 12 Nov '15

12 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12419 -gerrit commit 5c98efff267b880f5df3efd692c1c4b4d60ab1c8 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Thu Nov 12 23:54:12 2015 +0800 amdfwtool: Add amdfwtool to combine AMD firmware Combine all needed AMD firmware into one single firmware, which going to be added as one single CBFS module. Change-Id: Ib044098c1837592b8f7e9c6a7da4ba3a32117e25 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- Makefile.inc | 7 +- util/amdfwtool/Makefile | 70 +++++++++ util/amdfwtool/amdfwtool.c | 358 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 434 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 5b8e4dc..84a7e45 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -290,7 +290,7 @@ CFLAGS_common += -Os endif additional-dirs := $(objutil)/cbfstool $(objutil)/romcc $(objutil)/ifdtool \ - $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher \ + $(objutil)/ifdfake $(objutil)/options $(objutil)/fletcher $(objutil)/amdfwtool \ $(objutil)/cbootimage $(objutil)/bimgtool ####################################################################### @@ -353,6 +353,11 @@ $(FLETCHER): $(top)/util/fletcher/fletcher.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" $(HOSTCC) $(HOSTCFLAGS) -o $@ $< +AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool +$(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c + @printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage subdirs-y += util/nvidia diff --git a/util/amdfwtool/Makefile b/util/amdfwtool/Makefile new file mode 100644 index 0000000..bef2615 --- /dev/null +++ b/util/amdfwtool/Makefile @@ -0,0 +1,70 @@ +#***************************************************************************** +# +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of Advanced Micro Devices, Inc. nor the names of +# its contributors may be used to endorse or promote products derived +# from this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY +# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND +# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +#***************************************************************************** +HOSTCC ?= cc + +amdfwtool_exe : amdfwtool.c + $(HOSTCC) amdfwtool.c -o amdfwtool + +amdfwtool : amdfwtool_exe + +clean: + @rm -f amdfwtool.o amdfwtool amdfwtool.exe + +#$(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ +# $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ +# $(call strip_quotes, $(CONFIG_HUDSON_GEC_FWM_FILE)) \ +# $(call strip_quotes, $(CONFIG_AMDPUBKEY_FILE)) \ +# $(call strip_quotes, $(CONFIG_PUBSIGNEDKEY_FILE)) \ +# $(call strip_quotes, $(CONFIG_PSPBTLDR_FILE)) \ +# $(call strip_quotes, $(CONFIG_PSPRCVR_FILE)) \ +# $(call strip_quotes, $(CONFIG_PSPSCUREOS_FILE)) \ +# $(call strip_quotes, $(CONFIG_PSPNVRAM_FILE)) \ +# $(call strip_quotes, $(CONFIG_SMUFWM_FILE)) \ +# $(call strip_quotes, $(CONFIG_SMUSCS_FILE)) \ +# $(call strip_quotes, $(CONFIG_PSPSECUREDEBUG_FILE)) \ +# $(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \ +# $(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \ +# $(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \ +# $(AMDFWTOOL) +# $(AMDFWTOOL) \ +# --xhci $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ +# --imc $(call strip_quotes, $(CONFIG_HUDSON_IMC_FWM_FILE)) \ +# --pubkey $(call strip_quotes, $(CONFIG_AMDPUBKEY_FILE)) \ +# --bootloader $(call strip_quotes, $(CONFIG_PSPBTLDR_FILE)) \ +# --smufirmware $(call strip_quotes, $(CONFIG_SMUFWM_FILE)) \ +# --recovery $(call strip_quotes, $(CONFIG_PSPRCVR_FILE)) \ +# --rtmpubkey $(call strip_quotes, $(CONFIG_PUBSIGNEDKEY_FILE)) \ +# --secureos $(call strip_quotes, $(CONFIG_PSPSCUREOS_FILE)) \ +# --nvram $(call strip_quotes, $(CONFIG_PSPNVRAM_FILE)) \ +# --securedebug $(call strip_quotes, $(CONFIG_PSPSECUREDEBUG_FILE)) \ +# --trustlets $(call strip_quotes, $(CONFIG_PSPTRUSTLETS_FILE)) \ +# --trustletkey $(call strip_quotes, $(CONFIG_TRUSTLETKEY_FILE)) \ +# --smufirmware2 $(call strip_quotes, $(CONFIG_SMUFIRMWARE2_FILE)) \ +# --smuscs $(call strip_quotes, $(CONFIG_SMUSCS_FILE)) \ +# --output $@ + diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c new file mode 100644 index 0000000..efbf058 --- /dev/null +++ b/util/amdfwtool/amdfwtool.c @@ -0,0 +1,358 @@ +/* + * All Rights Reserved + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that: (1) source code + * distributions retain the above copyright notice and this paragraph + * in its entirety, and (2) distributions including binary code include + * the above copyright notice and this paragraph in its entirety in + * the documentation or other materials provided with the distribution. + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND + * WITHOUT ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT + * LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE. + * + */ + +#include <fcntl.h> +#include <errno.h> +#include <stdio.h> +#include <sys/stat.h> +#include <sys/types.h> +#include <unistd.h> +#include <string.h> +#include <stdlib.h> +#include <getopt.h> + +#define MAX_PSP_DIRECTORY_SIZE 512 +#define ALIGN(val, by) (((val) + (by)-1)&~((by)-1)) + +typedef unsigned int uint32_t; +typedef unsigned char uint8_t; +typedef unsigned short uint16_t; + +/* + * Creates the OSI Fletcher checksum. See 8473-1, Appendix C, section C.3. + * The checksum field of the passed PDU does not need to be reset to zero. + * + * The "Fletcher Checksum" was proposed in a paper by John G. Fletcher of + * Lawrence Livermore Labs. The Fletcher Checksum was proposed as an + * alternative to cyclical redundancy checks because it provides error- + * detection properties similar to cyclical redundancy checks but at the + * cost of a simple summation technique. Its characteristics were first + * published in IEEE Transactions on Communications in January 1982. One + * version has been adopted by ISO for use in the class-4 transport layer + * of the network protocol. + * + * This program expects: + * stdin: The input file to compute a checksum for. The input file + * not be longer than 256 bytes. + * stdout: Copied from the input file with the Fletcher's Checksum + * inserted 8 bytes after the beginning of the file. + * stderr: Used to print out error messages. + */ + +uint32_t fletcher32 (const uint16_t *pptr, int length) +{ + + uint32_t c0; + uint32_t c1; + uint32_t checksum; + int index; + + c0 = 0xFFFF; + c1 = 0xFFFF; + + for (index = 0; index < length; index++) { + /* + * Ignore the contents of the checksum field. + */ + c0 += *(pptr++); + c1 += c0; + if ((index % 360) == 0) { + c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow + c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow + } + + } + + c0 = (c0 & 0xFFFF) + (c0 >> 16); // Sum0 modulo 65535 + the overflow + c1 = (c1 & 0xFFFF) + (c1 >> 16); // Sum1 modulo 65535 + the overflow + checksum = (c1 << 16) | c0; + + return checksum; +} + +void usage() +{ + printf("Create AMD Firmware combination\n"); +} + +#define CONFIG_ROM_SIZE 0x800000 +typedef enum _amd_fw_type { + AMD_FW_PSP_PUBKEY = 0, + AMD_FW_PSP_BOOTLOADER = 1, + AMD_FW_PSP_SMU_FIRMWARE = 8, + AMD_FW_PSP_RECOVERY = 3, + AMD_FW_PSP_RTM_PUBKEY = 5, + AMD_FW_PSP_SECURED_OS = 2, + AMD_FW_PSP_NVRAM = 4, + AMD_FW_PSP_SECURED_DEBUG = 9, + AMD_FW_PSP_TRUSTLETS = 12, + AMD_FW_PSP_TRUSTLETKEY = 13, + AMD_FW_PSP_SMU_FIRMWARE2 = 18, + AMD_PSP_FUSE_CHAIN = 11, + AMD_FW_PSP_SMUSCS = 95, + + AMD_FW_IMC, + AMD_FW_GEC, + AMD_FW_XHCI, +} amd_fw_type; + +typedef struct _amd_fw_entry { + amd_fw_type type; + char *filename; +} amd_fw_entry; + +amd_fw_entry amd_psp_fw_table[] = { + { .type = AMD_FW_PSP_PUBKEY }, + { .type = AMD_FW_PSP_BOOTLOADER }, + { .type = AMD_FW_PSP_SMU_FIRMWARE }, + { .type = AMD_FW_PSP_RECOVERY }, + { .type = AMD_FW_PSP_RTM_PUBKEY }, + { .type = AMD_FW_PSP_SECURED_OS }, + { .type = AMD_FW_PSP_NVRAM }, + { .type = AMD_FW_PSP_SECURED_DEBUG }, + { .type = AMD_FW_PSP_TRUSTLETS }, + { .type = AMD_FW_PSP_TRUSTLETKEY }, + { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, + { .type = AMD_FW_PSP_SMUSCS }, + { .type = AMD_PSP_FUSE_CHAIN }, +}; + +amd_fw_entry amd_fw_table[] = { + { .type = AMD_FW_XHCI }, + { .type = AMD_FW_IMC }, + { .type = AMD_FW_GEC }, +}; + +void fill_psp_head(uint32_t *pspdir, int count) +{ + pspdir[0] = 'PSP$'; /* 1347637284 */ + pspdir[2] = count; /* size */ + pspdir[3] = 0; + pspdir[1] = fletcher32((uint16_t *)&pspdir[1], (count *16 + 16)/2 - 2); +} + +uint32_t integerate_one_fw(void *base, uint32_t pos, uint32_t *romsig, int i) +{ + int fd; + struct stat fd_stat; + + if (amd_fw_table[i].filename != NULL) { + fd = open (amd_fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + + switch (amd_fw_table[i].type) { + case AMD_FW_IMC: + romsig[1] = pos + 0xFF800000; + break; + case AMD_FW_GEC: + romsig[2] = pos + 0xFF800000; + break; + case AMD_FW_XHCI: + romsig[3] = pos + 0xFF800000; + break; + default: + /* Error */ + break; + } + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } + + return pos; +} + +uint32_t integerate_one_psp(void *base, uint32_t pos, uint32_t *pspdir, int i) +{ + int fd; + struct stat fd_stat; + + pspdir[4+4*i+0] = amd_psp_fw_table[i].type; + + if (amd_psp_fw_table[i].type == AMD_PSP_FUSE_CHAIN) { + pspdir[4+4*i+1] = 0xFFFFFFFF; + pspdir[4+4*i+2] = 1; + pspdir[4+4*i+3] = 0; + } else if (amd_psp_fw_table[i].filename != NULL) { + fd = open (amd_psp_fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + pspdir[4+4*i+1] = fd_stat.st_size; + + pspdir[4+4*i+2] = pos + 0xFF800000; + pspdir[4+4*i+3] = 0; + + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } + return pos; +} + +static const char *optstring = "x:i:g:p:b:s:r:k:o:n:d:t:u:w:m:h"; +static struct option long_options[] = { + {"xhci", required_argument, 0, 'x' }, + {"imc", required_argument, 0, 'i' }, + {"gec", required_argument, 0, 'g' }, + /* PSP */ + {"pubkey", required_argument, 0, 'p' }, + {"bootloader", required_argument, 0, 'b' }, + {"smufirmware", required_argument, 0, 's' }, + {"recovery", required_argument, 0, 'r' }, + {"rtmpubkey", required_argument, 0, 'k' }, + {"secureos", required_argument, 0, 'c' }, + {"nvram", required_argument, 0, 'n' }, + {"securedebug", required_argument, 0, 'd' }, + {"trustlets", required_argument, 0, 't' }, + {"trustletkey", required_argument, 0, 'u' }, + {"smufirmware2", required_argument, 0, 'w' }, + {"smuscs", required_argument, 0, 'm' }, + {"output", required_argument, 0, 'o' }, + {"help", no_argument, 0, 'h' }, + {NULL, 0, 0, 0 } +}; + +void register_fw_filename(amd_fw_type type, char filename[]) +{ + int i; + + for (i = 0; i < sizeof(amd_psp_fw_table)/sizeof(amd_fw_entry); i++) { + if (amd_psp_fw_table[i].type == type) { + amd_psp_fw_table[i].filename = filename; + } + } + for (i = 0; i < sizeof(amd_fw_table)/sizeof(amd_fw_entry); i++) { + if (amd_fw_table[i].type == type) { + amd_fw_table[i].filename = filename; + } + } +} + +int main(int argc, char **argv) +{ + int c, i; + + void *rom = NULL; + uint32_t current; + uint32_t *amd_romsig, *pspdir; + + int targetfd; + char *output; + + rom = malloc(CONFIG_ROM_SIZE); + memset (rom, 0xFF, CONFIG_ROM_SIZE); + if (!rom) { + //ERROR("Couldn't allocate memory for microcode update entries.\n"); + return 1; + } + amd_romsig = rom + 0x20000; /* TODO: Remove hardcode */ + amd_romsig[0] = 0x55AA55AA; /* romsig */ + amd_romsig[1] = 0; /* IMC */ + amd_romsig[2] = 0; /* GEC */ + amd_romsig[3] = 0; /* XHCI */ + amd_romsig[4] = 0; /* PSP */ + + current = 0x20100; /* TODO: Remove hardcode */ + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + + if (c == -1) + break; + + switch (c) { + case 'x': + register_fw_filename(AMD_FW_XHCI, optarg); + break; + case 'i': + register_fw_filename(AMD_FW_IMC, optarg); + break; + case 'g': + register_fw_filename(AMD_FW_GEC, optarg); + break; + case 'p': + register_fw_filename(AMD_FW_PSP_PUBKEY, optarg); + break; + case 'b': + register_fw_filename(AMD_FW_PSP_BOOTLOADER, optarg); + break; + case 's': + register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE, optarg); + break; + case 'r': + register_fw_filename(AMD_FW_PSP_RECOVERY, optarg); + break; + case 'k': + register_fw_filename(AMD_FW_PSP_RTM_PUBKEY, optarg); + break; + case 'c': + register_fw_filename(AMD_FW_PSP_SECURED_OS, optarg); + break; + case 'n': + register_fw_filename(AMD_FW_PSP_NVRAM, optarg); + break; + case 'd': + register_fw_filename(AMD_FW_PSP_SECURED_DEBUG, optarg); + break; + case 't': + register_fw_filename(AMD_FW_PSP_TRUSTLETS, optarg); + break; + case 'u': + register_fw_filename(AMD_FW_PSP_TRUSTLETKEY, optarg); + break; + case 'w': + register_fw_filename(AMD_FW_PSP_SMU_FIRMWARE2, optarg); + break; + case 'm': + register_fw_filename(AMD_FW_PSP_SMUSCS, optarg); + break; + + case 'o': + output = optarg; + break; + case 'h': + usage(); + return 1; + default: + break; + } + } + + for (i=0; i< sizeof(amd_fw_table) / sizeof(amd_fw_entry); i ++) { + current = integerate_one_fw(rom, current, amd_romsig, i); + } + + current = ALIGN(current, 0x10000); + pspdir = rom + current; + amd_romsig[4] = current + 0xFF800000; + current += 0x400; + for (i=0; i< sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); i ++) { + current = integerate_one_psp(rom, current, pspdir, i); + } + + fill_psp_head(pspdir, i); + + targetfd = open(output, O_RDWR | O_CREAT, 0666); + write(targetfd, amd_romsig, current - 0x20000); + close(targetfd); + free(rom); + return 0; +}

1 0

Patch set updated for coreboot: AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1
by Zheng Bao 12 Nov '15

12 Nov '15

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11752 -gerrit commit 5fe56693133c8d4bf38e192200eed1f50dd832e5 Author: zbao <fishbaozi(a)gmail.com> Date: Sat Nov 7 01:12:20 2015 +0800 AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1 1. This is required the BLOB change Ie86bb0cf AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5) 2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- .../amd/pi/00660F01/Proc/Fch/Common/FchDef.h | 2 ++ src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h | 18 ++++++++++++++---- .../amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h | 2 ++ 3 files changed, 18 insertions(+), 4 deletions(-) diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h index d0063a4..41f103b 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Common/FchDef.h @@ -340,6 +340,8 @@ VOID FchInitEnvLpcProgram (IN VOID *FchDataPtr); /// VOID FchSpiUnlock (IN VOID *FchDataPtr); VOID FchSpiLock (IN VOID *FchDataPtr); +VOID FchUsb3D3ColdCallback (IN VOID *FchDataPtr); +VOID FchUsb3D0Callback (IN VOID *FchDataPtr); /*--------------------------- Documentation Pages ---------------------------*/ VOID FchStall (IN UINT32 uSec, IN AMD_CONFIG_PARAMS *StdHeader); diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h index 7576cad..92201b8 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Fch/Fch.h @@ -2007,8 +2007,9 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_PMIOxC0_S5ResetStatus 0xFED803C0ul // S5ResetStatus #define FCH_PMIOxC0_S5ResetStatus_ThermalTrip (1 << 0) #define FCH_PMIOxC0_S5ResetStatus_FourSecondPwrBtn (1 << 1) -#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3ff | (1 << 20)) +#define FCH_PMIOxC0_S5ResetStatus_S_Status (0x3fe | (1 << 20)) #define FCH_PMIOxC0_S5ResetStatus_All_Status 0x3FFF03FFul +#define FCH_PMIOxC0_S5ResetStatus_Clr_Status 0x3FFF03FEul #define FCH_PMxC8_Misc 0xFED803C8ul // Misc #define FCH_PMxC8_Misc_UseAcpiStraps (1 << 4) @@ -2020,6 +2021,8 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x0E00 // #define FCH_MISCx28_ClkDrvStr2 0xFED80E28ul // ClkDrvStr2 +#define FCH_MISCx28_ClkDrvStr2_USB2_RefClk_Pwdn (1 << 30) +#define FCH_MISCx28_ClkDrvStr2_USB3_RefClk_Pwdn (1 << 31) #define FCH_MISCx40_MiscClkCntl1 0xFED80E40ul // MiscClkCntl1 #define FCH_MISCx40_MiscClkCntl1_CG1PLL_FBDIV_Test (1 << 26) @@ -2038,7 +2041,8 @@ FCH_MISC_REGF0 EQU 0F0h // offset : 0x1C00 // #define FCH_XHC_PMx00_Configure0 0xFED81C00ul // -#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 +#define FCH_XHC_PMx00_Configure0_U3P_D3Cold_PWRDN BIT15 +#define FCH_XHC_PMx00_Configure0_XHC_SMIB_EN BIT21 #define FCH_XHC_PMx10_Xhc_Memory_Configure 0xFED81C10ul // #define FCH_XHC_PMx18_Usb20_Link_Status 0xFED81C18ul // #define FCH_XHC_PMx20_Usb20_Wake_Control 0xFED81C20ul // @@ -2057,9 +2061,12 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_AOACx40_D3_CONTROL 0xFED81E40ul // #define FCH_AOACx41_D3_STATUS 0xFED81E40ul // #define FCH_AOACx5E_SATA_D3_CONTROL 0xFED81E5Eul // +#define FCH_AOACx64_EHCI_D3_CONTROL 0xFED81E64ul // +#define FCH_AOACx65_EHCI_D3_STATE 0xFED81E65ul // #define FCH_AOACx6E_USB3_D3_CONTROL 0xFED81E6Eul // -#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // -#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // +#define FCH_AOACx6F_USB3_D3_STATE 0xFED81E6Ful // +#define FCH_AOACx70_SD_D3_CONTROL 0xFED81E70ul // +#define FCH_AOACx7A_IMC_D3_CONTROL 0xFED81E7Aul // #define FCH_AOACx88Shadow_Register_SRAM_Addr 0xFED81E88ul // #define FCH_AOACx8CShadow_Register_SRAM_Data 0xFED81E8Cul // #define FCH_AOACx94S013_CONTROL 0xFED81E94ul // @@ -2070,6 +2077,9 @@ FCH_MISC_REGF0 EQU 0F0h #define FCH_AOACx9C_Shadow_Timer_Control_ShadowAcpiTimerEn (1 << 1) // #define FCH_AOACxA0_PwrGood_Control 0xFED81EA0ul // +#define FCH_AOACxA0_PwrGood_Control_XhcPwrGood (1 << 3) // +#define FCH_AOACxA0_PwrGood_Control_SwUsb3SlpShutdown (1 << 29) // +#define FCH_AOACxA0_PwrGood_Control_SwUsb2S5RstB (1 << 30) // #define FCH_AOAC_REG00 0x00 // PerfMonControl #define FCH_AOAC_REG04 0x04 // PerfMonTimeLimit diff --git a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h index 6108274..6115396 100644 --- a/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h +++ b/src/vendorcode/amd/pi/00660F01/Proc/Psp/PspBaseLib/PspBaseLib.h @@ -63,6 +63,8 @@ #define PSP_PCI_EXTRAPCIHDR_REG 0x48 ///< Extra PCI Header Ctr #define PSP_PCI_HTMSICAP_REG 0x5C ///< HT MSI Capability +#define PSP_MSR_PRIVATE_BLOCK_BAR 0xC00110A2 ///< PSP Private Block Base Address (PSP_ADDR) + #define D8F0x44_PmNxtPtrW_MASK 0xff #define PSP_MAILBOX_BASE 0x70 ///< Mailbox base offset on PCIe BAR

1 0

Patch set updated for coreboot: update intel fsp1_0 rangeley files to revision: POSTGOLD3
by Marcin Wojciechowski 12 Nov '15

12 Nov '15

Marcin Wojciechowski (marcin.wojciechowski(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12418 -gerrit commit 9fc010752ac79414b4a07d91ca9387ead09383fa Author: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> Date: Thu Nov 12 16:05:42 2015 +0100 update intel fsp1_0 rangeley files to revision: POSTGOLD3 Alligment of Intel Firmware Support Package 1.0 rangeley header and source files to the revision: POSTGOLD3 more info can be found here: http://goo.gl/8qXXdG Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> --- .../intel/fsp1_0/rangeley/include/fspguid.h | 69 +++++ .../intel/fsp1_0/rangeley/include/fspplatform.h | 3 +- .../intel/fsp1_0/rangeley/include/fspsupport.h | 95 +++++++ .../intel/fsp1_0/rangeley/include/fsptypes.h | 9 +- .../intel/fsp1_0/rangeley/include/fspvpd.h | 12 +- .../intel/fsp1_0/rangeley/srx/fsp_support.c | 288 +++++++++++++++++++++ 6 files changed, 468 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h new file mode 100644 index 0000000..22ff35d --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (C) 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_GUID_H__ +#define __FSP_GUID_H__ + +/** + + FSP specific GUID HOB definitions + + **/ +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { \ + 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + { \ + 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + { \ + 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ + } + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + { \ + 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ + } + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h index ce479bf..c35dca0 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013 - 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,6 +74,7 @@ typedef struct { UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin) + UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor UINT8 SDRAMDeviceType; // 33 SDRAM Device Type UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h new file mode 100644 index 0000000..39102fe --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h @@ -0,0 +1,95 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsptypes.h" +#include "fspfv.h" +#include "fspffs.h" +#include "fspapi.h" +#include "fsphob.h" +#include "fspguid.h" +#include "fspplatform.h" +#include "fspinfoheader.h" +#include "fspbootmode.h" +#include "fspvpd.h" + +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobListPtr + ); + +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobListPtr + ); + +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid + ); + +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *FspMemoryBase, + UINT64 *FspMemoryLength, + EFI_GUID *FspReservedMemoryGuid + ); + +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +VOID* +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h index 5912e01..3d2e663 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h @@ -100,13 +100,18 @@ typedef struct { #define TRUE ((BOOLEAN)(1==1)) #define FALSE ((BOOLEAN)(0==1)) +static inline void DebugDeadLoop(void) { + for (;;); +} + #define FSPAPI __attribute__((cdecl)) #define EFIAPI __attribute__((cdecl)) +#define _ASSERT(Expression) DebugDeadLoop() #define ASSERT(Expression) \ do { \ if (!(Expression)) { \ - for (;;); \ + _ASSERT (Expression); \ } \ } while (FALSE) @@ -175,4 +180,4 @@ typedef UINT32 EFI_STATUS; #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32)) -#endif +#endif \ No newline at end of file diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h index fba38a0..eefdb94 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,7 +50,8 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */ UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */ UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */ - UINT8 UnusedUpdSpace1[7]; /* Offset 0x0029 */ + UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */ + UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */ UINT8 PcdEnableLan; /* Offset 0x0030 */ UINT8 PcdEnableSata2; /* Offset 0x0031 */ UINT8 PcdEnableSata3; /* Offset 0x0032 */ @@ -65,13 +66,14 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */ + UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */ UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000102 +#define VPD_IMAGE_REV 0x00000130 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c new file mode 100644 index 0000000..6fe3eb0 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c @@ -0,0 +1,288 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#include <types.h> +#include <string.h> +#include "fspsupport.h" + +/** + This function retrieves the top of usable low memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable low memory top. + +**/ +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT32 MemLen; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemLen = 0x100000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemLen += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemLen; +} + +/** + This function retrieves the top of usable high memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable high memory top. + +**/ +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemTop; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemTop = 0x100000000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemTop += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemTop; +} + +/** + This function retrieves a special reserved memory region. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the GUID HOB is + located, the length will be updated. + @param OwnerGuid A pointer to the owner guild. + @retval Reserved region start address. 0 if this region does not exist. + +**/ +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *Base, + UINT64 *Length, + EFI_GUID *OwnerGuid +) +{ + EFI_PEI_HOB_POINTERS Hob; + + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobListPtr; + + /* + * Collect memory ranges + */ + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { + if (CompareGuid(&Hob.ResourceDescriptor->Owner, OwnerGuid)) { + *Base = (EFI_PHYSICAL_ADDRESS) (Hob.ResourceDescriptor->PhysicalStart); + *Length = (UINT64) (Hob.ResourceDescriptor->ResourceLength); + break; + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } +} + +/** + This function retrieves the TSEG reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the TSEG reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the TSEG reserved memory. + @retval others TSEG reserved memory base. + +**/ +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID TsegOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&TsegOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + +/** + This function retrieves the FSP reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the FSP reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the FSP reserved memory. + @retval others FSP reserved memory base. + +**/ +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&FspOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + + +/** + This function retrieves a GUIDed HOB data buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the + GUID HOB is located, the length will be updated. + @param Guid A pointer to HOB GUID. + @retval NULL Failed to find the GUID HOB. + @retval others GUID HOB data buffer pointer. + +**/ +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid +) +{ + UINT8 *GuidHob; + + /* FSP NVS DATA HOB */ + GuidHob = GetNextGuidHob(Guid, HobListPtr); + if (GuidHob == NULL) { + return NULL; + } else { + if (Length) { + *Length = GET_GUID_HOB_DATA_SIZE (GuidHob); + } + return GET_GUID_HOB_DATA (GuidHob); + } +} + +/** + This function retrieves FSP Non-volatile Storage HOB buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the NVS data buffer length. If the FSP NVS + HOB is located, the length will be updated. + @retval NULL Failed to find the NVS HOB. + @retval others FSP NVS data buffer pointer. + +**/ +VOID * +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspNvsHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspNvsHobGuid); +} + + +/** + This function retrieves Bootloader temporary stack buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the Bootloader temporary stack length. + If the HOB is located, the length will be updated. + @retval NULL Failed to find the Bootloader temporary stack HOB. + @retval others Bootloader temporary stackbuffer pointer. + +**/ +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspBootloaderTemporaryMemoryHobGuid); +}

1 0

New patch to review for coreboot: update intel fsp1_0 rangeley files to revision: POSTGOLD3
by Marcin Wojciechowski 12 Nov '15

12 Nov '15

Marcin Wojciechowski (marcin.wojciechowski(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12418 -gerrit commit d0cf8385645aa97f0dcab93bf5ea14a6ff3a4341 Author: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> Date: Thu Nov 12 16:05:42 2015 +0100 update intel fsp1_0 rangeley files to revision: POSTGOLD3 Alligment of Intel Firmware Support Package 1.0 rangeley header and source files to the revision: POSTGOLD3 more info can be found here: http://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-s… Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> --- .../intel/fsp1_0/rangeley/include/fspguid.h | 69 +++++ .../intel/fsp1_0/rangeley/include/fspplatform.h | 3 +- .../intel/fsp1_0/rangeley/include/fspsupport.h | 95 +++++++ .../intel/fsp1_0/rangeley/include/fsptypes.h | 9 +- .../intel/fsp1_0/rangeley/include/fspvpd.h | 12 +- .../intel/fsp1_0/rangeley/srx/fsp_support.c | 288 +++++++++++++++++++++ 6 files changed, 468 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h new file mode 100644 index 0000000..22ff35d --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (C) 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_GUID_H__ +#define __FSP_GUID_H__ + +/** + + FSP specific GUID HOB definitions + + **/ +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { \ + 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + { \ + 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + { \ + 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ + } + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + { \ + 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ + } + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h index ce479bf..c35dca0 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013 - 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,6 +74,7 @@ typedef struct { UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin) + UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor UINT8 SDRAMDeviceType; // 33 SDRAM Device Type UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h new file mode 100644 index 0000000..39102fe --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h @@ -0,0 +1,95 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsptypes.h" +#include "fspfv.h" +#include "fspffs.h" +#include "fspapi.h" +#include "fsphob.h" +#include "fspguid.h" +#include "fspplatform.h" +#include "fspinfoheader.h" +#include "fspbootmode.h" +#include "fspvpd.h" + +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobListPtr + ); + +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobListPtr + ); + +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid + ); + +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *FspMemoryBase, + UINT64 *FspMemoryLength, + EFI_GUID *FspReservedMemoryGuid + ); + +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +VOID* +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h index 5912e01..3d2e663 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h @@ -100,13 +100,18 @@ typedef struct { #define TRUE ((BOOLEAN)(1==1)) #define FALSE ((BOOLEAN)(0==1)) +static inline void DebugDeadLoop(void) { + for (;;); +} + #define FSPAPI __attribute__((cdecl)) #define EFIAPI __attribute__((cdecl)) +#define _ASSERT(Expression) DebugDeadLoop() #define ASSERT(Expression) \ do { \ if (!(Expression)) { \ - for (;;); \ + _ASSERT (Expression); \ } \ } while (FALSE) @@ -175,4 +180,4 @@ typedef UINT32 EFI_STATUS; #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32)) -#endif +#endif \ No newline at end of file diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h index fba38a0..eefdb94 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,7 +50,8 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */ UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */ UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */ - UINT8 UnusedUpdSpace1[7]; /* Offset 0x0029 */ + UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */ + UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */ UINT8 PcdEnableLan; /* Offset 0x0030 */ UINT8 PcdEnableSata2; /* Offset 0x0031 */ UINT8 PcdEnableSata3; /* Offset 0x0032 */ @@ -65,13 +66,14 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */ + UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */ UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000102 +#define VPD_IMAGE_REV 0x00000130 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c new file mode 100644 index 0000000..6fe3eb0 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c @@ -0,0 +1,288 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#include <types.h> +#include <string.h> +#include "fspsupport.h" + +/** + This function retrieves the top of usable low memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable low memory top. + +**/ +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT32 MemLen; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemLen = 0x100000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemLen += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemLen; +} + +/** + This function retrieves the top of usable high memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable high memory top. + +**/ +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemTop; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemTop = 0x100000000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemTop += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemTop; +} + +/** + This function retrieves a special reserved memory region. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the GUID HOB is + located, the length will be updated. + @param OwnerGuid A pointer to the owner guild. + @retval Reserved region start address. 0 if this region does not exist. + +**/ +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *Base, + UINT64 *Length, + EFI_GUID *OwnerGuid +) +{ + EFI_PEI_HOB_POINTERS Hob; + + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobListPtr; + + /* + * Collect memory ranges + */ + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { + if (CompareGuid(&Hob.ResourceDescriptor->Owner, OwnerGuid)) { + *Base = (EFI_PHYSICAL_ADDRESS) (Hob.ResourceDescriptor->PhysicalStart); + *Length = (UINT64) (Hob.ResourceDescriptor->ResourceLength); + break; + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } +} + +/** + This function retrieves the TSEG reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the TSEG reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the TSEG reserved memory. + @retval others TSEG reserved memory base. + +**/ +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID TsegOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&TsegOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + +/** + This function retrieves the FSP reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the FSP reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the FSP reserved memory. + @retval others FSP reserved memory base. + +**/ +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&FspOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + + +/** + This function retrieves a GUIDed HOB data buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the + GUID HOB is located, the length will be updated. + @param Guid A pointer to HOB GUID. + @retval NULL Failed to find the GUID HOB. + @retval others GUID HOB data buffer pointer. + +**/ +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid +) +{ + UINT8 *GuidHob; + + /* FSP NVS DATA HOB */ + GuidHob = GetNextGuidHob(Guid, HobListPtr); + if (GuidHob == NULL) { + return NULL; + } else { + if (Length) { + *Length = GET_GUID_HOB_DATA_SIZE (GuidHob); + } + return GET_GUID_HOB_DATA (GuidHob); + } +} + +/** + This function retrieves FSP Non-volatile Storage HOB buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the NVS data buffer length. If the FSP NVS + HOB is located, the length will be updated. + @retval NULL Failed to find the NVS HOB. + @retval others FSP NVS data buffer pointer. + +**/ +VOID * +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspNvsHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspNvsHobGuid); +} + + +/** + This function retrieves Bootloader temporary stack buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the Bootloader temporary stack length. + If the HOB is located, the length will be updated. + @retval NULL Failed to find the Bootloader temporary stack HOB. + @retval others Bootloader temporary stackbuffer pointer. + +**/ +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspBootloaderTemporaryMemoryHobGuid); +}

1 0

Patch merged into coreboot/master: AMD/Mullins: Fix the interrupt routing
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 861f920cdfa1f8a322ecd2a56da8c8a9fdfd1155 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Nov 9 20:22:36 2015 +0800 AMD/Mullins: Fix the interrupt routing The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. run 'cat /proc/interrupts' to see if devices actually use no-msi. Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/12363 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/12363 for details. -gerrit

1 0

Patch merged into coreboot/master: AMD/Kabini: Fix the interrupt routing
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 266609968b94c9b739dedcb6861ea1b50f34be85 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Mon Nov 9 20:13:19 2015 +0800 AMD/Kabini: Fix the interrupt routing The plugged devices on PCIe should use IOAPIC2 instead of standard IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1. The unchanged code worked because the OS uses MSI instead APIC. To test that, boot linux with parameter pci=nomsi and see if the devices like NIC work well as they do without the booting parameter. run 'cat /proc/interrupts' to see if the devices actually use no-msi. Change-Id: Id6d35224312aeb6e3a175ec9990e0bb34bad67e7 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/12362 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/12362 for details. -gerrit

1 0

New patch to review for coreboot: northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
by Timothy Pearson 11 Nov '15

11 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12417 -gerrit commit 3c5127694d2b7d317015e84a01ced305948ee79b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 19:01:41 2015 -0600 northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration The existing prefetcher configuration was incorrect; use the correct values from the AMD Family 10h and Family 15h BKDGs as appropriate. Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f696dae..b3f43fb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2408,9 +2408,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } while (!(val & (1 << Dr_MemClrStatus))); } - val = 0x0FE40FC0; /* BKDG recommended */ + if (is_fam15h()) + val = 0x0ce00f41; /* BKDG recommended */ + else + val = 0x0fe40fc0; /* BKDG recommended */ val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(dev, 0x11C, val); + Set_NB32(dev, 0x11c, val); } static u8 NodePresent_D(u8 Node)

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2015