coreboot-gerrit November 2015

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Patch set updated for coreboot: southbridge/amd/sb700: Fix SATA port 4/5 drive detection
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12000 -gerrit commit c814e631dfce84f1e5d1bd9f24cea010dfcbdcee Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 22 02:56:10 2015 -0500 southbridge/amd/sb700: Fix SATA port 4/5 drive detection Change-Id: I01481f25189d01b6f4ed778902b2ecc4d39c7912 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 42 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 38 insertions(+), 4 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index a59708f..8ccc7b6 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -122,6 +122,8 @@ static void sata_init(struct device *dev) uint8_t port_count; uint8_t max_port_count; uint8_t hba_reset_count; + uint8_t ide_io_enabled; + uint8_t ide_legacy_io_enabled; sata_ahci_mode = 0; if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) @@ -166,15 +168,27 @@ retry_init: } } - /* Disable combined mode */ + /* Enable combined mode */ byte = pci_read_config8(sm_dev, 0xad); - byte &= ~(1 << 3); + byte |= (1 << 3); pci_write_config8(sm_dev, 0xad, byte); device_t ide_dev; /* IDE Device */ ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + /* Disable legacy IDE mode (enable PATA_BAR0/2) */ + byte = pci_read_config8(ide_dev, 0x09); + ide_legacy_io_enabled = !(byte & 0x1); + byte |= 0x1; + pci_write_config8(ide_dev, 0x09, byte); + + /* Enable IDE I/O access (enable PATA_BAR0/2) */ + byte = pci_read_config8(ide_dev, 0x04); + ide_io_enabled = byte & 0x1; + byte |= 0x1; + pci_write_config8(ide_dev, 0x04, byte); + /* RPR 7.2 SATA Initialization */ /* Set the interrupt Mapping to INTG# */ byte = pci_read_config8(sm_dev, 0xaf); @@ -421,7 +435,8 @@ retry_init: /* Disable SATA controller */ byte = pci_read_config8(sm_dev, 0xad); - byte &= ~(0x1); + byte &= ~(1 << 0); + byte &= ~(1 << 3); pci_write_config8(sm_dev, 0xad, byte); mdelay(100); @@ -456,8 +471,27 @@ retry_init: } } + /* Restore IDE I/O access */ + if (!ide_io_enabled) { + byte = pci_read_config8(ide_dev, 0x04); + byte &= ~0x1; + pci_write_config8(ide_dev, 0x04, byte); + } + + /* Re-enable legacy IDE mode */ + if (ide_legacy_io_enabled) { + byte = pci_read_config8(ide_dev, 0x09); + byte &= ~0x1; + pci_write_config8(ide_dev, 0x09, byte); + } + /* Below is CIM InitSataLateFar */ - if (!sata_ahci_mode) { + if (sata_ahci_mode) { + /* Disable combined mode */ + byte = pci_read_config8(sm_dev, 0xad); + byte &= ~(1 << 3); + pci_write_config8(sm_dev, 0xad, byte); + } else { /* Enable interrupts from the HBA */ byte = read8(sata_bar5 + 0x4); byte |= 1 << 1;

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Patch set updated for coreboot: southbridge/amd/sb700: Fix random persistent SATA AHCI drive detection failure
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12001 -gerrit commit ba41b9cfa9a172187574175e894370bf94379b44 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 22 20:57:39 2015 -0500 southbridge/amd/sb700: Fix random persistent SATA AHCI drive detection failure Change-Id: I4202a62217a7aaeaba07e4b994a350e83e064c9c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 81 +++++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 39 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 8ccc7b6..235278d 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -121,7 +121,6 @@ static void sata_init(struct device *dev) uint8_t sata_alpm_enable; uint8_t port_count; uint8_t max_port_count; - uint8_t hba_reset_count; uint8_t ide_io_enabled; uint8_t ide_legacy_io_enabled; @@ -137,14 +136,20 @@ static void sata_init(struct device *dev) /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); - hba_reset_count = 0; - -retry_init: + /* WARNING + * Enabling the SATA link latency enhancement (SMBUS 0xAD bit 5) + * causes random persistent drive detection failures until it is cleared, + * with the probabability of detection failure rising exponentially with + * the number of drives attached to the controller! + * This happens on Rev15 H/W. + * Do NOT follow the RPR advice; leave this bit set at all times... + */ byte = pci_read_config8(sm_dev, 0xad); /* Disable SATA SMBUS */ byte |= (1 << 1); /* Enable SATA and power saving */ byte |= (1 << 0); + /* Disable link latency enhancement */ byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte); @@ -159,15 +164,6 @@ retry_init: printk(BIOS_SPEW, "rev_id=%x\n", rev_id); - if (sata_ahci_mode) { - /* Enable link latency enhancement on A14 and above */ - if (rev_id >= 0x14) { - byte = pci_read_config8(sm_dev, 0xad); - byte &= ~(1 << 5); - pci_write_config8(sm_dev, 0xad, byte); - } - } - /* Enable combined mode */ byte = pci_read_config8(sm_dev, 0xad); byte |= (1 << 3); @@ -281,6 +277,17 @@ retry_init: write32(sata_bar5 + 0xfc, dword); } + /* Enable SATA ports */ + byte = pci_read_config8(dev, 0x42); + if (max_port_count <= 6) { + byte |= 0x3f; + for (i = 0; i < max_port_count; i++) + byte &= ~(0x1 << i); + } else { + byte &= ~0x3f; + } + pci_write_config8(dev, 0x42, byte); + if (sata_ahci_mode) { /* FIXME * SeaBIOS does not know how to spin @@ -302,6 +309,9 @@ retry_init: write32(sata_bar5 + 0x04, dword); } + sb7xx_51xx_setup_sata_phys(dev); + sb7xx_51xx_setup_sata_port_indication(sata_bar5); + /* Write protect Sub-Class Code */ byte = pci_read_config8(dev, 0x40); byte &= ~(1 << 0); @@ -327,7 +337,7 @@ retry_init: else { dword &= ~(1 << 24 | 1 << 21); /* A14 and above */ dword &= ~0xFF80; /* 15:7 */ - dword |= 1 << 15 | 0x7F << 7; + dword |= 1 << 15 | 0x7F << 7 | 1 << 6; } pci_write_config32(dev, 0x48, dword); @@ -335,9 +345,6 @@ retry_init: byte = 0x10; pci_write_config8(dev, 0x46, byte); - sb7xx_51xx_setup_sata_phys(dev); - sb7xx_51xx_setup_sata_port_indication(sata_bar5); - /* Enable the I/O, MM, BusMaster access for SATA */ byte = pci_read_config8(dev, 0x4); byte |= 7 << 0; @@ -422,32 +429,28 @@ retry_init: if (i < 4) current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; else - current_bar = ide_bar0; + current_bar = (pci_read_config8(sm_dev, 0xad) & (0x1 << 4)) + ? ide_bar2 : ide_bar0; ret = sata_drive_detect(i, current_bar); if (ret == 0) { break; } else if (ret == 2) { - /* Reset PHY logic */ - word = pci_read_config16(dev, 0x84); - word &= ~(0x1 << 2); - word |= 0x1f8; - pci_write_config16(dev, 0x84, word); - - /* Disable SATA controller */ - byte = pci_read_config8(sm_dev, 0xad); - byte &= ~(1 << 0); - byte &= ~(1 << 3); - pci_write_config8(sm_dev, 0xad, byte); - - mdelay(100); - - /* Retry initialization */ - hba_reset_count++; - if (hba_reset_count < 16) - goto retry_init; - else - printk(BIOS_WARNING, "HBA reset count exceeded, " - "continuing but AHCI drives may not function\n"); + /* Read in Port-N Serial ATA Control Register */ + byte = read8(sata_bar5 + 0x12C + 0x80 * i); + + /* Set Reset Bit */ + byte |= 0x1; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1000ms */ + mdelay(1000); + + /* Clear Reset Bit */ + byte &= ~0x01; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); } } if (sata_ahci_mode)

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Patch merged into coreboot/master: src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startup
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 14ebf951e41c085aa2f8420fcf7452dc5761514e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Jun 21 16:27:03 2015 -0500 src/southbridge/amd/sb700: Reset SATA controller in AHCI mode during startup In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts), with the probability of a failure increasing with the number of disks connected to the controller. Resetting the SATA controller appears to show the true state of the underlying hardware, allowing the drive detection code to attempt link renegotiation as needed. Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11998 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/11998 for details. -gerrit

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Patch merged into coreboot/master: southbridge/amd/sb700: Do drive detection even in AHCI mode
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 398540f568e24090f2e47aff90776c80c79f858b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 21:31:15 2015 -0500 southbridge/amd/sb700: Do drive detection even in AHCI mode SeaBIOS AHCI drive detection randomly fails for drives present on the secondary channel of each AHCI SATA BAR. Forcing native drive detection in AHCI mode resolves this issue. Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11997 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11997 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Add sata_alpm CMOS option
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 795ee1a6cd45b9f8a791d4624eadb1b73414cede Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 14:04:40 2015 -0600 mainboard/asus/kgpe-d16: Add sata_alpm CMOS option Change-Id: I2f2658eb8b3142c86fef4ee50792f51954686cca Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12409 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12409 for details. -gerrit

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Patch merged into coreboot/master: mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS option
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit ef62eacb3bf23cca6a089924b2d629335b91bcd9 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 14:07:10 2015 -0600 mainboard/asus/kgpe-d16: Add dimm_spd_checksum CMOS option Change-Id: I12323d76ab90f643f4dd4351d7e99824ec24f9be Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12408 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> See http://review.coreboot.org/12408 for details. -gerrit

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Patch merged into coreboot/master: src/northbridge/amd/amdmct: Add option to override bad SPD checksum
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit f3b9fd32658a9a6788b87431464b84cda3c3c24b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 11 16:14:15 2015 -0500 src/northbridge/amd/amdmct: Add option to override bad SPD checksum Certain DIMMs, for example DIMMs on which the EEPROM has been modified by the end user, may not contain a valid SPD checksum. While this is not a normal condition, it may be useful to allow a checksum override while memory timing parameters are being altered, e.g. in the course of overclocking or underclocking, or when recovering from a bad SPD write. This is an advanced level feature primarily useful for debugging and development. Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11987 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/11987 for details. -gerrit

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Patch set updated for coreboot: mb/roda/rk9: Fix cbmem recovery on resume path
by Nico Huber 12 Nov '15

12 Nov '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12420 -gerrit commit fcdaf7a398143f4590b3023ccde426a7fcf55390 Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Nov 12 20:16:18 2015 +0100 mb/roda/rk9: Fix cbmem recovery on resume path By calling cbmem_recovery() with `0`, we rewrote the cbmem table even on the resume path. By that, we lost the OS' resume vector and ended up loading the payload. Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/mainboard/roda/rk9/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 4066240..e055be9 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -186,7 +186,7 @@ void main(unsigned long bist) init_iommu(); - cbmem_initted = !cbmem_recovery(0); + cbmem_initted = !cbmem_recovery(s3resume); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc.

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New patch to review for coreboot: [WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUME
by Nico Huber 12 Nov '15

12 Nov '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12421 -gerrit commit 7c07563b4484800cff079d1c6cbd62ccadaf7597 Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Nov 12 20:19:49 2015 +0100 [WIP] mb/roda/rk9: Enable CONFIG_HAVE_ACPI_RESUME Change-Id: Ifa7dd593f70921a99d937104960e26100de28089 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/mainboard/roda/rk9/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index a17717a..debed16 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select EC_ACPI select HAVE_OPTION_TABLE select INTEL_INT15

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New patch to review for coreboot: mb/roda/rk9: Fix cbmem recovery on resume path
by Nico Huber 12 Nov '15

12 Nov '15

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12420 -gerrit commit 86328f6450a803f5053efc4f6293c651f991a747 Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Nov 12 20:16:18 2015 +0100 mb/roda/rk9: Fix cbmem recovery on resume path Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/mainboard/roda/rk9/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 4066240..e055be9 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -186,7 +186,7 @@ void main(unsigned long bist) init_iommu(); - cbmem_initted = !cbmem_recovery(0); + cbmem_initted = !cbmem_recovery(s3resume); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc.

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coreboot-gerrit November 2015