coreboot-gerrit November 2015

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New patch to review for coreboot: x86: Add Kconfig to disable early bootblock postcodes
by Martin Roth 12 Nov '15

12 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12422 -gerrit commit dadfbfd7a5c87cfee9e38ebb4d29a2eff08f6346 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:02:42 2015 -0700 x86: Add Kconfig to disable early bootblock postcodes The Intel cave creek chipset needs to have port 80 routing configured before any post codes can be sent to port 80h. Sending post codes out before the routing is done will hang the system. This patch allows us to disable the first couple of post codes that go out before the routing can be configured. Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/console/Kconfig | 9 +++++++++ src/cpu/x86/16bit/entry16.inc | 3 ++- src/cpu/x86/32bit/entry32.inc | 2 ++ src/southbridge/intel/fsp_i89xx/Kconfig | 1 + 4 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index a2f893a..6776922 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -350,4 +350,13 @@ config POST_IO_PORT depending on the presence of coprocessors/microcontrollers or if the platform does not support IO in the conventional x86 manner. +config NO_EARLY_BOOTBLOCK_POSTCODES + def_bool n + help + Some chipsets require that the routing for the port 80h post + code port be configured before port 80h post codes are sent out. + This can be done in the boot block, but there are a couple of + post codes that go out before the chipset's bootblock initialization + can happen. This option suppresses those post codes. + endmenu diff --git a/src/cpu/x86/16bit/entry16.inc b/src/cpu/x86/16bit/entry16.inc index 4dad1e5..0480ee6 100644 --- a/src/cpu/x86/16bit/entry16.inc +++ b/src/cpu/x86/16bit/entry16.inc @@ -36,8 +36,9 @@ _start: cli /* Save the BIST result */ movl %eax, %ebp - +#if ! IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_RESET_VECTOR_CORRECT) +#endif /* IMMEDIATELY invalidate the translation lookaside buffer (TLB) before * executing any further code. Even though paging is disabled we diff --git a/src/cpu/x86/32bit/entry32.inc b/src/cpu/x86/32bit/entry32.inc index 5c3072e..7f6af53 100644 --- a/src/cpu/x86/32bit/entry32.inc +++ b/src/cpu/x86/32bit/entry32.inc @@ -56,7 +56,9 @@ __protected_start: /* Save the BIST value */ movl %eax, %ebp +#if ! IS_ENABLED(CONFIG_NO_EARLY_BOOTBLOCK_POSTCODES) post_code(POST_ENTER_PROTECTED_MODE) +#endif movw $ROM_DATA_SEG, %ax movw %ax, %ds diff --git a/src/southbridge/intel/fsp_i89xx/Kconfig b/src/southbridge/intel/fsp_i89xx/Kconfig index d1426d6..9d195d2 100644 --- a/src/southbridge/intel/fsp_i89xx/Kconfig +++ b/src/southbridge/intel/fsp_i89xx/Kconfig @@ -34,6 +34,7 @@ config SOUTH_BRIDGE_OPTIONS # dummy select SPI_FLASH select COMMON_FADT select HAVE_INTEL_FIRMWARE + select NO_EARLY_BOOTBLOCK_POSTCODES config EHCI_BAR hex

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Patch set updated for coreboot: northbridge/amd/amdmct: Clear memory before enabling ECC
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11996 -gerrit commit b61f3197515d88c46b04b6e5619c505482cb781e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Jun 20 20:02:49 2015 -0500 northbridge/amd/amdmct: Clear memory before enabling ECC Change-Id: I992e7040520570893ba6a213138dd57bfa14733b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 38 ++++++-------------------- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 38 +++++++++++++++++++++++++- 2 files changed, 46 insertions(+), 30 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4bfb08a..f696dae 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -47,8 +47,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA); static u8 NodePresent_D(u8 Node); static void SyncDCTsReady_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); @@ -1507,10 +1505,11 @@ restartinit: InterleaveChannels_D(pMCTstat, pDCTstatA); printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n"); - if (ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat,pDCTstatA); - } + ECCInit_D(pMCTstat, pDCTstatA); /* Setup ECC control and ECC check-bits*/ + + /* mctDoWarmResetMemClr_D(); */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); + MCTMemClr_D(pMCTstat,pDCTstatA); printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -2102,9 +2101,6 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ mctHookAfterAnyTraining(); - - /* mctDoWarmResetMemClr_D(); */ - MCTMemClr_D(pMCTstat, pDCTstatA); } static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat, @@ -2392,26 +2388,6 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, } } -static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstatA) -{ - /* Ensures that memory clear has completed on all node.*/ - u8 Node; - struct DCTStatStruc *pDCTstat; - - if (!mctGet_NVbits(NV_DQSTrainCTL)){ - /* callback to wrapper: mctDoWarmResetMemClr_D */ - } else { /* NV_DQSTrainCTL == 1 */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - pDCTstat = pDCTstatA + Node; - - if (pDCTstat->NodePresent) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - } - } -} - static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -3097,6 +3073,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, u16 proposedFreq; u16 word; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + /* Get CPU Si Revision defined limit (NPT) */ if (is_fam15h()) proposedFreq = 933; @@ -3121,6 +3099,8 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat, pDCTstat->PresetmaxFreq = word; } /* Check F3xE8[DdrMaxRate] for maximum DRAM data rate support */ + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 6ab33a3..8701bae 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,6 +84,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits; + uint32_t dword; + uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; + uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; + mctHookBeforeECC(); /* Construct these booleans, based on setup options, for easy handling @@ -107,6 +111,25 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) nvbits = mctGet_NVbits(NV_DramBKScrub); OF_ScrubCTL |= nvbits; + /* Prevent lockups on DRAM errors during ECC init */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + sync_flood_on_dram_err[Node] = (dword >> 30) & 0x1; + sync_flood_on_any_uc_err[Node] = (dword >> 21) & 0x1; + dword &= ~(0x1 << 30); + dword &= ~(0x1 << 21); + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ + DCTMemClr_Init_D(pMCTstat, pDCTstat); + DCTMemClr_Sync_D(pMCTstat, pDCTstat); + } + } + AllECC = 1; MemClrECC = 0; for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -153,7 +176,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* Node has Dram */ if (MemClrECC) { - MCTMemClrSync_D(pMCTstat, pDCTstatA); + DCTMemClr_Sync_D(pMCTstat, pDCTstat); } if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { @@ -166,6 +189,19 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } /* if Node present */ } + /* Restore previous MCA error handling settings */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; + dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } + } + if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else

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Patch set updated for coreboot: southbridge/amd/sb700: Recover if AHCI disk detection fails
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11999 -gerrit commit f7aa3387e1d1ea1425ac537aa2f238d7badcb38c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Mon Jun 22 02:21:29 2015 -0500 southbridge/amd/sb700: Recover if AHCI disk detection fails Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sata.c | 83 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 75 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sb700/sata.c b/src/southbridge/amd/sb700/sata.c index 63c07d8..a59708f 100644 --- a/src/southbridge/amd/sb700/sata.c +++ b/src/southbridge/amd/sb700/sata.c @@ -27,12 +27,15 @@ static int sata_drive_detect(int portnum, uint16_t iobar) { u8 byte, byte2; + u8 byte_prev, byte2_prev; int i = 0; + byte_prev = byte2_prev = 0; outb(0xa0 + 0x10 * (portnum % 2), iobar + 0x6); while (byte = inb(iobar + 0x6), byte2 = inb(iobar + 0x7), (byte != (0xa0 + 0x10 * (portnum % 2))) || ((byte2 & 0x88) != 0)) { - printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); + if ((byte != byte_prev) || (byte2 != byte2_prev)) + printk(BIOS_SPEW, "0x6=%x, 0x7=%x\n", byte, byte2); if (byte != (0xa0 + 0x10 * (portnum % 2))) { /* This will happen at the first iteration of this loop * if the first SATA port is unpopulated and the @@ -41,11 +44,22 @@ static int sata_drive_detect(int portnum, uint16_t iobar) printk(BIOS_DEBUG, "drive no longer selected after %i ms, " "retrying init\n", i * 10); return 1; - } else - printk(BIOS_SPEW, "drive detection not yet completed, " - "waiting...\n"); + } else { + if (i == 0) + printk(BIOS_SPEW, "drive detection not yet completed, " + "waiting...\n"); + } mdelay(10); i++; + byte_prev = byte; + byte2_prev = byte2; + + /* Detect stuck SATA controller and attempt reset */ + if (i > 1024) { + printk(BIOS_DEBUG, "drive detection not done after %i ms, " + "resetting HBA and retrying init\n", i * 10); + return 2; + } } printk(BIOS_SPEW, "drive detection done after %i ms\n", i * 10); return 0; @@ -101,12 +115,13 @@ static void sata_init(struct device *dev) uint16_t sata_bar0, sata_bar1, sata_bar2, sata_bar3, sata_bar4; uint16_t ide_bar0, ide_bar1, ide_bar2, ide_bar3; uint16_t current_bar; - int i, j; + int i, j, ret; uint8_t nvram; uint8_t sata_ahci_mode; uint8_t sata_alpm_enable; uint8_t port_count; uint8_t max_port_count; + uint8_t hba_reset_count; sata_ahci_mode = 0; if (get_option(&nvram, "sata_ahci_mode") == CB_SUCCESS) @@ -120,14 +135,23 @@ static void sata_init(struct device *dev) /* SATA SMBus Disable */ sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + hba_reset_count = 0; + +retry_init: byte = pci_read_config8(sm_dev, 0xad); /* Disable SATA SMBUS */ - byte |= (1 << 0); - /* Enable SATA and power saving */ byte |= (1 << 1); + /* Enable SATA and power saving */ + byte |= (1 << 0); byte |= (1 << 5); pci_write_config8(sm_dev, 0xad, byte); + /* Take the PHY logic out of reset */ + word = pci_read_config16(dev, 0x84); + word |= 0x1 << 2; + word &= ~0x1f8; + pci_write_config16(dev, 0x84, word); + /* get rev_id */ rev_id = pci_read_config8(sm_dev, 0x08) - 0x28; @@ -320,6 +344,26 @@ static void sata_init(struct device *dev) if (port_count > max_port_count) port_count = max_port_count; + /* Send COMRESET to all ports */ + for (i = 0; i < port_count; i++) { + /* Read in Port-N Serial ATA Control Register */ + byte = read8(sata_bar5 + 0x12C + 0x80 * i); + + /* Set Reset Bit */ + byte |= 0x1; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + + /* Clear Reset Bit */ + byte &= ~0x01; + write8((sata_bar5 + 0x12C + 0x80 * i), byte); + + /* Wait 1ms */ + mdelay(1); + } + /* RPR7.7 SATA drive detection. */ /* Use BAR5+0x128,BAR0 for Primary Slave */ /* Use BAR5+0x1A8,BAR0 for Primary Slave */ @@ -365,8 +409,31 @@ static void sata_init(struct device *dev) current_bar = ((i / 2) == 0) ? sata_bar0 : sata_bar2; else current_bar = ide_bar0; - if (!sata_drive_detect(i, current_bar)) + ret = sata_drive_detect(i, current_bar); + if (ret == 0) { break; + } else if (ret == 2) { + /* Reset PHY logic */ + word = pci_read_config16(dev, 0x84); + word &= ~(0x1 << 2); + word |= 0x1f8; + pci_write_config16(dev, 0x84, word); + + /* Disable SATA controller */ + byte = pci_read_config8(sm_dev, 0xad); + byte &= ~(0x1); + pci_write_config8(sm_dev, 0xad, byte); + + mdelay(100); + + /* Retry initialization */ + hba_reset_count++; + if (hba_reset_count < 16) + goto retry_init; + else + printk(BIOS_WARNING, "HBA reset count exceeded, " + "continuing but AHCI drives may not function\n"); + } } if (sata_ahci_mode) printk(BIOS_DEBUG, "AHCI device %d is %sready after %i tries\n",

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Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12417 -gerrit commit 592f9d2ae2ac17c3f42aac7f8c34224bdbb29f01 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Nov 11 19:01:41 2015 -0600 northbridge/amd/amdmct/mct_ddr3: Update prefetcher configuration The existing prefetcher configuration was incorrect; use the correct values from the AMD Family 10h and Family 15h BKDGs as appropriate. Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index f696dae..b3f43fb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2408,9 +2408,12 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, } while (!(val & (1 << Dr_MemClrStatus))); } - val = 0x0FE40FC0; /* BKDG recommended */ + if (is_fam15h()) + val = 0x0ce00f41; /* BKDG recommended */ + else + val = 0x0fe40fc0; /* BKDG recommended */ val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(dev, 0x11C, val); + Set_NB32(dev, 0x11c, val); } static u8 NodePresent_D(u8 Node)

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Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12006 -gerrit commit 1cc17122153c17187db7ffbd60c83cb195c0ed82 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 18:08:53 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 68 +++++++++++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 36 +++++++++++--- 2 files changed, 83 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 5107fee..b3572b1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ -static void AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, +static uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -static void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, +static uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -static void AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, +static uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); static void EnableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void DisableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -96,11 +96,12 @@ static void DisableAutoRefresh_D(struct MCTStatStruc *pMCTstat, } -static void PhyWLPass1(struct MCTStatStruc *pMCTstat, +static uint8_t PhyWLPass1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 dimm; u16 DIMMValid; + uint8_t status = 0; void *DCTPtr; dct &= 1; @@ -117,19 +118,22 @@ static void PhyWLPass1(struct MCTStatStruc *pMCTstat, PrepareC_DCT(pMCTstat, pDCTstat, dct); for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm ++) { if (DIMMValid & (1 << (dimm << 1))) { - AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, FirstPass); - AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, FirstPass); - AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, FirstPass); + status |= AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, FirstPass); + status |= AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, FirstPass); + status |= AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, FirstPass); } } } + + return status; } -static void PhyWLPass2(struct MCTStatStruc *pMCTstat, +static uint8_t PhyWLPass2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 dimm; u16 DIMMValid; + uint8_t status = 0; void *DCTPtr; dct &= 1; @@ -159,12 +163,14 @@ static void PhyWLPass2(struct MCTStatStruc *pMCTstat, DisableAutoRefresh_D(pMCTstat, pDCTstat); for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm ++) { if (DIMMValid & (1 << (dimm << 1))) { - AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, SecondPass); - AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, SecondPass); - AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, SecondPass); + status |= AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, SecondPass); + status |= AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, SecondPass); + status |= AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, SecondPass); } } } + + return status; } static uint16_t fam15h_next_highest_memclk_freq(uint16_t memclk_freq) @@ -179,6 +185,8 @@ static uint16_t fam15h_next_highest_memclk_freq(uint16_t memclk_freq) static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t Pass) { + uint8_t status; + uint8_t timeout; uint16_t final_target_freq; pDCTstat->C_MCTPtr = &(pDCTstat->s_C_MCTPtr); @@ -197,8 +205,21 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, } if (Pass == FirstPass) { - PhyWLPass1(pMCTstat, pDCTstat, 0); - PhyWLPass1(pMCTstat, pDCTstat, 1); + timeout = 0; + do { + status = 0; + timeout++; + status |= PhyWLPass1(pMCTstat, pDCTstat, 0); + status |= PhyWLPass1(pMCTstat, pDCTstat, 1); + if (status) + printk(BIOS_INFO, + "%s: Retrying write levelling due to invalid value(s) detected in first phase\n", + __func__); + } while (status && (timeout < 8)); + if (status) + printk(BIOS_INFO, + "%s: Uncorrectable invalid value(s) detected in first phase of write levelling\n", + __func__); } if (Pass == SecondPass) { @@ -207,6 +228,7 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, * NOTE: BIOS must program both DCTs to the same frequency. * NOTE: Fam15h steps the frequency, Fam10h slams the frequency. */ + uint8_t global_phy_training_status = 0; final_target_freq = pDCTstat->TargetFreq; while (pDCTstat->Speed != final_target_freq) { @@ -215,12 +237,28 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, else pDCTstat->TargetFreq = final_target_freq; SetTargetFreq(pMCTstat, pDCTstat); - PhyWLPass2(pMCTstat, pDCTstat, 0); - PhyWLPass2(pMCTstat, pDCTstat, 1); + timeout = 0; + do { + status = 0; + timeout++; + status |= PhyWLPass2(pMCTstat, pDCTstat, 0); + status |= PhyWLPass2(pMCTstat, pDCTstat, 1); + if (status) + printk(BIOS_INFO, + "%s: Retrying write levelling due to invalid value(s) detected in last phase\n", + __func__); + } while (status && (timeout < 8)); + global_phy_training_status |= status; } pDCTstat->TargetFreq = final_target_freq; + if (global_phy_training_status) + printk(BIOS_WARNING, + "%s: Uncorrectable invalid value(s) detected in second phase of write levelling; " + "continuing but system may be unstable!\n", + __func__); + uint8_t dct; for (dct = 0; dct < 2; dct++) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 48b72ca..496803e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -50,7 +50,7 @@ static int32_t abs(int32_t val) { */ /*----------------------------------------------------------------------------- - * void AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, + * uint8_t AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, * u8 Dimm, u8 Pass) * * Description: @@ -67,7 +67,7 @@ static int32_t abs(int32_t val) { * OUT *----------------------------------------------------------------------------- */ -void AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, +uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass) { u8 ByteLane; @@ -170,12 +170,15 @@ void AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta } pDCTData->WLCriticalGrossDelayPrevPass = 0x1f; + + return 0; } -void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, +uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass) { u8 ByteLane; + uint8_t status = 0; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; if (is_fam15h()) { @@ -202,19 +205,38 @@ void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta /* Compensate for occasional noise/instability causing sporadic training failure */ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + uint8_t faulty_value_detected = 0; uint16_t total_delay_seed = ((pDCTData->WLSeedGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLSeedFineDelay[index+ByteLane] & 0x1f); uint16_t total_delay_phy = ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f); - if (abs(total_delay_phy - total_delay_seed) > 0x20) { - printk(BIOS_DEBUG, "%s: overriding faulty phy value (seed: %04x phy: %04x step: %04x)\n", __func__, + if (pass == FirstPass) { + /* Allow a somewhat higher step threshold on the first pass + * For the most part, as long as the phy isn't stepping + * several clocks at once the values are probably valid. + */ + if (abs(total_delay_phy - total_delay_seed) > 0x30) + faulty_value_detected = 1; + } else { + /* Stepping memory clocks between adjacent allowed frequencies + * should not yield large phy value differences... + */ + + if (abs(total_delay_phy - total_delay_seed) > 0x20) + faulty_value_detected = 1; + } + if (faulty_value_detected) { + printk(BIOS_INFO, "%s: overriding faulty phy value (seed: %04x phy: %04x step: %04x)\n", __func__, total_delay_seed, total_delay_phy, abs(total_delay_phy - total_delay_seed)); pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; + status = 1; } } } + + return status; } -void AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, +uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass) { u8 ByteLane; @@ -281,6 +303,8 @@ void AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta * to the normal operating termination: */ prepareDimms(pMCTstat, pDCTstat, dct, dimm, FALSE); + + return 0; } /*----------------------------------------------------------------------------

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12007 -gerrit commit 07891ec97f952dff9f5b46abb4846d004d35daa2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 18:37:45 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 496803e..dfddb60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -203,6 +203,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT pDCTData->WLCriticalGrossDelayPrevPass = cgd; + if (pDCTstat->Speed != pDCTstat->TargetFreq) { + /* FIXME + * Using the Pass 1 training values causes major phy training problems on + * all Family 15h processors I tested (Pass 1 values are randomly too high, + * and Pass 2 cannot lock). + * Figure out why this is and fix it, then remove the bypass code below... + */ + if (pass == FirstPass) { + for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; + pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; + } + return 0; + } + } + /* Compensate for occasional noise/instability causing sporadic training failure */ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { uint8_t faulty_value_detected = 0;

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12004 -gerrit commit 29358c12c0179c15c3608783d2387d76eab6aa07 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 15:28:23 2015 -0500 northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 ++++++- src/northbridge/amd/amdmct/mct/mct_d.c | 12 ++++++++++++ src/northbridge/amd/amdmct/mct/mct_d.h | 7 +++++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +++++--- 5 files changed, 40 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 0c1971b..a922496 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1203,7 +1203,12 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, t->attributes = 0; t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 4 bits of the attributes field */ t->form_factor = MEMORY_FORMFACTOR_DIMM; - snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); + if (mem_info->dct_stat[node].Dual_Node_Package) { + snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node >> 1, + (mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1); + } else { + snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); + } t->device_locator = smbios_add_string(t->eos, string_buffer); if (IS_ENABLED(CONFIG_DIMM_DDR2)) t->memory_type = MEMORY_TYPE_DDR2; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 91d929a..0e59e1d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -232,6 +232,18 @@ restartinit: pDCTstat->dev_nbmisc = PA_NBMISC(Node); pDCTstat->NodeSysBase = node_sys_base; + if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) { + uint32_t dword; + pDCTstat->Dual_Node_Package = 1; + + /* Get the internal node number */ + dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); + dword = (dword >> 30) & 0x3; + pDCTstat->Internal_Node_ID = dword; + } else { + pDCTstat->Dual_Node_Package = 0; + } + print_tx("mctAutoInitMCT_D: mct_init Node ", Node); mct_init(pMCTstat, pDCTstat); mctNodeIDDebugPort_D(); diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 3845a87..552681f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -287,8 +287,11 @@ struct MCTStatStruc { struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ - u8 Node_ID; /* Node ID of current controller*/ - u8 ErrCode; /* Current error condition of Node + u8 Node_ID; /* Node ID of current controller*/ + uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ + uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t stopDCT; /* Set if the DCT will be stopped */ + u8 ErrCode; /* Current error condition of Node 0= no error 1= Variance Error, DCT is running but not in an optimal configuration. 2= Stop Error, DCT is NOT running diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 229073b..de0a508 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1396,6 +1396,18 @@ restartinit: pDCTstat->dev_nbctl = PA_NBCTL(Node); pDCTstat->NodeSysBase = node_sys_base; + if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) { + uint32_t dword; + pDCTstat->Dual_Node_Package = 1; + + /* Get the internal node number */ + dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); + dword = (dword >> 30) & 0x3; + pDCTstat->Internal_Node_ID = dword; + } else { + pDCTstat->Dual_Node_Package = 0; + } + printk(BIOS_DEBUG, "%s: mct_init Node %d\n", __func__, Node); mct_init(pMCTstat, pDCTstat); mctNodeIDDebugPort_D(); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index ffbad2b..8b8caca 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -331,9 +331,11 @@ struct amd_spd_node_data { struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ - u8 Node_ID; /* Node ID of current controller */ - uint8_t stopDCT; /* Set if the DCT will be stopped */ - u8 ErrCode; /* Current error condition of Node + u8 Node_ID; /* Node ID of current controller */ + uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ + uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t stopDCT; /* Set if the DCT will be stopped */ + u8 ErrCode; /* Current error condition of Node 0= no error 1= Variance Error, DCT is running but not in an optimal configuration. 2= Stop Error, DCT is NOT running

1 0

Patch set updated for coreboot: amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12005 -gerrit commit 2a6d3dc1f1e260b77ea4ad8d670af9af23e65d98 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 17:07:57 2015 -0500 amd/amdmct/mct_ddr3: Add Family 15h RDIMM timing and ODT values Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 422 +++++++++++++++++++--------- 1 file changed, 290 insertions(+), 132 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index de0a508..fa32901 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -828,28 +828,12 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT if (package_type == PT_GR) { /* Socket G34 */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ - if (MaxDimmsInstallable == 1) { - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00112222; - } - else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x10112222; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x20112222; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - calibration_code = 0x30112222; - } else if (MemClkFreq == 0x16) { - /* DDR3-1866 */ - calibration_code = 0x30332222; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ + if (pDCTstat->Status & (1 << SB_Registered)) { + /* RDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + if (MemClkFreq == 0x4) { /* DDR3-667 */ calibration_code = 0x00112222; @@ -862,36 +846,137 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { /* DDR3-1333 - DDR3-1600 */ calibration_code = 0x30112222; + } else if (MemClkFreq == 0x16) { + /* DDR3-1866 */ + calibration_code = 0x30332222; } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ + + if (rank_count_dimm0 == 4) { + calibration_code &= ~(0xff << 16); + calibration_code |= 0x22 << 16; + } + } else if (MaxDimmsInstallable == 2) { rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + if (dimm_count == 1) { + /* 1 DIMM detected */ + if (MemClkFreq == 0x4) { + /* DDR3-667 */ + calibration_code = 0x00112222; + } else if (MemClkFreq == 0x6) { + /* DDR3-800 */ + calibration_code = 0x10112222; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x20112222; + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + /* DDR3-1333 - DDR3-1600 */ + calibration_code = 0x30112222; + } + + if ((rank_count_dimm0 == 4) || (rank_count_dimm1 == 4)) { + calibration_code &= ~(0xff << 16); + calibration_code |= 0x22 << 16; + } + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; + rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + + if (MemClkFreq == 0x4) { + /* DDR3-667 */ + calibration_code = 0x10222222; + } else if (MemClkFreq == 0x6) { + /* DDR3-800 */ + calibration_code = 0x20222222; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x30222222; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x30222222; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + calibration_code = 0x30222222; + } + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + /* TODO + * LRDIMM support unimplemented + */ + } else { + /* UDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ + if (MaxDimmsInstallable == 1) { if (MemClkFreq == 0x4) { /* DDR3-667 */ - calibration_code = 0x10222222; + calibration_code = 0x00112222; } else if (MemClkFreq == 0x6) { /* DDR3-800 */ - calibration_code = 0x20222222; + calibration_code = 0x10112222; } else if (MemClkFreq == 0xa) { /* DDR3-1066 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x30222222; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - calibration_code = 0x30222222; - else - calibration_code = 0x30112222; + calibration_code = 0x20112222; + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + /* DDR3-1333 - DDR3-1600 */ + calibration_code = 0x30112222; + } else if (MemClkFreq == 0x16) { + /* DDR3-1866 */ + calibration_code = 0x30332222; } + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + if (MemClkFreq == 0x4) { + /* DDR3-667 */ + calibration_code = 0x00112222; + } else if (MemClkFreq == 0x6) { + /* DDR3-800 */ + calibration_code = 0x10112222; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x20112222; + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + /* DDR3-1333 - DDR3-1600 */ + calibration_code = 0x30112222; + } + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; + rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + + if (MemClkFreq == 0x4) { + /* DDR3-667 */ + calibration_code = 0x10222222; + } else if (MemClkFreq == 0x6) { + /* DDR3-800 */ + calibration_code = 0x20222222; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x30222222; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x30222222; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) + calibration_code = 0x30222222; + else + calibration_code = 0x30112222; + } + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ } } else { /* TODO @@ -923,41 +1008,69 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC if (package_type == PT_GR) { /* Socket G34 */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; - - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - if (rank_count_dimm0 == 1) + if (pDCTstat->Status & (1 << SB_Registered)) { + /* RDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ + if (MaxDimmsInstallable == 1) { + if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { + /* DDR3-667 - DDR3-800*/ calibration_code = 0x00000000; - else - calibration_code = 0x003b0000; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x00383837; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00363635; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if (rank_count_dimm0 == 1) - calibration_code = 0x00353533; - else - calibration_code = 0x00003533; - } else if (MemClkFreq == 0x16) { - /* DDR3-1866 */ - calibration_code = 0x00333330; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x003c3c3c; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x003a3a3a; + } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { + /* DDR3-1600 - DDR3-1866 */ + calibration_code = 0x00393939; + } + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { + /* DDR3-667 - DDR3-800*/ + calibration_code = 0x00000000; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x00393c39; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x00373a37; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + calibration_code = 0x00363936; + } + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6)) { + /* DDR3-667 - DDR3-800*/ + calibration_code = 0x00000000; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x003a3c3a; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x00383a38; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + calibration_code = 0x00353935; + } + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ + } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + /* TODO + * LRDIMM support unimplemented + */ + } else { + /* UDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ + if (MaxDimmsInstallable == 1) { rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; if (MemClkFreq == 0x4) { @@ -984,34 +1097,68 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC calibration_code = 0x00353533; else calibration_code = 0x00003533; + } else if (MemClkFreq == 0x16) { + /* DDR3-1866 */ + calibration_code = 0x00333330; } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + + if (MemClkFreq == 0x4) { + /* DDR3-667 */ + if (rank_count_dimm0 == 1) + calibration_code = 0x00000000; + else + calibration_code = 0x003b0000; + } else if (MemClkFreq == 0x6) { + /* DDR3-800 */ + if (rank_count_dimm0 == 1) + calibration_code = 0x00000000; + else + calibration_code = 0x003b0000; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x00383837; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x00363635; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + if (rank_count_dimm0 == 1) + calibration_code = 0x00353533; + else + calibration_code = 0x00003533; + } + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; + rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; - if (MemClkFreq == 0x4) { - /* DDR3-667 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0x6) { - /* DDR3-800 */ - calibration_code = 0x00390039; - } else if (MemClkFreq == 0xa) { - /* DDR3-1066 */ - calibration_code = 0x003a3a3a; - } else if (MemClkFreq == 0xe) { - /* DDR3-1333 */ - calibration_code = 0x00003939; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ - if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) - calibration_code = 0x00003738; + if (MemClkFreq == 0x4) { + /* DDR3-667 */ + calibration_code = 0x00390039; + } else if (MemClkFreq == 0x6) { + /* DDR3-800 */ + calibration_code = 0x00390039; + } else if (MemClkFreq == 0xa) { + /* DDR3-1066 */ + calibration_code = 0x003a3a3a; + } else if (MemClkFreq == 0xe) { + /* DDR3-1333 */ + calibration_code = 0x00003939; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + if ((rank_count_dimm0 == 1) && (rank_count_dimm1 == 1)) + calibration_code = 0x00003738; + } } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ } } else { /* TODO @@ -1043,55 +1190,66 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc if (package_type == PT_GR) { /* Socket G34 */ - /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ - if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; - - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { - /* DDR3-667 - DDR3-1333 */ - slow_access = 0; - } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { - /* DDR3-1600 - DDR3-1866 */ - if (rank_count_dimm0 == 1) - slow_access = 0; - else - slow_access = 1; - } - } else if (MaxDimmsInstallable == 2) { - if (dimm_count == 1) { - /* 1 DIMM detected */ + if (pDCTstat->Status & (1 << SB_Registered)) { + /* RDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ + slow_access = 0; + } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { + /* LRDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 75 */ + slow_access = 0; + } else { + /* UDIMM */ + /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ + if (MaxDimmsInstallable == 1) { rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { /* DDR3-667 - DDR3-1333 */ slow_access = 0; - } else if (MemClkFreq == 0x12) { - /* DDR3-1600 */ + } else if ((MemClkFreq == 0x12) || (MemClkFreq == 0x16)) { + /* DDR3-1600 - DDR3-1866 */ if (rank_count_dimm0 == 1) slow_access = 0; else slow_access = 1; } - } else if (dimm_count == 2) { - /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + } else if (MaxDimmsInstallable == 2) { + if (dimm_count == 1) { + /* 1 DIMM detected */ + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; - if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) - || (MemClkFreq == 0xa)) { - /* DDR3-667 - DDR3-1066 */ - slow_access = 0; - } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { - /* DDR3-1333 - DDR3-1600 */ - slow_access = 1; + if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) + || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { + /* DDR3-667 - DDR3-1333 */ + slow_access = 0; + } else if (MemClkFreq == 0x12) { + /* DDR3-1600 */ + if (rank_count_dimm0 == 1) + slow_access = 0; + else + slow_access = 1; + } + } else if (dimm_count == 2) { + /* 2 DIMMs detected */ + rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; + rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + + if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) + || (MemClkFreq == 0xa)) { + /* DDR3-667 - DDR3-1066 */ + slow_access = 0; + } else if ((MemClkFreq == 0xe) || (MemClkFreq == 0x12)) { + /* DDR3-1333 - DDR3-1600 */ + slow_access = 1; + } } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ } - } else if (MaxDimmsInstallable == 3) { - /* TODO - * 3 DIMM/channel support unimplemented - */ } } else { /* TODO

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12002 -gerrit commit 1c92a5231598d58389d0abfc5ab56361f210538d Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Wed Jun 24 19:15:09 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Fix lockups and wasted time during ECC init Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 144 +++++++++++++++---------- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 39 ++++++- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 22 +++- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 3 +- 4 files changed, 147 insertions(+), 61 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index b3f43fb..36c0d3e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1505,11 +1505,12 @@ restartinit: InterleaveChannels_D(pMCTstat, pDCTstatA); printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n"); - ECCInit_D(pMCTstat, pDCTstatA); /* Setup ECC control and ECC check-bits*/ - - /* mctDoWarmResetMemClr_D(); */ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat,pDCTstatA); + if (!ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ + /* Memory was not cleared during ECC setup */ + /* mctDoWarmResetMemClr_D(); */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); + MCTMemClr_D(pMCTstat,pDCTstatA); + } printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -1702,7 +1703,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, uint8_t x8_present = 0; uint8_t memclk_index; uint8_t interleave_channels = 0; - uint8_t redirect_ecc_scrub = 0; uint16_t trdrdsddc; uint16_t trdrddd; uint16_t cdd_trdrddd; @@ -1740,9 +1740,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, if (pDCTstat->DIMMValidDCT[0] && pDCTstat->DIMMValidDCT[1] && mctGet_NVbits(NV_Unganged)) interleave_channels = 1; - if ((pMCTstat->GStatus & 1 << GSB_ECCDIMMs) && mctGet_NVbits(NV_ECCRedir)) - redirect_ecc_scrub = 1; - dword = (Get_NB32_DCT(dev, dct, 0x240) >> 4) & 0xf; if (dword > 6) read_odt_delay = dword - 6; @@ -1934,21 +1931,10 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, dword |= (interleave_channels & 0x1) << 2; Set_NB32_DCT(dev, dct, 0x110, dword); /* DRAM Controller Select Low */ - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x58); /* Scrub Rate Control */ - dword &= ~(0x1f << 24); /* L3Scrub = NV_L3BKScrub */ - dword |= (mctGet_NVbits(NV_L3BKScrub) & 0x1f) << 24; - dword &= ~(0x1f); /* DramScrub = NV_DramBKScrub */ - dword |= mctGet_NVbits(NV_DramBKScrub) & 0x1f; - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x58, dword); /* Scrub Rate Control */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c); /* DRAM Scrub Address Low */ - dword &= ~(0x1); /* ScrubReDirEn = redirect_ecc_scrub */ - dword |= redirect_ecc_scrub & 0x1; - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c, dword); /* DRAM Scrub Address Low */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8); /* L3 Control 1 */ - dword &= ~(0x1 << 4); /* L3ScrbRedirDis = 0 */ - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8, dword); /* L3 Control 1 */ + /* NOTE + * ECC-related setup is performed as part of ECCInit_D and must not be located here, + * otherwise semi-random lockups will occur due to misconfigured scrubbing hardware! + */ /* FIXME * The BKDG-recommended settings cause memory corruption on the ASUS KGPE-D16. @@ -1990,11 +1976,17 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, dword |= ((((dword >> 8) & 0x1f) + 1) << 16); Set_NB32_DCT(dev, dct, 0x21c, dword); /* DRAM Timing 6 */ + /* Configure partial power down delay */ + dword = Get_NB32(dev, 0x244); /* DRAM Controller Miscellaneous 3 */ + dword &= ~0xf; /* PrtlChPDDynDly = 0x2 */ + dword |= 0x2; + Set_NB32(dev, 0x244, dword); /* DRAM Controller Miscellaneous 3 */ + /* Enable prefetchers */ - dword = Get_NB32_DCT(dev, dct, 0x110); /* Memory Controller Configuration High */ + dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ - Set_NB32_DCT(dev, dct, 0x110, dword); /* Memory Controller Configuration High */ + Set_NB32(dev, 0x11c, dword); /* Memory Controller Configuration High */ } } @@ -2099,6 +2091,19 @@ static void DQSTiming_D(struct MCTStatStruc *pMCTstat, pMCTstat->GStatus |= 1 << GSB_ConfigRestored; } + if (is_fam15h()) { + uint8_t Node; + struct DCTStatStruc *pDCTstat; + + /* Switch DCT control register to DCT 0 per Erratum 505 */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + pDCTstat = pDCTstatA + Node; + if (pDCTstat->NodePresent) { + fam15h_switch_dct(pDCTstat->dev_map, 0); + } + } + } + /* FIXME - currently uses calculated value TrainMaxReadLatency_D(pMCTstat, pDCTstatA); */ mctHookAfterAnyTraining(); } @@ -2345,6 +2350,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, * status are checked to ensure that memclr has completed. */ u8 Node; + uint32_t dword; struct DCTStatStruc *pDCTstat; if (!mctGet_NVbits(NV_DQSTrainCTL)){ @@ -2365,6 +2371,18 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat, } } } + + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + pDCTstat = pDCTstatA + Node; + + /* Configure and enable prefetchers */ + if (is_fam15h()) + dword = 0x0ce00f41; /* BKDG recommended */ + else + dword = 0x0fe40fc0; /* BKDG recommended */ + dword |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ + Set_NB32(pDCTstat->dev_dct, 0x11c, dword); + } } static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, @@ -2372,48 +2390,59 @@ static void DCTMemClr_Init_D(struct MCTStatStruc *pMCTstat, { u32 val; u32 dev; - u32 reg; + uint32_t dword; /* Initiates a memory clear operation on one node */ if (pDCTstat->DCTSysLimit) { dev = pDCTstat->dev_dct; - reg = 0x110; + + /* Disable prefetchers */ + dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ + dword |= 0x1 << 13; /* PrefIoDis = 1 */ + dword |= 0x1 << 12; /* PrefCpuDis = 1 */ + Set_NB32(dev, 0x11c, dword); /* Memory Controller Configuration High */ do { - val = Get_NB32(dev, reg); + val = Get_NB32(dev, 0x110); } while (val & (1 << MemClrBusy)); val |= (1 << MemClrInit); - Set_NB32(dev, reg, val); + Set_NB32(dev, 0x110, val); } } static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { - u32 val; - u32 dev = pDCTstat->dev_dct; - u32 reg; + uint32_t dword; + uint32_t dev = pDCTstat->dev_dct; + + printk(BIOS_DEBUG, "%s: Start\n", __func__); /* Ensure that a memory clear operation has completed on one node */ if (pDCTstat->DCTSysLimit){ - reg = 0x110; - + printk(BIOS_DEBUG, "%s: Waiting for memory clear to complete", __func__); do { - val = Get_NB32(dev, reg); - } while (val & (1 << MemClrBusy)); + dword = Get_NB32(dev, 0x110); + + printk(BIOS_DEBUG, "."); + } while (dword & (1 << MemClrBusy)); + printk(BIOS_DEBUG, "\n"); do { - val = Get_NB32(dev, reg); - } while (!(val & (1 << Dr_MemClrStatus))); + printk(BIOS_DEBUG, "."); + dword = Get_NB32(dev, 0x110); + } while (!(dword & (1 << Dr_MemClrStatus))); + printk(BIOS_DEBUG, "\n"); } - if (is_fam15h()) - val = 0x0ce00f41; /* BKDG recommended */ - else - val = 0x0fe40fc0; /* BKDG recommended */ - val |= MCCH_FlushWrOnStpGnt; /* Set for S3 */ - Set_NB32(dev, 0x11c, val); + /* Enable prefetchers */ + dword = Get_NB32(dev, 0x11c); /* Memory Controller Configuration High */ + dword &= ~(0x1 << 13); /* PrefIoDis = 0 */ + dword &= ~(0x1 << 12); /* PrefCpuDis = 0 */ + Set_NB32(dev, 0x11c, dword); /* Memory Controller Configuration High */ + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static u8 NodePresent_D(u8 Node) @@ -3354,8 +3383,8 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, dev = pDCTstat->dev_dct; /* Build Dram Control Register Value */ - DramConfigMisc2 = Get_NB32_DCT(dev, dct, 0xA8); /* Dram Control*/ - DramControl = Get_NB32_DCT(dev, dct, 0x78); /* Dram Control*/ + DramConfigMisc2 = Get_NB32_DCT(dev, dct, 0xa8); /* Dram Miscellaneous 2 */ + DramControl = Get_NB32_DCT(dev, dct, 0x78); /* Dram Control */ /* FIXME: Skip mct_checkForDxSupport */ /* REV_CALL mct_DoRdPtrInit if not Dx */ @@ -3410,9 +3439,15 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat, /* set only if x8 Registered DIMMs in System*/ DramConfigHi |= 1 << RDqsEn; - if (mctGet_NVbits(NV_CKE_CTL)) - /*Chip Select control of CKE*/ - DramConfigHi |= 1 << 16; + if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { + DramConfigLo |= 1 << 25; /* PendRefPaybackS3En = 1 */ + DramConfigLo |= 1 << 24; /* StagRefEn = 1 */ + DramConfigHi |= 1 << 16; /* PowerDownMode = 1 */ + } else { + if (mctGet_NVbits(NV_CKE_CTL)) + /*Chip Select control of CKE*/ + DramConfigHi |= 1 << 16; + } /* Control Bank Swizzle */ if (0) /* call back not needed mctBankSwizzleControl_D()) */ @@ -4120,8 +4155,7 @@ static void mct_preInitDCT(struct MCTStatStruc *pMCTstat, if (load_spd_hashes_from_nvram(pMCTstat, pDCTstat) < 0) { pDCTstat->spd_data.nvram_spd_match = 0; - } - else { + } else { compare_nvram_spd_hashes(pMCTstat, pDCTstat); } #else @@ -4319,8 +4353,8 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat, } for (i=i_start; i<i_end; i++) { index_reg = 0x98; - Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */ - Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */ + Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */ + Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */ } return pDCTstat->ErrCode; @@ -6110,11 +6144,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat, DramMRS |= 1 << 1; dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x84); + dword |= DramMRS; if (is_fam15h()) dword &= ~0x00800003; else dword &= ~0x00fc2f8f; - dword |= DramMRS; Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x84, dword); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 8701bae..1be46b1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -88,8 +88,13 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; + uint8_t redirect_ecc_scrub = 0; + mctHookBeforeECC(); + if ((pMCTstat->GStatus & 1 << GSB_ECCDIMMs) && mctGet_NVbits(NV_ECCRedir)) + redirect_ecc_scrub = 1; + /* Construct these booleans, based on setup options, for easy handling later in this procedure */ OB_NBECC = mctGet_NVbits(NV_NBECC); /* MCA ECC (MCE) enable bit */ @@ -226,12 +231,12 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } dev = pDCTstat->dev_nbmisc; val = curBase << 8; - if(OB_ECCRedir) { - val |= (1<<0); /* enable redirection */ + if (OB_ECCRedir) { + val |= (1<<0); /* enable redirection */ } - Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */ + Set_NB32(dev, 0x5c, val); /* Dram Scrub Addr Low */ val = curBase>>24; - Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */ + Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */ Set_NB32(dev, 0x58, OF_ScrubCTL); /*Scrub Control */ if (!is_fam15h()) { @@ -248,6 +253,32 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } } + + if (is_fam15h()) { + uint8_t dct; + + /* Disable training mode + * See fam15EnableTrainingMode for the non-ECC training mode tear-down code + */ + for (dct = 0; dct < 2; dct++) { + /* NOTE: Reads use DCT 0 and writes use the current DCT per Erratum 505 */ + dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, 0, 0x58); /* Scrub Rate Control */ + dword &= ~(0x1f << 24); /* L3Scrub = NV_L3BKScrub */ + dword |= (mctGet_NVbits(NV_L3BKScrub) & 0x1f) << 24; + dword &= ~(0x1f); /* DramScrub = NV_DramBKScrub */ + dword |= mctGet_NVbits(NV_DramBKScrub) & 0x1f; + Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x58, dword); /* Scrub Rate Control */ + + dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c); /* DRAM Scrub Address Low */ + dword &= ~(0x1); /* ScrubReDirEn = redirect_ecc_scrub */ + dword |= redirect_ecc_scrub & 0x1; + Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c, dword); /* DRAM Scrub Address Low */ + + dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8); /* L3 Control 1 */ + dword &= ~(0x1 << 4); /* L3ScrbRedirDis = 0 */ + Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8, dword); /* L3 Control 1 */ + } + } } /* this node has ECC enabled dram */ } /*Node has Dram */ } /*if Node present */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index a86c319..77acaec 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -19,7 +19,27 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, u8 dct, u32 misc2) { u32 val; - if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { + /* FIXME + * Mainboards need to be able to specify the maximum number of DIMMs installable per channel + * For now assume a maximum of 2 DIMMs per channel can be installed + */ + uint8_t MaxDimmsInstallable = 2; + + if (pDCTstat->LogicalCPUID & AMD_FAM15_ALL) { + uint8_t cs_mux_45; + uint8_t cs_mux_67; + + /* BKDG v3.14 Table 200 / Table 201 */ + if (MaxDimmsInstallable < 3) { + cs_mux_45 = 1; + cs_mux_67 = 1; + } else { + cs_mux_45 = 0; + cs_mux_67 = 0; + } + misc2 |= (cs_mux_45 & 0x1) << 26; + misc2 |= (cs_mux_67 & 0x1) << 27; + } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { if (pDCTstat->Status & (1 << SB_Registered)) { misc2 |= 1 << SubMemclkRegDly; if (mctGet_NVbits(NV_MAX_DIMMS) == 8) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index f3915a2..48b72ca 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -205,7 +205,8 @@ void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta uint16_t total_delay_seed = ((pDCTData->WLSeedGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLSeedFineDelay[index+ByteLane] & 0x1f); uint16_t total_delay_phy = ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f); if (abs(total_delay_phy - total_delay_seed) > 0x20) { - printk(BIOS_DEBUG, "%s: overriding faulty phy value\n", __func__); + printk(BIOS_DEBUG, "%s: overriding faulty phy value (seed: %04x phy: %04x step: %04x)\n", __func__, + total_delay_seed, total_delay_phy, abs(total_delay_phy - total_delay_seed)); pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; }

1 0

Patch set updated for coreboot: cpu/amd: Fix AMD Family 15h ECC initialization reliability issues
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12003 -gerrit commit 88d39ab5796231f992402c93b9622fdafe8b51c0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 15:07:34 2015 -0500 cpu/amd: Fix AMD Family 15h ECC initialization reliability issues Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/car/cache_as_ram.inc | 4 + src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 ++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 +-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 6 +- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 21 ++++- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 110 +++++++++++-------------- src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 6 +- src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 57 ++++++++----- 8 files changed, 136 insertions(+), 96 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 3295ccc..cbb1e39 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -359,12 +359,16 @@ clear_fixed_var_mtrr_out: simplemask CacheSize, 0 wrmsr + jmp_if_fam15h(fam15_skip_dram_mtrr_setup) + /* Enable memory access for first MBs using top_mem. */ movl $TOP_MEM, %ecx xorl %edx, %edx movl $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax wrmsr +fam15_skip_dram_mtrr_setup: + #if CONFIG_XIP_ROM_SIZE /* Enable write base caching so we can do execute in place (XIP) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index c9dca76..e4721a4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -313,6 +313,22 @@ static void STOP_CAR_AND_CPU(uint8_t skip_sharedc_config, uint32_t apicid) msr = rdmsr(BU_CFG2); msr.lo &= ~(1 << ClLinesToNbDis); wrmsr(BU_CFG2, msr); + } else { + /* Family 15h or later + * DRAM setup is delayed on Fam15 in order to prevent + * any DRAM access before ECC check bits are initialized. + * Each core also needs to have its initial DRAM map initialized + * before it is put to sleep, otherwise it will fail to wake + * in ramstage. To meet both of these goals, delay DRAM map + * setup until the last possible moment, where speculative + * memory access is highly unlikely before core halt... + */ + if (!skip_sharedc_config) { + /* Enable memory access for first MBs using top_mem */ + msr.hi = 0; + msr.lo = (CONFIG_RAMTOP + TOP_MEM_MASK) & (~TOP_MEM_MASK); + wrmsr(TOP_MEM, msr); + } } disable_cache_as_ram(skip_sharedc_config); // inline diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 36c0d3e..229073b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1465,8 +1465,7 @@ restartinit: HTMemMapInit_D(pMCTstat, pDCTstatA); /* Map local memory into system address space.*/ mctHookAfterHTMap(); - printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); - CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: mctHookAfterCPU\n"); mctHookAfterCPU(); /* Setup external northbridge(s) */ /* FIXME @@ -1489,9 +1488,6 @@ restartinit: printk(BIOS_DEBUG, "mctAutoInitMCT_D: DQSTiming_D\n"); DQSTiming_D(pMCTstat, pDCTstatA, allow_config_restore); /* Get Receiver Enable and DQS signal timing*/ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); - UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ - if (!allow_config_restore) { printk(BIOS_DEBUG, "mctAutoInitMCT_D: :OtherTiming\n"); mct_OtherTiming(pMCTstat, pDCTstatA); @@ -1512,6 +1508,12 @@ restartinit: MCTMemClr_D(pMCTstat,pDCTstatA); } + printk(BIOS_DEBUG, "mctAutoInitMCT_D: CPUMemTyping_D\n"); + CPUMemTyping_D(pMCTstat, pDCTstatA); /* Map dram into WB/UC CPU cacheability */ + + printk(BIOS_DEBUG, "mctAutoInitMCT_D: UMAMemTyping_D\n"); + UMAMemTyping_D(pMCTstat, pDCTstatA); /* Fix up for UMA sizing */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: mct_ForceNBPState0_Dis_Fam15\n"); for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { struct DCTStatStruc *pDCTstat; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 425f1ef..ffbad2b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -721,8 +721,10 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f2x9cx30[12]; uint32_t f2x9cx40[12]; - /* Other (1 dword) */ + /* Other (3 dwords) */ uint32_t f3x58; + uint32_t f3x5c; + uint32_t f3x60; /* Family 15h-specific registers (90 dwords) */ uint32_t f2x200; @@ -781,7 +783,7 @@ struct amd_s3_persistent_mct_channel_data { uint32_t f2x9cx0d0f0_0_f_31[9]; /* [lane] */ uint32_t f2x9cx0d0f8021; - /* TOTAL: 340 dwords */ + /* TOTAL: 342 dwords */ } __attribute__((packed)); struct amd_s3_persistent_node_data { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 537c616..9dbdcfb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -898,6 +898,16 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t dev = pDCTstat->dev_dct; uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; +#if DQS_TRAIN_DEBUG > 0 + printk(BIOS_DEBUG, "%s: Start\n", __func__); +#endif + + mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; + if (fam15h_freq_tab[mem_clk] == 0) { + pDCTstat->CH_MaxRdLat[dct] = 0x55; + return; + } + /* P is specified in PhyCLKs (1/2 MEMCLKs) */ for (nb_pstate = 0; nb_pstate < 2; nb_pstate++) { /* 2.10.5.8.5 (2) */ @@ -945,7 +955,6 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, t += 800; /* 2.10.5.8.5 (10) */ - mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; dword = Get_NB32(pDCTstat->dev_nbctl, (0x160 + (nb_pstate * 4))); /* Retrieve NbDid, NbFid */ nb_clk = (200 * (((dword >> 1) & 0x1f) + 0x4)) / (((dword >> 7) & 0x1)?2:1); n = (((((uint64_t)p * 1000000000000ULL)/(((uint64_t)fam15h_freq_tab[mem_clk] * 1000000ULL) * 2)) + ((uint64_t)t)) * ((uint64_t)nb_clk * 1000)) / 1000000000ULL; @@ -960,8 +969,16 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, Set_NB32_DCT_NBPstate(dev, dct, nb_pstate, 0x210, dword); /* Save result for later use */ - pDCTstat->CH_MaxRdLat[dct] = n; + pDCTstat->CH_MaxRdLat[dct] = n - 1; + +#if DQS_TRAIN_DEBUG > 0 + printk(BIOS_DEBUG, "%s: CH_MaxRdLat[%d]: %03x\n", __func__, dct, pDCTstat->CH_MaxRdLat[dct]); +#endif } + +#if DQS_TRAIN_DEBUG > 0 + printk(BIOS_DEBUG, "%s: Done\n", __func__); +#endif } static void start_dram_dqs_training_pattern_fam15(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 1be46b1..be63149 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -88,13 +88,8 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) uint8_t sync_flood_on_dram_err[MAX_NODES_SUPPORTED]; uint8_t sync_flood_on_any_uc_err[MAX_NODES_SUPPORTED]; - uint8_t redirect_ecc_scrub = 0; - mctHookBeforeECC(); - if ((pMCTstat->GStatus & 1 << GSB_ECCDIMMs) && mctGet_NVbits(NV_ECCRedir)) - redirect_ecc_scrub = 1; - /* Construct these booleans, based on setup options, for easy handling later in this procedure */ OB_NBECC = mctGet_NVbits(NV_NBECC); /* MCA ECC (MCE) enable bit */ @@ -113,8 +108,11 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) OF_ScrubCTL |= (u32) nvbits << 8; } + nvbits = mctGet_NVbits(NV_L3BKScrub); + OF_ScrubCTL |= (nvbits & 0x1f) << 24; /* L3Scrub = NV_L3BKScrub */ + nvbits = mctGet_NVbits(NV_DramBKScrub); - OF_ScrubCTL |= nvbits; + OF_ScrubCTL |= nvbits; /* DramScrub = NV_DramBKScrub */ /* Prevent lockups on DRAM errors during ECC init */ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { @@ -129,6 +127,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) dword &= ~(0x1 << 21); Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + /* Clear MC4 error status */ + pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); + pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); + /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ DCTMemClr_Init_D(pMCTstat, pDCTstat); DCTMemClr_Sync_D(pMCTstat, pDCTstat); @@ -166,6 +168,9 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) if(LDramECC) { /* if ECC is enabled on this dram */ if (OB_NBECC) { mct_EnableDatIntlv_D(pMCTstat, pDCTstat); + val = Get_NB32(pDCTstat->dev_dct, 0x110); + val |= 1 << 5; /* DctDatIntLv = 1 */ + Set_NB32(pDCTstat->dev_dct, 0x110, val); dev = pDCTstat->dev_nbmisc; reg = 0x44; /* MCA NB Configuration */ val = Get_NB32(dev, reg); @@ -176,37 +181,16 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) printk(BIOS_DEBUG, " ECC enabled on node: %02x\n", Node); } } /* this node has ECC enabled dram */ + + if (MemClrECC) { + DCTMemClr_Sync_D(pMCTstat, pDCTstat); + } } else { LDramECC = 0; } /* Node has Dram */ - - if (MemClrECC) { - DCTMemClr_Sync_D(pMCTstat, pDCTstat); - } - - if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { - /* Set up message triggered C1E */ - val = pci_read_config32(pDCTstat->dev_nbmisc, 0xd4); - val &= ~(0x1 << 15); /* StutterScrubEn = DRAM scrub enabled */ - val |= (mctGet_NVbits(NV_DramBKScrub)?1:0) << 15; - pci_write_config32(pDCTstat->dev_nbmisc, 0xd4, val); - } } /* if Node present */ } - /* Restore previous MCA error handling settings */ - for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { - struct DCTStatStruc *pDCTstat; - pDCTstat = pDCTstatA + Node; - - if (NodePresent_D(Node)) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; - dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } - } - if(AllECC) pMCTstat->GStatus |= 1<<GSB_ECCDIMMs; else @@ -225,19 +209,26 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /*WE/RE is checked because memory config may have been */ if((val & 3)==3) { /* Node has dram populated */ if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */ - if (is_fam15h()) { - /* Erratum 505 */ - fam15h_switch_dct(pDCTstat->dev_map, 0); - } dev = pDCTstat->dev_nbmisc; val = curBase << 8; if (OB_ECCRedir) { - val |= (1<<0); /* enable redirection */ + val |= (1 << 0); /* Enable redirection */ } Set_NB32(dev, 0x5c, val); /* Dram Scrub Addr Low */ - val = curBase>>24; + val = curBase >> 24; Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */ - Set_NB32(dev, 0x58, OF_ScrubCTL); /*Scrub Control */ + + /* Set scrub rate controls */ + if (is_fam15h()) { + /* Erratum 505 */ + fam15h_switch_dct(pDCTstat->dev_map, 0); + } + Set_NB32(dev, 0x58, OF_ScrubCTL); /* Scrub Control */ + if (is_fam15h()) { + fam15h_switch_dct(pDCTstat->dev_map, 1); /* Erratum 505 */ + Set_NB32(dev, 0x58, OF_ScrubCTL); /* Scrub Control */ + fam15h_switch_dct(pDCTstat->dev_map, 0); /* Erratum 505 */ + } if (!is_fam15h()) { /* Divisor should not be set deeper than @@ -254,36 +245,31 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) } } - if (is_fam15h()) { - uint8_t dct; - - /* Disable training mode - * See fam15EnableTrainingMode for the non-ECC training mode tear-down code - */ - for (dct = 0; dct < 2; dct++) { - /* NOTE: Reads use DCT 0 and writes use the current DCT per Erratum 505 */ - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, 0, 0x58); /* Scrub Rate Control */ - dword &= ~(0x1f << 24); /* L3Scrub = NV_L3BKScrub */ - dword |= (mctGet_NVbits(NV_L3BKScrub) & 0x1f) << 24; - dword &= ~(0x1f); /* DramScrub = NV_DramBKScrub */ - dword |= mctGet_NVbits(NV_DramBKScrub) & 0x1f; - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x58, dword); /* Scrub Rate Control */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c); /* DRAM Scrub Address Low */ - dword &= ~(0x1); /* ScrubReDirEn = redirect_ecc_scrub */ - dword |= redirect_ecc_scrub & 0x1; - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x5c, dword); /* DRAM Scrub Address Low */ - - dword = Get_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8); /* L3 Control 1 */ - dword &= ~(0x1 << 4); /* L3ScrbRedirDis = 0 */ - Set_NB32_DCT(pDCTstat->dev_nbmisc, dct, 0x1b8, dword); /* L3 Control 1 */ - } + if (pDCTstat->LogicalCPUID & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { + /* Set up message triggered C1E */ + val = pci_read_config32(pDCTstat->dev_nbmisc, 0xd4); + val &= ~(0x1 << 15); /* StutterScrubEn = DRAM scrub enabled */ + val |= (mctGet_NVbits(NV_DramBKScrub)?1:0) << 15; + pci_write_config32(pDCTstat->dev_nbmisc, 0xd4, val); } } /* this node has ECC enabled dram */ } /*Node has Dram */ } /*if Node present */ } + /* Restore previous MCA error handling settings */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (NodePresent_D(Node)) { + dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); + dword |= (sync_flood_on_dram_err[Node] & 0x1) << 30; + dword |= (sync_flood_on_any_uc_err[Node] & 0x1) << 21; + Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); + } + } + if(mctGet_NVbits(NV_SyncOnUnEccEn)) setSyncOnUnEccEn_D(pMCTstat, pDCTstatA); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c index 6cf4135..b7c0476 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c @@ -228,9 +228,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat Cache32bTOP = val; pMCTstat->Sub4GCacheTop = val; - /*====================================================================== - * Clear variable MTRR values - *======================================================================*/ + /*====================================================================== + * Clear variable MTRR values + *======================================================================*/ addr = 0x200; lo = 0; hi = lo; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 6e92f3a..ae2cca1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -85,6 +85,28 @@ static uint32_t read_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint3 return pci_read_config32(dev, reg); } +static void write_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) { + if (is_fam15h()) { + uint32_t dword; +#ifdef __PRE_RAM__ + device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); +#else + device_t dev_fn1 = dev_find_slot(0, PCI_DEVFN(0x18 + node, 1)); +#endif + + /* Select DCT */ + dword = pci_read_config32(dev_fn1, 0x10c); + dword &= ~0x1; + dword |= (dct & 0x1); + pci_write_config32(dev_fn1, 0x10c, dword); + } else { + /* Apply offset */ + reg += dct * 0x100; + } + + pci_write_config32(dev, reg, value); +} + static uint32_t read_amd_dct_index_register(device_t dev, uint32_t index_ctl_reg, uint32_t index) { uint32_t dword; @@ -485,29 +507,17 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da /* Other */ /* ECC scrub rate control */ - data->f3x58 = pci_read_config32(dev_fn3, 0x58); + data->f3x58 = read_config32_dct(dev_fn3, node, 0, 0x58); + + /* ECC scrub location */ + write_config32_dct(dev_fn3, node, 0, 0x58, 0x0); /* Disable sequential scrub to work around non-atomic location read */ + data->f3x5c = read_config32_dct(dev_fn3, node, 0, 0x5c); + data->f3x60 = read_config32_dct(dev_fn3, node, 0, 0x60); + write_config32_dct(dev_fn3, node, 0, 0x58, data->f3x58); /* Re-enable sequential scrub */ } } } #else -static void write_config32_dct(device_t dev, uint8_t node, uint8_t dct, uint32_t reg, uint32_t value) { - if (is_fam15h()) { - uint32_t dword; - device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); - - /* Select DCT */ - dword = pci_read_config32(dev_fn1, 0x10c); - dword &= ~0x1; - dword |= (dct & 0x1); - pci_write_config32(dev_fn1, 0x10c, dword); - } else { - /* Apply offset */ - reg += dct * 0x100; - } - - pci_write_config32(dev, reg, value); -} - static void write_config32_dct_nbpstate(device_t dev, uint8_t node, uint8_t dct, uint8_t nb_pstate, uint32_t reg, uint32_t value) { uint32_t dword; device_t dev_fn1 = PCI_DEV(0, 0x18 + node, 1); @@ -609,8 +619,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (is_fam15h()) { for (i=0; i<4; i++) write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]); - } - else { + } else { write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78); } @@ -1056,8 +1065,12 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste if (!persistent_data->node[node].node_present) continue; + /* ECC scrub location */ + write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, 0, 0x5c, data->f3x5c); + write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, 0, 0x60, data->f3x60); + /* ECC scrub rate control */ - pci_write_config32(PCI_DEV(0, 0x18 + node, 3), 0x58, data->f3x58); + write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, 0, 0x58, data->f3x58); if (is_fam15h()) /* Set LockDramCfg and CC6SaveEn */

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coreboot-gerrit November 2015