coreboot-gerrit November 2015

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New patch to review for coreboot: sconfig: get rid of root_complex special case
by Patrick Georgi 12 Nov '15

12 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12428 -gerrit commit 04092d9187c1c2642502d53bc05e79af3392ce5d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Nov 13 00:37:04 2015 +0100 sconfig: get rid of root_complex special case Instead of requiring that devicetree.cb starts with a "chip" node, allow this to be implicit (like the root node and the mainboard "chip"), in which case an implicit chip node is added as parent to the (now) top-level device nodes. TEST=built random modified board without change applied, applied change, built board again, compared the generated $(obj)/mainboard/*/*/static.c of both builds, and made sure they differ only in renaming *_root_complex_ops to dummy_1_chip_ops. Change-Id: I0e5413b77e82ee19cc473b52e72f9f97fd38e69d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/advansus/a785e-i/devicetree.cb | 232 +++-- src/mainboard/amd/bettong/devicetree.cb | 104 +- src/mainboard/amd/bimini_fam10/devicetree.cb | 183 ++-- src/mainboard/amd/dbm690t/devicetree.cb | 206 ++-- src/mainboard/amd/dinar/devicetree.cb | 172 ++-- src/mainboard/amd/inagua/devicetree.cb | 144 ++- src/mainboard/amd/lamar/devicetree.cb | 178 ++-- src/mainboard/amd/mahogany/devicetree.cb | 208 ++-- src/mainboard/amd/mahogany_fam10/devicetree.cb | 241 +++-- src/mainboard/amd/olivehill/devicetree.cb | 102 +- src/mainboard/amd/olivehillplus/devicetree.cb | 102 +- src/mainboard/amd/parmer/devicetree.cb | 123 ++- src/mainboard/amd/persimmon/devicetree.cb | 264 +++-- src/mainboard/amd/pistachio/devicetree.cb | 132 ++- src/mainboard/amd/serengeti_cheetah/devicetree.cb | 258 +++-- .../amd/serengeti_cheetah_fam10/devicetree.cb | 239 +++-- src/mainboard/amd/south_station/devicetree.cb | 176 ++-- src/mainboard/amd/thatcher/devicetree.cb | 149 ++- src/mainboard/amd/tilapia_fam10/devicetree.cb | 241 +++-- src/mainboard/amd/torpedo/devicetree.cb | 140 ++- src/mainboard/amd/union_station/devicetree.cb | 128 ++- src/mainboard/asrock/939a785gmh/devicetree.cb | 224 ++-- src/mainboard/asrock/e350m1/devicetree.cb | 246 +++-- src/mainboard/asrock/imb-a180/devicetree.cb | 180 ++-- src/mainboard/asus/a8n_e/devicetree.cb | 222 ++-- src/mainboard/asus/a8v-e_deluxe/devicetree.cb | 176 ++-- src/mainboard/asus/a8v-e_se/devicetree.cb | 176 ++-- src/mainboard/asus/f2a85-m/devicetree.cb | 215 ++-- src/mainboard/asus/f2a85-m_le/devicetree.cb | 213 ++-- src/mainboard/asus/k8v-x/devicetree.cb | 200 ++-- src/mainboard/asus/kfsn4-dre/devicetree.cb | 352 ++++--- src/mainboard/asus/kfsn4-dre_k8/devicetree.cb | 358 ++++--- src/mainboard/asus/kgpe-d16/devicetree.cb | 448 ++++---- src/mainboard/asus/m2n-e/devicetree.cb | 177 ++-- src/mainboard/asus/m2v-mx_se/devicetree.cb | 134 ++- src/mainboard/asus/m2v/devicetree.cb | 126 ++- src/mainboard/asus/m4a78-em/devicetree.cb | 196 ++-- src/mainboard/asus/m4a785-m/devicetree.cb | 196 ++-- src/mainboard/asus/m4a785t-m/devicetree.cb | 200 ++-- src/mainboard/asus/m5a88-v/devicetree.cb | 240 +++-- src/mainboard/avalue/eax-785e/devicetree.cb | 214 ++-- src/mainboard/bap/ode_e20XX/devicetree.cb | 184 ++-- src/mainboard/biostar/am1ml/devicetree.cb | 182 ++-- src/mainboard/broadcom/blast/devicetree.cb | 210 ++-- src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb | 171 ++-- src/mainboard/gigabyte/m57sli/devicetree.cb | 20 +- src/mainboard/gigabyte/ma785gm/devicetree.cb | 211 ++-- src/mainboard/gigabyte/ma785gmt/devicetree.cb | 211 ++-- src/mainboard/gigabyte/ma78gm/devicetree.cb | 213 ++-- src/mainboard/gizmosphere/gizmo/devicetree.cb | 98 +- src/mainboard/gizmosphere/gizmo2/devicetree.cb | 78 +- src/mainboard/hp/abm/devicetree.cb | 138 ++- src/mainboard/hp/dl145_g1/devicetree.cb | 246 +++-- src/mainboard/hp/dl145_g3/devicetree.cb | 159 ++- src/mainboard/hp/dl165_g6_fam10/devicetree.cb | 165 ++- src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 123 ++- src/mainboard/iei/kino-780am2-fam10/devicetree.cb | 132 ++- src/mainboard/iwill/dk8_htx/devicetree.cb | 202 ++-- src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 228 ++--- src/mainboard/jetway/pa78vm5/devicetree.cb | 206 ++-- src/mainboard/kontron/kt690/devicetree.cb | 216 ++-- src/mainboard/lenovo/g505s/devicetree.cb | 131 ++- src/mainboard/lippert/frontrunner-af/devicetree.cb | 172 ++-- src/mainboard/lippert/toucan-af/devicetree.cb | 186 ++-- src/mainboard/msi/ms7135/devicetree.cb | 130 ++- src/mainboard/msi/ms7260/devicetree.cb | 258 +++-- src/mainboard/msi/ms9185/devicetree.cb | 158 ++- src/mainboard/msi/ms9282/devicetree.cb | 304 +++--- src/mainboard/msi/ms9652_fam10/devicetree.cb | 257 +++-- src/mainboard/nvidia/l1_2pvv/devicetree.cb | 322 +++--- src/mainboard/pcengines/apu1/devicetree.cb | 164 ++- src/mainboard/siemens/sitemp_g1p1/devicetree.cb | 222 ++-- src/mainboard/sunw/ultra40/devicetree.cb | 270 +++-- src/mainboard/sunw/ultra40m2/devicetree.cb | 262 +++-- src/mainboard/supermicro/h8dme/devicetree.cb | 226 ++-- src/mainboard/supermicro/h8dmr/devicetree.cb | 254 +++-- src/mainboard/supermicro/h8dmr_fam10/devicetree.cb | 266 +++-- src/mainboard/supermicro/h8qgi/devicetree.cb | 408 ++++---- src/mainboard/supermicro/h8qme_fam10/devicetree.cb | 204 ++-- src/mainboard/supermicro/h8scm/devicetree.cb | 398 ++++---- src/mainboard/supermicro/h8scm_fam10/devicetree.cb | 229 ++--- src/mainboard/technexion/tim5690/devicetree.cb | 194 ++-- src/mainboard/technexion/tim8690/devicetree.cb | 198 ++-- src/mainboard/tyan/s2912/devicetree.cb | 242 +++-- src/mainboard/tyan/s2912_fam10/devicetree.cb | 246 +++-- src/mainboard/tyan/s8226/devicetree.cb | 398 ++++---- src/mainboard/winent/mb6047/devicetree.cb | 220 ++-- util/sconfig/lex.yy.c_shipped | 61 +- util/sconfig/main.c | 36 +- util/sconfig/sconfig.h | 1 + util/sconfig/sconfig.tab.c_shipped | 1078 +++++++++----------- util/sconfig/sconfig.tab.h_shipped | 99 +- util/sconfig/sconfig.y | 17 +- 93 files changed, 9487 insertions(+), 9732 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/devicetree.cb b/src/mainboard/advansus/a785e-i/devicetree.cb index f7db1cc..3249716 100644 --- a/src/mainboard/advansus/a785e-i/devicetree.cb +++ b/src/mainboard/advansus/a785e-i/devicetree.cb @@ -1,124 +1,122 @@ # sample config for advansus/A785E-I -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_ASB2 #L1 and DDR3 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_ASB2 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id. - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # Ethernet - device pci a.0 on end # Ethernet - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "3" # Configuration D - register "port_enable" = "0x6f6" - register "gfx_dev2_dev3" = "0" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - register "gfx_tmds" = "1" - register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 - register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL - end - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id. + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # Ethernet + device pci a.0 on end # Ethernet + register "gppsb_configuration" = "4" # Configuration E + register "gpp_configuration" = "3" # Configuration D + register "port_enable" = "0x6f6" + register "gfx_dev2_dev3" = "0" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + register "gfx_tmds" = "1" + register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 + register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL + end + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf - end # LPC 0x439d - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - #register "gpp_configuration" = "0" #4:0:0:0 - #register "gpp_configuration" = "2" #2:2:0:0 - #register "gpp_configuration" = "3" #2:1:1:0 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - end # device pci 18.0 + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf + end # LPC 0x439d + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 15.0 on end # PCIe 0 + device pci 15.1 on end # PCIe 1 + device pci 15.2 on end # PCIe 2 + device pci 15.3 on end # PCIe 3 + device pci 16.0 on end # USB + device pci 16.2 on end # USB + #register "gpp_configuration" = "0" #4:0:0:0 + #register "gpp_configuration" = "2" #2:2:0:0 + #register "gpp_configuration" = "3" #2:1:1:0 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain -end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end +end #domain diff --git a/src/mainboard/amd/bettong/devicetree.cb b/src/mainboard/amd/bettong/devicetree.cb index e490423..42b016d 100644 --- a/src/mainboard/amd/bettong/devicetree.cb +++ b/src/mainboard/amd/bettong/devicetree.cb @@ -12,62 +12,60 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/pi/00660F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00660F01 - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/pi/00660F01 + device lapic 10 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00660F01 # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00660F01 # CPU side of HT root complex - chip northbridge/amd/pi/00660F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 3.0 on end # Edge Connector - device pci 3.1 on end # Edge Connector - end #chip northbridge/amd/pi/00660F01 + chip northbridge/amd/pi/00660F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + device pci 3.0 on end # Edge Connector + device pci 3.1 on end # Edge Connector + end #chip northbridge/amd/pi/00660F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 9.0 on end # HDA - device pci 9.2 on end # HDA - device pci 10.0 on end # USB - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - #device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 9.0 on end # HDA + device pci 9.2 on end # HDA + device pci 10.0 on end # USB + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + #device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/pi/00660F01 # CPU side of HT root complex - end #domain -end #northbridge/amd/pi/00660F01/root_complex + end #chip northbridge/amd/pi/00660F01 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/bimini_fam10/devicetree.cb b/src/mainboard/amd/bimini_fam10/devicetree.cb index 0bcc9c1..ff50725 100644 --- a/src/mainboard/amd/bimini_fam10/devicetree.cb +++ b/src/mainboard/amd/bimini_fam10/devicetree.cb @@ -1,95 +1,92 @@ - # sample config for amd/bimini_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_ASB2 #L1 and DDR3 - device lapic 0 on end - end +# sample config for amd/bimini_fam10 +device cpu_cluster 0 on + chip cpu/amd/socket_ASB2 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 off end # - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "2" # Configuration C - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 on end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - register "gpp_configuration" = "4" - end #southbridge/amd/sb800 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 off end # + register "gppsb_configuration" = "4" # Configuration E + register "gpp_configuration" = "2" # Configuration C + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb800 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 off end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 on end # Gec + device pci 15.0 on end # PCIe 0 + device pci 15.1 on end # PCIe 1 + device pci 15.2 on end # PCIe 2 + device pci 15.3 on end # PCIe 3 + device pci 16.0 on end # USB + device pci 16.2 on end # USB + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "gpp_configuration" = "4" + end #southbridge/amd/sb800 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end +end #domain +#for node 32 to node 63 +#device domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +#end #domain diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb index 898537b..3ce243e 100644 --- a/src/mainboard/amd/dbm690t/devicetree.cb +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -8,114 +8,112 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_S1G1 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" +end +device domain 0 on + subsystemid 0x1022 0x3050 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end # Internal Graphics 0x791F end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 114ec73..67113ec 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -13,92 +13,90 @@ # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family15 - device lapic 0x20 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end end - device domain 0 on - subsystemid 0x1022 0x1705 inherit - chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs - chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex - device pci 0.0 on end # HT Root Complex - device pci 0.1 off end # CLKCONFIG - device pci 2.0 on end # GPP1 Port0 - device pci 3.0 off end # GPP1 Port1 - device pci 4.0 off end # GPP3a Port0 - device pci 5.0 off end # GPP3a Port1 - device pci 6.0 off end # GPP3a Port2 - device pci 7.0 off end # GPP3a Port3 - device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time - device pci 9.0 off end # GPP3a Port4 - device pci a.0 off end # GPP3a Port5 - device pci b.0 off end # GPP2 Port0 (Not for sr5650) - device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) - device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 - register "port_enable" = "0x2104" - end # northbridge/amd/cimx/rd890 - chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB1 - device pci 12.1 on end # USB1 - device pci 12.2 on end # USB1 - device pci 13.0 on end # USB2 - device pci 13.1 on end # USB2 - device pci 13.2 on end # USB2 - device pci 14.0 on # SM - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC - chip superio/smsc/sch4037 # SIO SMSC SCH4037 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - irq 0x74 = 2 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - irq 0x74 = 4 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 on # COM2 / IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - end #SIO SMSC SCH4037 - end #LPC - device pci 14.4 on end # PCI bridge, 0x4384 - device pci 14.5 on end # USB 3 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb700 - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end +end +device domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology to satisfy both f10 and f15 CPUs + chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 off end # GPP3a Port0 + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 off end # GPP3a Port4 + device pci a.0 off end # GPP3a Port5 + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x2104" + end # northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on # SM + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/smsc/sch4037 # SIO SMSC SCH4037 + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + irq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + irq 0x74 = 4 + end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + end #SIO SMSC SCH4037 + end #LPC + device pci 14.4 on end # PCI bridge, 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 - { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 - }" - end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family15/root_complex + register "spdAddrLookup" = " + { + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - Channel 0-3 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - Channel 0-3 + }" + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index ce1a893..906ef83 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -12,81 +12,79 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge MXM lane 0 - device pci 5.0 off end # PCIE P2P bridge MXM lane 1 - device pci 6.0 on end # PCIE P2P bridge LAN - device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge, 9802 to 9806 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge MXM lane 0 + device pci 5.0 off end # PCIE P2P bridge MXM lane 1 + device pci 6.0 on end # PCIE P2P bridge LAN + device pci 7.0 on end # PCIE P2P bridge MINIPCIE SLOT1 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # OHCI FS/LS USB - device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA Express Card - device pci 15.1 on end # PCIe PortB NEC USB3.0 - device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 - device pci 15.3 on end # PCIe PortD PCIE X1 SLOT - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + end # kbc1100 + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # OHCI FS/LS USB + device pci 14.6 on end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA Express Card + device pci 15.1 on end # PCIe PortB NEC USB3.0 + device pci 15.2 on end # PCIe PortC MINIPCIE SLOT2 + device pci 15.3 on end # PCIe PortD PCIE X1 SLOT + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - #device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + #device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/lamar/devicetree.cb b/src/mainboard/amd/lamar/devicetree.cb index 593f95b..3e67a30 100644 --- a/src/mainboard/amd/lamar/devicetree.cb +++ b/src/mainboard/amd/lamar/devicetree.cb @@ -13,102 +13,100 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/pi/00630F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00630F01 - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/pi/00630F01 + device lapic 10 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00630F01 # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00630F01 # CPU side of HT root complex - chip northbridge/amd/pi/00630F01 # PCI side of HT root complex - device pci 0.0 on end # 0x1422 Root Complex - device pci 0.2 off end # 0x1423 IOMMU - device pci 1.0 on end # 0x13XX Internal Graphics - device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio - device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge - device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) - device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 - device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge - device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) - device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) - device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 - device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 - device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 - device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge -# device pci 4.1 on end # 0x1426 P2P bridge for UMI link -# device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 -# device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 -# device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 -# device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 - end #chip northbridge/amd/pi/00630F01 + chip northbridge/amd/pi/00630F01 # PCI side of HT root complex + device pci 0.0 on end # 0x1422 Root Complex + device pci 0.2 off end # 0x1423 IOMMU + device pci 1.0 on end # 0x13XX Internal Graphics + device pci 1.1 on end # 0x1308 DisplayPort/HDMI Audio + device pci 2.0 on end # 0x1424 GFX PCIe Host Bridge + device pci 2.1 on end # 0x1425 P2P Bridge for GFX PCIe Port 0 (PCIe x16 slot J119) + device pci 2.2 off end # 0x1425 P2P Bridge for GFX PCIe Port 1 + device pci 3.0 on end # 0x1424 GPP PCIe Host Bridge + device pci 3.1 on end # 0x1426 P2P Bridge for GPP PCIe Port 0 (PCIe x4 slot J118) + device pci 3.2 on end # 0x1426 P2P Bridge for GPP PCIe Port 1 (PCIe x4 slot J120) + device pci 3.3 off end # 0x1426 P2P Bridge for GPP PCIe Port 2 + device pci 3.4 off end # 0x1426 P2P Bridge for GPP PCIe Port 3 + device pci 3.5 off end # 0x1426 P2P Bridge for GPP PCIe Port 4 + device pci 4.0 on end # 0x1424 UMI PCIe Host Bridge +# device pci 4.1 on end # 0x1426 P2P bridge for UMI link +# device pci 4.2 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 3 +# device pci 4.3 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 2 +# device pci 4.4 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 1 +# device pci 4.5 off end # 0x1426 Virtual P2P bridge for SB PCIe Port 0 + end #chip northbridge/amd/pi/00630F01 - chip southbridge/amd/pi/hudson - device pci 10.0 on end # 0x7814 XHCI HC0 - device pci 10.1 on end # 0x7814 XHCI HC1 - device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) - device pci 12.0 on end # 0x7807 USB OHCI - device pci 12.2 on end # 0x7808 USB EHCI - device pci 13.0 on end # 0x7807 USB OHCI - device pci 13.2 on end # 0x7808 USB EHCI - device pci 14.0 on # 0x780B SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/pi/hudson + device pci 10.0 on end # 0x7814 XHCI HC0 + device pci 10.1 on end # 0x7814 XHCI HC1 + device pci 11.0 on end # 0x7800-0x7805 SATA (device ID depends on mode) + device pci 12.0 on end # 0x7807 USB OHCI + device pci 12.2 on end # 0x7808 USB EHCI + device pci 13.0 on end # 0x7807 USB OHCI + device pci 13.2 on end # 0x7808 USB EHCI + device pci 14.0 on # 0x780B SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # 0x780C IDE + device pci 14.2 on end # 0x780D HDA + device pci 14.3 on # 0x780E LPC + chip superio/fintek/f81216h + register "conf_key_mode" = "0x77" + device pnp 4e.0 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 4e.1 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # 0x780C IDE - device pci 14.2 on end # 0x780D HDA - device pci 14.3 on # 0x780E LPC - chip superio/fintek/f81216h - register "conf_key_mode" = "0x77" - device pnp 4e.0 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.1 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.2 off end # COM3 - device pnp 4e.3 off end # COM4 - device pnp 4e.8 off end # WDT - end # f81865f - end #LPC - device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. - device pci 14.5 on end # 0x7809 USB OHCI - device pci 14.7 on end # 0x7806 SD Flash Controller - device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) - device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) - device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) - device pci 15.3 off end # 0x43A3 SB GPP Port 3 - register "gpp_configuration" = "4" - device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) - end #southbridge/amd/pi/hudson + device pnp 4e.2 off end # COM3 + device pnp 4e.3 off end # COM4 + device pnp 4e.8 off end # WDT + end # f81865f + end #LPC + device pci 14.4 on end # 0x780F PCI :: PCI-b conflict with GPIO. + device pci 14.5 on end # 0x7809 USB OHCI + device pci 14.7 on end # 0x7806 SD Flash Controller + device pci 15.0 on end # 0x43A0 SB GPP Port 0 (Integrated Realtek GbE Controller) + device pci 15.1 on end # 0x43A1 SB GPP Port 1 (mPCIe slot J122) + device pci 15.2 on end # 0x43A2 SB GPP Port 2 (mPCIe slot J123) + device pci 15.3 off end # 0x43A3 SB GPP Port 3 + register "gpp_configuration" = "4" + device pci 16.0 on end # 0x7809 USB OHCI (when the xHCI device is disabled) + end #southbridge/amd/pi/hudson - device pci 18.0 on end # 0x141A HT Configuration - device pci 18.1 on end # 0x141B Address Maps - device pci 18.2 on end # 0x141C DRAM Configuration - device pci 18.3 on end # 0x141D Miscellaneous - device pci 18.4 on end # 0x141E Power Management - device pci 18.5 on end # 0x141F Northbridge + device pci 18.0 on end # 0x141A HT Configuration + device pci 18.1 on end # 0x141B Address Maps + device pci 18.2 on end # 0x141C DRAM Configuration + device pci 18.3 on end # 0x141D Miscellaneous + device pci 18.4 on end # 0x141E Power Management + device pci 18.5 on end # 0x141F Northbridge - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/pi/00630F01 # CPU side of HT root complex - end #domain -end #northbridge/amd/pi/00630F01/root_complex + end #chip northbridge/amd/pi/00630F01 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb index 56efd84..feffe6f 100644 --- a/src/mainboard/amd/mahogany/devicetree.cb +++ b/src/mainboard/amd/mahogany/devicetree.cb @@ -8,114 +8,112 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "1" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8718f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index 5000b0c..0cc8eb9 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -1,129 +1,126 @@ # sample config for amd/mahogany_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM2r2 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "1" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8718f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end +end #domain +#for node 32 to node 63 +#device domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +#end #domain diff --git a/src/mainboard/amd/olivehill/devicetree.cb b/src/mainboard/amd/olivehill/devicetree.cb index 5f0d09a..bf038f4 100644 --- a/src/mainboard/amd/olivehill/devicetree.cb +++ b/src/mainboard/amd/olivehill/devicetree.cb @@ -12,61 +12,59 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family16kb/root_complex + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index ee0cd98..df26577 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -12,61 +12,59 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/pi/00730F01/root_complex - device cpu_cluster 0 on - chip cpu/amd/pi/00730F01 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/pi/00730F01 + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00730F01 # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - chip northbridge/amd/pi/00730F01 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 off end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - device pci 8.0 on end # Platform Security Processor - end #chip northbridge/amd/pi/00730F01 + chip northbridge/amd/pi/00730F01 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + device pci 8.0 on end # Platform Security Processor + end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI #0 - device pci 13.0 on end # EHCI #1 - device pci 14.0 on # SMBus - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SMbus - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - device pci 16.0 on end # EHCI #2 - end #chip southbridge/amd/pi/hudson + chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI #0 + device pci 13.0 on end # EHCI #1 + device pci 14.0 on # SMBus + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SMbus + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + device pci 16.0 on end # EHCI #2 + end #chip southbridge/amd/pi/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses - }" + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2} }, // socket 0, channel 0, slots 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex - end #domain -end #northbridge/amd/pi/00730F01/root_complex + end #chip northbridge/amd/pi/00730F01 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/parmer/devicetree.cb b/src/mainboard/amd/parmer/devicetree.cb index 29d0a53..a1b5c8b 100644 --- a/src/mainboard/amd/parmer/devicetree.cb +++ b/src/mainboard/amd/parmer/devicetree.cb @@ -12,73 +12,70 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 on end # PCIE Slot1 x1 - device pci 7.0 on end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 on end # PCIE Slot1 x1 + device pci 7.0 on end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/hudson + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index afab841..7b82cb5 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -12,146 +12,144 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge PCIe slot - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge PCIe slot + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - #set up SB800 Fan control registers and IMC fan controls - register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common - register "fan0_enabled" = "1" - register "fan1_enabled" = "1" - register "imc_fan_zone0_enabled" = "1" - register "imc_fan_zone1_enabled" = "1" + #set up SB800 Fan control registers and IMC fan controls + register "imc_port_address" = "0x6E" # 0x2E and 0x6E are common + register "fan0_enabled" = "1" + register "fan1_enabled" = "1" + register "imc_fan_zone0_enabled" = "1" + register "imc_fan_zone1_enabled" = "1" - register "fan0_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "fan1_config_vals" = "{ \ - FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ - FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan0_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x08, 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" + register "fan1_config_vals" = "{ \ + FAN_INPUT_INTERNAL_DIODE, FAN_POLARITY_HIGH, \ + FREQ_25KHZ, 0x10, 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }" - register "imc_zone0_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" - register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone0_temp_offset" = "0x00" # No temp offset - register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping + register "imc_zone0_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT0" + register "imc_zone0_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN0 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone0_temp_offset" = "0x00" # No temp offset + register "imc_zone0_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone0_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone0_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone0_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone0_ramping" = "0x00" # Disable Fan PWM ramping and stepping - register "imc_zone1_mode1" = " \ - IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ - IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" - register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ - IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" - register "imc_zone1_temp_offset" = "0x00" # No temp offset - register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis - register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address - register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number - register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate - register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping + register "imc_zone1_mode1" = " \ + IMC_MODE1_FAN_ENABLED | IMC_MODE1_FAN_IMC_CONTROLLED | \ + IMC_MODE1_FAN_STEP_MODE | IMC_MODE1_FANOUT1" + register "imc_zone1_mode2" = " IMC_MODE2_TEMPIN_SB_TSI | \ + IMC_MODE2_FANIN1 | IMC_MODE2_TEMP_AVERAGING_DISABLED" + register "imc_zone1_temp_offset" = "0x00" # No temp offset + register "imc_zone1_hysteresis" = "0x05" # Degrees C Hysteresis + register "imc_zone1_smbus_addr" = "0x98" # Temp Sensor SMBus address + register "imc_zone1_smbus_num" = "IMC_TEMP_SENSOR_ON_SMBUS_3" # SMBUS number + register "imc_zone1_pwm_step" = "0x01" # Fan PWM stepping rate + register "imc_zone1_ramping" = "0x00" # Disable Fan PWM ramping and stepping - # T56N has a Maximum operating temperature of 90C - # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C - # ZONEX_FANSPEEDS - Fan speeds as a "percentage" - register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" - register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" - register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" - register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" + # T56N has a Maximum operating temperature of 90C + # ZONEX_THRESHOLDS - _AC0 - _AC7, _CRT - Temp Threshold in degrees C + # ZONEX_FANSPEEDS - Fan speeds as a "percentage" + register "imc_zone0_thresholds" = "{ 87, 82, 77, 72, 65, 1, 0, 0, 90 }" + register "imc_zone0_fanspeeds" = "{100, 7, 5, 4, 3, 2, 0, 0 }" + register "imc_zone1_thresholds" = "{ 85, 80, 75, 65, 1, 0, 0, 0, 90 }" + register "imc_zone1_fanspeeds" = "{100, 10, 6, 4, 3, 0, 0, 0 }" - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb index 805df7c..0a1cfc2 100644 --- a/src/mainboard/amd/pistachio/devicetree.cb +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -8,73 +8,71 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge, K8 HT Configuration - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - # device pci 0.1 off end # CLK - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" +end +device domain 0 on + subsystemid 0x1022 0x3050 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge, K8 HT Configuration + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + # device pci 0.1 off end # CLK + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end # Internal Graphics 0x791F end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 off end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 off end - end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x438d - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - end #southbridge/amd/sb600 - end # device pci 18.0 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 off end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 off end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x438d + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + end #southbridge/amd/sb600 + end # device pci 18.0 - device pci 18.1 on end # K8 Address Map - device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode - device pci 18.3 on end # K8 Miscellaneous Control - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.1 on end # K8 Address Map + device pci 18.2 on end # K8 DRAM Controller and HT Trace Mode + device pci 18.3 on end # K8 Miscellaneous Control + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index 8ff0e3e..8a4c2f2 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -1,147 +1,145 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory +device cpu_cluster 0 on + chip cpu/amd/socket_F + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on device pci 0.0 on end device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end + device pci 0.2 off end + device pci 1.0 off end end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-2-0 + device i2c 54 on end end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 + chip drivers/generic/generic #dimm 1-2-1 + device i2c 55 on end end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 + chip drivers/generic/generic #dimm 1-3-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-3-1 + device i2c 57 on end end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end end end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/i2c/i2cmux # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-2-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-2-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-3-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-3-1 - device i2c 57 on end - end - end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - chip southbridge/amd/amd8151 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 1.0 on end - end - end # device pci 19.0 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 + device pci 19.0 on # northbridge + chip southbridge/amd/amd8151 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 1.0 on end + end + end # device pci 19.0 - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end - end #domain -end +end #domain diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index 54c34f8..bc477c2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -1,137 +1,134 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F_1207 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_F_1207 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/amd/amd8132 - # the on/off keyword is mandatory +end +device domain 0 on + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + # devices on link 0, link 0 == LDT 0 + chip southbridge/amd/amd8132 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on device pci 0.0 on end device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end + device pci 0.2 off end + device pci 1.0 off end end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + end + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + chip drivers/i2c/i2cmux2 # pca9556 smbus mux + device i2c 18 on #0 pca9516 1 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 + end + device i2c 18 on #1 pca9516 2 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end end end end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - chip drivers/i2c/i2cmux2 # pca9556 smbus mux - device i2c 18 on #0 pca9516 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 18 on #1 pca9516 2 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - end - end - end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - end - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end +end #domain +#for node 32 to node 63 +#device domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +#end #domain diff --git a/src/mainboard/amd/south_station/devicetree.cb b/src/mainboard/amd/south_station/devicetree.cb index 0488f5b..62f5f85 100644 --- a/src/mainboard/amd/south_station/devicetree.cb +++ b/src/mainboard/amd/south_station/devicetree.cb @@ -12,96 +12,94 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM -## chip drivers/generic/generic #dimm 0-0-0 -## device i2c 50 on end -## end -## chip drivers/generic/generic #dimm 0-0-1 -## device i2c 51 on end -## end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81865f - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 off end # Hardware Monitor - device pnp 4e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end # f81865f - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81865f + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 off end # Hardware Monitor + device pnp 4e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + end # f81865f + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/thatcher/devicetree.cb b/src/mainboard/amd/thatcher/devicetree.cb index e7715fa..8d9d124 100644 --- a/src/mainboard/amd/thatcher/devicetree.cb +++ b/src/mainboard/amd/thatcher/devicetree.cb @@ -12,88 +12,85 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x8 - device pci 3.0 off end - device pci 4.0 on end # LAN - device pci 5.0 on end # PCIE MINI0 - device pci 6.0 on end # PCIE MINI1 - device pci 7.0 off end - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x8 + device pci 3.0 off end + device pci 4.0 on end # LAN + device pci 5.0 on end # PCIE MINI0 + device pci 6.0 on end # PCIE MINI1 + device pci 7.0 off end + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/lpc47n217 + device pnp 2e.3 off # Parallel + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/lpc47n217 - device pnp 2e.3 off # Parallel - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end #chip superio/smsc/lpc47n217 - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/hudson + end #chip superio/smsc/lpc47n217 + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 77fd875..64244b2 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -1,130 +1,127 @@ # sample config for amd/tilapia_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8718f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end +end #domain +#for node 32 to node 63 +#device domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +#end #domain diff --git a/src/mainboard/amd/torpedo/devicetree.cb b/src/mainboard/amd/torpedo/devicetree.cb index 2ce1dfd..27af741 100644 --- a/src/mainboard/amd/torpedo/devicetree.cb +++ b/src/mainboard/amd/torpedo/devicetree.cb @@ -12,74 +12,72 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family12/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family12 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1705 inherit - chip northbridge/amd/agesa/family12 # CPU side of HT root complex - chip northbridge/amd/agesa/family12 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics Bridge - device pci 1.1 on end # Audio Controller - device pci 2.0 on end # Root Port - device pci 3.0 on end # Root Port - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge - chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus - device pci 10.0 on end # USB XHCI - device pci 10.1 on end # USB XHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE - device pci 14.2 on end # HDA - device pci 14.3 on # LPC - chip superio/smsc/kbc1100 - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end # kbc1100 - end #LPC - device pci 14.4 on end # PCI bridge - device pci 14.5 on end # USB 2 - device pci 14.6 on end # Ethernet Controller - device pci 14.7 on end # SD Flash Controller - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb900 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family12/root_complex +device cpu_cluster 0 on + chip cpu/amd/agesa/family12 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1705 inherit + chip northbridge/amd/agesa/family12 # CPU side of HT root complex + chip northbridge/amd/agesa/family12 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics Bridge + device pci 1.1 on end # Audio Controller + device pci 2.0 on end # Root Port + device pci 3.0 on end # Root Port + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge + chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pri bus + device pci 10.0 on end # USB XHCI + device pci 10.1 on end # USB XHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE + device pci 14.2 on end # HDA + device pci 14.3 on # LPC + chip superio/smsc/kbc1100 + device pnp 2e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end # kbc1100 + end #LPC + device pci 14.4 on end # PCI bridge + device pci 14.5 on end # USB 2 + device pci 14.6 on end # Ethernet Controller + device pci 14.7 on end # SD Flash Controller + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB + device pci 15.2 on end # PCIe PortC + device pci 15.3 on end # PCIe PortD + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb900 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family12 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/amd/union_station/devicetree.cb b/src/mainboard/amd/union_station/devicetree.cb index d7d80ac..7702a54 100644 --- a/src/mainboard/amd/union_station/devicetree.cb +++ b/src/mainboard/amd/union_station/devicetree.cb @@ -12,72 +12,70 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM -## chip drivers/generic/generic #dimm 0-0-0 -## device i2c 50 on end -## end -## chip drivers/generic/generic #dimm 0-0-1 -## device i2c 51 on end -## end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM +## chip drivers/generic/generic #dimm 0-0-0 +## device i2c 50 on end +## end +## chip drivers/generic/generic #dimm 0-0-1 +## device i2c 51 on end +## end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "0" #4:0:0:0 (really need to disable all 4 somehow) + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/asrock/939a785gmh/devicetree.cb b/src/mainboard/asrock/939a785gmh/devicetree.cb index 8b40b9f..5010917 100644 --- a/src/mainboard/asrock/939a785gmh/devicetree.cb +++ b/src/mainboard/asrock/939a785gmh/devicetree.cb @@ -9,123 +9,121 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_939 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_939 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge 16x slot - device pci 3.0 off end # used in dual slot config - device pci 4.0 off end # GPPSB - device pci 5.0 off end # GPPSB - device pci 6.0 off end # GPPSB - device pci 7.0 off end # GPPSB - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # GPP for x1 slot - device pci a.0 on end # GPP for internal network adapter - register "gppsb_configuration" = "4" # Configuration ? - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x60c" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge 16x slot + device pci 3.0 off end # used in dual slot config + device pci 4.0 off end # GPPSB + device pci 5.0 off end # GPPSB + device pci 6.0 off end # GPPSB + device pci 7.0 off end # GPPSB + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # GPP for x1 slot + device pci a.0 on end # GPP for internal network adapter + register "gppsb_configuration" = "4" # Configuration ? + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x60c" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - #device pnp 2e.6 off # SPI - #end - device pnp 2e.307 off # GPIO6 - end - device pnp 2e.8 on # WDTO#, PLED - end - device pnp 2e.009 on # GPIO2 - end - device pnp 2e.109 on # GPIO3 - end - device pnp 2e.209 on # GPIO4 - end - device pnp 2e.309 off # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # HWM - io 0x60 = 0x290 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w8362 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + #device pnp 2e.6 off # SPI + #end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 on # WDTO#, PLED + end + device pnp 2e.009 on # GPIO2 + end + device pnp 2e.109 on # GPIO3 + end + device pnp 2e.209 on # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w8362 - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/asrock/e350m1/devicetree.cb b/src/mainboard/asrock/e350m1/devicetree.cb index e8b3ea5..574a9ff 100644 --- a/src/mainboard/asrock/e350m1/devicetree.cb +++ b/src/mainboard/asrock/e350m1/devicetree.cb @@ -12,138 +12,136 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge + device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC + chip superio/nuvoton/nct5572d + device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die + device pnp 2e.1 off end # LPT1; same as FDC + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.3 off # IR + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC - chip superio/nuvoton/nct5572d - device pnp 2e.0 off end # FDC; not externally available on the NCT5572D, but on the die - device pnp 2e.1 off end # LPT1; same as FDC - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # IR - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - irq 0x70 = 0 - end - device pnp 2e.107 off end # GPIO6 - device pnp 2e.207 off end # GPIO7 - device pnp 2e.307 on # GPIO8 - irq 0x23 = 0x28 - irq 0xe4 = 0xbf - irq 0xed = 0x27 - end - device pnp 2e.407 off end # GPIO9 - device pnp 2e.8 off end # WDT - device pnp 2e.009 on # GPIO2 - irq 0x2a = 0x42 - irq 0xe0 = 0xe3 - end - device pnp 2e.109 off end # GPIO3 - device pnp 2e.209 off end # GPIO4 - device pnp 2e.309 off end # GPIO5 - device pnp 2e.a on # ACPI - irq 0xe7 = 0x10 - end - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - io 0x62 = 0x0000 # SB-TSI currently not implemented - irq 0x70 = 5 - end - device pnp 2e.c off end # PECI - device pnp 2e.d on # SUSLED - irq 0xec = 0x90 - end - device pnp 2e.e off # CIRWKUP - io 0x60 = 0x0000 - irq 0x70 = 0 - end - device pnp 2e.f off end # GPIO_PP_OD + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB: NIC - device pci 15.2 on end # PCIe PortC: USB3 - device pci 15.3 off end # PCIe PortD - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 + device pnp 2e.6 off # CIR + io 0x60 = 0x100 + irq 0x70 = 0 + end + device pnp 2e.107 off end # GPIO6 + device pnp 2e.207 off end # GPIO7 + device pnp 2e.307 on # GPIO8 + irq 0x23 = 0x28 + irq 0xe4 = 0xbf + irq 0xed = 0x27 + end + device pnp 2e.407 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.009 on # GPIO2 + irq 0x2a = 0x42 + irq 0xe0 = 0xe3 + end + device pnp 2e.109 off end # GPIO3 + device pnp 2e.209 off end # GPIO4 + device pnp 2e.309 off end # GPIO5 + device pnp 2e.a on # ACPI + irq 0xe7 = 0x10 + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + io 0x62 = 0x0000 # SB-TSI currently not implemented + irq 0x70 = 5 + end + device pnp 2e.c off end # PECI + device pnp 2e.d on # SUSLED + irq 0xec = 0x90 + end + device pnp 2e.e off # CIRWKUP + io 0x60 = 0x0000 + irq 0x70 = 0 + end + device pnp 2e.f off end # GPIO_PP_OD + end + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB: NIC + device pci 15.2 on end # PCIe PortC: USB3 + device pci 15.3 off end # PCIe PortD + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 - # gpp_configuration options - #0000: PortA lanes[3:0] - #0001: N/A - #0010: PortA lanes[1:0], PortB lanes[3:2] - #0011: PortA lanes[1:0], PortB lane2, PortC lane3 - #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. - register "gpp_configuration" = "4" + # gpp_configuration options + #0000: PortA lanes[3:0] + #0001: N/A + #0010: PortA lanes[1:0], PortB lanes[3:2] + #0011: PortA lanes[1:0], PortB lane2, PortC lane3 + #0100: PortA lane0, PortB lane1, PortC lane2, PortD lane3. + register "gpp_configuration" = "4" - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/asrock/imb-a180/devicetree.cb b/src/mainboard/asrock/imb-a180/devicetree.cb index e769420..0e44abf 100644 --- a/src/mainboard/asrock/imb-a180/devicetree.cb +++ b/src/mainboard/asrock/imb-a180/devicetree.cb @@ -12,102 +12,100 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # mPCIe slot + device pci 2.3 on end # Realtek NIC + device pci 2.4 on end # Edge Connector + device pci 2.5 on end # Edge Connector + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on + chip superio/winbond/w83627uhg + device pnp 2e.0 off end # FDC + device pnp 2e.1 off end # LPT1 + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627uhg - device pnp 2e.0 off end # FDC - device pnp 2e.1 off end # LPT1 - device pnp 2e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # KEYBRD - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HWMON - device pnp 2e.c off end # PECI - device pnp 2e.d on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.e on # COM5 - io 0x60 = 0x3e0 - irq 0x70 = 4 - end - device pnp 2e.f on # COM6 - io 0x60 = 0x2e0 - irq 0x70 = 3 - end - end # w83627uhg - end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + device pnp 2e.5 on # KEYBRD + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 on # COM3 + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.8 off end # WDT + device pnp 2e.9 off end # GPIO + device pnp 2e.a off end # ACPI + device pnp 2e.b off end # HWMON + device pnp 2e.c off end # PECI + device pnp 2e.d on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.e on # COM5 + io 0x60 = 0x3e0 + irq 0x70 = 4 + end + device pnp 2e.f on # COM6 + io 0x60 = 0x2e0 + irq 0x70 = 3 + end + end # w83627uhg + end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family16kb/root_complex + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +end #domain diff --git a/src/mainboard/asus/a8n_e/devicetree.cb b/src/mainboard/asus/a8n_e/devicetree.cb index bbbfeb8..4b6adc9 100644 --- a/src/mainboard/asus/a8n_e/devicetree.cb +++ b/src/mainboard/asus/a8n_e/devicetree.cb @@ -1,121 +1,119 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_939 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_939 # CPU socket + device lapic 0 on end # Local APIC of the CPU end +end - device domain 0 on # PCI domain - subsystemid 0x1043 0x815a inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x0000 - irq 0x70 = 0x00 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x71 = 2 - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 - irq 0x71 = 2 - end - device pnp 2e.7 on # GPIO config - io 0x60 = 0x0800 - io 0x62 = 0x0808 - io 0x64 = 0x0810 - # Set GPIO 1 & 2 - io 0x25 = 0x0000 - # Set GPIO 3 & 4 - io 0x27 = 0x2540 - # GPIO Polarity for Set 3 - io 0xb2 = 0x2100 - # GPIO Pin Internal Pull up for Set 3 - io 0xba = 0x0100 - # Simple I/O register config - io 0xc0 = 0x0000 - io 0xc2 = 0x2540 - io 0xc8 = 0x0000 - io 0xca = 0x0500 - end - device pnp 2e.8 on # MIDI port - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.a off # IR (N/A on this board) - io 0x60 = 0x310 - irq 0x70 = 11 - end +device domain 0 on # PCI domain + subsystemid 0x1043 0x815a inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x0000 + irq 0x70 = 0x00 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x71 = 2 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + irq 0x71 = 2 + end + device pnp 2e.7 on # GPIO config + io 0x60 = 0x0800 + io 0x62 = 0x0808 + io 0x64 = 0x0810 + # Set GPIO 1 & 2 + io 0x25 = 0x0000 + # Set GPIO 3 & 4 + io 0x27 = 0x2540 + # GPIO Polarity for Set 3 + io 0xb2 = 0x2100 + # GPIO Pin Internal Pull up for Set 3 + io 0xba = 0x0100 + # Simple I/O register config + io 0xc0 = 0x0000 + io 0xc2 = 0x2540 + io 0xc8 = 0x0000 + io 0xca = 0x0500 + end + device pnp 2e.8 on # MIDI port + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.a off # IR (N/A on this board) + io 0x60 = 0x310 + irq 0x70 = 11 end end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # TODO - # register "mac_eeprom_smbus" = "3" - # register "mac_eeprom_addr" = "0x51" end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # TODO + # register "mac_eeprom_smbus" = "3" + # register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb index 5e56acc..5186b6d 100644 --- a/src/mainboard/asus/a8v-e_deluxe/devicetree.cb +++ b/src/mainboard/asus/a8v-e_deluxe/devicetree.cb @@ -1,97 +1,95 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device lapic 0 on end # APIC - end +device cpu_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC end - device domain 0 on # PCI domain - subsystemid 1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO 5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end +end +device domain 0 on # PCI domain + subsystemid 1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 end end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/a8v-e_se/devicetree.cb b/src/mainboard/asus/a8v-e_se/devicetree.cb index f2d078a..02818dc 100644 --- a/src/mainboard/asus/a8v-e_se/devicetree.cb +++ b/src/mainboard/asus/a8v-e_se/devicetree.cb @@ -1,97 +1,95 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # CPU - device lapic 0 on end # APIC - end +device cpu_cluster 0 on # APIC cluster + chip cpu/amd/socket_939 # CPU + device lapic 0 on end # APIC end - device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 off # PS/2 keyboard & mouse (off) - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x201 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 on # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 on # GPIO 5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 (N/A on this board) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 off # PS/2 keyboard & mouse (off) + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x201 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 on # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 on # GPIO 5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 end end - device pci 12.0 off end # VIA LAN (off, other chip used) - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 end + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 6b728d5..5f4d79b 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -12,122 +12,119 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end end +end + +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 blue - device pci 3.0 off end # unused? - device pci 4.0 on end # PCIE 4x black - device pci 5.0 off end # unused? - device pci 6.0 off end # unused? - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register hwm_ctl_register = "0xc0" + register hwm_main_ctl_register = "0x33" + register hwm_adc_temp_chan_en_reg = "0x38" + register hwm_fan1_ctl_pwm = "0x00" + register hwm_fan2_ctl_pwm = "0x00" + register hwm_fan3_ctl_pwm = "0x00" - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 on end # PCIe 0 - onboard PCIe 1x - device pci 15.1 on end # PCIe 1 onboard gigabit - device pci 15.2 off end # unused - device pci 15.3 off end # unused + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused - end #chip southbridge/amd/hudson + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA4}, {0xA2, 0xA6}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +end #domain diff --git a/src/mainboard/asus/f2a85-m_le/devicetree.cb b/src/mainboard/asus/f2a85-m_le/devicetree.cb index c209942..84575a4 100644 --- a/src/mainboard/asus/f2a85-m_le/devicetree.cb +++ b/src/mainboard/asus/f2a85-m_le/devicetree.cb @@ -12,120 +12,117 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end end +end + +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIE SLOT0 x16 blue - device pci 3.0 off end # unused? - device pci 4.0 on end # PCIE 4x black - device pci 5.0 off end # unused? - device pci 6.0 off end # unused? - device pci 7.0 off end # LAN - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register hwm_ctl_register = "0xc0" + register hwm_main_ctl_register = "0x33" + register hwm_adc_temp_chan_en_reg = "0x38" + register hwm_fan1_ctl_pwm = "0x00" + register hwm_fan2_ctl_pwm = "0x00" + register hwm_fan3_ctl_pwm = "0x00" - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 10.1 on end # XHCI HC1 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - register hwm_ctl_register = "0xc0" - register hwm_main_ctl_register = "0x33" - register hwm_adc_temp_chan_en_reg = "0x38" - register hwm_fan1_ctl_pwm = "0x00" - register hwm_fan2_ctl_pwm = "0x00" - register hwm_fan3_ctl_pwm = "0x00" - - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0x290 - io 0x62 = 0x220 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0x228 #SMI - io 0x62 = 0x300 #Simple I/O - io 0x64 = 0x238 #Phony resource IT8603E does not have it - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 on end # PCIe 0 - onboard PCIe 1x - device pci 15.1 on end # PCIe 1 onboard gigabit - device pci 15.2 off end # unused - device pci 15.3 off end # unused - end #chip southbridge/amd/hudson + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +end #domain diff --git a/src/mainboard/asus/k8v-x/devicetree.cb b/src/mainboard/asus/k8v-x/devicetree.cb index 7764413..5154546 100644 --- a/src/mainboard/asus/k8v-x/devicetree.cb +++ b/src/mainboard/asus/k8v-x/devicetree.cb @@ -1,113 +1,111 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # APIC cluster - chip cpu/amd/socket_754 # CPU - device lapic 0 on end # APIC - end +device cpu_cluster 0 on # APIC cluster + chip cpu/amd/socket_754 # CPU + device lapic 0 on end # APIC end - device domain 0 on # PCI domain - subsystemid 0x1043 0x80ed inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0" # Enable SB functions - register "fn_ctrl_hi" = "0xad" # Enable SB functions - register "usb2_termination_set" = "1" - register "usb2_termination_a" = "8" - register "usb2_termination_b" = "8" - register "usb2_termination_c" = "6" - register "usb2_termination_d" = "6" - register "usb2_termination_e" = "6" - register "usb2_termination_f" = "6" - register "usb2_termination_g" = "6" - register "usb2_termination_h" = "6" - register "usb2_dpll_set" = "1" - register "usb2_dpll_delay" = "3" - register "int_efgh_as_gpio" = "1" - register "enable_gpo3" = "1" - register "disable_gpo26_gpo27" = "1" - register "enable_aol_2_smb_slave" = "1" - register "enable_gpo5" = "1" - register "gpio15_12_dir_output" = "1" - device pci 0.0 on # HT - subsystemid 0x1043 0x80a3 - end - device pci a.0 on # GbE - subsystemid 0x1043 0x811a - end - device pci f.0 on end # SATA - device pci f.1 on end # IDE - device pci 10.0 on end # USB1 - device pci 10.1 on end # USB1 - device pci 10.2 on end # USB1 - device pci 10.3 on end # USB1 - device pci 10.4 on end # USB2 - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0x80ed inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0" # Enable SB functions + register "fn_ctrl_hi" = "0xad" # Enable SB functions + register "usb2_termination_set" = "1" + register "usb2_termination_a" = "8" + register "usb2_termination_b" = "8" + register "usb2_termination_c" = "6" + register "usb2_termination_d" = "6" + register "usb2_termination_e" = "6" + register "usb2_termination_f" = "6" + register "usb2_termination_g" = "6" + register "usb2_termination_h" = "6" + register "usb2_dpll_set" = "1" + register "usb2_dpll_delay" = "3" + register "int_efgh_as_gpio" = "1" + register "enable_gpo3" = "1" + register "disable_gpo26_gpo27" = "1" + register "enable_aol_2_smb_slave" = "1" + register "enable_gpo5" = "1" + register "gpio15_12_dir_output" = "1" + device pci 0.0 on # HT + subsystemid 0x1043 0x80a3 + end + device pci a.0 on # GbE + subsystemid 0x1043 0x811a + end + device pci f.0 on end # SATA + device pci f.1 on end # IDE + device pci 10.0 on end # USB1 + device pci 10.1 on end # USB1 + device pci 10.2 on end # USB1 + device pci 10.3 on end # USB1 + device pci 10.4 on end # USB2 + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip superio/winbond/w83697hf # Super I/O + register "hwmon_fan1_divisor" = "128" + register "hwmon_fan2_divisor" = "4" + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.3 off # Com2 (N/A on this board) end - chip superio/winbond/w83697hf # Super I/O - register "hwmon_fan1_divisor" = "128" - register "hwmon_fan2_divisor" = "4" - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 (N/A on this board) - end - device pnp 2e.6 off # CIR - end - device pnp 2e.7 off # Game port/GPIO 1 - end - device pnp 2e.8 off # MIDI/GPIO 5 - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - irq 0x24 = 0x28 # Global CR24 change bit3: MEMW# Enable - end + device pnp 2e.6 off # CIR + end + device pnp 2e.7 off # Game port/GPIO 1 + end + device pnp 2e.8 off # MIDI/GPIO 5 + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 + irq 0x24 = 0x28 # Global CR24 change bit3: MEMW# Enable end end - device pci 11.5 on # AC97 Audio - subsystemid 0x1043 0x80b0 - end - device pci 11.6 on end # AC97 Modem - device pci 12.0 off end # VIA LAN (off, other chip used) end - chip southbridge/via/k8t890 # "Southbridge" K8T890 + device pci 11.5 on # AC97 Audio + subsystemid 0x1043 0x80b0 end + device pci 11.6 on end # AC97 Modem + device pci 12.0 off end # VIA LAN (off, other chip used) + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/kfsn4-dre/devicetree.cb b/src/mainboard/asus/kfsn4-dre/devicetree.cb index 50e2862..5d0adb0 100644 --- a/src/mainboard/asus/kfsn4-dre/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre/devicetree.cb @@ -1,194 +1,192 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8162 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x1000000000" # 64GB - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 2e.0 on # Floppy - # Set up interface resources - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off end # Parallel port - device pnp 2e.2 on # Com1 - # Set up interface resources - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - # Set up interface resources - io 0x60 = 0x2f8 - irq 0x70 = 3 - # Select correct package I/O pins - io 0xf1 = 0x04 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - # Set up interface resources - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 2e.8 off end # GPIO 2 - device pnp 2e.9 on end # GPIO 3, GPIO 4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - # Set up interface resources - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0x8162 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x1000000000" # 64GB + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 on # Floppy + # Set up interface resources + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # Com1 + # Set up interface resources + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end + device pnp 2e.3 on # Com2 + # Set up interface resources + io 0x60 = 0x2f8 + irq 0x70 = 3 + # Select correct package I/O pins + io 0xf1 = 0x04 end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end + device pnp 2e.5 on # PS/2 keyboard & mouse + # Set up interface resources + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/i2c/w83793 - register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs - register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 - register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40 - register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation) - register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2 - register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4 - register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C - register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C - register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C - register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C - register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C - register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C - register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C - register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C - register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C - register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C - register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C - register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C - register "critical_temperature" = "80" # Set critical temperature to 80°C - register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain - register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode - register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything - register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1) - register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2) - register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3) - register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4) - register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1) - register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2) - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V - register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V - register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V - register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V - register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V - register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V - register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V - register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V - register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V - register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V - register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V - register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V - register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V - register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V - register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V - register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V - register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V - register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - device i2c 0x2f on end + device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 on end # GPIO 3, GPIO 4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + # Set up interface resources + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on end # SM 1 - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # AC'97 Audio (N/A) - device pci 4.1 off end # AC'97 Modem (N/A) - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 0 - device pci 8.0 on end # SATA 1 - device pci 9.0 on # Bridge - device pci 4.0 on end # VGA + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end end - device pci a.0 off end - device pci b.0 on # Bridge - device pci 0.0 on end # NIC A + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end end - device pci c.0 on # Bridge - device pci 0.0 on end # LSI SAS + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end end - device pci d.0 on # Bridge - device pci 0.0 on end # NIC B + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end end - device pci e.0 on # Bridge - # Slot # PCI E 0 + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end end - device pci f.0 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + chip drivers/i2c/w83793 + register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs + register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 + register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40 + register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation) + register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2 + register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4 + register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C + register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C + register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C + register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C + register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C + register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C + register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C + register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C + register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C + register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C + register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C + register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C + register "critical_temperature" = "80" # Set critical temperature to 80°C + register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain + register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode + register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything + register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1) + register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2) + register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3) + register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4) + register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1) + register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2) + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V + register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V + register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V + register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V + register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V + register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V + register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V + register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V + register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V + register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V + register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V + register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V + register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V + register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V + register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V + register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V + register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V + register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + device i2c 0x2f on end + end + end + device pci 1.1 on end # SM 1 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # AC'97 Audio (N/A) + device pci 4.1 off end # AC'97 Modem (N/A) + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 0 + device pci 8.0 on end # SATA 1 + device pci 9.0 on # Bridge + device pci 4.0 on end # VGA + end + device pci a.0 off end + device pci b.0 on # Bridge + device pci 0.0 on end # NIC A + end + device pci c.0 on # Bridge + device pci 0.0 on end # LSI SAS + end + device pci d.0 on # Bridge + device pci 0.0 on end # NIC B + end + device pci e.0 on # Bridge + # Slot # PCI E 0 end + device pci f.0 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end end end diff --git a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb index a02b234..d8e24b5 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb +++ b/src/mainboard/asus/kfsn4-dre_k8/devicetree.cb @@ -1,197 +1,195 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8162 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x1000000000" # 64GB - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 2e.0 on # Floppy - # Set up interface resources - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off end # Parallel port - device pnp 2e.2 on # Com1 - # Set up interface resources - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - # Set up interface resources - io 0x60 = 0x2f8 - irq 0x70 = 3 - # Select correct package I/O pins - io 0xf1 = 0x04 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - # Set up interface resources - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 2e.8 off end # GPIO 2 - device pnp 2e.9 on end # GPIO 3, GPIO 4 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - # Set up interface resources - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0x8162 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x1000000000" # 64GB + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 [SB on link 1] + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 on # Floppy + # Set up interface resources + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end + device pnp 2e.1 off end # Parallel port + device pnp 2e.2 on # Com1 + # Set up interface resources + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end + device pnp 2e.3 on # Com2 + # Set up interface resources + io 0x60 = 0x2f8 + irq 0x70 = 3 + # Select correct package I/O pins + io 0xf1 = 0x04 end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end + device pnp 2e.5 on # PS/2 keyboard & mouse + # Set up interface resources + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/i2c/w83793 - register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs - register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 - register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40 - register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation) - register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) - register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2 - register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4 - register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C - register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C - register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C - register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C - register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C - register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C - register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C - register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C - register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C - register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C - register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C - register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C - register "critical_temperature" = "80" # Set critical temperature to 80°C - register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain - register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode - register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything - register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1) - register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2) - register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3) - register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4) - register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1) - register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2) - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V - register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V - register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V - register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V - register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V - register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V - register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V - register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V - register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V - register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V - register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V - register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V - register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V - register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V - register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V - register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V - register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V - register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - device i2c 0x2f on end + device pnp 2e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 2e.8 off end # GPIO 2 + device pnp 2e.9 on end # GPIO 3, GPIO 4 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + # Set up interface resources + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on end # SM 1 - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # AC'97 Audio (N/A) - device pci 4.1 off end # AC'97 Modem (N/A) - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 0 - device pci 8.0 on end # SATA 1 - device pci 9.0 on # Bridge - device pci 4.0 on end # VGA + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end end - device pci a.0 off end - device pci b.0 on # Bridge - device pci 0.0 on end # NIC A + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end end - device pci c.0 on # Bridge - device pci 0.0 on end # LSI SAS + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end end - device pci d.0 on # Bridge - device pci 0.0 on end # NIC B + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end end - device pci e.0 on # Bridge - # Slot # PCI E 0 + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end end - device pci f.0 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + chip drivers/i2c/w83793 + register "mfc" = "0x29" # Enable FANIN1/FANIN12, FANIN9/FANIN10, and FANIN8/FANCTRL8 inputs + register "fanin" = "0x7f" # Enable monitoring of FANIN6 - FANIN12 + register "fanin_sel" = "0x0f" # Connect FANIN9 - FANIN12 to pins 37 - 40 + register "peci_agent_conf" = "0x33" # Set Intel CPU PECI agent domain (not used by AMD but may affect chip operation) + register "tcase0" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tcase1" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tcase2" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tcase3" = "94" # Set maximum Intel CPU case temperature to 94°C (not used by AMD but may affect chip operation) + register "tr_enable" = "0x03" # Enable montoring of TR1 and TR2 + register "td_mode_select" = "0x05" # Use internal temperature sensors and disable unconnected TD3/TD4 + register "td1_critical_temperature" = "85" # Set TD1 (CPU0) critical temperature to 85°C + register "td1_critical_hysteresis" = "80" # Set TD1 (CPU0) critical hysteresis temperature to 80°C + register "td1_warning_temperature" = "70" # Set TD1 (CPU0) warning temperature to 70°C + register "td1_warning_hysteresis" = "65" # Set TD1 (CPU0) warning hysteresis temperature to 65°C + register "td2_critical_temperature" = "85" # Set TD2 (CPU1) critical temperature to 85°C + register "td2_critical_hysteresis" = "80" # Set TD2 (CPU1) critical hysteresis temperature to 80°C + register "td2_warning_temperature" = "70" # Set TD2 (CPU1) warning temperature to 70°C + register "td2_warning_hysteresis" = "65" # Set TD2 (CPU1) warning hysteresis temperature to 65°C + register "tr1_critical_temperature" = "60" # Set TR1 (mainboard) critical temperature to 60°C + register "tr1_critical_hysteresis" = "55" # Set TR1 (mainboard) critical hysteresis temperature to 55°C + register "tr1_warning_temperature" = "50" # Set TR1 (mainboard) warning temperature to 50°C + register "tr1_warning_hysteresis" = "45" # Set TR1 (mainboard) warning hysteresis temperature to 45°C + register "critical_temperature" = "80" # Set critical temperature to 80°C + register "fanctrl1" = "0x48" # Set Fan 4 and Fan 7 to output buffer mode, all others to open drain + register "fanctrl2" = "0x01" # Set Fan 4 to Fan 7 to output buffer mode, Fan 1 to DC mode + register "first_valid_fan_number" = "2" # Fan 1/Fan 2 controls and sensors are not connected to anything + register "td1_fan_select" = "0x00" # All fans to manual mode (no dependence on TD1) + register "td2_fan_select" = "0x00" # All fans to manual mode (no dependence on TD2) + register "td3_fan_select" = "0x00" # All fans to manual mode (no dependence on TD3) + register "td4_fan_select" = "0x00" # All fans to manual mode (no dependence on TD4) + register "tr1_fan_select" = "0x00" # All fans to manual mode (no dependence on TR1) + register "tr2_fan_select" = "0x00" # All fans to manual mode (no dependence on TR2) + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcorea_high_limit_mv" = "1500" # VCOREA (Node 0) high limit to 1.5V + register "vcorea_low_limit_mv" = "900" # VCOREA (Node 0) low limit to 0.9V + register "vcoreb_high_limit_mv" = "1500" # VCOREB (Node 1) high limit to 1.5V + register "vcoreb_low_limit_mv" = "900" # VCOREB (Node 1) low limit to 0.9V + register "vtt_high_limit_mv" = "1250" # VTT (HT link voltage) high limit to 1.25V + register "vtt_low_limit_mv" = "1150" # VTT (HT link voltage) low limit to 1.15V + register "vsen1_high_limit_mv" = "1900" # VSEN1 (Node 0 RAM voltage) high limit to 1.9V + register "vsen1_low_limit_mv" = "1700" # VSEN1 (Node 0 RAM voltage) low limit to 1.7V + register "vsen2_high_limit_mv" = "1900" # VSEN2 (Node 1 RAM voltage) high limit to 1.9V + register "vsen2_low_limit_mv" = "1700" # VSEN2 (Node 1 RAM voltage) low limit to 1.7V + register "vsen3_high_limit_mv" = "3500" # VSEN3 (+3.3V) high limit to 3.5V + register "vsen3_low_limit_mv" = "3100" # VSEN3 (+3.3V) low limit to 3.1V + register "vsen4_high_limit_mv" = "1070" # VSEN4 (+12V, scaling factor ~12.15) high limit to 13V + register "vsen4_low_limit_mv" = "905" # VSEN4 (+12V, scaling factor ~12.15) low limit to 11V + register "vdd_high_limit_mv" = "5200" # 5VDD high limit to 5.2V + register "vdd_low_limit_mv" = "4800" # 5VDD low limit to 4.8V + register "vsb_high_limit_mv" = "5200" # 5VSB high limit to 5.2V + register "vsb_low_limit_mv" = "4800" # 5VSB low limit to 4.8V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + device i2c 0x2f on end + end + end + device pci 1.1 on end # SM 1 + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # AC'97 Audio (N/A) + device pci 4.1 off end # AC'97 Modem (N/A) + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 0 + device pci 8.0 on end # SATA 1 + device pci 9.0 on # Bridge + device pci 4.0 on end # VGA + end + device pci a.0 off end + device pci b.0 on # Bridge + device pci 0.0 on end # NIC A + end + device pci c.0 on # Bridge + device pci 0.0 on end # LSI SAS + end + device pci d.0 on # Bridge + device pci 0.0 on end # NIC B + end + device pci e.0 on # Bridge + # Slot # PCI E 0 end + device pci f.0 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end # Link 0 == LDT 0 - device pci 19.0 on end # Link 1 == LDT 1 - device pci 19.0 on end # Link 2 == LDT 2 - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end end + device pci 18.0 on end # Link 2 == LDT 2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end # Link 0 == LDT 0 + device pci 19.0 on end # Link 1 == LDT 1 + device pci 19.0 on end # Link 2 == LDT 2 + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end end end diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index abe6d16..9fa14c6 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -1,244 +1,242 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8163 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - register "maximum_memory_capacity" = "0x4000000000" # 256GB - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on end # Link 1 == LDT 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] - chip southbridge/amd/sr5650 # Primary southbridge - device pci 0.0 on end # HT Root Complex 0x9600 - device pci 0.1 on end # CLKCONFIG - device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) - # Slot # PCI E 1 / PCI E 2 +end +device domain 0 on # PCI domain + subsystemid 0x1043 0x8163 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + register "maximum_memory_capacity" = "0x4000000000" # 256GB + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on end # Link 1 == LDT 1 + device pci 18.0 on end # Link 2 == LDT 2 + device pci 18.0 on # Link 3 == LDT 3 [SB on link 3] + chip southbridge/amd/sr5650 # Primary southbridge + device pci 0.0 on end # HT Root Complex 0x9600 + device pci 0.1 on end # CLKCONFIG + device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) + # Slot # PCI E 1 / PCI E 2 + end + device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) + device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) + # PIKE SAS + end + device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1) + device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2) + device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3) + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on # Bridge (GPP3a Port4) + # Onboard # NIC A + end + device pci a.0 on # Bridge (GPP3a Port5) + # Onboard # NIC B + end + device pci b.0 on # Bridge (GPP2 Port0) + # Slot # PCI E 4 + end + device pci c.0 on # Bridge (GPP2 Port1) + # Slot # PCI E 5 + end + device pci d.0 on # Bridge (GPP3b Port0) + # Slot # PCI E 3 + end + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 + register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 + register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured + end + chip southbridge/amd/sb700 # Secondary southbridge + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic # DIMM n-0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM n-0-0-1 + device i2c 51 on end end - device pci 3.0 off end # PCIE P2P bridge 0x960b (GPP1 Port1) - device pci 4.0 on # PCIE P2P bridge 0x9604 (GPP3a Port0) - # PIKE SAS + chip drivers/generic/generic # DIMM n-0-1-0 + device i2c 52 on end end - device pci 5.0 off end # PCIE P2P bridge 0x9605 (GPP3a Port1) - device pci 6.0 off end # PCIE P2P bridge 0x9606 (GPP3a Port2) - device pci 7.0 off end # PCIE P2P bridge 0x9607 (GPP3a Port3) - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on # Bridge (GPP3a Port4) - # Onboard # NIC A + chip drivers/generic/generic # DIMM n-0-1-1 + device i2c 53 on end end - device pci a.0 on # Bridge (GPP3a Port5) - # Onboard # NIC B + chip drivers/generic/generic # DIMM n-1-0-0 + device i2c 54 on end end - device pci b.0 on # Bridge (GPP2 Port0) - # Slot # PCI E 4 + chip drivers/generic/generic # DIMM n-1-0-1 + device i2c 55 on end end - device pci c.0 on # Bridge (GPP2 Port1) - # Slot # PCI E 5 + chip drivers/generic/generic # DIMM n-1-1-0 + device i2c 56 on end end - device pci d.0 on # Bridge (GPP3b Port0) - # Slot # PCI E 3 + chip drivers/generic/generic # DIMM n-1-1-1 + device i2c 57 on end + end + chip drivers/i2c/w83795 + register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 + register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions + register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 + register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 + register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 + register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 + register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT + register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) + register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) + register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) + register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) + register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) + register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) + register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 + register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 + register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 + register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 + register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 + register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 + register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C + register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C + register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C + register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C + register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C + register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C + register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C + register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C + register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V + register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V + register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V + register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V + register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V + register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V + register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V + register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V + register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V + register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V + register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V + register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V + register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V + register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V + register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V + register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V + register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V + register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V + register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V + register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V + register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V + register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V + register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V + register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V + register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V + register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V + register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V + register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V + register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller + device i2c 0x2f on end end - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "port_enable" = "0x3f1c" # Enable all ports except 0, 1, 5, 6, and 7 - register "pcie_settling_time" = "1000000" # Allow PIKE to be detected / configured end - chip southbridge/amd/sb700 # Secondary southbridge - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic # DIMM n-0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM n-0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM n-0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM n-0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM n-1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM n-1-0-1 - device i2c 55 on end + device pci 14.1 on end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 (KGPE-D16 omits audio option) + device pci 14.3 on # LPC 0x439d (SMBUS primary controller) + chip superio/nuvoton/nct5572d # Super I/O + device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 + device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM n-1-1-0 - device i2c 56 on end + device pnp 2e.3 off end # IR: Not available on the KGPE-D16 + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM n-1-1-1 - device i2c 57 on end - end - chip drivers/i2c/w83795 - register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 - register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions - register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 - register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 - register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 - register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 - register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT - register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) - register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) - register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) - register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) - register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) - register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) - register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 - register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 - register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 - register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 - register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 - register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 - register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C - register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C - register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C - register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C - register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C - register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C - register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C - register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C - register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V - register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V - register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V - register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V - register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V - register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V - register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V - register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V - register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V - register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V - register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V - register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V - register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V - register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V - register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V - register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V - register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V - register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V - register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V - register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V - register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V - register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V - register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V - register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V - register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V - register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V - register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V - register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V - register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - register "smbus_aux" = "1" # Device located on auxiliary SMBUS controller - device i2c 0x2f on end - end - end - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 (KGPE-D16 omits audio option) - device pci 14.3 on # LPC 0x439d (SMBUS primary controller) - chip superio/nuvoton/nct5572d # Super I/O - device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 - device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off end # IR: Not available on the KGPE-D16 - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR: Not available on the KGPE-D16 - device pnp 2e.7 off end # GIPO689 - device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO235 - device pnp 2e.a on end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - io 0x62 = 0x0000 # SB-TSI currently not implemented - irq 0x70 = 5 - end - device pnp 2e.c off end # PECI - device pnp 2e.d off end # SUSLED - device pnp 2e.e off end # CIRWKUP - device pnp 2e.f off end # GPIO_PP_OD + device pnp 2e.6 off end # CIR: Not available on the KGPE-D16 + device pnp 2e.7 off end # GIPO689 + device pnp 2e.8 off end # WDT + device pnp 2e.9 off end # GPIO235 + device pnp 2e.a on end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + io 0x62 = 0x0000 # SB-TSI currently not implemented + irq 0x70 = 5 end + device pnp 2e.c off end # PECI + device pnp 2e.d off end # SUSLED + device pnp 2e.e off end # CIRWKUP + device pnp 2e.f off end # GPIO_PP_OD end - device pci 14.4 on # Bridge - device pci 1.0 on end # VGA - device pci 2.0 on end # FireWire - device pci 3.0 on # Slot - # Slot # PCI 0 - end + end + device pci 14.4 on # Bridge + device pci 1.0 on end # VGA + device pci 2.0 on end # FireWire + device pci 3.0 on # Slot + # Slot # PCI 0 end - device pci 14.5 on end # USB OHCI2 0x4399 end + device pci 14.5 on end # USB OHCI2 0x4399 end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 19.0 on end # Socket 0 node 1 - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - device pci 19.5 on end - device pci 1a.0 on end # Socket 1 node 0 - device pci 1a.1 on end - device pci 1a.2 on end - device pci 1a.3 on end - device pci 1a.4 on end - device pci 1a.5 on end - device pci 1b.0 on end # Socket 1 node 1 - device pci 1b.1 on end - device pci 1b.2 on end - device pci 1b.3 on end - device pci 1b.4 on end - device pci 1b.5 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 19.0 on end # Socket 0 node 1 + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + device pci 19.5 on end + device pci 1a.0 on end # Socket 1 node 0 + device pci 1a.1 on end + device pci 1a.2 on end + device pci 1a.3 on end + device pci 1a.4 on end + device pci 1a.5 on end + device pci 1b.0 on end # Socket 1 node 1 + device pci 1b.1 on end + device pci 1b.2 on end + device pci 1b.3 on end + device pci 1b.4 on end + device pci 1b.5 on end end end diff --git a/src/mainboard/asus/m2n-e/devicetree.cb b/src/mainboard/asus/m2n-e/devicetree.cb index 5938684..82b1c1d 100644 --- a/src/mainboard/asus/m2n-e/devicetree.cb +++ b/src/mainboard/asus/m2n-e/devicetree.cb @@ -13,105 +13,102 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## - -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_AM2 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_AM2 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1043 0x8239 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A) - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - io 0x62 = 0x000 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x000 - irq 0x70 = 0 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ - end - device pnp 2e.6 on # PS/2 mouse - irq 0x70 = 12 # PS/2 mouse IRQ - end - device pnp 2e.7 off # GPIO - io 0x60 = 0x0000 # SMI# Normal Run Access - io 0x62 = 0x800 # Simple I/O - io 0x64 = 0x0000 # Serial Flash I/F - end - device pnp 2e.8 off # MIDI (N/A) - end - device pnp 2e.9 off # Game port (N/A) - end - device pnp 2e.a off # Consumer IR (N/A) - end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0x8239 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8716f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A) + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + io 0x62 = 0x000 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x000 + irq 0x70 = 0 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard IRQ end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 # PS/2 mouse IRQ end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.7 off # GPIO + io 0x60 = 0x0000 # SMI# Normal Run Access + io 0x62 = 0x800 # Simple I/O + io 0x64 = 0x0000 # Serial Flash I/F end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.8 off # MIDI (N/A) end + device pnp 2e.9 off # Game port (N/A) + end + device pnp 2e.a off # Consumer IR (N/A) + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # Azalia (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A) - device pci a.0 on end # PCI E 5 (PCIEX4) - device pci b.0 off end # PCI E 4 - device pci c.0 on end # PCI E 3 (PCIEX1_2) - device pci d.0 on end # PCI E 2 (PCIEX1_1) - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 (PCIEX16_1) - register "ide0_enable" = "1" # Primary IDE - register "ide1_enable" = "0" # Secondary IDE (N/A) - register "sata0_enable" = "1" - register "sata1_enable" = "1" end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # Azalia (HD Audio) + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC (N/A) + device pci a.0 on end # PCI E 5 (PCIEX4) + device pci b.0 off end # PCI E 4 + device pci c.0 on end # PCI E 3 (PCIEX1_2) + device pci d.0 on end # PCI E 2 (PCIEX1_1) + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 (PCIEX16_1) + register "ide0_enable" = "1" # Primary IDE + register "ide1_enable" = "0" # Secondary IDE (N/A) + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/m2v-mx_se/devicetree.cb b/src/mainboard/asus/m2v-mx_se/devicetree.cb index 213e3ea..740a5bb 100644 --- a/src/mainboard/asus/m2v-mx_se/devicetree.cb +++ b/src/mainboard/asus/m2v-mx_se/devicetree.cb @@ -1,77 +1,75 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device lapic 0 on end # APIC - end +device cpu_cluster 0 on # APIC cluster + chip cpu/amd/socket_AM2 # CPU + device lapic 0 on end # APIC end - device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x1d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x1d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR - end - end - device pci 12.0 on end # VIA LAN - device pci 13.0 on end # br - device pci 13.1 on end # br2 need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8M890 - end + device pnp 2e.4 on # Environment controller + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR + end + end + device pci 12.0 on end # VIA LAN + device pci 13.0 on end # br + device pci 13.1 on end # br2 need to have it here to discover it + end + chip southbridge/via/k8t890 # "Southbridge" K8M890 end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/m2v/devicetree.cb b/src/mainboard/asus/m2v/devicetree.cb index 61d94ba..96d5dfd 100644 --- a/src/mainboard/asus/m2v/devicetree.cb +++ b/src/mainboard/asus/m2v/devicetree.cb @@ -1,75 +1,73 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device lapic 0 on end # APIC - end +device cpu_cluster 0 on # APIC cluster + chip cpu/amd/socket_AM2 # CPU + device lapic 0 on end # APIC end - device domain 0 on # PCI domain - subsystemid 0x1043 0 inherit - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 - chip southbridge/via/vt8237r # Southbridge - register "ide0_enable" = "1" # Enable IDE channel 0 - register "ide1_enable" = "1" # Enable IDE channel 1 - register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 - register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 - register "fn_ctrl_lo" = "0xc0" # Enable SB functions - register "fn_ctrl_hi" = "0x0d" # Enable SB functions - device pci 0.0 on end # HT - device pci f.1 on end # IDE - device pci 11.0 on # LPC - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end +end +device domain 0 on # PCI domain + subsystemid 0x1043 0 inherit + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x0d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.2 off end # Com2 (N/A on this board) + device pnp 2e.3 on # Lpt1 + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 end - chip superio/ite/it8712f # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off end # Com2 (N/A on this board) - device pnp 2e.3 on # Lpt1 - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.4 on # Environment controller - io 0x60 = 0xd00 - io 0x62 = 0xc00 - irq 0x70 = 0x00 - end - device pnp 2e.5 off end # PS/2 keyboard - device pnp 2e.6 off end # PS/2 mouse - device pnp 2e.7 off end # GPIO config - device pnp 2e.8 off end # Midi port - device pnp 2e.9 off end # Game port - device pnp 2e.a off end # IR + device pnp 2e.4 on # Environment controller + io 0x60 = 0xd00 + io 0x62 = 0xc00 + irq 0x70 = 0x00 end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR end - device pci 12.0 off end # VIA LAN (off, other chip used) - device pci 13.0 on end # br - device pci 13.1 on end # br2, need to have it here to discover it - end - chip southbridge/via/k8t890 # "Southbridge" K8T890 end + device pci 12.0 off end # VIA LAN (off, other chip used) + device pci 13.0 on end # br + device pci 13.1 on end # br2, need to have it here to discover it + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/asus/m4a78-em/devicetree.cb b/src/mainboard/asus/m4a78-em/devicetree.cb index e760c17..80d132f 100644 --- a/src/mainboard/asus/m4a78-em/devicetree.cb +++ b/src/mainboard/asus/m4a78-em/devicetree.cb @@ -1,106 +1,104 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1043 0x83f1 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" +end +device domain 0 on + subsystemid 0x1043 0x83f1 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # bridge to RTL8112 PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - end - device pnp 2e.9 off # GAME - end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + end + device pnp 2e.9 off # GAME + end + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # chip northbridge - end #domain -end # northbridge/amd/amdfam10/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge +end #domain diff --git a/src/mainboard/asus/m4a785-m/devicetree.cb b/src/mainboard/asus/m4a785-m/devicetree.cb index 4549ead..b8a020d 100644 --- a/src/mainboard/asus/m4a785-m/devicetree.cb +++ b/src/mainboard/asus/m4a785-m/devicetree.cb @@ -1,106 +1,104 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1043 0x83a2 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" +end +device domain 0 on + subsystemid 0x1043 0x83a2 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 off end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - end - device pnp 2e.9 off # GAME - end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + end + device pnp 2e.9 off # GAME + end + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # chip northbridge - end #domain -end # northbridge/amd/amdfam10/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge +end #domain diff --git a/src/mainboard/asus/m4a785t-m/devicetree.cb b/src/mainboard/asus/m4a785t-m/devicetree.cb index 9783989..2d7d85c 100644 --- a/src/mainboard/asus/m4a785t-m/devicetree.cb +++ b/src/mainboard/asus/m4a785t-m/devicetree.cb @@ -1,108 +1,106 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1043 0x83a2 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on # Internal Graphics P2P bridge 0x9602 - device pci 5.0 on end # onboard VGA - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" +end +device domain 0 on + subsystemid 0x1043 0x83a2 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on # Internal Graphics P2P bridge 0x9602 + device pci 5.0 on end # onboard VGA end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # bridge to RTL8111/8168B PCI Express Gigabit Ethernet + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8712f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.8 off # MIDI end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.9 off # GAME end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8712f - device pnp 2e.0 off end # Floppy - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # Environment Controller - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - end - device pnp 2e.9 off # GAME - end - device pnp 2e.a off end # CIR - end #superio - end #LPC - device pci 14.4 on end # PCI to PCI Bridge [1002:4384] - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.a off end # CIR + end #superio + end #LPC + device pci 14.4 on end # PCI to PCI Bridge [1002:4384] + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # chip northbridge - end #domain -end # northbridge/amd/amdfam10/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # chip northbridge +end #domain diff --git a/src/mainboard/asus/m5a88-v/devicetree.cb b/src/mainboard/asus/m5a88-v/devicetree.cb index 65ddf30..e4209a5 100644 --- a/src/mainboard/asus/m5a88-v/devicetree.cb +++ b/src/mainboard/asus/m5a88-v/devicetree.cb @@ -1,124 +1,122 @@ # sample config for advansus/A785E-I -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id. - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # Ethernet - device pci a.0 on end # Ethernet - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "3" # Configuration D - register "port_enable" = "0x6f6" - register "gfx_dev2_dev3" = "0" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - register "gfx_tmds" = "1" - register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 - register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL - end - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC host controller [1002:439d] - chip superio/ite/it8721f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/ite/it8721f - end # LPC host controller [1002:439d] - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 15.0 on end # PCIe 0 - device pci 15.1 on end # PCIe 1 - device pci 15.2 on end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - #register "gpp_configuration" = "0" #4:0:0:0 - #register "gpp_configuration" = "2" #2:2:0:0 - #register "gpp_configuration" = "3" #2:1:1:0 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain end +device domain 0 on + subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id. + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # Ethernet + device pci a.0 on end # Ethernet + register "gppsb_configuration" = "4" # Configuration E + register "gpp_configuration" = "3" # Configuration D + register "port_enable" = "0x6f6" + register "gfx_dev2_dev3" = "0" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + register "gfx_tmds" = "1" + register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15 + register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL + end + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC host controller [1002:439d] + chip superio/ite/it8721f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/ite/it8721f + end # LPC host controller [1002:439d] + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 15.0 on end # PCIe 0 + device pci 15.1 on end # PCIe 1 + device pci 15.2 on end # PCIe 2 + device pci 15.3 on end # PCIe 3 + device pci 16.0 on end # USB + device pci 16.2 on end # USB + #register "gpp_configuration" = "0" #4:0:0:0 + #register "gpp_configuration" = "2" #2:2:0:0 + #register "gpp_configuration" = "3" #2:1:1:0 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end +end #domain diff --git a/src/mainboard/avalue/eax-785e/devicetree.cb b/src/mainboard/avalue/eax-785e/devicetree.cb index 42ddf01..03721be 100644 --- a/src/mainboard/avalue/eax-785e/devicetree.cb +++ b/src/mainboard/avalue/eax-785e/devicetree.cb @@ -1,111 +1,109 @@ # sample config for avalue/EAX-785E -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id. - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 - device pci 2.0 on end # GFX_RX0-7/TX0-7 PCIEx16_1 slot - device pci 3.0 on end # GFX_RX8-15/TX8-15 PCIEx16_2 slot - device pci 4.0 on end # PortB GPP_RX/TX0 PCIEx1_1 slot - device pci 5.0 on end # PortC GPP_RX/TX1 PCIEx1_2 slot - device pci 6.0 on end # PortD GPP_RX/TX2 PCIEx1_3 slot - device pci 7.0 on end # PortE GPP_RX/TX3 PCIEx1_4 slot - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # Ethernet - device pci a.0 on end # Ethernet - register "gppsb_configuration" = "4" # Configuration E - register "gpp_configuration" = "3" # Configuration D - register "port_enable" = "0x6FE" - register "gfx_dev2_dev3" = "0" #no use - register "gfx_dual_slot" = "1" # 0 single slot, 1 dual slot - register "gfx_lane_reversal" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - register "gfx_tmds" = "1" - register "gfx_pcie_config" = "4" # 2x8 GFX, one on Lanes 0-7, one on Lanes 8-15 - register "gfx_ddi_config" = "0" # no DDI_SL - end - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 Keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf - end # LPC 0x439d - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 on end # PCIe 3 - device pci 16.0 on end # USB - device pci 16.2 on end # USB - #register "gpp_configuration" = "0" #4:0:0:0 - #register "gpp_configuration" = "2" #2:2:0:0 - #register "gpp_configuration" = "3" #2:1:1:0 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - end # device pci 18.0 - - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain end +device domain 0 on + subsystemid 0x1612 0x3060 inherit #TODO: Set the correctly subsystem id. + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9712 + device pci 2.0 on end # GFX_RX0-7/TX0-7 PCIEx16_1 slot + device pci 3.0 on end # GFX_RX8-15/TX8-15 PCIEx16_2 slot + device pci 4.0 on end # PortB GPP_RX/TX0 PCIEx1_1 slot + device pci 5.0 on end # PortC GPP_RX/TX1 PCIEx1_2 slot + device pci 6.0 on end # PortD GPP_RX/TX2 PCIEx1_3 slot + device pci 7.0 on end # PortE GPP_RX/TX3 PCIEx1_4 slot + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # Ethernet + device pci a.0 on end # Ethernet + register "gppsb_configuration" = "4" # Configuration E + register "gpp_configuration" = "3" # Configuration D + register "port_enable" = "0x6FE" + register "gfx_dev2_dev3" = "0" #no use + register "gfx_dual_slot" = "1" # 0 single slot, 1 dual slot + register "gfx_lane_reversal" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + register "gfx_tmds" = "1" + register "gfx_pcie_config" = "4" # 2x8 GFX, one on Lanes 0-7, one on Lanes 8-15 + register "gfx_ddi_config" = "0" # no DDI_SL + end + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 Keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf + end # LPC 0x439d + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 on end # PCIe 3 + device pci 16.0 on end # USB + device pci 16.2 on end # USB + #register "gpp_configuration" = "0" #4:0:0:0 + #register "gpp_configuration" = "2" #2:2:0:0 + #register "gpp_configuration" = "3" #2:1:1:0 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + end # device pci 18.0 + + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end +end #domain diff --git a/src/mainboard/bap/ode_e20XX/devicetree.cb b/src/mainboard/bap/ode_e20XX/devicetree.cb index a598a99..b2b2225 100644 --- a/src/mainboard/bap/ode_e20XX/devicetree.cb +++ b/src/mainboard/bap/ode_e20XX/devicetree.cb @@ -12,102 +12,100 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe Slot - device pci 2.2 on end # PCIe Q7 Realtek GBit LAN - device pci 2.3 on end # PCIe CB Realtek GBit LAN - device pci 2.4 on end # PCIe BAP FPGA - device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T) - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe Slot + device pci 2.2 on end # PCIe Q7 Realtek GBit LAN + device pci 2.3 on end # PCIe CB Realtek GBit LAN + device pci 2.4 on end # PCIe BAP FPGA + device pci 2.5 on end # PCIe BAP FPGA (unused, for 050T) + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f81866d - register "hwm_amd_tsi_addr" = "0x98" # Set to AMD - register "hwm_amd_tsi_control" = "0x02" # Set to AMD - register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM - register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode - register "hwm_fan3_control" = "0x00" # Fan control 23kHz - register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz - register "hwm_fan2_bound1" = "0x3C" # 60°C - register "hwm_fan2_bound2" = "0x32" # 50°C - register "hwm_fan2_bound3" = "0x28" # 40°C - register "hwm_fan2_bound4" = "0x1E" # 30°C - register "hwm_fan2_seg1_speed" = "0xFF" # 100% - register "hwm_fan2_seg2_speed" = "0xD9" # 85% - register "hwm_fan2_seg3_speed" = "0xB2" # 70% - register "hwm_fan2_seg4_speed" = "0x99" # 60% - register "hwm_fan2_seg5_speed" = "0x80" # 50% - register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 on # Hardware Monitor - io 0x60 = 0x295 - irq 0x70 = 0 - end - device pnp 4e.5 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.6 off end # GPIO - device pnp 4e.7 on end # WDT - device pnp 4e.a off end # PME - device pnp 4e.10 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.11 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.12 off # COM3 - end - device pnp 4e.13 off # COM4 - end - device pnp 4e.14 off # COM5 - end - device pnp 4e.15 off # COM6 - end - end # f81866d - end #LPC - device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f81866d + register "hwm_amd_tsi_addr" = "0x98" # Set to AMD + register "hwm_amd_tsi_control" = "0x02" # Set to AMD + register "hwm_fan_select" = "0xC0" # Sets Fan2 to PWM + register "hwm_fan_mode" = "0xD5" # Sets FAN1-3 to Auto RPM mode + register "hwm_fan3_control" = "0x00" # Fan control 23kHz + register "hwm_fan2_temp_map_select" = "0x1E" # Fan control 23kHz + register "hwm_fan2_bound1" = "0x3C" # 60°C + register "hwm_fan2_bound2" = "0x32" # 50°C + register "hwm_fan2_bound3" = "0x28" # 40°C + register "hwm_fan2_bound4" = "0x1E" # 30°C + register "hwm_fan2_seg1_speed" = "0xFF" # 100% + register "hwm_fan2_seg2_speed" = "0xD9" # 85% + register "hwm_fan2_seg3_speed" = "0xB2" # 70% + register "hwm_fan2_seg4_speed" = "0x99" # 60% + register "hwm_fan2_seg5_speed" = "0x80" # 50% + register "hwm_temp_sens_type" = "0x04" # Sets temp sensor 1 type to to thermistor + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # Hardware Monitor + io 0x60 = 0x295 + irq 0x70 = 0 + end + device pnp 4e.5 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.6 off end # GPIO + device pnp 4e.7 on end # WDT + device pnp 4e.a off end # PME + device pnp 4e.10 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.11 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.12 off # COM3 + end + device pnp 4e.13 off # COM4 + end + device pnp 4e.14 off # COM5 + end + device pnp 4e.15 off # COM6 + end + end # f81866d + end #LPC + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family16kb/root_complex + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +end #domain diff --git a/src/mainboard/biostar/am1ml/devicetree.cb b/src/mainboard/biostar/am1ml/devicetree.cb index 9b31bc6..7966c2e 100644 --- a/src/mainboard/biostar/am1ml/devicetree.cb +++ b/src/mainboard/biostar/am1ml/devicetree.cb @@ -13,103 +13,101 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1002 0x439d inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +device domain 0 on + subsystemid 0x1002 0x439d inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end - device pci 2.1 on end - device pci 2.2 on end - device pci 2.3 on end - device pci 2.4 on end - device pci 2.5 on end - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end + device pci 2.1 on end + device pci 2.2 on end + device pci 2.3 on end + device pci 2.4 on end + device pci 2.5 on end + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # there is no legacy ide + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # there is no legacy ide - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8728f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - io 0x62 = 0 - drq 0x74 = 4 - irq 0x70 = 5 - end - device pnp 2e.4 on # Env Controller - io 0x60 = 0xa00 - io 0x62 = 0xa20 - irq 0x70 = 0 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO - io 0x60 = 0xa40 - io 0x62 = 0xa40 - io 0x64 = 0 - irq 0x70 = 0 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8728f - end #device pci 14.3 # LPC - device pci 14.7 off end # SD - end #chip southbridge/amd/hudson + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + io 0x62 = 0 + drq 0x74 = 4 + irq 0x70 = 5 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0xa00 + io 0x62 = 0xa20 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0xa40 + io 0x62 = 0xa40 + io 0x64 = 0 + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.7 off end # SD + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2} }, - }" + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2} }, + }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family16kb/root_complex + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +end #domain diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index 3e02a19..e46b014 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -1,122 +1,120 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end end - device domain 0 on - subsystemid 0x161f 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 +end +device domain 0 on + subsystemid 0x161f 0x3050 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # northbridge + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on # Legacy pci main 0x0205 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 71 on end #0 pca9554 0 - device i2c 71 on end #0 pca9554 1 - device i2c 71 on end #0 pca9554 2 - device i2c 71 on end #0 pca9554 3 - device i2c 71 on end #0 pca9554 4 - device i2c 71 on end #0 pca9554 5 - device i2c 71 on #0 pca9554 6 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on # Legacy pci main 0x0205 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 71 on end #0 pca9554 0 + device i2c 71 on end #0 pca9554 1 + device i2c 71 on end #0 pca9554 2 + device i2c 71 on end #0 pca9554 3 + device i2c 71 on end #0 pca9554 4 + device i2c 71 on end #0 pca9554 5 + device i2c 71 on #0 pca9554 6 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end end - device i2c 71 on #1 pca9554 7 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end end - end - - end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + end + device i2c 71 on #1 pca9554 7 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end end end end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 4.0 on end # it is in bcm5785_0 bus + end - end # device pci 18.0 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end + end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 4.0 on end # it is in bcm5785_0 bus + end + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end - end #domain -end +end #domain diff --git a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb index 33b8505..6a16296 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb +++ b/src/mainboard/gigabyte/ga_2761gxdk/devicetree.cb @@ -1,92 +1,89 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1039 0x1234 inherit - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/sis/sis966 - device pci 0.0 on end # Northbridge - device pci 1.0 on # AGP bridge - device pci 0.0 on end - end - device pci 2.0 on # LPC - chip superio/ite/it8716f - device pnp 2e.0 off # Floppy (N/A) - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 (N/A) - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel port (N/A) - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 off # PS/2 keyboard (N/A) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 off # Mouse (N/A) - irq 0x70 = 12 - end - device pnp 2e.8 off # MIDI (N/A) - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME (N/A) - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR (N/A) +device cpu_cluster 0 on + chip cpu/amd/socket_AM2 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1039 0x1234 inherit + chip northbridge/amd/amdk8 #mc0 + device pci 18.0 on + # devices on link 0, link 0 == LDT 0 + chip southbridge/sis/sis966 + device pci 0.0 on end # Northbridge + device pci 1.0 on # AGP bridge + device pci 0.0 on end + end + device pci 2.0 on # LPC + chip superio/ite/it8716f + device pnp 2e.0 off # Floppy (N/A) + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 (N/A) + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel port (N/A) + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 off # PS/2 keyboard (N/A) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end + device pnp 2e.6 off # Mouse (N/A) + irq 0x70 = 12 + end + device pnp 2e.8 off # MIDI (N/A) + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # GAME (N/A) + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR (N/A) end - - device pci 2.5 off end # IDE (SiS5513) - device pci 2.6 off end # Modem (SiS7013) - device pci 2.7 off end # Audio (SiS7012) - device pci 3.0 on end # USB (SiS7001,USB1.1) - device pci 3.1 on end # USB (SiS7001,USB1.1) - device pci 3.3 on end # USB (SiS7002,USB2.0) - device pci 4.0 on end # NIC (SiS191) - device pci 5.0 on end # SATA (SiS1183,Native Mode) - device pci 6.0 on end # PCI-e x1 - device pci 7.0 on end # PCI-e x1 - device pci a.0 off end - device pci b.0 off end - device pci c.0 off end - device pci d.0 off end - device pci e.0 off end - device pci f.0 off end # HD Audio (SiS7502) - - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - end # PCI domain + device pci 2.5 off end # IDE (SiS5513) + device pci 2.6 off end # Modem (SiS7013) + device pci 2.7 off end # Audio (SiS7012) + device pci 3.0 on end # USB (SiS7001,USB1.1) + device pci 3.1 on end # USB (SiS7001,USB1.1) + device pci 3.3 on end # USB (SiS7002,USB2.0) + device pci 4.0 on end # NIC (SiS191) + device pci 5.0 on end # SATA (SiS1183,Native Mode) + device pci 6.0 on end # PCI-e x1 + device pci 7.0 on end # PCI-e x1 + device pci a.0 off end + device pci b.0 off end + device pci c.0 off end + device pci d.0 off end + device pci e.0 off end + device pci f.0 off end # HD Audio (SiS7502) + + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end # device pci 18.0 + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # mc0 -end #root_complex +end # PCI domain diff --git a/src/mainboard/gigabyte/m57sli/devicetree.cb b/src/mainboard/gigabyte/m57sli/devicetree.cb index efbf76e..1398f18 100644 --- a/src/mainboard/gigabyte/m57sli/devicetree.cb +++ b/src/mainboard/gigabyte/m57sli/devicetree.cb @@ -1,8 +1,7 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_AM2 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_AM2 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end end device domain 0 on # PCI domain subsystemid 0x1022 0x2b80 inherit @@ -142,13 +141,12 @@ device domain 0 on # PCI domain # 1: SMBus under 2e.8, 2: SM0 3: SM1 register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" - end end - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/gigabyte/ma785gm/devicetree.cb b/src/mainboard/gigabyte/ma785gm/devicetree.cb index c7d9932..44c863c 100644 --- a/src/mainboard/gigabyte/ma785gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gm/devicetree.cb @@ -1,115 +1,112 @@ # sample config for gigabyte/ma785gm -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9601 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 off end # - device pci a.0 on end # PCIE P2P bridge 0x9609 - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9601 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 off end # + device pci a.0 on end # PCIE P2P bridge 0x9609 + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8718f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain - #for node 32 to node 63 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end +end #domain diff --git a/src/mainboard/gigabyte/ma785gmt/devicetree.cb b/src/mainboard/gigabyte/ma785gmt/devicetree.cb index bd98313..d4241b3 100644 --- a/src/mainboard/gigabyte/ma785gmt/devicetree.cb +++ b/src/mainboard/gigabyte/ma785gmt/devicetree.cb @@ -1,115 +1,112 @@ # sample config for gigabyte/ma785gmt -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM3 #L1 and DDR3 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM3 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "2" +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "2" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8718f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end - end #domain - #for node 32 to node 63 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end +end #domain diff --git a/src/mainboard/gigabyte/ma78gm/devicetree.cb b/src/mainboard/gigabyte/ma78gm/devicetree.cb index 8d81fbe..251c5f9 100644 --- a/src/mainboard/gigabyte/ma78gm/devicetree.cb +++ b/src/mainboard/gigabyte/ma78gm/devicetree.cb @@ -1,115 +1,112 @@ # sample config for gigabyte/ma78gm -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM2r2 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "1" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8718f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/ite/it8718f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end +end #domain diff --git a/src/mainboard/gizmosphere/gizmo/devicetree.cb b/src/mainboard/gizmosphere/gizmo/devicetree.cb index 3a1b5d0..7a8b65b 100644 --- a/src/mainboard/gizmosphere/gizmo/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo/devicetree.cb @@ -13,54 +13,52 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed - device pci 14.5 off end # USB 2 - device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector - device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector - device pci 16.0 off end # OHCI USB3 - device pci 16.2 off end # EHCI USB3 - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.4 on end # PCIB 0x4384, NOTE: this device must always be enabled or removed + device pci 14.5 off end # USB 2 + device pci 15.0 on end # PCIe PortA # PCIe x1 to high speed edge connector + device pci 15.1 on end # PCIe PortB # PCIe x1 to high speed edge connector + device pci 16.0 off end # OHCI USB3 + device pci 16.2 off end # EHCI USB3 + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/gizmosphere/gizmo2/devicetree.cb b/src/mainboard/gizmosphere/gizmo2/devicetree.cb index 625e033..3a876d2 100644 --- a/src/mainboard/gizmosphere/gizmo2/devicetree.cb +++ b/src/mainboard/gizmosphere/gizmo2/devicetree.cb @@ -12,49 +12,47 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # PCIe GFX Bridge - device pci 2.2 on end # PCIe GPP mini PCIe - device pci 2.3 on end # PCIe LAN - device pci 2.4 on end # PCIe x2 to high speed edge connector - device pci 2.5 on end # PCIe x2 to high speed edge connector - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9835 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # PCIe GFX Bridge + device pci 2.2 on end # PCIe GPP mini PCIe + device pci 2.3 on end # PCIe LAN + device pci 2.4 on end # PCIe x2 to high speed edge connector + device pci 2.5 on end # PCIe x2 to high speed edge connector + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on end # LPC 0x439d - device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on end # LPC 0x439d + device pci 14.7 on end # SD + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family16kb/root_complex + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +end #domain diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index 5ff52aa..4e65138 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -13,79 +13,77 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family16kb/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family16kb - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 off end # unused - device pci 2.2 on end # GPP0: NIC - device pci 2.3 on end # GPP1: NIC - device pci 2.4 off end # GPP2: unused - device pci 2.5 off end # GPP3: unused - end #chip northbridge/amd/agesa/family16kb + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 off end # unused + device pci 2.2 on end # GPP0: NIC + device pci 2.3 on end # GPP1: NIC + device pci 2.4 off end # GPP2: unused + device pci 2.5 off end # GPP3: unused + end #chip northbridge/amd/agesa/family16kb - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + device pnp 4e.0 off end # FDC + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d - device pnp 4e.0 off end # FDC - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.8 off end # GPIO/WDT - device pnp 4e.f off end # GPIO - device pnp 4e.10 off end # COM3 used by port 80 - device pnp 4e.11 on # COM4 - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 4e.14 off end # PORT80 - register "irq_trigger_type" = "0" # 0 edge, 1 level - end # nct5104d - end #LPC - device pci 14.7 off end # SD - device pci 16.0 on end # USB - device pci 16.2 on end # USB - end #chip southbridge/amd/hudson + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.8 off end # GPIO/WDT + device pnp 4e.f off end # GPIO + device pnp 4e.10 off end # COM3 used by port 80 + device pnp 4e.11 on # COM4 + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 4e.14 off end # PORT80 + register "irq_trigger_type" = "0" # 0 edge, 1 level + end # nct5104d + end #LPC + device pci 14.7 off end # SD + device pci 16.0 on end # USB + device pci 16.2 on end # USB + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses - }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family16kb/root_complex + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex +end #domain diff --git a/src/mainboard/hp/dl145_g1/devicetree.cb b/src/mainboard/hp/dl145_g1/devicetree.cb index 2d4adee..b361343 100644 --- a/src/mainboard/hp/dl145_g1/devicetree.cb +++ b/src/mainboard/hp/dl145_g1/devicetree.cb @@ -1,141 +1,139 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x7460 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end # link 0 - device pci 18.0 on end # link 1 - device pci 18.0 on # link 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on # PCIX Bridge A - # PCI-X expansion slot cards auto-detected here - end - device pci 0.1 on end # IOAPIC A - device pci 1.0 on # PCIX Bridge B - # On-board BCM5704 dual port ethernet chip auto-detected here - # Optional SCSI board also (?) +end +device domain 0 on + subsystemid 0x1022 0x7460 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on end # link 0 + device pci 18.0 on end # link 1 + device pci 18.0 on # link 2 + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on # PCIX Bridge A + # PCI-X expansion slot cards auto-detected here + end + device pci 0.1 on end # IOAPIC A + device pci 1.0 on # PCIX Bridge B + # On-board BCM5704 dual port ethernet chip auto-detected here + # Optional SCSI board also (?) + end + device pci 1.1 on end # IOAPIC B + device pci 2.0 off end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent of the next one + # PCI bridge + device pci 0.0 on + device pci 0.0 on end # OHCI-based USB controller 0 + device pci 0.1 on end # OCHI-based USB controller 1 + device pci 0.2 on end # EHCI-based USB2 controller + device pci 1.0 off end # LAN Ethernet controller + #device pci 4.0 on end # VGA PCI-card (auto detected) + end + device pci 1.0 on # LPC Bridge + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + #io 0x60 = 0x3f0 + #irq 0x70 = 6 + #drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + #io 0x60 = 0x378 + #irq 0x70 = 7 + #drq 0x74 = 1 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + #io 0x60 = 0x2f8 + #irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # CIR + end + device pnp 2e.7 off # GAM_MIDI_GPIO1 + #io 0x60 = 0x201 + #io 0x62 = 0x330 + #irq 0x70 = 9 + end + device pnp 2e.8 on # GPIO2 (watchdog timer) + end + device pnp 2e.9 on # GPIO3 + end + device pnp 2e.a on # ACPI + end + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end end - device pci 1.1 on end # IOAPIC B - device pci 2.0 off end end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent of the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end # OHCI-based USB controller 0 - device pci 0.1 on end # OCHI-based USB controller 1 - device pci 0.2 on end # EHCI-based USB2 controller - device pci 1.0 off end # LAN Ethernet controller - #device pci 4.0 on end # VGA PCI-card (auto detected) + device pci 1.1 on end # EIDE controller + device pci 1.2 on + chip drivers/generic/generic + device i2c 8 on end # Some HW-monitor/sensor? end - device pci 1.0 on # LPC Bridge - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - #io 0x60 = 0x3f0 - #irq 0x70 = 6 - #drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - #io 0x60 = 0x378 - #irq 0x70 = 7 - #drq 0x74 = 1 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - #io 0x60 = 0x2f8 - #irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR + end + device pci 1.2 on + chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms. + device i2c 18 on #0 pca9516 (?) + # Some dimms also listen to address 30-33 + # It's some kind of write-protect function + # The 50-53 addresses are the interesting ones. + chip drivers/generic/generic #dimm H0-0 + device i2c 50 on end end - device pnp 2e.7 off # GAM_MIDI_GPIO1 - #io 0x60 = 0x201 - #io 0x62 = 0x330 - #irq 0x70 = 9 + chip drivers/generic/generic #dimm H0-1 + device i2c 51 on end end - device pnp 2e.8 on # GPIO2 (watchdog timer) + chip drivers/generic/generic #dimm H0-2 + device i2c 52 on end end - device pnp 2e.9 on # GPIO3 + chip drivers/generic/generic #dimm H0-3 + device i2c 53 on end end - device pnp 2e.a on # ACPI + end + device i2c 18 on #1 pca9516 (?) + chip drivers/generic/generic #dimm H1-0 + device i2c 50 on end end - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 + chip drivers/generic/generic #dimm H1-1 + device i2c 51 on end end - end - end - device pci 1.1 on end # EIDE controller - device pci 1.2 on - chip drivers/generic/generic - device i2c 8 on end # Some HW-monitor/sensor? - end - end - device pci 1.2 on - chip drivers/i2c/i2cmux # Multplexed DIMM spd eeproms. - device i2c 18 on #0 pca9516 (?) - # Some dimms also listen to address 30-33 - # It's some kind of write-protect function - # The 50-53 addresses are the interesting ones. - chip drivers/generic/generic #dimm H0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm H0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm H0-2 - device i2c 52 on end - end - chip drivers/generic/generic #dimm H0-3 - device i2c 53 on end - end + chip drivers/generic/generic #dimm H1-2 + device i2c 52 on end end - device i2c 18 on #1 pca9516 (?) - chip drivers/generic/generic #dimm H1-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm H1-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm H1-2 - device i2c 52 on end - end - chip drivers/generic/generic #dimm H1-3 - device i2c 53 on end - end + chip drivers/generic/generic #dimm H1-3 + device i2c 53 on end end end end - device pci 1.2 on - chip drivers/generic/generic - device i2c 69 on end # Texas Instruments cdc960 clock synthesizer - end - end # SMBus 2.0 controller - device pci 1.3 on # System management registers (ACPI) - end # System management - #device pci 1.4 off end - device pci 1.5 off end # AC97 Audio - device pci 1.6 off end # AC97 Modem - register "ide0_enable" = "1" - register "ide1_enable" = "1" end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end + device pci 1.2 on + chip drivers/generic/generic + device i2c 69 on end # Texas Instruments cdc960 clock synthesizer + end + end # SMBus 2.0 controller + device pci 1.3 on # System management registers (ACPI) + end # System management + #device pci 1.4 off end + device pci 1.5 off end # AC97 Audio + device pci 1.6 off end # AC97 Modem + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/hp/dl145_g3/devicetree.cb b/src/mainboard/hp/dl145_g3/devicetree.cb index b7f450e..2e1d066 100644 --- a/src/mainboard/hp/dl145_g3/devicetree.cb +++ b/src/mainboard/hp/dl145_g3/devicetree.cb @@ -1,85 +1,82 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_F + device lapic 0 on end end - device domain 0 on - chip northbridge/amd/amdk8 # northbridge - device pci 18.0 on # devices on link 0 - chip southbridge/broadcom/bcm21000 # HT2100 - device pci 0.0 on - end # bridge to slot PCI-E 4x ?? - device pci 1.0 on - end - device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? - end - device pci 4.0 on - end # unused - device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC - end +end +device domain 0 on + chip northbridge/amd/amdk8 # northbridge + device pci 18.0 on # devices on link 0 + chip southbridge/broadcom/bcm21000 # HT2100 + device pci 0.0 on + end # bridge to slot PCI-E 4x ?? + device pci 1.0 on end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.3 off # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA + device pci 2.0 on + end # unused + device pci 3.0 on # bridge to slot PCI-E 16x ?? + end + device pci 4.0 on + end # unused + device pci 5.0 on + device pci 4.0 on end # BCM5715 NIC + device pci 4.1 on end # BCM5715 NIC end end - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # amdk8 - - end #domain -end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PCI/PCI-X bridge 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on end # Legacy pci main 0x0205 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.3 off # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.4 off end # SWC + device pnp 4e.5 off end # Mouse + device pnp 4e.6 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.f off end # XBUS + device pnp 4e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end # end superio + end # end pci 1.2 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # VGA + end + end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # amdk8 +end #domain diff --git a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb index e321393..1a74c33 100644 --- a/src/mainboard/hp/dl165_g6_fam10/devicetree.cb +++ b/src/mainboard/hp/dl165_g6_fam10/devicetree.cb @@ -1,88 +1,85 @@ -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F_1207 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_F_1207 + device lapic 0 on end end - device domain 0 on - chip northbridge/amd/amdfam10 # northbridge - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # devices on link 2 - chip southbridge/broadcom/bcm21000 # HT2100 - device pci 0.0 on - end # bridge to slot PCI-E 4x ?? - device pci 1.0 on - end - device pci 2.0 on - end # unused - device pci 3.0 on # bridge to slot PCI-E 16x ?? - end - device pci 4.0 on - end # unused - device pci 5.0 on - device pci 4.0 on end # BCM5715 NIC - device pci 4.1 on end # BCM5715 NIC - end +end +device domain 0 on + chip northbridge/amd/amdfam10 # northbridge + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # devices on link 2 + chip southbridge/broadcom/bcm21000 # HT2100 + device pci 0.0 on + end # bridge to slot PCI-E 4x ?? + device pci 1.0 on end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PCI/PCI-X bridge 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on end # Legacy pci main 0x0205 - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 4e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.3 off # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.4 off end # SWC - device pnp 4e.5 off end # Mouse - device pnp 4e.6 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 4e.7 off end # GPIO - device pnp 4e.f off end # XBUS - device pnp 4e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end - end # end superio - end # end pci 1.2 - device pci 1.3 off end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # VGA + device pci 2.0 on + end # unused + device pci 3.0 on # bridge to slot PCI-E 16x ?? + end + device pci 4.0 on + end # unused + device pci 5.0 on + device pci 4.0 on end # BCM5715 NIC + device pci 4.1 on end # BCM5715 NIC end end - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # amdfam10 - - end #domain -end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PCI/PCI-X bridge 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on end # Legacy pci main 0x0205 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.3 off # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.4 off end # SWC + device pnp 4e.5 off end # Mouse + device pnp 4e.6 off # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 4e.7 off end # GPIO + device pnp 4e.f off end # XBUS + device pnp 4e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end # end superio + end # end pci 1.2 + device pci 1.3 off end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # VGA + end + end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end # amdfam10 +end #domain diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb index a27b551..fc93a48 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb +++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb @@ -12,74 +12,71 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15tn/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15tn - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15tn + device lapic 10 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 8.0 off end # NB/SB Link P2P bridge - end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + chip northbridge/amd/agesa/family15tn # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 8.0 off end # NB/SB Link P2P bridge + end #chip northbridge/amd/agesa/family15tn # PCI side of HT root complex - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address end - device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. - device pci 14.5 on end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 on end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/hudson + end + device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO. + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 on end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15tn/root_complex + end #chip northbridge/amd/agesa/family15tn # CPU side of HT root complex +end #domain diff --git a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb index 1dffb4b..71d2d17 100644 --- a/src/mainboard/iei/kino-780am2-fam10/devicetree.cb +++ b/src/mainboard/iei/kino-780am2-fam10/devicetree.cb @@ -1,70 +1,68 @@ # Config for iei/kino-780am2-fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM2r2 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 on end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 on end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "1" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71859 + device pnp 2e.3 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71859 - device pnp 2e.3 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - end #SIO - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end #domain -end #root_complex + end #SIO + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end +end #domain diff --git a/src/mainboard/iwill/dk8_htx/devicetree.cb b/src/mainboard/iwill/dk8_htx/devicetree.cb index c49c97a..c077a17 100644 --- a/src/mainboard/iwill/dk8_htx/devicetree.cb +++ b/src/mainboard/iwill/dk8_htx/devicetree.cb @@ -1,117 +1,115 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # northbridge - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory +device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # northbridge + chip southbridge/amd/amd8131 + # the on/off keyword is mandatory + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on end + device pci 1.1 on end + end + chip southbridge/amd/amd8111 + # this "device pci 0.0" is the parent the next one + # PCI bridge + device pci 0.0 on device pci 0.0 on end device pci 0.1 on end - device pci 1.0 on end - device pci 1.1 on end + device pci 0.2 off end + device pci 1.0 off end end - chip southbridge/amd/amd8111 - # this "device pci 0.0" is the parent the next one - # PCI bridge - device pci 0.0 on - device pci 0.0 on end - device pci 0.1 on end - device pci 0.2 off end - device pci 1.0 off end - end - device pci 1.0 on - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 on # GPIO2 - io 0x07 = 0x08ff - io 0x30 = 0x01ff - io 0x2b = 0xd0ff - io 0xf0 = 0xef16 - end - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end + device pci 1.0 on + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on end - device pci 1.2 on end - device pci 1.3 on - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end + device pnp 2e.6 off # CIR + io 0x60 = 0x100 end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end + device pnp 2e.7 off # GAME_MIDI_GIPO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end + device pnp 2e.8 on # GPIO2 + io 0x07 = 0x08ff + io 0x30 = 0x01ff + io 0x2b = 0xd0ff + io 0xf0 = 0xef16 end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 end - end # acpi - device pci 1.5 off end - device pci 1.6 off end - register "ide0_enable" = "1" - register "ide1_enable" = "1" + end end - end # device pci 18.0 + device pci 1.1 on end + device pci 1.2 on end + device pci 1.3 on + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic #dimm 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 57 on end + end + end # acpi + device pci 1.5 off end + device pci 1.6 off end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end - end #domain -end +end #domain diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb index 0db35ce..4e44e9d 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb +++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb @@ -13,135 +13,133 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] -# device pci 1.1 on end # Internal Audio P2P bridge 0x1314 - device pci 4.0 on end # PCIE P2P bridge PCIe slot - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] +# device pci 1.1 on end # Internal Audio P2P bridge 0x1314 + device pci 4.0 on end # PCIE P2P bridge PCIe slot + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 on end # GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71869ad - register "multi_function_register_1" = "0x01" - register "multi_function_register_2" = "0x6f" - register "multi_function_register_3" = "0x24" - register "multi_function_register_4" = "0x00" - register "multi_function_register_5" = "0x60" + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71869ad + register "multi_function_register_1" = "0x01" + register "multi_function_register_2" = "0x6f" + register "multi_function_register_3" = "0x24" + register "multi_function_register_4" = "0x00" + register "multi_function_register_5" = "0x60" # HWM configuration registers - register "hwm_smbus_address" = "0x98" - register "hwm_smbus_control_reg" = "0x02" - register "hwm_fan_type_sel_reg" = "0x00" - register "hwm_fan1_temp_adj_rate_reg" = "0x33" - register "hwm_fan_mode_sel_reg" = "0x07" - register "hwm_fan1_idx_rpm_mode" = "0x0e" - register "hwm_fan1_seg1_speed_count" = "0xff" - register "hwm_fan1_seg2_speed_count" = "0x0e" - register "hwm_fan1_seg3_speed_count" = "0x07" - register "hwm_fan1_temp_map_sel" = "0x8c" + register "hwm_smbus_address" = "0x98" + register "hwm_smbus_control_reg" = "0x02" + register "hwm_fan_type_sel_reg" = "0x00" + register "hwm_fan1_temp_adj_rate_reg" = "0x33" + register "hwm_fan_mode_sel_reg" = "0x07" + register "hwm_fan1_idx_rpm_mode" = "0x0e" + register "hwm_fan1_seg1_speed_count" = "0xff" + register "hwm_fan1_seg2_speed_count" = "0x0e" + register "hwm_fan1_seg3_speed_count" = "0x07" + register "hwm_fan1_temp_map_sel" = "0x8c" # # XXX: 4e is the default index port and .xy is the # LDN indexing the pnp_info array found in the superio.c # NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124, # see page 18 from Fintek F71869 V1.1 datasheet. - device pnp 2e.00 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.01 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end + device pnp 2e.00 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.01 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end # COM2 not physically wired on board. - device pnp 2e.02 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.03 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.04 on # Hardware Monitor - io 0x60 = 0x225 # Fintek datasheet says 0x295. - irq 0x70 = 0 - end - device pnp 2e.05 on # KBC - io 0x60 = 0x060 - irq 0x70 = 1 # Keyboard IRQ - irq 0x72 = 12 # Mouse IRQ - end - device pnp 2e.06 off end # GPIO - device pnp 2e.07 on end # WDT - device pnp 2e.08 off end # CIR - device pnp 2e.0a on end # PME - end # f71869ad - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 on end # OHCI FS/LS USB (0x4399) - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) - device pci 15.1 on end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 (0x4397) - device pci 16.2 on end # EHCI USB 10-13 (0x4396) - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes. - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + device pnp 2e.02 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.03 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.04 on # Hardware Monitor + io 0x60 = 0x225 # Fintek datasheet says 0x295. + irq 0x70 = 0 + end + device pnp 2e.05 on # KBC + io 0x60 = 0x060 + irq 0x70 = 1 # Keyboard IRQ + irq 0x72 = 12 # Mouse IRQ + end + device pnp 2e.06 off end # GPIO + device pnp 2e.07 on end # WDT + device pnp 2e.08 off end # CIR + device pnp 2e.0a on end # PME + end # f71869ad + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 on end # OHCI FS/LS USB (0x4399) + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA (0x43a0) GbE MAC: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 (10ec:8168) + device pci 15.1 on end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 (0x4397) + device pci 16.2 on end # EHCI USB 10-13 (0x4396) + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - PortA-D on 15.0-3 are each x1 lanes. + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end # # TODO: Verify the proper SocketId/MemChannelId/DimmId addresses of the SPD # with i2cdump tool. # Notes: 0xa0=0x50*2, 0xa2=0x51*2.. 0x50-0x54 are usually RAM modules on the SMBus. # - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/jetway/pa78vm5/devicetree.cb b/src/mainboard/jetway/pa78vm5/devicetree.cb index 783e4ae..3cb44d8 100644 --- a/src/mainboard/jetway/pa78vm5/devicetree.cb +++ b/src/mainboard/jetway/pa78vm5/devicetree.cb @@ -1,110 +1,106 @@ # sample config for jetway/PA78VM5 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_AM2r2 #L1 and DDR2 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3060 inherit - chip northbridge/amd/amdfam10 - device pci 18.0 on # northbridge - chip southbridge/amd/rs780 - device pci 0.0 on end # HT 0x9600 - device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 on end # PCIE P2P bridge 0x960b - device pci 4.0 on end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 off end # PCIE P2P bridge 0x9606 - device pci 7.0 off end # PCIE P2P bridge 0x9607 - device pci 8.0 off end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - register "gppsb_configuration" = "1" # Configuration B - register "gpp_configuration" = "3" # Configuration D default - register "port_enable" = "0x6fc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "1" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" - end - chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end +end +device domain 0 on + subsystemid 0x1022 0x3060 inherit + chip northbridge/amd/amdfam10 + device pci 18.0 on # northbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "1" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/fintek/f71863fg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/fintek/f71863fg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8718f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end -# device pci 00.5 on end - end - end #domain - #for node 32 to node 63 + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8718f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 -end + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end +# device pci 00.5 on end + end +end #domain diff --git a/src/mainboard/kontron/kt690/devicetree.cb b/src/mainboard/kontron/kt690/devicetree.cb index 3ab3337..bb32e11 100644 --- a/src/mainboard/kontron/kt690/devicetree.cb +++ b/src/mainboard/kontron/kt690/devicetree.cb @@ -8,118 +8,116 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_S1G1 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1488 0x6900 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" +end +device domain 0 on + subsystemid 0x1488 0x6900 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end # Internal Graphics 0x791F end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - #device pnp 2e.6 off # SPI - #end - device pnp 2e.307 off # GPIO 1 - end - device pnp 2e.8 on # WDTO#, PLED - end - device pnp 2e.009 off # GPIO2 - end - device pnp 2e.109 off # GPIO3 - end - device pnp 2e.209 off # GPIO4 - end - device pnp 2e.309 off # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b on # HWM - io 0x60 = 0xa10 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w83627dhg - #chip superio/smsc/fdc37n972 - # seems this chip is not used? + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + #device pnp 2e.6 off # SPI #end - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0888" - end #southbridge/amd/sb600 - end # device pci 18.0 + device pnp 2e.307 off # GPIO 1 + end + device pnp 2e.8 on # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0xa10 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w83627dhg + #chip superio/smsc/fdc37n972 + # seems this chip is not used? + #end + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "hda_viddid" = "0x10ec0888" + end #southbridge/amd/sb600 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index 1a9da04..516bcd9 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -12,78 +12,75 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15rl/root_complex - - device cpu_cluster 0 on - chip cpu/amd/agesa/family15rl - device lapic 10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15rl + device lapic 10 on end end +end - device domain 0 on - subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/agesa/family15rl # CPU side of HT root complex +device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/agesa/family15rl # CPU side of HT root complex - chip northbridge/amd/agesa/family15rl # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU - device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX - device pci 1.1 on end # Internal Multimedia - device pci 2.0 off end - device pci 3.0 off end - device pci 4.0 on end # PCIE MINI0 - device pci 5.0 on end # PCIE MINI1 - device pci 6.0 off end # - device pci 7.0 off end # - device pci 8.0 off end # NB/SB Link P2P bridge ? - device pci 9.0 off end # - end #chip northbridge/amd/agesa/family15rl # PCI side of HT root complex + chip northbridge/amd/agesa/family15rl # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 off end + device pci 3.0 off end + device pci 4.0 on end # PCIE MINI0 + device pci 5.0 on end # PCIE MINI1 + device pci 6.0 off end # + device pci 7.0 off end # + device pci 8.0 off end # NB/SB Link P2P bridge ? + device pci 9.0 off end # + end #chip northbridge/amd/agesa/family15rl # PCI side of HT root complex - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 off end # FCH USB XHCI Controller HC0 (N.B. breaks EHCI debug!!!) - device pci 11.0 on end # FCH SATA Controller [AHCI mode] - device pci 12.0 on end # FCH USB OHCI Controller - device pci 12.2 on end # FCH USB EHCI Controller - device pci 13.0 on end # FCH USB OHCI Controller - device pci 13.2 on end # FCH USB EHCI Controller - device pci 14.0 on # SMBUS - chip drivers/generic/generic #dimm 0 - device i2c 50 on end # 7-bit SPD address - end - chip drivers/generic/generic #dimm 1 - device i2c 51 on end # 7-bit SPD address - end - end # SM - device pci 14.2 on end # FCH Azalia Controller - device pci 14.3 on # FCH LPC Bridge [1022:780e] - chip ec/compal/ene932 - # 60/64 KBC - device pnp ff.1 on end # dummy address - end + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 off end # FCH USB XHCI Controller HC0 (N.B. breaks EHCI debug!!!) + device pci 11.0 on end # FCH SATA Controller [AHCI mode] + device pci 12.0 on end # FCH USB OHCI Controller + device pci 12.2 on end # FCH USB EHCI Controller + device pci 13.0 on end # FCH USB OHCI Controller + device pci 13.2 on end # FCH USB EHCI Controller + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.2 on end # FCH Azalia Controller + device pci 14.3 on # FCH LPC Bridge [1022:780e] + chip ec/compal/ene932 + # 60/64 KBC + device pnp ff.1 on end # dummy address end - device pci 14.4 on end # FCH PCI Bridge [1022:780f] - device pci 14.5 off end # USB 2 - device pci 14.6 off end # Gec - device pci 14.7 off end # SD - device pci 15.0 off end # PCIe 0 - device pci 15.1 off end # PCIe 1 - device pci 15.2 off end # PCIe 2 - device pci 15.3 off end # PCIe 3 - end #chip southbridge/amd/hudson + end + device pci 14.4 on end # FCH PCI Bridge [1022:780f] + device pci 14.5 off end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 off end # PCIe 0 + device pci 15.1 off end # PCIe 1 + device pci 15.2 off end # PCIe 2 + device pci 15.3 off end # PCIe 3 + end #chip southbridge/amd/hudson - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0x00}, {0xA2, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family15rl # CPU side of HT root complex - end #domain -end #chip northbridge/amd/agesa/family15rl/root_complex + end #chip northbridge/amd/agesa/family15rl # CPU side of HT root complex +end #domain diff --git a/src/mainboard/lippert/frontrunner-af/devicetree.cb b/src/mainboard/lippert/frontrunner-af/devicetree.cb index 61a7035..a2de511 100644 --- a/src/mainboard/lippert/frontrunner-af/devicetree.cb +++ b/src/mainboard/lippert/frontrunner-af/devicetree.cb @@ -12,95 +12,93 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC - device pci 5.0 off end # PCIE P2P bridge - device pci 6.0 off end # PCIE P2P bridge - device pci 7.0 off end # PCIE P2P bridge - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC + device pci 5.0 off end # PCIE P2P bridge + device pci 6.0 off end # PCIE P2P bridge + device pci 7.0 off end # PCIE P2P bridge + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/smsc/smscsuperio - device pnp 4e.0 off end # Floppy - device pnp 4e.3 off end # Parallel Port - device pnp 4e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 4e.A on # Runtime Regs - io 0x60 = 0x0E00 - drq 0xF0 = 0x0B # no 32kHz - end - end # smscsuperio - end #LPC - device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 off end # PCIe PortA - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/smsc/smscsuperio + device pnp 4e.0 off end # Floppy + device pnp 4e.3 off end # Parallel Port + device pnp 4e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.7 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.A on # Runtime Regs + io 0x60 = 0x0E00 + drq 0xF0 = 0x0B # no 32kHz + end + end # smscsuperio + end #LPC + device pci 14.4 on end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 off end # PCIe PortA + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 # end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/lippert/toucan-af/devicetree.cb b/src/mainboard/lippert/toucan-af/devicetree.cb index 2f742ff..247a7bc 100644 --- a/src/mainboard/lippert/toucan-af/devicetree.cb +++ b/src/mainboard/lippert/toucan-af/devicetree.cb @@ -12,101 +12,99 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] - #device pci 1.1 on end # Internal HDMI Audio - device pci 4.0 on end # PCIE P2P bridge - device pci 5.0 on end # PCIE P2P bridge - device pci 6.0 on end # PCIE P2P bridge - device pci 7.0 on end # PCIE P2P bridge on-board NIC - device pci 8.0 off end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x980[2456] + #device pci 1.1 on end # Internal HDMI Audio + device pci 4.0 on end # PCIE P2P bridge + device pci 5.0 on end # PCIE P2P bridge + device pci 6.0 on end # PCIE P2P bridge + device pci 7.0 on end # PCIE P2P bridge on-board NIC + device pci 8.0 off end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 off end - end - end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627dhg - device pnp 4e.0 off end # Floppy - device pnp 4e.1 off end # Parallel Port - device pnp 4e.2 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # Keyboard, Mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - #device pnp 4e.6 off end # SPI - device pnp 4e.307 off end # GPIO6 - device pnp 4e.8 off end # WDTO, PLED - device pnp 4e.009 off end # GPIO2 - device pnp 4e.109 off end # GPIO3 - device pnp 4e.209 off end # GPIO4 - device pnp 4e.309 off end # GPIO5 - device pnp 4e.A off end # ACPI - device pnp 4e.B off end # HW Monitor - end # w83627dhg - end #LPC - device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} - device pci 14.5 off end # OHCI FS/LS USB - device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA - device pci 15.1 on end # PCIe PortB - device pci 15.2 on end # PCIe PortC - device pci 15.3 on end # PCIe PortD - device pci 16.0 off end # OHCI USB 10-13 - device pci 16.2 off end # EHCI USB 10-13 - register "gpp_configuration" = "4" #1:1:1:1 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 off end + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627dhg + device pnp 4e.0 off end # Floppy + device pnp 4e.1 off end # Parallel Port + device pnp 4e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # Keyboard, Mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + #device pnp 4e.6 off end # SPI + device pnp 4e.307 off end # GPIO6 + device pnp 4e.8 off end # WDTO, PLED + device pnp 4e.009 off end # GPIO2 + device pnp 4e.109 off end # GPIO3 + device pnp 4e.209 off end # GPIO4 + device pnp 4e.309 off end # GPIO5 + device pnp 4e.A off end # ACPI + device pnp 4e.B off end # HW Monitor + end # w83627dhg + end #LPC + device pci 14.4 off end # PCIB 0x4384, NOTE: PCI interface pins shared with GPIO {GPIO 35:0} + device pci 14.5 off end # OHCI FS/LS USB + device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA + device pci 15.1 on end # PCIe PortB + device pci 15.2 on end # PCIe PortC + device pci 15.3 on end # PCIe PortD + device pci 16.0 off end # OHCI USB 10-13 + device pci 16.2 off end # EHCI USB 10-13 + register "gpp_configuration" = "4" #1:1:1:1 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end - register "spdAddrLookup" = " - { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses - }" + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb index e3f0c8c..e1c7b0e 100644 --- a/src/mainboard/msi/ms7135/devicetree.cb +++ b/src/mainboard/msi/ms7135/devicetree.cb @@ -1,75 +1,73 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_754 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_754 # CPU socket + device lapic 0 on end # Local APIC of the CPU end +end - device domain 0 on # PCI domain - subsystemid 0x1462 0x7135 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 4e.8 off end # GPIO 2 - device pnp 4e.9 off end # GPIO 3, GPIO 4 - device pnp 4e.a off end # ACPI - device pnp 4e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end +device domain 0 on # PCI domain + subsystemid 0x1462 0x7135 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 4e.8 off end # GPIO 2 + device pnp 4e.9 off end # GPIO 3, GPIO 4 + device pnp 4e.a off end # ACPI + device pnp 4e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on end # SMbus - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 (N/A) - device pci c.0 off end # PCI E 2 (N/A) - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" end + device pci 1.1 on end # SMbus + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 (N/A) + device pci c.0 off end # PCI E 2 (N/A) + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/msi/ms7260/devicetree.cb b/src/mainboard/msi/ms7260/devicetree.cb index 717ad00..b9867df 100644 --- a/src/mainboard/msi/ms7260/devicetree.cb +++ b/src/mainboard/msi/ms7260/devicetree.cb @@ -1,143 +1,141 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_AM2 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_AM2 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1462 0x7260 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 / IrDA - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard IRQ - irq 0x72 = 12 # PS/2 mouse IRQ - end - device pnp 4e.106 off # Serial flash interface (SFI) - # io 0x62 = 0x100 - end - device pnp 4e.007 off # GPIO 1 - end - device pnp 4e.107 off # Game port - # io 0x60 = 0x220 # Datasheet: 0x201 - end - device pnp 4e.207 off # MIDI - # io 0x62 = 0x300 # Datasheet: 0x330 - # irq 0x70 = 9 - end - device pnp 4e.307 off # GPIO 6 - end - device pnp 4e.8 off # WDTO#, PLED - end - device pnp 4e.009 off # GPIO 2 - end - device pnp 4e.109 off # GPIO 3 - end - device pnp 4e.209 off # GPIO 4 - end - device pnp 4e.309 off # GPIO 5 - end - device pnp 4e.a off # ACPI - end - device pnp 4e.b on # Hardware monitor - io 0x60 = 0xa10 - # TODO: IRQ? - end +end +device domain 0 on # PCI domain + subsystemid 0x1462 0x7260 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 4e.3 on # Com2 / IrDA + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 4e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard IRQ + irq 0x72 = 12 # PS/2 mouse IRQ end - end - # TODO: Check if the stuff below is correct / needed. - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device pnp 4e.106 off # Serial flash interface (SFI) + # io 0x62 = 0x100 + end + device pnp 4e.007 off # GPIO 1 + end + device pnp 4e.107 off # Game port + # io 0x60 = 0x220 # Datasheet: 0x201 + end + device pnp 4e.207 off # MIDI + # io 0x62 = 0x300 # Datasheet: 0x330 + # irq 0x70 = 9 + end + device pnp 4e.307 off # GPIO 6 + end + device pnp 4e.8 off # WDTO#, PLED + end + device pnp 4e.009 off # GPIO 2 + end + device pnp 4e.109 off # GPIO 3 end + device pnp 4e.209 off # GPIO 4 + end + device pnp 4e.309 off # GPIO 5 + end + device pnp 4e.a off # ACPI + end + device pnp 4e.b on # Hardware monitor + io 0x60 = 0xa10 + # TODO: IRQ? + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + end + # TODO: Check if the stuff below is correct / needed. + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 off end # SATA 2 (N/A on this board) - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA (HD Audio) - device pci 8.0 on end # NIC - device pci 9.0 off end # NIC (N/A on this board) - device pci a.0 off end # PCI E 5 (N/A on this board?) - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # TODO: Check the two lines below. - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 off end # SATA 2 (N/A on this board) + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA (HD Audio) + device pci 8.0 on end # NIC + device pci 9.0 off end # NIC (N/A on this board) + device pci a.0 off end # PCI E 5 (N/A on this board?) + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # TODO: Check the two lines below. + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/msi/ms9185/devicetree.cb b/src/mainboard/msi/ms9185/devicetree.cb index 3c9168d..453e201 100644 --- a/src/mainboard/msi/ms9185/devicetree.cb +++ b/src/mainboard/msi/ms9185/devicetree.cb @@ -1,85 +1,83 @@ -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_F + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 +end +device domain 0 on + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # northbridge + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - device pci e.1 on end # SATA 0x024a bx_a001 - device pci e.2 on end # SATA 0x024a bx_a001 - device pci e.3 on end # SATA 0x024a bx_a001 - end - device pci 1.0 on # Legacy pci main 0x0205 - end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 - end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + device pci e.1 on end # SATA 0x024a bx_a001 + device pci e.2 on end # SATA 0x024a bx_a001 + device pci e.3 on end # SATA 0x024a bx_a001 + end + device pci 1.0 on # Legacy pci main 0x0205 + end + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 end end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 3.0 on end # it is in bcm5785_0 bus end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # amdk8 - end #domain -end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 3.0 on end # it is in bcm5785_0 bus + end + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end # amdk8 +end #domain diff --git a/src/mainboard/msi/ms9282/devicetree.cb b/src/mainboard/msi/ms9282/devicetree.cb index 747347e..a5a3987 100644 --- a/src/mainboard/msi/ms9282/devicetree.cb +++ b/src/mainboard/msi/ms9282/devicetree.cb @@ -1,182 +1,180 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1462 0x9282 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 +end +device domain 0 on # PCI domain + subsystemid 0x1462 0x9282 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off end # WDTO#, PLED + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux + device i2c 70 on # 0 pca9554 1 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 54 on end end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 55 on end end - device pnp 2e.007 off # GPIO 1 + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 56 on end end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 57 on end end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 + end + device i2c 70 on # 0 pca9554 2 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end end - device pnp 2e.307 off # GPIO 6 + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end end - device pnp 2e.8 off end # WDTO#, PLED - device pnp 2e.009 off # GPIO 2 + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end end - device pnp 2e.109 off # GPIO 3 + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end end - device pnp 2e.209 off # GPIO 4 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 54 on end end - device pnp 2e.309 off # GPIO 5 + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 55 on end end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 56 on end end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux - device i2c 70 on # 0 pca9554 1 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 57 on end - end - end - device i2c 70 on # 0 pca9554 2 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 57 on end - end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 57 on end end end end - device pci 1.1 on # SM 1 - chip drivers/i2c/i2cmux2 # pca9554 SMBus mux - device i2c 72 on # PCA9554 channel 1 - chip drivers/i2c/adm1027 # HWM ADT7476 1 - device i2c 2e on end - end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/i2cmux2 # pca9554 SMBus mux + device i2c 72 on # PCA9554 channel 1 + chip drivers/i2c/adm1027 # HWM ADT7476 1 + device i2c 2e on end end - device i2c 72 on # PCA9545 channel 2 - chip drivers/i2c/adm1027 # HWM ADT7463 - device i2c 2e on end - end + end + device i2c 72 on # PCA9545 channel 2 + chip drivers/i2c/adm1027 # HWM ADT7463 + device i2c 2e on end end - device i2c 72 on end # PCA9545 channel 3 - device i2c 72 on # PCA9545 channel 4 - chip drivers/i2c/adm1027 # HWM ADT7476 2 - device i2c 2e on end - end + end + device i2c 72 on end # PCA9545 channel 3 + device i2c 72 on # PCA9545 channel 4 + chip drivers/i2c/adm1027 # HWM ADT7476 2 + device i2c 2e on end end end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # P2P - device pci 4.0 on end - end - device pci 7.0 on end # reserve - device pci 8.0 on end # MAC0 - device pci 9.0 on end # MAC1 - device pci a.0 on - device pci 0.0 on - device pci 4.0 on end # PCI-E LAN1 - device pci 4.1 on end # PCI-E LAN2 - end - end # 0x376 - device pci b.0 on end # PCI E 0x374 - device pci c.0 on end - device pci d.0 on # SAS - device pci 0.0 on end - end # PCI E 1 0x378 - device pci e.0 on end # PCI E 0 0x375 - device pci f.0 on end # PCI E 0x377, PCI-E slot - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # P2P + device pci 4.0 on end + end + device pci 7.0 on end # reserve + device pci 8.0 on end # MAC0 + device pci 9.0 on end # MAC1 + device pci a.0 on + device pci 0.0 on + device pci 4.0 on end # PCI-E LAN1 + device pci 4.1 on end # PCI-E LAN2 + end + end # 0x376 + device pci b.0 on end # PCI E 0x374 + device pci c.0 on end + device pci d.0 on # SAS + device pci 0.0 on end + end # PCI E 1 0x378 + device pci e.0 on end # PCI E 0 0x375 + device pci f.0 on end # PCI E 0x377, PCI-E slot + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/msi/ms9652_fam10/devicetree.cb b/src/mainboard/msi/ms9652_fam10/devicetree.cb index 51d5bf3..9c3f2f6 100644 --- a/src/mainboard/msi/ms9652_fam10/devicetree.cb +++ b/src/mainboard/msi/ms9652_fam10/devicetree.cb @@ -16,150 +16,147 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## - -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1462 0x9652 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on # Link 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 on # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end +end +device domain 0 on # PCI domain + subsystemid 0x1462 0x9652 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on # Link 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 on # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.307 off # GPIO 6 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.8 off # WDTO#, PLED end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.009 off # GPIO 2 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.109 off # GPIO 3 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.209 off # GPIO 4 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.309 off # GPIO 5 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - # chip drivers/generic/generic # MAC EEPROM - # device i2c 51 on end - # end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + # chip drivers/generic/generic # MAC EEPROM + # device i2c 51 on end + # end end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.0 on end # HT 1.0 - device pci 18.0 on end # HT 2.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end end + device pci 18.0 on end # HT 1.0 + device pci 18.0 on end # HT 2.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end end end diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb index 5709db7..c66cc74 100644 --- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb +++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb @@ -1,180 +1,178 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end +end +device domain 0 on # PCI domain + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.007 off # GPIO 1 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end - end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 72e89c0..3feb648 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -13,90 +13,88 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family14/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family14 - device lapic 0 on end - end - end - device domain 0 on - subsystemid 0x1022 0x1510 inherit - chip northbridge/amd/agesa/family14 # CPU side of HT root complex -# device pci 18.0 on # northbridge - chip northbridge/amd/agesa/family14 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] - device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 - device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 - device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 - device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 - device pci 8.0 on end # NB/SB Link P2P bridge - end # agesa northbridge +device cpu_cluster 0 on + chip cpu/amd/agesa/family14 + device lapic 0 on end + end +end +device domain 0 on + subsystemid 0x1022 0x1510 inherit + chip northbridge/amd/agesa/family14 # CPU side of HT root complex +# device pci 18.0 on # northbridge + chip northbridge/amd/agesa/family14 # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 off end # Internal Graphics P2P bridge 0x980[2456] + device pci 4.0 on end # PCIE P2P bridge on-board NIC 3 + device pci 5.0 on end # PCIE P2P bridge on-board NIC 2 + device pci 6.0 on end # PCIE P2P bridge on-board NIC 1 + device pci 7.0 on end # PCIE P2P bridge miniPCIe slot 1 + device pci 8.0 on end # NB/SB Link P2P bridge + end # agesa northbridge - chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # OHCI USB 0-4 - device pci 12.2 on end # EHCI USB 0-4 - device pci 13.0 on end # OHCI USB 5-9 - device pci 13.2 on end # EHCI USB 5-9 - device pci 14.0 on end # SMBus - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 - device pci 14.3 on # LPC 0x439d - chip superio/nuvoton/nct5104d - register "irq_trigger_type" = "0" - device pnp 2e.0 off end - device pnp 2e.2 on - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.10 off - # UART C is conditionally turned on - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.11 off - # UART D is conditionally turned on - io 0x60 = 0x2e8 - irq 0x70 = 3 - end - device pnp 2e.8 off end - device pnp 2e.f off end - # GPIO0 and GPIO1 are conditionally turned on - device pnp 2e.007 off end - device pnp 2e.107 off end - device pnp 2e.607 off end - device pnp 2e.e off end + chip southbridge/amd/cimx/sb800 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # OHCI USB 0-4 + device pci 12.2 on end # EHCI USB 0-4 + device pci 13.0 on end # OHCI USB 5-9 + device pci 13.2 on end # EHCI USB 5-9 + device pci 14.0 on end # SMBus + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + register "irq_trigger_type" = "0" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 end - end #LPC - device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 - device pci 14.5 off end # OHCI FS/LS USB - #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) - device pci 15.0 on end # PCIe PortA miniPCIe slot 2 - device pci 15.1 off end # PCIe PortB - device pci 15.2 off end # PCIe PortC - device pci 15.3 off end # PCIe PortD - device pci 16.0 on end # OHCI USB 10-13 - device pci 16.2 on end # EHCI USB 10-13 - register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 - register "disconnect_pcib" = "1" - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/cimx/sb800 -# end # device pci 18.0 + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 off + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 off + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.8 off end + device pnp 2e.f off end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 off end + device pnp 2e.107 off end + device pnp 2e.607 off end + device pnp 2e.e off end + end + end #LPC + device pci 14.4 on end # PCIB 0x4384 always active; pins remapped to gpio by disconnect_pcib = 1 + device pci 14.5 off end # OHCI FS/LS USB + #device pci 14.6 off end # Hudson-E1 GbE MAC: Broadcom BCM5785 (14E4:1699) + device pci 15.0 on end # PCIe PortA miniPCIe slot 2 + device pci 15.1 off end # PCIe PortB + device pci 15.2 off end # PCIe PortC + device pci 15.3 off end # PCIe PortD + device pci 16.0 on end # OHCI USB 10-13 + device pci 16.2 on end # EHCI USB 10-13 + register "gpp_configuration" = "4" # GPP_CFGMODE_X1111 + register "disconnect_pcib" = "1" + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/cimx/sb800 +# end # device pci 18.0 # These seem unnecessary - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end - end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family14/root_complex + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb index e47703f..4d83bc4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/devicetree.cb +++ b/src/mainboard/siemens/sitemp_g1p1/devicetree.cb @@ -8,127 +8,125 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_S1G1 + device lapic 0 on end end - device domain 0 on - subsystemid 0x110a 0x4076 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on # Northbridge configuration space (0x7910) - end - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on # Internal Graphics 0x791F - end - device pci 5.2 on # - end - end - device pci 2.0 on # PCIE P2P bridge 0x7913 (external GFX-port0) - end - device pci 3.0 off # PCIE P2P bridge 0x791b (external GFX-port1) +end +device domain 0 on + subsystemid 0x110a 0x4076 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on # Northbridge configuration space (0x7910) + end + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + device pci 5.0 on # Internal Graphics 0x791F end - device pci 4.0 on # PCIE P2P bridge port 0 (0x7914) + device pci 5.2 on # end - device pci 5.0 on # PCIE P2P bridge port 1 (0x7915) + end + device pci 2.0 on # PCIE P2P bridge 0x7913 (external GFX-port0) + end + device pci 3.0 off # PCIE P2P bridge 0x791b (external GFX-port1) + end + device pci 4.0 on # PCIE P2P bridge port 0 (0x7914) + end + device pci 5.0 on # PCIE P2P bridge port 1 (0x7915) + end + device pci 6.0 on # PCIE P2P bridge port 2 (0x7916) + end + device pci 7.0 on # PCIE P2P bridge port 3 (0x7917) + end + device pci 8.0 off # NB/SB Link P2P bridge + end + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "1" # needed for DVI output, but this results in a conflict if PLX installed ! + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" # 4 (0x8) if PLX installed + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end end - device pci 6.0 on # PCIE P2P bridge port 2 (0x7916) + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end end - device pci 7.0 on # PCIE P2P bridge port 3 (0x7917) + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end end - device pci 8.0 off # NB/SB Link P2P bridge + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end end - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "1" # needed for DVI output, but this results in a conflict if PLX installed ! - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" # 4 (0x8) if PLX installed - end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e -# register "ide0_enable" = "1" -# register "sata0_enable" = "1" - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e +# register "ide0_enable" = "1" +# register "sata0_enable" = "1" + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/sunw/ultra40/devicetree.cb b/src/mainboard/sunw/ultra40/devicetree.cb index 9f9bb67..2bc2018 100644 --- a/src/mainboard/sunw/ultra40/devicetree.cb +++ b/src/mainboard/sunw/ultra40/devicetree.cb @@ -1,151 +1,149 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x108e 0x0040 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47m10x # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 off # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end +end +device domain 0 on # PCI domain + subsystemid 0x108e 0x0040 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47m10x # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.7 off # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master CK804 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave CK804 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master CK804 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave CK804 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.0 on end # Link 2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 19.0 on end # Link 0 - device pci 19.0 on # Link 1 == LDT 1 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end + device pci 18.0 on end # Link 2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 19.0 on end # Link 0 + device pci 19.0 on # Link 1 == LDT 1 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end end end diff --git a/src/mainboard/sunw/ultra40m2/devicetree.cb b/src/mainboard/sunw/ultra40m2/devicetree.cb index 9982459..7e4d401 100644 --- a/src/mainboard/sunw/ultra40m2/devicetree.cb +++ b/src/mainboard/sunw/ultra40m2/devicetree.cb @@ -1,147 +1,145 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x108e 0x6676 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on end # Link 0 == LDT 0 - device pci 18.0 on # Link 1 == LDT 1 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/dme1737 # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 2 - end - device pnp 2e.4 on # COM1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # COM2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # PS/2 (connectors not populated) - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.a on # Runtime Registers - io 0x60 = 0x600 - end - end - # There's an Infineon SLB9635TT12 TPM on this LPC bus. - # There's also an Akom AK2001 7-segment port 0x80 decoder on - # this LPC bus. - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end +end +device domain 0 on # PCI domain + subsystemid 0x108e 0x6676 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end # Link 0 == LDT 0 + device pci 18.0 on # Link 1 == LDT 1 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/dme1737 # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.5 off # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.7 on # PS/2 (connectors not populated) + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.a on # Runtime Registers + io 0x60 = 0x600 end end - device pci 1.1 on # SM 1 - #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!) - # device i2c 18 on end - #end - chip drivers/generic/generic # EMC6D103 HWM (for CPUs) - device i2c 2d on end - end - chip drivers/generic/generic # DME1737 HWM - device i2c 2e on end - end - #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM - # device i2c 51 on end - #end - #chip drivers/generic/generic # front panel module FRU 24C64 EEPROM - # device i2c 52 on end - #end - #chip drivers/generic/generic # HDD 0-3 backplane FRU 24C64 EEPROM - # device i2c 53 on end - #end - # there are more SMbus devices on this bus + # There's an Infineon SLB9635TT12 TPM on this LPC bus. + # There's also an Akom AK2001 7-segment port 0x80 decoder on + # this LPC bus. + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 off end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 off end # NIC - device pci 9.0 off end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" end - end - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 off end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + device pci 1.1 on # SM 1 + #chip drivers/generic/generic # PCA9556 GPIO on HDD backplanes (address conflict!) + # device i2c 18 on end + #end + chip drivers/generic/generic # EMC6D103 HWM (for CPUs) + device i2c 2d on end + end + chip drivers/generic/generic # DME1737 HWM + device i2c 2e on end + end + #chip drivers/generic/generic # HDD 4-7 backplane FRU 24C64 EEPROM + # device i2c 51 on end + #end + #chip drivers/generic/generic # front panel module FRU 24C64 EEPROM + # device i2c 52 on end + #end + #chip drivers/generic/generic # HDD 0-3 backplane FRU 24C64 EEPROM + # device i2c 53 on end + #end + # there are more SMbus devices on this bus end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 off end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 off end # NIC + device pci 9.0 off end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 off end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/supermicro/h8dme/devicetree.cb b/src/mainboard/supermicro/h8dme/devicetree.cb index 754e316..d80f2c7 100644 --- a/src/mainboard/supermicro/h8dme/devicetree.cb +++ b/src/mainboard/supermicro/h8dme/devicetree.cb @@ -1,126 +1,124 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end +end +device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 - device i2c 48 off end - device i2c 49 off end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 + device i2c 48 off end + device i2c 49 off end end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/supermicro/h8dmr/devicetree.cb b/src/mainboard/supermicro/h8dmr/devicetree.cb index b363674..ed1bf3c 100644 --- a/src/mainboard/supermicro/h8dmr/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr/devicetree.cb @@ -1,146 +1,144 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end +end +device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb index 9e52d07..81d84a4 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb @@ -1,152 +1,150 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2.0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end +end +device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2.0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on end # NEC PCI-X - device pci 0.1 on # NEC PCI-X - device pci 4.0 on end # SCSI - device pci 4.1 on end # SCSI - end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end end end diff --git a/src/mainboard/supermicro/h8qgi/devicetree.cb b/src/mainboard/supermicro/h8qgi/devicetree.cb index 5ba52b6..f6d18b6 100644 --- a/src/mainboard/supermicro/h8qgi/devicetree.cb +++ b/src/mainboard/supermicro/h8qgi/devicetree.cb @@ -12,211 +12,209 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family15 - device lapic 0x20 on end #f15 - #device lapic 0x10 on end #f10 - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x20 on end #f15 + #device lapic 0x10 on end #f10 end - device domain 0 on - subsystemid 0x15d9 0xab11 inherit #SuperMicro - chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology - chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex - device pci 0.0 on end # HT Root Complex 0x9600 - device pci 0.1 off end # CLKCONFIG - device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 - device pci 3.0 off end # GPP1 Port1 - device pci 4.0 off end # GPP3a Port0 x4 SAS - device pci 5.0 off end # GPP3a Port1 - device pci 6.0 off end # GPP3a Port2 - device pci 7.0 off end # GPP3a Port3 - device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time - device pci 9.0 off end # GPP3a Port4 x1 NC - device pci a.0 off end # GPP3a Port5 x1 NC - device pci b.0 off end # GPP2 Port0 (Not for sr5650) - device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) - device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 - register "port_enable" = "0x2104" - end #northbridge/amd/cimx/rd890 - chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB1 - device pci 12.1 on end # USB1 - device pci 12.2 on end # USB1 - device pci 13.0 on end # USB2 - device pci 13.1 on end # USB2 - device pci 13.2 on end # USB2 - device pci 14.0 on end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8qgi not have codec. - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 0x01 #keyboard - irq 0x72 = 0x0C #mouse - end - device pnp 2e.6 off # SPI - end - device pnp 2e.307 off # GPIO6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO2 - end - device pnp 2e.109 off # GPIO3 - end - device pnp 2e.209 off # GPIO4 - end - device pnp 2e.309 off # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b off # HWM - io 0x60 = 0x290 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w83627dhg - chip drivers/i2c/w83795 - register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 - register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions - register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 - register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 - register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 - register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 - register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT - register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) - register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) - register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) - register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) - register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) - register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) - register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 - register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 - register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 - register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 - register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 - register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 - register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C - register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C - register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C - register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C - register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C - register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C - register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C - register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C - register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V - register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V - register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V - register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V - register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V - register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V - register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V - register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V - register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V - register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V - register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V - register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V - register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V - register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V - register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V - register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V - register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V - register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V - register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V - register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V - register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V - register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V - register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V - register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V - register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V - register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V - register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V - register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V - register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - register "smbus_aux" = "0" # Device located on primary SMBUS - device pnp 5e on #hwm - end - end #drivers/i2c/w83795 - end # LPC - device pci 14.4 on - device pci 4.0 on end # onboard VGA - end # PCI 0x4384 - device pci 14.5 on end # USB 3 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/cimx/sb700 - end # device pci 18.0 +end +device domain 0 on + subsystemid 0x15d9 0xab11 inherit #SuperMicro + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex 0x9600 + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 off end # GPP3a Port0 x4 SAS + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 off end # GPP3a Port4 x1 NC + device pci a.0 off end # GPP3a Port5 x1 NC + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x2104" + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8qgi not have codec. + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 #keyboard + irq 0x72 = 0x0C #mouse + end + device pnp 2e.6 off # SPI + end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b off # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 + register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions + register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 + register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 + register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 + register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 + register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT + register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) + register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) + register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) + register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) + register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) + register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) + register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 + register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 + register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 + register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 + register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 + register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 + register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C + register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C + register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C + register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C + register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C + register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C + register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C + register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C + register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V + register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V + register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V + register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V + register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V + register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V + register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V + register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V + register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V + register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V + register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V + register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V + register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V + register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V + register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V + register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V + register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V + register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V + register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V + register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V + register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V + register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V + register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V + register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V + register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V + register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V + register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V + register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V + register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + register "smbus_aux" = "0" # Device located on primary SMBUS + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 + end # LPC + device pci 14.4 on + device pci 4.0 on end # onboard VGA + end # PCI 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end # southbridge/amd/cimx/sb700 + end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end #f15 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end #f15 - register "spdAddrLookup" = " - { - { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 - { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 - { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 2 - { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 3 - }" - end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family15/root_complex + register "spdAddrLookup" = " + { + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 0 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 1 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 2 + { {0xAC, 0xAE}, {0xA8, 0xAA}, {0xA4, 0xA6}, {0xA0, 0xA2}, }, // socket 3 + }" + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb index 6956b45..5162493 100644 --- a/src/mainboard/supermicro/h8qme_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8qme_fam10/devicetree.cb @@ -1,115 +1,113 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end +end +device domain 0 on # PCI domain + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - end - device pci 1.1 on end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end + end + device pci 1.1 on end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end + end + device pci 8.0 off end + device pci 9.0 off end + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end end + device pci 1.1 on end end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end end end diff --git a/src/mainboard/supermicro/h8scm/devicetree.cb b/src/mainboard/supermicro/h8scm/devicetree.cb index 3b22407..a571052 100644 --- a/src/mainboard/supermicro/h8scm/devicetree.cb +++ b/src/mainboard/supermicro/h8scm/devicetree.cb @@ -12,206 +12,204 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family15 - device lapic 0x10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x10 on end end - device domain 0 on - subsystemid 0x15d9 0xab11 inherit #Supermicro - chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology - chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex - device pci 0.0 on end # HT Root Complex 0x9600 - device pci 0.1 on end # CLKCONFIG - device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 - device pci 3.0 on end # GPP1 Port1 - device pci 4.0 on end # GPP3a Port0 x4 SAS - device pci 5.0 off end # GPP3a Port1 - device pci 6.0 off end # GPP3a Port2 - device pci 7.0 off end # GPP3a Port3 - device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time - device pci 9.0 on end # GPP3a Port4 x1 NC - device pci a.0 on end # GPP3a Port5 x1 NC - device pci b.0 off end # GPP2 Port0 (Not for sr5650) - device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) - device pci d.0 off end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 - register "gpp1_configuration" = "1" # Configuration 16:0 default - #register "gpp2_configuration" = "0" # Configuration 8:8 - register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 - register "port_enable" = "0x61f" - end #northbridge/amd/cimx/rd890 - chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB1 - device pci 12.1 on end # USB1 - device pci 12.2 on end # USB1 - device pci 13.0 on end # USB2 - device pci 13.1 on end # USB2 - device pci 13.2 on end # USB2 - device pci 14.0 on end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8scm not have codec. - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 0x01 #keyboard - irq 0x72 = 0x0C #mouse - end - device pnp 2e.6 off # SPI - end - device pnp 2e.307 off # GPIO6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO2 - end - device pnp 2e.109 off # GPIO3 - end - device pnp 2e.209 off # GPIO4 - end - device pnp 2e.309 off # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b off # HWM - io 0x60 = 0x290 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w83627dhg - chip drivers/i2c/w83795 - register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 - register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions - register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 - register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 - register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 - register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 - register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT - register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) - register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) - register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) - register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) - register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) - register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) - register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 - register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 - register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 - register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 - register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 - register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 - register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C - register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C - register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C - register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C - register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C - register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C - register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C - register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C - register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V - register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V - register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V - register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V - register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V - register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V - register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V - register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V - register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V - register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V - register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V - register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V - register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V - register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V - register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V - register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V - register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V - register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V - register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V - register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V - register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V - register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V - register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V - register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V - register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V - register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V - register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V - register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V - register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - register "smbus_aux" = "0" # Device located on primary SMBUS - device pnp 5e on #hwm - end - end #drivers/i2c/w83795 - end # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 3 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/cimx/sb700 - end # device pci 18.0 +end +device domain 0 on + subsystemid 0x15d9 0xab11 inherit #Supermicro + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex 0x9600 + device pci 0.1 on end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 + device pci 3.0 on end # GPP1 Port1 + device pci 4.0 on end # GPP3a Port0 x4 SAS + device pci 5.0 off end # GPP3a Port1 + device pci 6.0 off end # GPP3a Port2 + device pci 7.0 off end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 on end # GPP3a Port4 x1 NC + device pci a.0 on end # GPP3a Port5 x1 NC + device pci b.0 off end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 off end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "1" # Configuration 16:0 default + #register "gpp2_configuration" = "0" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x61f" + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8scm not have codec. + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 #keyboard + irq 0x72 = 0x0C #mouse + end + device pnp 2e.6 off # SPI + end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b off # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 + register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions + register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 + register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 + register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 + register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 + register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT + register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) + register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) + register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) + register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) + register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) + register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) + register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 + register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 + register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 + register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 + register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 + register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 + register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C + register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C + register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C + register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C + register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C + register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C + register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C + register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C + register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V + register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V + register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V + register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V + register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V + register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V + register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V + register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V + register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V + register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V + register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V + register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V + register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V + register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V + register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V + register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V + register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V + register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V + register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V + register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V + register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V + register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V + register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V + register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V + register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V + register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V + register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V + register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V + register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + register "smbus_aux" = "0" # Device located on primary SMBUS + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 + end # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end # southbridge/amd/cimx/sb700 + end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end #f15 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end #f15 - register "spdAddrLookup" = " - { - { {0xA4, 0xA6}, {0xA0, 0xA2}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 0 - { {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 (unused) - }" - end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family15/root_complex + register "spdAddrLookup" = " + { + { {0xA4, 0xA6}, {0xA0, 0xA2}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 0 + { {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 (unused) + }" + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb index 82229da..22584fe 100644 --- a/src/mainboard/supermicro/h8scm_fam10/devicetree.cb +++ b/src/mainboard/supermicro/h8scm_fam10/devicetree.cb @@ -3,121 +3,118 @@ # GPP3A (dev9,A) --> Lan1, Lan2 # sample config for supermicro/h8scm_fam10 -chip northbridge/amd/amdfam10/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_C32 #L1 and DDR3 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_C32 #L1 and DDR3 + device lapic 0 on end end - device domain 0 on - subsystemid 0x15d9 0x1511 inherit - chip northbridge/amd/amdfam10 - ##device pci 18.0 on end - ##device pci 18.0 on end - device pci 18.0 on # northbridge - chip southbridge/amd/sr5650 - device pci 0.0 on end # HT 0x9600 - device pci 0.1 on end # CLKCONFIG - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 - device pci 3.0 off end # PCIE P2P bridge 0x960b - device pci 4.0 off end # PCIE P2P bridge 0x9604 - device pci 5.0 off end # PCIE P2P bridge 0x9605 - device pci 6.0 on end # PCIE P2P bridge 0x9606 - device pci 7.0 on end # PCIE P2P bridge 0x9607 - device pci 8.0 on end # NB/SB Link P2P bridge - device pci 9.0 on end # - device pci a.0 on end # - device pci b.0 on end # - device pci c.0 on end # - device pci d.0 on end # - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "1" # Configuration 8:8 - #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 - register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 - register "port_enable" = "0x1ffc" - end - chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB - device pci 12.1 on end # USB - device pci 12.2 on end # USB - device pci 13.0 on end # USB - device pci 13.1 on end # USB - device pci 13.2 on end # USB - device pci 14.0 on end # SM - device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec. - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end #superio/winbond/w83627hf - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 2 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end #southbridge/amd/sb700 - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end - end #domain - #for node 32 to node 63 -# device domain 0 on -# chip northbridge/amd/amdfam10 -# device pci 00.0 on end# northbridge -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.0 on end -# device pci 00.1 on end -# device pci 00.2 on end -# device pci 00.3 on end -# device pci 00.4 on end -# device pci 00.5 on end -# end -# end #domain - end +device domain 0 on + subsystemid 0x15d9 0x1511 inherit + chip northbridge/amd/amdfam10 + ##device pci 18.0 on end + ##device pci 18.0 on end + device pci 18.0 on # northbridge + chip southbridge/amd/sr5650 + device pci 0.0 on end # HT 0x9600 + device pci 0.1 on end # CLKCONFIG + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 off end # PCIE P2P bridge 0x960b + device pci 4.0 off end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 on end # PCIE P2P bridge 0x9606 + device pci 7.0 on end # PCIE P2P bridge 0x9607 + device pci 8.0 on end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + device pci b.0 on end # + device pci c.0 on end # + device pci d.0 on end # + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "1" # Configuration 8:8 + #register "gpp3a_configuration" = "2" # Configuration 4:1:1:0:0:0 + register "gpp3a_configuration" = "11" # Configuration 1:1:1:1:1:1 + register "port_enable" = "0x1ffc" + end + chip southbridge/amd/sb700 # (model:sp5100) it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, h8scm doesnt have codec. + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627hf + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 off # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO_GAME_MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO_PLED + device pnp 2e.9 off end # GPIO_SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end #superio/winbond/w83627hf + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end #southbridge/amd/sb700 + end # device pci 18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end +end #domain +#for node 32 to node 63 +#device domain 0 on +# chip northbridge/amd/amdfam10 +# device pci 00.0 on end# northbridge +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.0 on end +# device pci 00.1 on end +# device pci 00.2 on end +# device pci 00.3 on end +# device pci 00.4 on end +# device pci 00.5 on end +# end +#end #domain diff --git a/src/mainboard/technexion/tim5690/devicetree.cb b/src/mainboard/technexion/tim5690/devicetree.cb index bf462e2..d896c2a 100644 --- a/src/mainboard/technexion/tim5690/devicetree.cb +++ b/src/mainboard/technexion/tim5690/devicetree.cb @@ -8,105 +8,103 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_S1G1 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "1" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "0" - register "gfx_link_width" = "0" +end +device domain 0 on + subsystemid 0x1022 0x3050 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end # Internal Graphics 0x791F end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "1" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "0" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/technexion/tim8690/devicetree.cb b/src/mainboard/technexion/tim8690/devicetree.cb index 8d1df8b..8ec4bc0 100644 --- a/src/mainboard/technexion/tim8690/devicetree.cb +++ b/src/mainboard/technexion/tim8690/devicetree.cb @@ -8,108 +8,106 @@ #Define gfx_compliance, 0: didn't support compliance, 1: support #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 -chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_S1G1 - device lapic 0 on end - end +device cpu_cluster 0 on + chip cpu/amd/socket_S1G1 + device lapic 0 on end end - device domain 0 on - subsystemid 0x1022 0x3050 inherit - chip northbridge/amd/amdk8 - device pci 18.0 on # southbridge - chip southbridge/amd/rs690 - device pci 0.0 on end # HT 0x7910 - device pci 1.0 on # Internal Graphics P2P bridge 0x7912 - device pci 5.0 on end # Internal Graphics 0x791F - end - device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 - device pci 3.0 off end # PCIE P2P bridge 0x791b - device pci 4.0 on end # PCIE P2P bridge 0x7914 - device pci 5.0 on end # PCIE P2P bridge 0x7915 - device pci 6.0 on end # PCIE P2P bridge 0x7916 - device pci 7.0 on end # PCIE P2P bridge 0x7917 - device pci 8.0 off end # NB/SB Link P2P bridge - register "gpp_configuration" = "4" - register "port_enable" = "0xfc" - register "gfx_dev2_dev3" = "1" - register "gfx_dual_slot" = "0" - register "gfx_lane_reversal" = "0" - register "gfx_tmds" = "0" - register "gfx_compliance" = "0" - register "gfx_reconfiguration" = "1" - register "gfx_link_width" = "0" +end +device domain 0 on + subsystemid 0x1022 0x3050 inherit + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs690 + device pci 0.0 on end # HT 0x7910 + device pci 1.0 on # Internal Graphics P2P bridge 0x7912 + device pci 5.0 on end # Internal Graphics 0x791F end - chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus - device pci 12.0 on end # SATA 0x4380 - device pci 13.0 on end # USB 0x4387 - device pci 13.1 on end # USB 0x4388 - device pci 13.2 on end # USB 0x4389 - device pci 13.3 on end # USB 0x438a - device pci 13.4 on end # USB 0x438b - device pci 13.5 on end # USB 2 0x4386 - device pci 14.0 on # SM 0x4385 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x7913 + device pci 3.0 off end # PCIE P2P bridge 0x791b + device pci 4.0 on end # PCIE P2P bridge 0x7914 + device pci 5.0 on end # PCIE P2P bridge 0x7915 + device pci 6.0 on end # PCIE P2P bridge 0x7916 + device pci 7.0 on end # PCIE P2P bridge 0x7917 + device pci 8.0 off end # NB/SB Link P2P bridge + register "gpp_configuration" = "4" + register "port_enable" = "0xfc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "0" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb600 # it is under NB/SB Link, but on the same pri bus + device pci 12.0 on end # SATA 0x4380 + device pci 13.0 on end # USB 0x4387 + device pci 13.1 on end # USB 0x4388 + device pci 13.2 on end # USB 0x4389 + device pci 13.3 on end # USB 0x438a + device pci 13.4 on end # USB 0x438b + device pci 13.5 on end # USB 2 0x4386 + device pci 14.0 on # SM 0x4385 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.1 on end # IDE 0x438c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x438d + chip superio/ite/it8712f + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 off end # EC + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 off # GPIO, must be closed for unresolved reason. + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end + device pnp 2e.9 off # GAME + io 0x60 = 0x220 end - end # SM - device pci 14.1 on end # IDE 0x438c - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on # LPC 0x438d - chip superio/ite/it8712f - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 off end # EC - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 off # GPIO, must be closed for unresolved reason. - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end #superio/ite/it8712f - end #LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # ACI 0x4382 - device pci 14.6 on end # MCI 0x438e - register "hda_viddid" = "0x10ec0882" - end #southbridge/amd/sb600 - end # device pci 18.0 + device pnp 2e.a off end # CIR + end #superio/ite/it8712f + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # ACI 0x4382 + device pci 14.6 on end # MCI 0x438e + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb600 + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #northbridge/amd/amdk8 - end #domain -end #northbridge/amd/amdk8/root_complex + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 +end #domain diff --git a/src/mainboard/tyan/s2912/devicetree.cb b/src/mainboard/tyan/s2912/devicetree.cb index 42f764a..2e2f2a7 100644 --- a/src/mainboard/tyan/s2912/devicetree.cb +++ b/src/mainboard/tyan/s2912/devicetree.cb @@ -1,138 +1,136 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end +end +device domain 0 on # PCI domain + subsystemid 0x10f1 0x2912 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/src/mainboard/tyan/s2912_fam10/devicetree.cb b/src/mainboard/tyan/s2912_fam10/devicetree.cb index 485c7e0e..b8228e6 100644 --- a/src/mainboard/tyan/s2912_fam10/devicetree.cb +++ b/src/mainboard/tyan/s2912_fam10/devicetree.cb @@ -1,141 +1,139 @@ -chip northbridge/amd/amdfam10/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F_1207 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x10f1 0x2912 inherit - chip northbridge/amd/amdfam10 # Northbridge / RAM controller - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on # SB on link 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO, game port, MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO PLED - device pnp 2e.9 off end # GPIO SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end +end +device domain 0 on # PCI domain + subsystemid 0x10f1 0x2912 inherit + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 end end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 4.0 on end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end end - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 4.0 on end end + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end end end diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index ddcf769..cfdf71d 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -12,206 +12,204 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/agesa/family15/root_complex - device cpu_cluster 0 on - chip cpu/amd/agesa/family15 - device lapic 0x10 on end - end +device cpu_cluster 0 on + chip cpu/amd/agesa/family15 + device lapic 0x10 on end end - device domain 0 on - subsystemid 0x15d9 0xab11 inherit #Tyan - chip northbridge/amd/agesa/family15 # CPU side of HT root complex - device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology - chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex - device pci 0.0 on end # HT Root Complex 0x9600 - device pci 0.1 off end # CLKCONFIG - device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 - device pci 3.0 off end # GPP1 Port1 - device pci 4.0 on end # GPP3a Port0 x4 SAS - device pci 5.0 on end # GPP3a Port1 - device pci 6.0 on end # GPP3a Port2 - device pci 7.0 on end # GPP3a Port3 - device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time - device pci 9.0 on end # GPP3a Port4 x1 NC - device pci a.0 on end # GPP3a Port5 x1 NC - device pci b.0 on end # GPP2 Port0 (Not for sr5650) - device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) - device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 - register "gpp1_configuration" = "0" # Configuration 16:0 default - register "gpp2_configuration" = "0" # Configuration 8:8 - register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 - register "port_enable" = "0x3ef6" - end #northbridge/amd/cimx/rd890 - chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus - device pci 11.0 on end # SATA - device pci 12.0 on end # USB1 - device pci 12.1 on end # USB1 - device pci 12.2 on end # USB1 - device pci 13.0 on end # USB2 - device pci 13.1 on end # USB2 - device pci 13.2 on end # USB2 - device pci 14.0 on end # SM - device pci 14.1 off end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383, s8226 not have codec. - device pci 14.3 on # LPC 0x439d - chip superio/winbond/w83627dhg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 0x01 #keyboard - irq 0x72 = 0x0C #mouse - end - device pnp 2e.6 off # SPI - end - device pnp 2e.307 off # GPIO6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO2 - end - device pnp 2e.109 off # GPIO3 - end - device pnp 2e.209 off # GPIO4 - end - device pnp 2e.309 off # GPIO5 - end - device pnp 2e.a off # ACPI - end - device pnp 2e.b off # HWM - io 0x60 = 0x290 - end - device pnp 2e.c off # PECI, SST - end - end #superio/winbond/w83627dhg - chip drivers/i2c/w83795 - register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 - register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions - register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 - register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 - register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 - register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 - register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT - register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) - register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) - register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) - register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) - register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) - register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) - register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 - register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 - register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 - register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 - register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 - register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 - register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C - register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C - register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C - register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C - register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C - register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C - register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C - register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C - register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C - register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C - register "fan1_nonstop" = "7" # Set Fan 1 minimum speed - register "fan2_nonstop" = "7" # Set Fan 2 minimum speed - register "fan3_nonstop" = "7" # Set Fan 3 minimum speed - register "fan4_nonstop" = "7" # Set Fan 4 minimum speed - register "fan5_nonstop" = "7" # Set Fan 5 minimum speed - register "fan6_nonstop" = "7" # Set Fan 6 minimum speed - register "fan7_nonstop" = "7" # Set Fan 7 minimum speed - register "fan8_nonstop" = "7" # Set Fan 8 minimum speed - register "default_speed" = "100" # All fans to full speed on power up - register "fan1_duty" = "100" # Fan 1 to full speed - register "fan2_duty" = "100" # Fan 2 to full speed - register "fan3_duty" = "100" # Fan 3 to full speed - register "fan4_duty" = "100" # Fan 4 to full speed - register "fan5_duty" = "100" # Fan 5 to full speed - register "fan6_duty" = "100" # Fan 6 to full speed - register "fan7_duty" = "100" # Fan 7 to full speed - register "fan8_duty" = "100" # Fan 8 to full speed - register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V - register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V - register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V - register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V - register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V - register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V - register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V - register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V - register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V - register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V - register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V - register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V - register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V - register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V - register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V - register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V - register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V - register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V - register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V - register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V - register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V - register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V - register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V - register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V - register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V - register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V - register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V - register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V - register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V - register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V - register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V - register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V - register "smbus_aux" = "0" # Device located on primary SMBUS - device pnp 5e on #hwm - end - end #drivers/i2c/w83795 - end # LPC - device pci 14.4 on end # PCI 0x4384 - device pci 14.5 on end # USB 3 - register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE - end # southbridge/amd/cimx/sb700 - end # device pci 18.0 +end +device domain 0 on + subsystemid 0x15d9 0xab11 inherit #Tyan + chip northbridge/amd/agesa/family15 # CPU side of HT root complex + device pci 18.0 on # Put IO-HUB at link_num 0, Instead of HT Link topology + chip northbridge/amd/cimx/rd890 # Southbridge PCI side of HT Root complex + device pci 0.0 on end # HT Root Complex 0x9600 + device pci 0.1 off end # CLKCONFIG + device pci 2.0 on end # GPP1 Port0 x16 SLOT4, 0x5A16 + device pci 3.0 off end # GPP1 Port1 + device pci 4.0 on end # GPP3a Port0 x4 SAS + device pci 5.0 on end # GPP3a Port1 + device pci 6.0 on end # GPP3a Port2 + device pci 7.0 on end # GPP3a Port3 + device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time + device pci 9.0 on end # GPP3a Port4 x1 NC + device pci a.0 on end # GPP3a Port5 x1 NC + device pci b.0 on end # GPP2 Port0 (Not for sr5650) + device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670) + device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576 + register "gpp1_configuration" = "0" # Configuration 16:0 default + register "gpp2_configuration" = "0" # Configuration 8:8 + register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1 + register "port_enable" = "0x3ef6" + end #northbridge/amd/cimx/rd890 + chip southbridge/amd/cimx/sb700 # it is under NB/SB Link, but on the same pci bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB1 + device pci 12.1 on end # USB1 + device pci 12.2 on end # USB1 + device pci 13.0 on end # USB2 + device pci 13.1 on end # USB2 + device pci 13.2 on end # USB2 + device pci 14.0 on end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 off end # HDA 0x4383, s8226 not have codec. + device pci 14.3 on # LPC 0x439d + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + ## though UARTs are on the NUVOTON BMC, superio only used to support PS2 KB/MS## + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 0x01 #keyboard + irq 0x72 = 0x0C #mouse + end + device pnp 2e.6 off # SPI + end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO2 + end + device pnp 2e.109 off # GPIO3 + end + device pnp 2e.209 off # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b off # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w83627dhg + chip drivers/i2c/w83795 + register "fanin_ctl1" = "0xff" # Enable monitoring of FANIN1 - FANIN8 + register "fanin_ctl2" = "0x00" # Connect FANIN11 - FANIN14 to alternate functions + register "temp_ctl1" = "0x2a" # Enable monitoring of DTS, VSEN12, and VSEN13 + register "temp_ctl2" = "0x01" # Enable monitoring of TD1/TR1 + register "temp_dtse" = "0x03" # Enable DTS1 and DTS2 + register "volt_ctl1" = "0xff" # Enable monitoring of VSEN1 - VSEN8 + register "volt_ctl2" = "0xf7" # Enable monitoring of VSEN9 - VSEN11, 3VDD, 3VSB, and VBAT + register "temp1_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp1) + register "temp2_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp2) + register "temp3_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp3) + register "temp4_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp4) + register "temp5_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp5) + register "temp6_fan_select" = "0x00" # All fans to manual mode (no dependence on Temp6) + register "temp1_source_select" = "0x00" # Use TD1/TR1 as data source for Temp1 + register "temp2_source_select" = "0x00" # Use TD2/TR2 as data source for Temp2 + register "temp3_source_select" = "0x00" # Use TD3/TR3 as data source for Temp3 + register "temp4_source_select" = "0x00" # Use TD4/TR4 as data source for Temp4 + register "temp5_source_select" = "0x00" # Use TR5 as data source for Temp5 + register "temp6_source_select" = "0x00" # Use TR6 as data source for Temp6 + register "tr1_critical_temperature" = "85" # Set TD1/TR1 critical temperature to 85°C + register "tr1_critical_hysteresis" = "80" # Set TD1/TR1 critical hysteresis temperature to 80°C + register "tr1_warning_temperature" = "70" # Set TD1/TR1 warning temperature to 70°C + register "tr1_warning_hysteresis" = "65" # Set TD1/TR1 warning hysteresis temperature to 65°C + register "dts_critical_temperature" = "85" # Set DTS (CPU) critical temperature to 85°C + register "dts_critical_hysteresis" = "80" # Set DTS (CPU) critical hysteresis temperature to 80°C + register "dts_warning_temperature" = "70" # Set DTS (CPU) warning temperature to 70°C + register "dts_warning_hysteresis" = "65" # Set DTS (CPU) warning hysteresis temperature to 65°C + register "temp1_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp2_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp3_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp4_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp5_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp6_critical_temperature" = "80" # Set Temp1 critical temperature to 80°C + register "temp1_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp2_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp3_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp4_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp5_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "temp6_target_temperature" = "80" # Set Temp1 target temperature to 80°C + register "fan1_nonstop" = "7" # Set Fan 1 minimum speed + register "fan2_nonstop" = "7" # Set Fan 2 minimum speed + register "fan3_nonstop" = "7" # Set Fan 3 minimum speed + register "fan4_nonstop" = "7" # Set Fan 4 minimum speed + register "fan5_nonstop" = "7" # Set Fan 5 minimum speed + register "fan6_nonstop" = "7" # Set Fan 6 minimum speed + register "fan7_nonstop" = "7" # Set Fan 7 minimum speed + register "fan8_nonstop" = "7" # Set Fan 8 minimum speed + register "default_speed" = "100" # All fans to full speed on power up + register "fan1_duty" = "100" # Fan 1 to full speed + register "fan2_duty" = "100" # Fan 2 to full speed + register "fan3_duty" = "100" # Fan 3 to full speed + register "fan4_duty" = "100" # Fan 4 to full speed + register "fan5_duty" = "100" # Fan 5 to full speed + register "fan6_duty" = "100" # Fan 6 to full speed + register "fan7_duty" = "100" # Fan 7 to full speed + register "fan8_duty" = "100" # Fan 8 to full speed + register "vcore1_high_limit_mv" = "1500" # VCORE1 (Node 0) high limit to 1.5V + register "vcore1_low_limit_mv" = "900" # VCORE1 (Node 0) low limit to 0.9V + register "vcore2_high_limit_mv" = "1500" # VCORE2 (Node 1) high limit to 1.5V + register "vcore2_low_limit_mv" = "900" # VCORE2 (Node 1) low limit to 0.9V + register "vsen3_high_limit_mv" = "1600" # VSEN1 (Node 0 RAM voltage) high limit to 1.6V + register "vsen3_low_limit_mv" = "1100" # VSEN1 (Node 0 RAM voltage) low limit to 1.1V + register "vsen4_high_limit_mv" = "1600" # VSEN2 (Node 1 RAM voltage) high limit to 1.6V + register "vsen4_low_limit_mv" = "1100" # VSEN2 (Node 1 RAM voltage) low limit to 1.1V + register "vsen5_high_limit_mv" = "1250" # VSEN5 (Node 0 HT link voltage) high limit to 1.25V + register "vsen5_low_limit_mv" = "1150" # VSEN5 (Node 0 HT link voltage) low limit to 1.15V + register "vsen6_high_limit_mv" = "1250" # VSEN6 (Node 1 HT link voltage) high limit to 1.25V + register "vsen6_low_limit_mv" = "1150" # VSEN6 (Node 1 HT link voltage) low limit to 1.15V + register "vsen7_high_limit_mv" = "1150" # VSEN7 (Northbridge core voltage) high limit to 1.15V + register "vsen7_low_limit_mv" = "1050" # VSEN7 (Northbridge core voltage) low limit to 1.05V + register "vsen8_high_limit_mv" = "1900" # VSEN8 (+1.8V) high limit to 1.9V + register "vsen8_low_limit_mv" = "1700" # VSEN8 (+1.8V) low limit to 1.7V + register "vsen9_high_limit_mv" = "1250" # VSEN9 (+1.2V) high limit to 1.25V + register "vsen9_low_limit_mv" = "1150" # VSEN9 (+1.2V) low limit to 1.15V + register "vsen10_high_limit_mv" = "1150" # VSEN10 (+1.1V) high limit to 1.15V + register "vsen10_low_limit_mv" = "1050" # VSEN10 (+1.1V) low limit to 1.05V + register "vsen11_high_limit_mv" = "1625" # VSEN11 (5VSB, scaling factor ~3.2) high limit to 5.2V + register "vsen11_low_limit_mv" = "1500" # VSEN11 (5VSB, scaling factor ~3.2) low limit to 4.8V + register "vsen12_high_limit_mv" = "1083" # VSEN12 (+12V, scaling factor ~12) high limit to 13V + register "vsen12_low_limit_mv" = "917" # VSEN12 (+12V, scaling factor ~12) low limit to 11V + register "vsen13_high_limit_mv" = "1625" # VSEN13 (+5V, scaling factor ~3.2) high limit to 5.2V + register "vsen13_low_limit_mv" = "1500" # VSEN13 (+5V, scaling factor ~3.2) low limit to 4.8V + register "vdd_high_limit_mv" = "3500" # 3VDD high limit to 3.5V + register "vdd_low_limit_mv" = "3100" # 3VDD low limit to 3.1V + register "vsb_high_limit_mv" = "3500" # 3VSB high limit to 3.5V + register "vsb_low_limit_mv" = "3100" # 3VSB low limit to 3.1V + register "vbat_high_limit_mv" = "3500" # VBAT (+3V) high limit to 3.5V + register "vbat_low_limit_mv" = "2500" # VBAT (+3V) low limit to 2.5V + register "smbus_aux" = "0" # Device located on primary SMBUS + device pnp 5e on #hwm + end + end #drivers/i2c/w83795 + end # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 3 + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + end # southbridge/amd/cimx/sb700 + end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end #f15 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end #f15 - register "spdAddrLookup" = " - { - { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 - { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 - }" - end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex - end #domain -end #northbridge/amd/agesa/family15/root_complex + register "spdAddrLookup" = " + { + { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 + { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 + }" + end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex +end #domain diff --git a/src/mainboard/winent/mb6047/devicetree.cb b/src/mainboard/winent/mb6047/devicetree.cb index 81f5aae..fb9bd70 100644 --- a/src/mainboard/winent/mb6047/devicetree.cb +++ b/src/mainboard/winent/mb6047/devicetree.cb @@ -1,120 +1,118 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_940 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end +device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU end - device domain 0 on # PCI domain - subsystemid 0x10de 0xcb84 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # Consumer IR - device pnp 2e.7 off end # Game port, MIDI, GPIO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 0 - end +end +device domain 0 on # PCI domain + subsystemid 0x10de 0xcb84 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # Consumer IR + device pnp 2e.7 off end # Game port, MIDI, GPIO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 0 end end - device pci 1.1 on # SM 0 - # chip drivers/generic/generic # DIMM 0-0-0 - # device i2c 50 on end - # end - # chip drivers/generic/generic # DIMM 0-0-1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # DIMM 0-1-0 - # device i2c 52 on end - # end - # chip drivers/generic/generic # DIMM 0-1-1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end - end - # device pci 1.1 on # SM 1 - # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - # device i2c 2d on end - # end - # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - # device i2c 2e on end - # end - # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - # device i2c 2a on end - # end - # chip drivers/generic/generic # Winbond HWM 0x92 - # device i2c 49 on end - # end - # chip drivers/generic/generic # Winbond HWM 0x94 - # device i2c 4a on end - # end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end # end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # device pci 6.0 on end - end - device pci a.0 on end # NIC - device pci b.0 on end # PCI E 3 - device pci c.0 on end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "0" - register "sata0_enable" = "1" - register "sata1_enable" = "1" + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # device pci 6.0 on end end + device pci a.0 on end # NIC + device pci b.0 on end # PCI E 3 + device pci c.0 on end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "0" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - device pci 18.0 on end # Link 1 - device pci 18.0 on end # Link 2 == LDT 2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end end + device pci 18.0 on end # Link 1 + device pci 18.0 on end # Link 2 == LDT 2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end end end diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index eb759d2..58853a6 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -8,7 +8,7 @@ #define FLEX_SCANNER #define YY_FLEX_MAJOR_VERSION 2 #define YY_FLEX_MINOR_VERSION 5 -#define YY_FLEX_SUBMINOR_VERSION 35 +#define YY_FLEX_SUBMINOR_VERSION 39 #if YY_FLEX_SUBMINOR_VERSION > 0 #define FLEX_BETA #endif @@ -161,7 +161,12 @@ typedef unsigned int flex_uint32_t; typedef struct yy_buffer_state *YY_BUFFER_STATE; #endif -extern int yyleng; +#ifndef YY_TYPEDEF_YY_SIZE_T +#define YY_TYPEDEF_YY_SIZE_T +typedef size_t yy_size_t; +#endif + +extern yy_size_t yyleng; extern FILE *yyin, *yyout; @@ -170,6 +175,7 @@ extern FILE *yyin, *yyout; #define EOB_ACT_LAST_MATCH 2 #define YY_LESS_LINENO(n) + #define YY_LINENO_REWIND_TO(ptr) /* Return all but the first "n" matched characters back to the input stream. */ #define yyless(n) \ @@ -187,11 +193,6 @@ extern FILE *yyin, *yyout; #define unput(c) yyunput( c, (yytext_ptr) ) -#ifndef YY_TYPEDEF_YY_SIZE_T -#define YY_TYPEDEF_YY_SIZE_T -typedef size_t yy_size_t; -#endif - #ifndef YY_STRUCT_YY_BUFFER_STATE #define YY_STRUCT_YY_BUFFER_STATE struct yy_buffer_state @@ -209,7 +210,7 @@ struct yy_buffer_state /* Number of characters read into yy_ch_buf, not including EOB * characters. */ - int yy_n_chars; + yy_size_t yy_n_chars; /* Whether we "own" the buffer - i.e., we know we created it, * and can realloc() it to grow it, and should free() it to @@ -279,8 +280,8 @@ static YY_BUFFER_STATE * yy_buffer_stack = 0; /**< Stack as an array. */ /* yy_hold_char holds the character lost when yytext is formed. */ static char yy_hold_char; -static int yy_n_chars; /* number of characters read into yy_ch_buf */ -int yyleng; +static yy_size_t yy_n_chars; /* number of characters read into yy_ch_buf */ +yy_size_t yyleng; /* Points to current character in buffer. */ static char *yy_c_buf_p = (char *) 0; @@ -308,7 +309,7 @@ static void yy_init_buffer (YY_BUFFER_STATE b,FILE *file ); YY_BUFFER_STATE yy_scan_buffer (char *base,yy_size_t size ); YY_BUFFER_STATE yy_scan_string (yyconst char *yy_str ); -YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,int len ); +YY_BUFFER_STATE yy_scan_bytes (yyconst char *bytes,yy_size_t len ); void *yyalloc (yy_size_t ); void *yyrealloc (void *,yy_size_t ); @@ -552,10 +553,6 @@ char *yytext; * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. */ #include "sconfig.tab.h" @@ -599,7 +596,7 @@ FILE *yyget_out (void ); void yyset_out (FILE * out_str ); -int yyget_leng (void ); +yy_size_t yyget_leng (void ); char *yyget_text (void ); @@ -773,6 +770,8 @@ YY_DECL yy_load_buffer_state( ); } + { + while ( 1 ) /* loops until end-of-file is reached */ { yy_cp = (yy_c_buf_p); @@ -789,7 +788,7 @@ YY_DECL yy_match: do { - register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)]; + register YY_CHAR yy_c = yy_ec[YY_SC_TO_UI(*yy_cp)] ; if ( yy_accept[yy_current_state] ) { (yy_last_accepting_state) = yy_current_state; @@ -1085,6 +1084,7 @@ case YY_STATE_EOF(INITIAL): "fatal flex scanner internal error--no action found" ); } /* end of action switch */ } /* end of scanning one token */ + } /* end of user's declarations */ } /* end of yylex */ /* yy_get_next_buffer - try to read in a new buffer @@ -1140,21 +1140,21 @@ static int yy_get_next_buffer (void) else { - int num_to_read = + yy_size_t num_to_read = YY_CURRENT_BUFFER_LVALUE->yy_buf_size - number_to_move - 1; while ( num_to_read <= 0 ) { /* Not enough room in the buffer - grow it. */ /* just a shorter name for the current buffer */ - YY_BUFFER_STATE b = YY_CURRENT_BUFFER; + YY_BUFFER_STATE b = YY_CURRENT_BUFFER_LVALUE; int yy_c_buf_p_offset = (int) ((yy_c_buf_p) - b->yy_ch_buf); if ( b->yy_is_our_buffer ) { - int new_size = b->yy_buf_size * 2; + yy_size_t new_size = b->yy_buf_size * 2; if ( new_size <= 0 ) b->yy_buf_size += b->yy_buf_size / 8; @@ -1185,7 +1185,7 @@ static int yy_get_next_buffer (void) /* Read in more data. */ YY_INPUT( (&YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[number_to_move]), - (yy_n_chars), (size_t) num_to_read ); + (yy_n_chars), num_to_read ); YY_CURRENT_BUFFER_LVALUE->yy_n_chars = (yy_n_chars); } @@ -1280,7 +1280,7 @@ static int yy_get_next_buffer (void) yy_current_state = yy_nxt[yy_base[yy_current_state] + (unsigned int) yy_c]; yy_is_jam = (yy_current_state == 115); - return yy_is_jam ? 0 : yy_current_state; + return yy_is_jam ? 0 : yy_current_state; } static void yyunput (int c, register char * yy_bp ) @@ -1295,7 +1295,7 @@ static int yy_get_next_buffer (void) if ( yy_cp < YY_CURRENT_BUFFER_LVALUE->yy_ch_buf + 2 ) { /* need to shift things up to make room */ /* +2 for EOB chars. */ - register int number_to_move = (yy_n_chars) + 2; + register yy_size_t number_to_move = (yy_n_chars) + 2; register char *dest = &YY_CURRENT_BUFFER_LVALUE->yy_ch_buf[ YY_CURRENT_BUFFER_LVALUE->yy_buf_size + 2]; register char *source = @@ -1344,7 +1344,7 @@ static int yy_get_next_buffer (void) else { /* need more input */ - int offset = (yy_c_buf_p) - (yytext_ptr); + yy_size_t offset = (yy_c_buf_p) - (yytext_ptr); ++(yy_c_buf_p); switch ( yy_get_next_buffer( ) ) @@ -1504,10 +1504,6 @@ static void yy_load_buffer_state (void) yyfree((void *) b ); } -#ifndef __cplusplus -extern int isatty (int ); -#endif /* __cplusplus */ - /* Initializes or reinitializes a buffer. * This function is sometimes called more than once on the same buffer, * such as during a yyrestart() or at EOF. @@ -1620,7 +1616,7 @@ void yypop_buffer_state (void) */ static void yyensure_buffer_stack (void) { - int num_to_alloc; + yy_size_t num_to_alloc; if (!(yy_buffer_stack)) { @@ -1717,12 +1713,12 @@ YY_BUFFER_STATE yy_scan_string (yyconst char * yystr ) * * @return the newly allocated buffer state object. */ -YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, int _yybytes_len ) +YY_BUFFER_STATE yy_scan_bytes (yyconst char * yybytes, yy_size_t _yybytes_len ) { YY_BUFFER_STATE b; char *buf; yy_size_t n; - int i; + yy_size_t i; /* Get memory for full buffer, including space for trailing EOB's. */ n = _yybytes_len + 2; @@ -1804,7 +1800,7 @@ FILE *yyget_out (void) /** Get the length of the current token. * */ -int yyget_leng (void) +yy_size_t yyget_leng (void) { return yyleng; } @@ -1951,3 +1947,4 @@ void yyfree (void * ptr ) } #define YYTABLES_NAME "yytables" + diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5eb74da..f48a902 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -164,14 +164,9 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { char *chip_h = malloc(strlen(path)+18); sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { - if (strstr(path, "/root_complex")) { - fprintf(stderr, "WARNING: Use of deprecated chip component %s\n", - path); - } else { - fprintf(stderr, "ERROR: Chip component %s does not exist.\n", - path); - exit(1); - } + fprintf(stderr, "ERROR: Chip component %s does not exist.\n", + path); + exit(1); } if (scan_mode == STATIC_MODE) @@ -195,6 +190,31 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { return new_chip; } +struct device *new_dummy_chip(struct device *parent, struct device *bus) { + static int count = 0; + struct device *new_chip = new_dev(parent, bus); + new_chip->chiph_exists = 0; + new_chip->name = malloc(30); + if (new_chip->name == NULL) { + fprintf(stderr, "malloc failed\n"); + exit(1); + } + sprintf(new_chip->name, "dummy_%d_chip", ++count); + new_chip->name_underscore = new_chip->name; + new_chip->type = chip; + new_chip->chip = new_chip; + + if (parent->latestchild) { + parent->latestchild->next_sibling = new_chip; + parent->latestchild->sibling = new_chip; + } + parent->latestchild = new_chip; + if (!parent->children) + parent->children = new_chip; + + return new_chip; +} + void add_header(struct device *dev) { int include_exists = 0; struct header *h = &headers; diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index 2c35eb3..d9c8eb4 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -90,6 +90,7 @@ void fold_in(struct device *parent); void postprocess_devtree(void); struct device *new_chip(struct device *parent, struct device *bus, char *path); +struct device *new_dummy_chip(struct device *parent, struct device *bus); void add_header(struct device *dev); struct device *new_device(struct device *parent, struct device *busdev, const int bus, const char *devnum, int enabled); void alias_siblings(struct device *d); diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 8424936..e18ff5b 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,19 +1,19 @@ -/* A Bison parser, made by GNU Bison 2.5. */ +/* A Bison parser, made by GNU Bison 3.0.2. */ /* Bison implementation for Yacc-like parsers in C - - Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc. - + + Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ @@ -26,7 +26,7 @@ special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. - + This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ @@ -44,7 +44,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "2.5" +#define YYBISON_VERSION "3.0.2" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -58,8 +58,6 @@ /* Pull parsers. */ #define YYPULL 1 -/* Using locations. */ -#define YYLSP_NEEDED 0 @@ -80,10 +78,6 @@ * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc. */ #include "sconfig.h" @@ -93,10 +87,13 @@ static struct device *cur_parent, *cur_bus; -/* Enabling traces. */ -#ifndef YYDEBUG -# define YYDEBUG 0 -#endif +# ifndef YY_NULLPTR +# if defined __cplusplus && 201103L <= __cplusplus +# define YY_NULLPTR nullptr +# else +# define YY_NULLPTR 0 +# endif +# endif /* Enabling verbose error messages. */ #ifdef YYERROR_VERBOSE @@ -106,51 +103,56 @@ static struct device *cur_parent, *cur_bus; # define YYERROR_VERBOSE 0 #endif -/* Enabling the token table. */ -#ifndef YYTOKEN_TABLE -# define YYTOKEN_TABLE 0 +/* In a future release of Bison, this section will be replaced + by #include "sconfig.tab.h_shipped". */ +#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +/* Debug traces. */ +#ifndef YYDEBUG +# define YYDEBUG 0 +#endif +#if YYDEBUG +extern int yydebug; #endif - -/* Tokens. */ +/* Token type. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE - /* Put the tokens into the symbol table, so that GDB and other debuggers - know about them. */ - enum yytokentype { - CHIP = 258, - DEVICE = 259, - REGISTER = 260, - BOOL = 261, - BUS = 262, - RESOURCE = 263, - END = 264, - EQUALS = 265, - HEX = 266, - STRING = 267, - PCI = 268, - PNP = 269, - I2C = 270, - APIC = 271, - CPU_CLUSTER = 272, - CPU = 273, - DOMAIN = 274, - IRQ = 275, - DRQ = 276, - IO = 277, - NUMBER = 278, - SUBSYSTEMID = 279, - INHERIT = 280, - IOAPIC_IRQ = 281, - IOAPIC = 282, - PCIINT = 283 - }; + enum yytokentype + { + CHIP = 258, + DEVICE = 259, + REGISTER = 260, + BOOL = 261, + BUS = 262, + RESOURCE = 263, + END = 264, + EQUALS = 265, + HEX = 266, + STRING = 267, + PCI = 268, + PNP = 269, + I2C = 270, + APIC = 271, + CPU_CLUSTER = 272, + CPU = 273, + DOMAIN = 274, + IRQ = 275, + DRQ = 276, + IO = 277, + NUMBER = 278, + SUBSYSTEMID = 279, + INHERIT = 280, + IOAPIC_IRQ = 281, + IOAPIC = 282, + PCIINT = 283 + }; #endif - - +/* Value type. */ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED -typedef union YYSTYPE +typedef union YYSTYPE YYSTYPE; +union YYSTYPE { @@ -159,14 +161,18 @@ typedef union YYSTYPE int number; - -} YYSTYPE; +}; # define YYSTYPE_IS_TRIVIAL 1 -# define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 #endif +extern YYSTYPE yylval; + +int yyparse (void); + +#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ + /* Copy the second part of user declarations. */ @@ -183,11 +189,8 @@ typedef unsigned char yytype_uint8; #ifdef YYTYPE_INT8 typedef YYTYPE_INT8 yytype_int8; -#elif (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) -typedef signed char yytype_int8; #else -typedef short int yytype_int8; +typedef signed char yytype_int8; #endif #ifdef YYTYPE_UINT16 @@ -207,8 +210,7 @@ typedef short int yytype_int16; # define YYSIZE_T __SIZE_TYPE__ # elif defined size_t # define YYSIZE_T size_t -# elif ! defined YYSIZE_T && (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) +# elif ! defined YYSIZE_T # include <stddef.h> /* INFRINGES ON USER NAME SPACE */ # define YYSIZE_T size_t # else @@ -222,39 +224,68 @@ typedef short int yytype_int16; # if defined YYENABLE_NLS && YYENABLE_NLS # if ENABLE_NLS # include <libintl.h> /* INFRINGES ON USER NAME SPACE */ -# define YY_(msgid) dgettext ("bison-runtime", msgid) +# define YY_(Msgid) dgettext ("bison-runtime", Msgid) # endif # endif # ifndef YY_ -# define YY_(msgid) msgid +# define YY_(Msgid) Msgid +# endif +#endif + +#ifndef YY_ATTRIBUTE +# if (defined __GNUC__ \ + && (2 < __GNUC__ || (__GNUC__ == 2 && 96 <= __GNUC_MINOR__))) \ + || defined __SUNPRO_C && 0x5110 <= __SUNPRO_C +# define YY_ATTRIBUTE(Spec) __attribute__(Spec) +# else +# define YY_ATTRIBUTE(Spec) /* empty */ +# endif +#endif + +#ifndef YY_ATTRIBUTE_PURE +# define YY_ATTRIBUTE_PURE YY_ATTRIBUTE ((__pure__)) +#endif + +#ifndef YY_ATTRIBUTE_UNUSED +# define YY_ATTRIBUTE_UNUSED YY_ATTRIBUTE ((__unused__)) +#endif + +#if !defined _Noreturn \ + && (!defined __STDC_VERSION__ || __STDC_VERSION__ < 201112) +# if defined _MSC_VER && 1200 <= _MSC_VER +# define _Noreturn __declspec (noreturn) +# else +# define _Noreturn YY_ATTRIBUTE ((__noreturn__)) # endif #endif /* Suppress unused-variable warnings by "using" E. */ #if ! defined lint || defined __GNUC__ -# define YYUSE(e) ((void) (e)) +# define YYUSE(E) ((void) (E)) #else -# define YYUSE(e) /* empty */ +# define YYUSE(E) /* empty */ #endif -/* Identity function, used to suppress warnings about constant conditions. */ -#ifndef lint -# define YYID(n) (n) +#if defined __GNUC__ && 407 <= __GNUC__ * 100 + __GNUC_MINOR__ +/* Suppress an incorrect diagnostic about yylval being uninitialized. */ +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN \ + _Pragma ("GCC diagnostic push") \ + _Pragma ("GCC diagnostic ignored \"-Wuninitialized\"")\ + _Pragma ("GCC diagnostic ignored \"-Wmaybe-uninitialized\"") +# define YY_IGNORE_MAYBE_UNINITIALIZED_END \ + _Pragma ("GCC diagnostic pop") #else -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) -static int -YYID (int yyi) -#else -static int -YYID (yyi) - int yyi; +# define YY_INITIAL_VALUE(Value) Value #endif -{ - return yyi; -} +#ifndef YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN +# define YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN +# define YY_IGNORE_MAYBE_UNINITIALIZED_END +#endif +#ifndef YY_INITIAL_VALUE +# define YY_INITIAL_VALUE(Value) /* Nothing. */ #endif + #if ! defined yyoverflow || YYERROR_VERBOSE /* The parser invokes alloca or malloc; define the necessary symbols. */ @@ -272,9 +303,9 @@ YYID (yyi) # define alloca _alloca # else # define YYSTACK_ALLOC alloca -# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) +# if ! defined _ALLOCA_H && ! defined EXIT_SUCCESS # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */ + /* Use EXIT_SUCCESS as a witness for stdlib.h. */ # ifndef EXIT_SUCCESS # define EXIT_SUCCESS 0 # endif @@ -284,8 +315,8 @@ YYID (yyi) # endif # ifdef YYSTACK_ALLOC - /* Pacify GCC's `empty if-body' warning. */ -# define YYSTACK_FREE(Ptr) do { /* empty */; } while (YYID (0)) + /* Pacify GCC's 'empty if-body' warning. */ +# define YYSTACK_FREE(Ptr) do { /* empty */; } while (0) # ifndef YYSTACK_ALLOC_MAXIMUM /* The OS might guarantee only one guard page at the bottom of the stack, and a page size can be as small as 4096 bytes. So we cannot safely @@ -301,7 +332,7 @@ YYID (yyi) # endif # if (defined __cplusplus && ! defined EXIT_SUCCESS \ && ! ((defined YYMALLOC || defined malloc) \ - && (defined YYFREE || defined free))) + && (defined YYFREE || defined free))) # include <stdlib.h> /* INFRINGES ON USER NAME SPACE */ # ifndef EXIT_SUCCESS # define EXIT_SUCCESS 0 @@ -309,15 +340,13 @@ YYID (yyi) # endif # ifndef YYMALLOC # define YYMALLOC malloc -# if ! defined malloc && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) +# if ! defined malloc && ! defined EXIT_SUCCESS void *malloc (YYSIZE_T); /* INFRINGES ON USER NAME SPACE */ # endif # endif # ifndef YYFREE # define YYFREE free -# if ! defined free && ! defined EXIT_SUCCESS && (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) +# if ! defined free && ! defined EXIT_SUCCESS void free (void *); /* INFRINGES ON USER NAME SPACE */ # endif # endif @@ -327,7 +356,7 @@ void free (void *); /* INFRINGES ON USER NAME SPACE */ #if (! defined yyoverflow \ && (! defined __cplusplus \ - || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) + || (defined YYSTYPE_IS_TRIVIAL && YYSTYPE_IS_TRIVIAL))) /* A type that is properly aligned for any stack member. */ union yyalloc @@ -352,61 +381,63 @@ union yyalloc elements in the stack, and YYPTR gives the new location of the stack. Advance YYPTR to a properly aligned location for the next stack. */ -# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ - do \ - { \ - YYSIZE_T yynewbytes; \ - YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ - Stack = &yyptr->Stack_alloc; \ - yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ - yyptr += yynewbytes / sizeof (*yyptr); \ - } \ - while (YYID (0)) +# define YYSTACK_RELOCATE(Stack_alloc, Stack) \ + do \ + { \ + YYSIZE_T yynewbytes; \ + YYCOPY (&yyptr->Stack_alloc, Stack, yysize); \ + Stack = &yyptr->Stack_alloc; \ + yynewbytes = yystacksize * sizeof (*Stack) + YYSTACK_GAP_MAXIMUM; \ + yyptr += yynewbytes / sizeof (*yyptr); \ + } \ + while (0) #endif #if defined YYCOPY_NEEDED && YYCOPY_NEEDED -/* Copy COUNT objects from FROM to TO. The source and destination do +/* Copy COUNT objects from SRC to DST. The source and destination do not overlap. */ # ifndef YYCOPY # if defined __GNUC__ && 1 < __GNUC__ -# define YYCOPY(To, From, Count) \ - __builtin_memcpy (To, From, (Count) * sizeof (*(From))) +# define YYCOPY(Dst, Src, Count) \ + __builtin_memcpy (Dst, Src, (Count) * sizeof (*(Src))) # else -# define YYCOPY(To, From, Count) \ - do \ - { \ - YYSIZE_T yyi; \ - for (yyi = 0; yyi < (Count); yyi++) \ - (To)[yyi] = (From)[yyi]; \ - } \ - while (YYID (0)) +# define YYCOPY(Dst, Src, Count) \ + do \ + { \ + YYSIZE_T yyi; \ + for (yyi = 0; yyi < (Count); yyi++) \ + (Dst)[yyi] = (Src)[yyi]; \ + } \ + while (0) # endif # endif #endif /* !YYCOPY_NEEDED */ /* YYFINAL -- State number of the termination state. */ -#define YYFINAL 3 +#define YYFINAL 6 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 39 +#define YYLAST 41 /* YYNTOKENS -- Number of terminals. */ #define YYNTOKENS 29 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 13 +#define YYNNTS 19 /* YYNRULES -- Number of rules. */ -#define YYNRULES 22 -/* YYNRULES -- Number of states. */ -#define YYNSTATES 41 +#define YYNRULES 30 +/* YYNSTATES -- Number of states. */ +#define YYNSTATES 48 -/* YYTRANSLATE(YYLEX) -- Bison symbol number corresponding to YYLEX. */ +/* YYTRANSLATE[YYX] -- Symbol number corresponding to YYX as returned + by yylex, with out-of-bounds checking. */ #define YYUNDEFTOK 2 #define YYMAXUTOK 283 -#define YYTRANSLATE(YYX) \ +#define YYTRANSLATE(YYX) \ ((unsigned int) (YYX) <= YYMAXUTOK ? yytranslate[YYX] : YYUNDEFTOK) -/* YYTRANSLATE[YYLEX] -- Bison symbol number corresponding to YYLEX. */ +/* YYTRANSLATE[TOKEN-NUM] -- Symbol number corresponding to TOKEN-NUM + as returned by yylex, without out-of-bounds checking. */ static const yytype_uint8 yytranslate[] = { 0, 2, 2, 2, 2, 2, 2, 2, 2, 2, @@ -441,38 +472,17 @@ static const yytype_uint8 yytranslate[] = }; #if YYDEBUG -/* YYPRHS[YYN] -- Index of the first RHS symbol of rule number YYN in - YYRHS. */ -static const yytype_uint8 yyprhs[] = -{ - 0, 0, 3, 4, 7, 10, 13, 16, 17, 20, - 23, 26, 29, 32, 33, 34, 40, 41, 49, 54, - 59, 63, 68 -}; - -/* YYRHS -- A `-1'-separated list of the rules' RHS. */ -static const yytype_int8 yyrhs[] = -{ - 30, 0, -1, -1, 31, 34, -1, 32, 36, -1, - 32, 34, -1, 32, 39, -1, -1, 33, 36, -1, - 33, 34, -1, 33, 38, -1, 33, 40, -1, 33, - 41, -1, -1, -1, 3, 12, 35, 32, 9, -1, - -1, 4, 7, 23, 6, 37, 33, 9, -1, 8, - 23, 10, 23, -1, 5, 12, 10, 12, -1, 24, - 23, 23, -1, 24, 23, 23, 25, -1, 26, 23, - 28, 23, -1 -}; - -/* YYRLINE[YYN] -- source line where rule number YYN was defined. */ + /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_uint8 yyrline[] = { - 0, 35, 35, 35, 37, 37, 37, 37, 39, 39, - 39, 39, 39, 39, 41, 41, 51, 51, 63, 66, - 69, 72, 75 + 0, 31, 31, 31, 32, 32, 33, 33, 35, 35, + 46, 46, 48, 48, 48, 48, 50, 50, 50, 50, + 50, 50, 52, 52, 62, 62, 74, 77, 80, 83, + 86 }; #endif -#if YYDEBUG || YYERROR_VERBOSE || YYTOKEN_TABLE +#if YYDEBUG || YYERROR_VERBOSE || 0 /* YYTNAME[SYMBOL-NUM] -- String name of the symbol SYMBOL-NUM. First, the terminals, then, starting at YYNTOKENS, nonterminals. */ static const char *const yytname[] = @@ -481,14 +491,16 @@ static const char *const yytname[] = "BUS", "RESOURCE", "END", "EQUALS", "HEX", "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", "$accept", - "devtree", "$@1", "chipchildren", "devicechildren", "chip", "@2", - "device", "@3", "resource", "registers", "subsystemid", "ioapic_irq", 0 + "devtree", "devtree_chip", "$@1", "devtree_devs", "$@2", + "top_level_devices", "@3", "devices", "chipchildren", "devicechildren", + "chip", "@4", "device", "@5", "resource", "registers", "subsystemid", + "ioapic_irq", YY_NULLPTR }; #endif # ifdef YYPRINT -/* YYTOKNUM[YYLEX-NUM] -- Internal token number corresponding to - token YYLEX-NUM. */ +/* YYTOKNUM[NUM] -- (External) token number corresponding to the + (internal) symbol number NUM (which must be that of a token). */ static const yytype_uint16 yytoknum[] = { 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, @@ -497,185 +509,138 @@ static const yytype_uint16 yytoknum[] = }; # endif -/* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ -static const yytype_uint8 yyr1[] = +#define YYPACT_NINF -15 + +#define yypact_value_is_default(Yystate) \ + (!!((Yystate) == (-15))) + +#define YYTABLE_NINF -5 + +#define yytable_value_is_error(Yytable_value) \ + 0 + + /* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing + STATE-NUM. */ +static const yytype_int8 yypact[] = { - 0, 29, 31, 30, 32, 32, 32, 32, 33, 33, - 33, 33, 33, 33, 35, 34, 37, 36, 38, 39, - 40, 40, 41 + 1, 10, -15, 8, -15, -15, -15, 0, -15, -15, + -15, -15, 13, -15, 7, -15, 4, -5, 12, -15, + -15, -15, -15, 14, 9, -15, 15, -15, -15, -3, + -1, -15, 2, 3, -15, -15, -15, -15, -15, 18, + 6, 5, 11, 16, 17, -15, -15, -15 }; -/* YYR2[YYN] -- Number of symbols composing right hand side of rule YYN. */ -static const yytype_uint8 yyr2[] = + /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. + Performed when YYTABLE does not specify something else to do. Zero + means the default is an error. */ +static const yytype_uint8 yydefact[] = { - 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 0, 0, 5, 0, 7, 4, 4, - 3, 4, 4 + 6, 0, 2, 0, 3, 8, 1, 0, 5, 7, + 11, 22, 9, 15, 0, 10, 0, 0, 0, 23, + 13, 12, 14, 0, 0, 24, 0, 21, 27, 0, + 0, 25, 0, 0, 17, 16, 18, 19, 20, 0, + 0, 0, 0, 28, 0, 26, 29, 30 }; -/* YYDEFACT[STATE-NAME] -- Default reduction number in state STATE-NUM. - Performed when YYTABLE doesn't specify something else to do. Zero - means the default is an error. */ -static const yytype_uint8 yydefact[] = + /* YYPGOTO[NTERM-NUM]. */ +static const yytype_int8 yypgoto[] = { - 2, 0, 0, 1, 0, 3, 14, 7, 0, 0, - 0, 15, 5, 4, 6, 0, 0, 0, 0, 16, - 19, 13, 0, 0, 17, 0, 0, 9, 8, 10, - 11, 12, 0, 0, 0, 0, 20, 0, 18, 21, - 22 + -15, -15, -15, -15, -15, -15, -15, -15, -15, -15, + -15, -14, -15, -13, -15, -15, -15, -15, -15 }; -/* YYDEFGOTO[NTERM-NUM]. */ + /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 22, 5, 7, 13, 21, 29, - 14, 30, 31 + -1, 1, 2, 3, 4, 5, 9, 10, 12, 16, + 29, 8, 13, 15, 27, 36, 22, 37, 38 }; -/* YYPACT[STATE-NUM] -- Index in YYTABLE of the portion describing - STATE-NUM. */ -#define YYPACT_NINF -10 -static const yytype_int8 yypact[] = + /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If + positive, shift that token. If negative, reduce the rule whose + number is the opposite. If YYTABLE_NINF, syntax error. */ +static const yytype_int8 yytable[] = { - -10, 3, 1, -10, -2, -10, -10, -10, 4, 5, - -1, -10, -10, -10, -10, -9, 7, 9, 6, -10, - -10, -10, -3, -4, -10, 2, 8, -10, -10, -10, - -10, -10, 10, 11, 0, 12, 13, 14, -10, -10, - -10 + 7, 14, 20, 21, -4, 30, 31, 7, 14, 18, + 6, 7, 11, 19, 17, 34, 35, 14, 23, 26, + 25, 32, 39, 33, 24, 40, 41, 28, 42, 43, + 0, 0, 0, 44, 45, 0, 0, 0, 0, 0, + 47, 46 }; -/* YYPGOTO[NTERM-NUM]. */ -static const yytype_int8 yypgoto[] = +static const yytype_int8 yycheck[] = { - -10, -10, -10, -10, -10, -6, -10, 17, -10, -10, - -10, -10, -10 + 3, 4, 16, 16, 3, 8, 9, 3, 4, 5, + 0, 3, 12, 9, 7, 29, 29, 4, 23, 10, + 6, 24, 23, 26, 12, 23, 23, 12, 10, 23, + -1, -1, -1, 28, 23, -1, -1, -1, -1, -1, + 23, 25 }; -/* YYTABLE[YYPACT[STATE-NUM]]. What to do in state STATE-NUM. If - positive, shift that token. If negative, reduce the rule which - number is the opposite. If YYTABLE_NINF, syntax error. */ -#define YYTABLE_NINF -1 -static const yytype_uint8 yytable[] = + /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing + symbol of state STATE-NUM. */ +static const yytype_uint8 yystos[] = { - 4, 9, 12, 3, 4, 23, 24, 4, 9, 10, - 6, 16, 15, 11, 17, 19, 27, 18, 20, 32, - 35, 25, 0, 26, 0, 33, 0, 0, 37, 0, - 0, 34, 0, 0, 36, 38, 0, 40, 39, 28 + 0, 30, 31, 32, 33, 34, 0, 3, 40, 35, + 36, 12, 37, 41, 4, 42, 38, 7, 5, 9, + 40, 42, 45, 23, 12, 6, 10, 43, 12, 39, + 8, 9, 24, 26, 40, 42, 44, 46, 47, 23, + 23, 23, 10, 23, 28, 23, 25, 23 }; -#define yypact_value_is_default(yystate) \ - ((yystate) == (-10)) - -#define yytable_value_is_error(yytable_value) \ - YYID (0) - -static const yytype_int8 yycheck[] = + /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ +static const yytype_uint8 yyr1[] = { - 3, 4, 8, 0, 3, 8, 9, 3, 4, 5, - 12, 12, 7, 9, 23, 6, 22, 10, 12, 23, - 10, 24, -1, 26, -1, 23, -1, -1, 28, -1, - -1, 23, -1, -1, 23, 23, -1, 23, 25, 22 + 0, 29, 30, 30, 32, 31, 34, 33, 36, 35, + 37, 37, 38, 38, 38, 38, 39, 39, 39, 39, + 39, 39, 41, 40, 43, 42, 44, 45, 46, 46, + 47 }; -/* YYSTOS[STATE-NUM] -- The (internal number of the) accessing - symbol of state STATE-NUM. */ -static const yytype_uint8 yystos[] = + /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ +static const yytype_uint8 yyr2[] = { - 0, 30, 31, 0, 3, 34, 12, 35, 32, 4, - 5, 9, 34, 36, 39, 7, 12, 23, 10, 6, - 12, 37, 33, 8, 9, 24, 26, 34, 36, 38, - 40, 41, 23, 23, 23, 10, 23, 28, 23, 25, - 23 + 0, 2, 1, 1, 0, 2, 0, 2, 0, 2, + 2, 0, 2, 2, 2, 0, 2, 2, 2, 2, + 2, 0, 0, 5, 0, 7, 4, 4, 3, 4, + 4 }; -#define yyerrok (yyerrstatus = 0) -#define yyclearin (yychar = YYEMPTY) -#define YYEMPTY (-2) -#define YYEOF 0 - -#define YYACCEPT goto yyacceptlab -#define YYABORT goto yyabortlab -#define YYERROR goto yyerrorlab - - -/* Like YYERROR except do call yyerror. This remains here temporarily - to ease the transition to the new meaning of YYERROR, for GCC. - Once GCC version 2 has supplanted version 1, this can go. However, - YYFAIL appears to be in use. Nevertheless, it is formally deprecated - in Bison 2.4.2's NEWS entry, where a plan to phase it out is - discussed. */ - -#define YYFAIL goto yyerrlab -#if defined YYFAIL - /* This is here to suppress warnings from the GCC cpp's - -Wunused-macros. Normally we don't worry about that warning, but - some users do, and we want to make it easy for users to remove - YYFAIL uses, which will produce warnings from Bison 2.5. */ -#endif -#define YYRECOVERING() (!!yyerrstatus) +#define yyerrok (yyerrstatus = 0) +#define yyclearin (yychar = YYEMPTY) +#define YYEMPTY (-2) +#define YYEOF 0 -#define YYBACKUP(Token, Value) \ -do \ - if (yychar == YYEMPTY && yylen == 1) \ - { \ - yychar = (Token); \ - yylval = (Value); \ - YYPOPSTACK (1); \ - goto yybackup; \ - } \ - else \ - { \ - yyerror (YY_("syntax error: cannot back up")); \ - YYERROR; \ - } \ -while (YYID (0)) - - -#define YYTERROR 1 -#define YYERRCODE 256 - - -/* YYLLOC_DEFAULT -- Set CURRENT to span from RHS[1] to RHS[N]. - If N is 0, then set CURRENT to the empty location which ends - the previous symbol: RHS[0] (always defined). */ - -#define YYRHSLOC(Rhs, K) ((Rhs)[K]) -#ifndef YYLLOC_DEFAULT -# define YYLLOC_DEFAULT(Current, Rhs, N) \ - do \ - if (YYID (N)) \ - { \ - (Current).first_line = YYRHSLOC (Rhs, 1).first_line; \ - (Current).first_column = YYRHSLOC (Rhs, 1).first_column; \ - (Current).last_line = YYRHSLOC (Rhs, N).last_line; \ - (Current).last_column = YYRHSLOC (Rhs, N).last_column; \ - } \ - else \ - { \ - (Current).first_line = (Current).last_line = \ - YYRHSLOC (Rhs, 0).last_line; \ - (Current).first_column = (Current).last_column = \ - YYRHSLOC (Rhs, 0).last_column; \ - } \ - while (YYID (0)) -#endif +#define YYACCEPT goto yyacceptlab +#define YYABORT goto yyabortlab +#define YYERROR goto yyerrorlab -/* This macro is provided for backward compatibility. */ +#define YYRECOVERING() (!!yyerrstatus) -#ifndef YY_LOCATION_PRINT -# define YY_LOCATION_PRINT(File, Loc) ((void) 0) -#endif +#define YYBACKUP(Token, Value) \ +do \ + if (yychar == YYEMPTY) \ + { \ + yychar = (Token); \ + yylval = (Value); \ + YYPOPSTACK (yylen); \ + yystate = *yyssp; \ + goto yybackup; \ + } \ + else \ + { \ + yyerror (YY_("syntax error: cannot back up")); \ + YYERROR; \ + } \ +while (0) +/* Error token number */ +#define YYTERROR 1 +#define YYERRCODE 256 -/* YYLEX -- calling `yylex' with the right arguments. */ -#ifdef YYLEX_PARAM -# define YYLEX yylex (YYLEX_PARAM) -#else -# define YYLEX yylex () -#endif /* Enable debugging if requested. */ #if YYDEBUG @@ -685,54 +650,46 @@ while (YYID (0)) # define YYFPRINTF fprintf # endif -# define YYDPRINTF(Args) \ -do { \ - if (yydebug) \ - YYFPRINTF Args; \ -} while (YYID (0)) +# define YYDPRINTF(Args) \ +do { \ + if (yydebug) \ + YYFPRINTF Args; \ +} while (0) -# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ -do { \ - if (yydebug) \ - { \ - YYFPRINTF (stderr, "%s ", Title); \ - yy_symbol_print (stderr, \ - Type, Value); \ - YYFPRINTF (stderr, "\n"); \ - } \ -} while (YYID (0)) +/* This macro is provided for backward compatibility. */ +#ifndef YY_LOCATION_PRINT +# define YY_LOCATION_PRINT(File, Loc) ((void) 0) +#endif -/*--------------------------------. -| Print this symbol on YYOUTPUT. | -`--------------------------------*/ +# define YY_SYMBOL_PRINT(Title, Type, Value, Location) \ +do { \ + if (yydebug) \ + { \ + YYFPRINTF (stderr, "%s ", Title); \ + yy_symbol_print (stderr, \ + Type, Value); \ + YYFPRINTF (stderr, "\n"); \ + } \ +} while (0) + + +/*----------------------------------------. +| Print this symbol's value on YYOUTPUT. | +`----------------------------------------*/ -/*ARGSUSED*/ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) static void yy_symbol_value_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) -#else -static void -yy_symbol_value_print (yyoutput, yytype, yyvaluep) - FILE *yyoutput; - int yytype; - YYSTYPE const * const yyvaluep; -#endif { + FILE *yyo = yyoutput; + YYUSE (yyo); if (!yyvaluep) return; # ifdef YYPRINT if (yytype < YYNTOKENS) YYPRINT (yyoutput, yytoknum[yytype], *yyvaluep); -# else - YYUSE (yyoutput); # endif - switch (yytype) - { - default: - break; - } + YYUSE (yytype); } @@ -740,22 +697,11 @@ yy_symbol_value_print (yyoutput, yytype, yyvaluep) | Print this symbol on YYOUTPUT. | `--------------------------------*/ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) static void yy_symbol_print (FILE *yyoutput, int yytype, YYSTYPE const * const yyvaluep) -#else -static void -yy_symbol_print (yyoutput, yytype, yyvaluep) - FILE *yyoutput; - int yytype; - YYSTYPE const * const yyvaluep; -#endif { - if (yytype < YYNTOKENS) - YYFPRINTF (yyoutput, "token %s (", yytname[yytype]); - else - YYFPRINTF (yyoutput, "nterm %s (", yytname[yytype]); + YYFPRINTF (yyoutput, "%s %s (", + yytype < YYNTOKENS ? "token" : "nterm", yytname[yytype]); yy_symbol_value_print (yyoutput, yytype, yyvaluep); YYFPRINTF (yyoutput, ")"); @@ -766,16 +712,8 @@ yy_symbol_print (yyoutput, yytype, yyvaluep) | TOP (included). | `------------------------------------------------------------------*/ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) static void yy_stack_print (yytype_int16 *yybottom, yytype_int16 *yytop) -#else -static void -yy_stack_print (yybottom, yytop) - yytype_int16 *yybottom; - yytype_int16 *yytop; -#endif { YYFPRINTF (stderr, "Stack now"); for (; yybottom <= yytop; yybottom++) @@ -786,49 +724,42 @@ yy_stack_print (yybottom, yytop) YYFPRINTF (stderr, "\n"); } -# define YY_STACK_PRINT(Bottom, Top) \ -do { \ - if (yydebug) \ - yy_stack_print ((Bottom), (Top)); \ -} while (YYID (0)) +# define YY_STACK_PRINT(Bottom, Top) \ +do { \ + if (yydebug) \ + yy_stack_print ((Bottom), (Top)); \ +} while (0) /*------------------------------------------------. | Report that the YYRULE is going to be reduced. | `------------------------------------------------*/ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) -static void -yy_reduce_print (YYSTYPE *yyvsp, int yyrule) -#else static void -yy_reduce_print (yyvsp, yyrule) - YYSTYPE *yyvsp; - int yyrule; -#endif +yy_reduce_print (yytype_int16 *yyssp, YYSTYPE *yyvsp, int yyrule) { + unsigned long int yylno = yyrline[yyrule]; int yynrhs = yyr2[yyrule]; int yyi; - unsigned long int yylno = yyrline[yyrule]; YYFPRINTF (stderr, "Reducing stack by rule %d (line %lu):\n", - yyrule - 1, yylno); + yyrule - 1, yylno); /* The symbols being reduced. */ for (yyi = 0; yyi < yynrhs; yyi++) { YYFPRINTF (stderr, " $%d = ", yyi + 1); - yy_symbol_print (stderr, yyrhs[yyprhs[yyrule] + yyi], - &(yyvsp[(yyi + 1) - (yynrhs)]) - ); + yy_symbol_print (stderr, + yystos[yyssp[yyi + 1 - yynrhs]], + &(yyvsp[(yyi + 1) - (yynrhs)]) + ); YYFPRINTF (stderr, "\n"); } } -# define YY_REDUCE_PRINT(Rule) \ -do { \ - if (yydebug) \ - yy_reduce_print (yyvsp, Rule); \ -} while (YYID (0)) +# define YY_REDUCE_PRINT(Rule) \ +do { \ + if (yydebug) \ + yy_reduce_print (yyssp, yyvsp, Rule); \ +} while (0) /* Nonzero means print parse trace. It is left uninitialized so that multiple parsers can coexist. */ @@ -842,7 +773,7 @@ int yydebug; /* YYINITDEPTH -- initial size of the parser's stacks. */ -#ifndef YYINITDEPTH +#ifndef YYINITDEPTH # define YYINITDEPTH 200 #endif @@ -865,15 +796,8 @@ int yydebug; # define yystrlen strlen # else /* Return the length of YYSTR. */ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) static YYSIZE_T yystrlen (const char *yystr) -#else -static YYSIZE_T -yystrlen (yystr) - const char *yystr; -#endif { YYSIZE_T yylen; for (yylen = 0; yystr[yylen]; yylen++) @@ -889,16 +813,8 @@ yystrlen (yystr) # else /* Copy YYSRC to YYDEST, returning the address of the terminating '\0' in YYDEST. */ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) static char * yystpcpy (char *yydest, const char *yysrc) -#else -static char * -yystpcpy (yydest, yysrc) - char *yydest; - const char *yysrc; -#endif { char *yyd = yydest; const char *yys = yysrc; @@ -928,27 +844,27 @@ yytnamerr (char *yyres, const char *yystr) char const *yyp = yystr; for (;;) - switch (*++yyp) - { - case '\'': - case ',': - goto do_not_strip_quotes; - - case '\\': - if (*++yyp != '\\') - goto do_not_strip_quotes; - /* Fall through. */ - default: - if (yyres) - yyres[yyn] = *yyp; - yyn++; - break; - - case '"': - if (yyres) - yyres[yyn] = '\0'; - return yyn; - } + switch (*++yyp) + { + case '\'': + case ',': + goto do_not_strip_quotes; + + case '\\': + if (*++yyp != '\\') + goto do_not_strip_quotes; + /* Fall through. */ + default: + if (yyres) + yyres[yyn] = *yyp; + yyn++; + break; + + case '"': + if (yyres) + yyres[yyn] = '\0'; + return yyn; + } do_not_strip_quotes: ; } @@ -971,12 +887,11 @@ static int yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, yytype_int16 *yyssp, int yytoken) { - YYSIZE_T yysize0 = yytnamerr (0, yytname[yytoken]); + YYSIZE_T yysize0 = yytnamerr (YY_NULLPTR, yytname[yytoken]); YYSIZE_T yysize = yysize0; - YYSIZE_T yysize1; enum { YYERROR_VERBOSE_ARGS_MAXIMUM = 5 }; /* Internationalized format string. */ - const char *yyformat = 0; + const char *yyformat = YY_NULLPTR; /* Arguments of yyformat. */ char const *yyarg[YYERROR_VERBOSE_ARGS_MAXIMUM]; /* Number of reported tokens (one for the "unexpected", one per @@ -984,10 +899,6 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, int yycount = 0; /* There are many possibilities here to consider: - - Assume YYFAIL is not used. It's too flawed to consider. See - <http://lists.gnu.org/archive/html/bison-patches/2009-12/msg00024.html> - for details. YYERROR is fine as it does not invoke this - function. - If this state is a consistent state with a default action, then the only way this function was invoked is if the default action is an error action. In that case, don't check for expected @@ -1036,11 +947,13 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, break; } yyarg[yycount++] = yytname[yyx]; - yysize1 = yysize + yytnamerr (0, yytname[yyx]); - if (! (yysize <= yysize1 - && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) - return 2; - yysize = yysize1; + { + YYSIZE_T yysize1 = yysize + yytnamerr (YY_NULLPTR, yytname[yyx]); + if (! (yysize <= yysize1 + && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; + yysize = yysize1; + } } } } @@ -1060,10 +973,12 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, # undef YYCASE_ } - yysize1 = yysize + yystrlen (yyformat); - if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) - return 2; - yysize = yysize1; + { + YYSIZE_T yysize1 = yysize + yystrlen (yyformat); + if (! (yysize <= yysize1 && yysize1 <= YYSTACK_ALLOC_MAXIMUM)) + return 2; + yysize = yysize1; + } if (*yymsg_alloc < yysize) { @@ -1100,48 +1015,20 @@ yysyntax_error (YYSIZE_T *yymsg_alloc, char **yymsg, | Release the memory associated to this symbol. | `-----------------------------------------------*/ -/*ARGSUSED*/ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) static void yydestruct (const char *yymsg, int yytype, YYSTYPE *yyvaluep) -#else -static void -yydestruct (yymsg, yytype, yyvaluep) - const char *yymsg; - int yytype; - YYSTYPE *yyvaluep; -#endif { YYUSE (yyvaluep); - if (!yymsg) yymsg = "Deleting"; YY_SYMBOL_PRINT (yymsg, yytype, yyvaluep, yylocationp); - switch (yytype) - { - - default: - break; - } + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN + YYUSE (yytype); + YY_IGNORE_MAYBE_UNINITIALIZED_END } -/* Prevent warnings from -Wmissing-prototypes. */ -#ifdef YYPARSE_PARAM -#if defined __STDC__ || defined __cplusplus -int yyparse (void *YYPARSE_PARAM); -#else -int yyparse (); -#endif -#else /* ! YYPARSE_PARAM */ -#if defined __STDC__ || defined __cplusplus -int yyparse (void); -#else -int yyparse (); -#endif -#endif /* ! YYPARSE_PARAM */ /* The lookahead symbol. */ @@ -1149,7 +1036,6 @@ int yychar; /* The semantic value of the lookahead symbol. */ YYSTYPE yylval; - /* Number of syntax errors so far. */ int yynerrs; @@ -1158,37 +1044,18 @@ int yynerrs; | yyparse. | `----------*/ -#ifdef YYPARSE_PARAM -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) -int -yyparse (void *YYPARSE_PARAM) -#else -int -yyparse (YYPARSE_PARAM) - void *YYPARSE_PARAM; -#endif -#else /* ! YYPARSE_PARAM */ -#if (defined __STDC__ || defined __C99__FUNC__ \ - || defined __cplusplus || defined _MSC_VER) int yyparse (void) -#else -int -yyparse () - -#endif -#endif { int yystate; /* Number of tokens to shift before error messages enabled. */ int yyerrstatus; /* The stacks and their tools: - `yyss': related to states. - `yyvs': related to semantic values. + 'yyss': related to states. + 'yyvs': related to semantic values. - Refer to the stacks thru separate pointers, to allow yyoverflow + Refer to the stacks through separate pointers, to allow yyoverflow to reallocate them elsewhere. */ /* The state stack. */ @@ -1206,7 +1073,7 @@ yyparse () int yyn; int yyresult; /* Lookahead token as an internal (translated) token number. */ - int yytoken; + int yytoken = 0; /* The variables used to return semantic value and location from the action routines. */ YYSTYPE yyval; @@ -1224,9 +1091,8 @@ yyparse () Keep to zero when no symbol should be popped. */ int yylen = 0; - yytoken = 0; - yyss = yyssa; - yyvs = yyvsa; + yyssp = yyss = yyssa; + yyvsp = yyvs = yyvsa; yystacksize = YYINITDEPTH; YYDPRINTF ((stderr, "Starting parse\n")); @@ -1235,14 +1101,6 @@ yyparse () yyerrstatus = 0; yynerrs = 0; yychar = YYEMPTY; /* Cause a token to be read. */ - - /* Initialize stack pointers. - Waste one element of value and location stack - so that they stay on the same level as the state stack. - The wasted elements are never initialized. */ - yyssp = yyss; - yyvsp = yyvs; - goto yysetstate; /*------------------------------------------------------------. @@ -1263,23 +1121,23 @@ yyparse () #ifdef yyoverflow { - /* Give user a chance to reallocate the stack. Use copies of - these so that the &'s don't force the real ones into - memory. */ - YYSTYPE *yyvs1 = yyvs; - yytype_int16 *yyss1 = yyss; - - /* Each stack pointer address is followed by the size of the - data in use in that stack, in bytes. This used to be a - conditional around just the two extra args, but that might - be undefined if yyoverflow is a macro. */ - yyoverflow (YY_("memory exhausted"), - &yyss1, yysize * sizeof (*yyssp), - &yyvs1, yysize * sizeof (*yyvsp), - &yystacksize); - - yyss = yyss1; - yyvs = yyvs1; + /* Give user a chance to reallocate the stack. Use copies of + these so that the &'s don't force the real ones into + memory. */ + YYSTYPE *yyvs1 = yyvs; + yytype_int16 *yyss1 = yyss; + + /* Each stack pointer address is followed by the size of the + data in use in that stack, in bytes. This used to be a + conditional around just the two extra args, but that might + be undefined if yyoverflow is a macro. */ + yyoverflow (YY_("memory exhausted"), + &yyss1, yysize * sizeof (*yyssp), + &yyvs1, yysize * sizeof (*yyvsp), + &yystacksize); + + yyss = yyss1; + yyvs = yyvs1; } #else /* no yyoverflow */ # ifndef YYSTACK_RELOCATE @@ -1287,22 +1145,22 @@ yyparse () # else /* Extend the stack our own way. */ if (YYMAXDEPTH <= yystacksize) - goto yyexhaustedlab; + goto yyexhaustedlab; yystacksize *= 2; if (YYMAXDEPTH < yystacksize) - yystacksize = YYMAXDEPTH; + yystacksize = YYMAXDEPTH; { - yytype_int16 *yyss1 = yyss; - union yyalloc *yyptr = - (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); - if (! yyptr) - goto yyexhaustedlab; - YYSTACK_RELOCATE (yyss_alloc, yyss); - YYSTACK_RELOCATE (yyvs_alloc, yyvs); + yytype_int16 *yyss1 = yyss; + union yyalloc *yyptr = + (union yyalloc *) YYSTACK_ALLOC (YYSTACK_BYTES (yystacksize)); + if (! yyptr) + goto yyexhaustedlab; + YYSTACK_RELOCATE (yyss_alloc, yyss); + YYSTACK_RELOCATE (yyvs_alloc, yyvs); # undef YYSTACK_RELOCATE - if (yyss1 != yyssa) - YYSTACK_FREE (yyss1); + if (yyss1 != yyssa) + YYSTACK_FREE (yyss1); } # endif #endif /* no yyoverflow */ @@ -1311,10 +1169,10 @@ yyparse () yyvsp = yyvs + yysize - 1; YYDPRINTF ((stderr, "Stack size increased to %lu\n", - (unsigned long int) yystacksize)); + (unsigned long int) yystacksize)); if (yyss + yystacksize - 1 <= yyssp) - YYABORT; + YYABORT; } YYDPRINTF ((stderr, "Entering state %d\n", yystate)); @@ -1343,7 +1201,7 @@ yybackup: if (yychar == YYEMPTY) { YYDPRINTF ((stderr, "Reading a token: ")); - yychar = YYLEX; + yychar = yylex (); } if (yychar <= YYEOF) @@ -1383,7 +1241,9 @@ yybackup: yychar = YYEMPTY; yystate = yyn; + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN *++yyvsp = yylval; + YY_IGNORE_MAYBE_UNINITIALIZED_END goto yynewstate; @@ -1406,7 +1266,7 @@ yyreduce: yylen = yyr2[yyn]; /* If YYLEN is nonzero, implement the default value of the action: - `$$ = $1'. + '$$ = $1'. Otherwise, the following line sets YYVAL to garbage. This behavior is undocumented and Bison @@ -1419,75 +1279,118 @@ yyreduce: YY_REDUCE_PRINT (yyn); switch (yyn) { - case 2: + case 4: + + { cur_parent = cur_bus = head; } + + break; + + case 5: + + { postprocess_devtree(); } + + break; + + case 6: { cur_parent = cur_bus = head; } + break; - case 3: + case 7: { postprocess_devtree(); } + + break; + + case 8: + + { + (yyval.device) = new_dummy_chip(cur_parent, cur_bus); + cur_parent = (yyval.device); + +} + + break; + + case 9: + + { + cur_parent = (yyvsp[-1].device)->parent; + fold_in((yyvsp[-1].device)); + add_header((yyvsp[-1].device)); +} + break; - case 14: + case 22: { - (yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[(2) - (2)].string)); + (yyval.device) = new_chip(cur_parent, cur_bus, (yyvsp[0].string)); cur_parent = (yyval.device); } + break; - case 15: + case 23: { - cur_parent = (yyvsp[(3) - (5)].device)->parent; - fold_in((yyvsp[(3) - (5)].device)); - add_header((yyvsp[(3) - (5)].device)); + cur_parent = (yyvsp[-2].device)->parent; + fold_in((yyvsp[-2].device)); + add_header((yyvsp[-2].device)); } + break; - case 16: + case 24: { - (yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[(2) - (4)].number), (yyvsp[(3) - (4)].string), (yyvsp[(4) - (4)].number)); + (yyval.device) = new_device(cur_parent, cur_bus, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.device); cur_bus = (yyval.device); } + break; - case 17: + case 25: { - cur_parent = (yyvsp[(5) - (7)].device)->parent; - cur_bus = (yyvsp[(5) - (7)].device)->bus; - fold_in((yyvsp[(5) - (7)].device)); - alias_siblings((yyvsp[(5) - (7)].device)->children); + cur_parent = (yyvsp[-2].device)->parent; + cur_bus = (yyvsp[-2].device)->bus; + fold_in((yyvsp[-2].device)); + alias_siblings((yyvsp[-2].device)->children); } + break; - case 18: + case 26: + + { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } - { add_resource(cur_parent, (yyvsp[(1) - (4)].number), strtol((yyvsp[(2) - (4)].string), NULL, 0), strtol((yyvsp[(4) - (4)].string), NULL, 0)); } break; - case 19: + case 27: + + { add_register(cur_parent, (yyvsp[-2].string), (yyvsp[0].string)); } - { add_register(cur_parent, (yyvsp[(2) - (4)].string), (yyvsp[(4) - (4)].string)); } break; - case 20: + case 28: + + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (3)].string), NULL, 16), strtol((yyvsp[(3) - (3)].string), NULL, 16), 0); } break; - case 21: + case 29: + + { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } - { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), strtol((yyvsp[(3) - (4)].string), NULL, 16), 1); } break; - case 22: + case 30: + + { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } - { add_ioapic_info(cur_parent, strtol((yyvsp[(2) - (4)].string), NULL, 16), (yyvsp[(3) - (4)].string), strtol((yyvsp[(4) - (4)].string), NULL, 16)); } break; @@ -1513,7 +1416,7 @@ yyreduce: *++yyvsp = yyval; - /* Now `shift' the result of the reduction. Determine what state + /* Now 'shift' the result of the reduction. Determine what state that goes to, based on the state we popped back to and the rule number reduced by. */ @@ -1528,9 +1431,9 @@ yyreduce: goto yynewstate; -/*------------------------------------. -| yyerrlab -- here on detecting error | -`------------------------------------*/ +/*--------------------------------------. +| yyerrlab -- here on detecting error. | +`--------------------------------------*/ yyerrlab: /* Make sure we have latest lookahead translation. See comments at user semantic actions for why this is necessary. */ @@ -1581,20 +1484,20 @@ yyerrlab: if (yyerrstatus == 3) { /* If just tried and failed to reuse lookahead token after an - error, discard it. */ + error, discard it. */ if (yychar <= YYEOF) - { - /* Return failure if at end of input. */ - if (yychar == YYEOF) - YYABORT; - } + { + /* Return failure if at end of input. */ + if (yychar == YYEOF) + YYABORT; + } else - { - yydestruct ("Error: discarding", - yytoken, &yylval); - yychar = YYEMPTY; - } + { + yydestruct ("Error: discarding", + yytoken, &yylval); + yychar = YYEMPTY; + } } /* Else will try to reuse lookahead token after shifting the error @@ -1613,7 +1516,7 @@ yyerrorlab: if (/*CONSTCOND*/ 0) goto yyerrorlab; - /* Do not reclaim the symbols of the rule which action triggered + /* Do not reclaim the symbols of the rule whose action triggered this YYERROR. */ YYPOPSTACK (yylen); yylen = 0; @@ -1626,35 +1529,37 @@ yyerrorlab: | yyerrlab1 -- common code for both syntax error and YYERROR. | `-------------------------------------------------------------*/ yyerrlab1: - yyerrstatus = 3; /* Each real token shifted decrements this. */ + yyerrstatus = 3; /* Each real token shifted decrements this. */ for (;;) { yyn = yypact[yystate]; if (!yypact_value_is_default (yyn)) - { - yyn += YYTERROR; - if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) - { - yyn = yytable[yyn]; - if (0 < yyn) - break; - } - } + { + yyn += YYTERROR; + if (0 <= yyn && yyn <= YYLAST && yycheck[yyn] == YYTERROR) + { + yyn = yytable[yyn]; + if (0 < yyn) + break; + } + } /* Pop the current state because it cannot handle the error token. */ if (yyssp == yyss) - YYABORT; + YYABORT; yydestruct ("Error: popping", - yystos[yystate], yyvsp); + yystos[yystate], yyvsp); YYPOPSTACK (1); yystate = *yyssp; YY_STACK_PRINT (yyss, yyssp); } + YY_IGNORE_MAYBE_UNINITIALIZED_BEGIN *++yyvsp = yylval; + YY_IGNORE_MAYBE_UNINITIALIZED_END /* Shift the error token. */ @@ -1678,7 +1583,7 @@ yyabortlab: yyresult = 1; goto yyreturn; -#if !defined(yyoverflow) || YYERROR_VERBOSE +#if !defined yyoverflow || YYERROR_VERBOSE /*-------------------------------------------------. | yyexhaustedlab -- memory exhaustion comes here. | `-------------------------------------------------*/ @@ -1697,14 +1602,14 @@ yyreturn: yydestruct ("Cleanup: discarding lookahead", yytoken, &yylval); } - /* Do not reclaim the symbols of the rule which action triggered + /* Do not reclaim the symbols of the rule whose action triggered this YYABORT or YYACCEPT. */ YYPOPSTACK (yylen); YY_STACK_PRINT (yyss, yyssp); while (yyssp != yyss) { yydestruct ("Cleanup: popping", - yystos[*yyssp], yyvsp); + yystos[*yyssp], yyvsp); YYPOPSTACK (1); } #ifndef yyoverflow @@ -1715,6 +1620,7 @@ yyreturn: if (yymsg != yymsgbuf) YYSTACK_FREE (yymsg); #endif - /* Make sure YYID is used. */ - return YYID (yyresult); + return yyresult; } + + diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 150906e..092e971 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,19 +1,19 @@ -/* A Bison parser, made by GNU Bison 2.5. */ +/* A Bison parser, made by GNU Bison 3.0.2. */ /* Bison interface for Yacc-like parsers in C - - Copyright (C) 1984, 1989-1990, 2000-2011 Free Software Foundation, Inc. - + + Copyright (C) 1984, 1989-1990, 2000-2013 Free Software Foundation, Inc. + This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or (at your option) any later version. - + This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. - + You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>. */ @@ -26,50 +26,58 @@ special exception, which will cause the skeleton and the resulting Bison output files to be licensed under the GNU General Public License without this special exception. - + This special exception was added by the Free Software Foundation in version 2.2 of Bison. */ +#ifndef YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +/* Debug traces. */ +#ifndef YYDEBUG +# define YYDEBUG 0 +#endif +#if YYDEBUG +extern int yydebug; +#endif -/* Tokens. */ +/* Token type. */ #ifndef YYTOKENTYPE # define YYTOKENTYPE - /* Put the tokens into the symbol table, so that GDB and other debuggers - know about them. */ - enum yytokentype { - CHIP = 258, - DEVICE = 259, - REGISTER = 260, - BOOL = 261, - BUS = 262, - RESOURCE = 263, - END = 264, - EQUALS = 265, - HEX = 266, - STRING = 267, - PCI = 268, - PNP = 269, - I2C = 270, - APIC = 271, - CPU_CLUSTER = 272, - CPU = 273, - DOMAIN = 274, - IRQ = 275, - DRQ = 276, - IO = 277, - NUMBER = 278, - SUBSYSTEMID = 279, - INHERIT = 280, - IOAPIC_IRQ = 281, - IOAPIC = 282, - PCIINT = 283 - }; + enum yytokentype + { + CHIP = 258, + DEVICE = 259, + REGISTER = 260, + BOOL = 261, + BUS = 262, + RESOURCE = 263, + END = 264, + EQUALS = 265, + HEX = 266, + STRING = 267, + PCI = 268, + PNP = 269, + I2C = 270, + APIC = 271, + CPU_CLUSTER = 272, + CPU = 273, + DOMAIN = 274, + IRQ = 275, + DRQ = 276, + IO = 277, + NUMBER = 278, + SUBSYSTEMID = 279, + INHERIT = 280, + IOAPIC_IRQ = 281, + IOAPIC = 282, + PCIINT = 283 + }; #endif - - +/* Value type. */ #if ! defined YYSTYPE && ! defined YYSTYPE_IS_DECLARED -typedef union YYSTYPE +typedef union YYSTYPE YYSTYPE; +union YYSTYPE { @@ -78,11 +86,14 @@ typedef union YYSTYPE int number; - -} YYSTYPE; +}; # define YYSTYPE_IS_TRIVIAL 1 -# define yystype YYSTYPE /* obsolescent; will be withdrawn */ # define YYSTYPE_IS_DECLARED 1 #endif + extern YYSTYPE yylval; + +int yyparse (void); + +#endif /* !YY_YY_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 66c5b6d..b0493e8 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -28,7 +28,22 @@ static struct device *cur_parent, *cur_bus; %token CHIP DEVICE REGISTER BOOL BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT %% -devtree: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; +devtree: devtree_chip | devtree_devs ; +devtree_chip: { cur_parent = cur_bus = head; } chip { postprocess_devtree(); } ; +devtree_devs: { cur_parent = cur_bus = head; } top_level_devices { postprocess_devtree(); } ; + +top_level_devices: { + $<device>$ = new_dummy_chip(cur_parent, cur_bus); + cur_parent = $<device>$; + +} + devices { + cur_parent = $<device>1->parent; + fold_in($<device>1); + add_header($<device>1); +}; + +devices: devices device | /* empty */ ; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ;

1 0

New patch to review for coreboot: 3rdparty/blobs: Update for latest Carrizo Blobs
by Martin Roth 12 Nov '15

12 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12425 -gerrit commit 6c5a0f536ef0c64a953733908dce4a6312f40d7f Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:44:49 2015 -0700 3rdparty/blobs: Update for latest Carrizo Blobs Update the 3rdparty/blobs submodule to bring in the latest CarrizoPI binaries. Change-Id: I65769ebe7b2aa6508d0d6ab2df34a092751e1078 Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/blobs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index aab093f..b0eeddd 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit aab093f0824b6d26b57a1ce220ba0d577e37ad49 +Subproject commit b0eeddd4f5c583818e66521f2552cd3448b357b2

1 0

Patch merged into coreboot/master: AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 2603812c8709f03e8df6dd2425f5f743291666b9 Author: zbao <fishbaozi(a)gmail.com> Date: Sat Nov 7 01:12:20 2015 +0800 AMD Merlin Falcon: update vendorcode header files to CarrizoPI 1.1.0.1 1. This is required the BLOB change Ie86bb0cf AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5) 2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the boards can boot to Windows 10. PCIe slots, USB and NIC work. Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07 Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com> Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com> Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: http://review.coreboot.org/11752 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11752 for details. -gerrit

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12010 -gerrit commit 6ba3ee80474ef67d47a5cde3687c6b9beb463c7a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 14:15:57 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Add missing Family 15h RDIMM Rtt values The existing code did not set Rtt timing parameters when registered DIMMs were used with Family 15h processors. Set the Rtt values according to the BKDG recommendations. Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 4 +- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 201 ++++++++++++++++++++++++++- 2 files changed, 198 insertions(+), 7 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 033f07b..c3c3976 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -903,8 +903,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT } } else if (MaxDimmsInstallable == 3) { /* TODO - * 3 DIMM/channel support unimplemented - */ + * 3 DIMM/channel support unimplemented + */ } } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { /* LRDIMM */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 3b53b11..3300716 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -38,6 +38,10 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d uint8_t frequency_index; uint8_t rank_count = pDCTstat->DimmRanks[(dimm * 2) + dct]; + uint8_t rank_count_dimm0; + uint8_t rank_count_dimm1; + uint8_t rank_count_dimm2; + if (is_fam15h()) frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; else @@ -50,11 +54,80 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d uint8_t MaxDimmsInstallable = 2; if (is_fam15h()) { - if (pDCTstat->Status & (1 << SB_Registered)) { + if (pDCTstat->Status & (1 << SB_LoadReduced)) { /* TODO - * RDIMM unimplemented + * LRDIMM unimplemented */ + } else if (pDCTstat->Status & (1 << SB_Registered)) { + /* RDIMM */ + if (package_type == PT_GR) { + /* Socket G34: Fam15h BKDG v3.14 Table 57 */ + if (MaxDimmsInstallable == 1) { + if ((frequency_index == 0x4) || (frequency_index == 0x6) + || (frequency_index == 0xa) || (frequency_index == 0xe)) { + /* DDR3-667 - DDR3-1333 */ + if (rank_count < 3) + term = 0x0; + else + term = 0x2; + } else { + /* DDR3-1600 */ + term = 0x0; + } + } else if (MaxDimmsInstallable == 2) { + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((frequency_index == 0x4) || (frequency_index == 0x6)) { + /* DDR3-667 - DDR3-800 */ + if ((number_of_dimms == 1) && ((rank_count_dimm0 < 4) + && (rank_count_dimm1 < 4))) + term = 0x0; + else + term = 0x2; + } else if (frequency_index == 0xa) { + /* DDR3-1066 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x0; + else + term = 0x2; + } else { + term = 0x1; + } + } else if (frequency_index == 0xe) { + /* DDR3-1333 */ + term = 0x2; + } else { + /* DDR3-1600 */ + if (number_of_dimms == 1) + term = 0x0; + else + term = 0x1; + } + } else if (MaxDimmsInstallable == 3) { + rank_count_dimm2 = pDCTstat->DimmRanks[(2 * 2) + dct]; + + if ((frequency_index == 0xa) || (frequency_index == 0xe)) { + /* DDR3-1066 - DDR3-1333 */ + if (rank_count_dimm2 < 4) + term = 0x1; + else + term = 0x2; + } else if (frequency_index == 0x12) { + /* DDR3-1600 */ + term = 0x1; + } else { + term = 0x2; + } + } + } else { + /* TODO + * Other sockets unimplemented + */ + } } else { + /* UDIMM */ if (package_type == PT_GR) { /* Socket G34: Fam15h BKDG v3.14 Table 56 */ if (MaxDimmsInstallable == 1) { @@ -99,6 +172,9 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; uint8_t frequency_index; + uint8_t rank_count_dimm0; + uint8_t rank_count_dimm1; + if (is_fam15h()) frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; else @@ -116,10 +192,125 @@ static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t * LRDIMM unimplemented */ } else if (pDCTstat->Status & (1 << SB_Registered)) { - /* TODO - * RDIMM unimplemented - */ + /* RDIMM */ + if (package_type == PT_GR) { + /* Socket G34: Fam15h BKDG v3.14 Table 57 */ + if (MaxDimmsInstallable == 1) { + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + + if ((frequency_index == 0x4) || (frequency_index == 0x6)) { + /* DDR3-667 - DDR3-800 */ + if (rank_count_dimm0 < 4) { + term = 0x2; + } else { + if (!rank) + term = 0x2; + else + term = 0x0; + } + } else if (frequency_index == 0xa) { + /* DDR3-1066 */ + term = 0x1; + } else if (frequency_index == 0xe) { + /* DDR3-1333 */ + if (rank_count_dimm0 < 4) { + term = 0x1; + } else { + if (!rank) + term = 0x3; + else + term = 0x0; + } + } else { + term = 0x3; + } + } else if (MaxDimmsInstallable == 2) { + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; + + if ((frequency_index == 0x4) || (frequency_index == 0x6)) { + /* DDR3-667 - DDR3-800 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x2; + else if (rank) + term = 0x0; + else + term = 0x2; + } else { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { + term = 0x3; + } else { + if (rank_count_dimm0 == 4) { + if (rank_count_dimm1 == 1) + term = 0x5; + else + term = 0x1; + } else if (rank_count_dimm1 == 4) { + if (rank_count_dimm0 == 1) + term = 0x5; + else + term = 0x1; + } + if (rank) + term = 0x0; + } + } + } else if (frequency_index == 0xa) { + /* DDR3-1066 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x1; + else if (rank) + term = 0x0; + else + term = 0x1; + } else { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { + term = 0x3; + } else { + if (rank_count_dimm0 == 4) { + if (rank_count_dimm1 == 1) + term = 0x5; + else + term = 0x1; + } else if (rank_count_dimm1 == 4) { + if (rank_count_dimm0 == 1) + term = 0x5; + else + term = 0x1; + } + if (rank) + term = 0x0; + } + } + } else if (frequency_index == 0xe) { + /* DDR3-1333 */ + if (number_of_dimms == 1) { + if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) + term = 0x1; + else if (rank) + term = 0x0; + else + term = 0x3; + } else { + term = 0x5; + } + } else { + /* DDR3-1600 */ + if (number_of_dimms == 1) + term = 0x3; + else + term = 0x4; + } + } else if (MaxDimmsInstallable == 3) { + /* TODO + * 3 DIMM/channel support unimplemented + */ + } + } } else { + /* UDIMM */ if (package_type == PT_GR) { /* Socket G34: Fam15h BKDG v3.14 Table 56 */ if (MaxDimmsInstallable == 1) {

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in use
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12011 -gerrit commit 0050433c066d04a623a81518e85ebdf3fed69cef Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 17:49:25 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Set SkewMemClk when both DCTs are in use When both DCTs of a node are in use the DRAM clocks should be skewed with respect to one another in order to reduce cross-channel interference. Set the clock skew bit according to the BKDG recommendations. Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 41 +++++++++++++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 2 +- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index c3c3976..e7fee19 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2653,7 +2653,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC /* Reset DCT registers */ ClearDCT_D(pMCTstat, pDCTstat, dct); - pDCTstat->stopDCT = 1; /*preload flag with 'disable' */ + pDCTstat->stopDCT[dct] = 1; /* preload flag with 'disable' */ if (!is_fam15h()) { /* Enable DDR3 support */ @@ -2664,7 +2664,7 @@ static void DCTPreInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDC /* Read the SPD information into the data structures */ if (mct_DIMMPresence(pMCTstat, pDCTstat, dct) < SC_StopError) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: mct_DIMMPresence Done\n"); + printk(BIOS_DEBUG, "\t\tDCTPreInit_D: mct_DIMMPresence Done\n"); } } @@ -2690,17 +2690,40 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst printk(BIOS_DEBUG, "\t\tDCTInit_D: AutoConfig_D Done\n"); if (PlatformSpec_D(pMCTstat, pDCTstat, dct) < SC_StopError) { printk(BIOS_DEBUG, "\t\tDCTInit_D: PlatformSpec_D Done\n"); - pDCTstat->stopDCT = 0; - if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { - printk(BIOS_DEBUG, "\t\tDCTInit_D: StartupDCT_D\n"); - StartupDCT_D(pMCTstat, pDCTstat, dct); /*yeaahhh! */ - } + pDCTstat->stopDCT[dct] = 0; } } } } - if (pDCTstat->stopDCT) { + +} + +static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) +{ + uint32_t dword; + + /* Finalize DRAM init on a single node */ + if (is_fam15h()) { + /* Set memory clock skew if needed */ + if (dct == 0) { + if (!pDCTstat->stopDCT[0] && !pDCTstat->stopDCT[1]) { + dword = Get_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a); + dword |= (0x1 << 4); /* SkewMemClk = 1 */ + Set_NB32_index_wait_DCT(pDCTstat->dev_dct, dct, 0x98, 0x0d0fe00a, dword); + } + } + } + + if (!pDCTstat->stopDCT[dct]) { + if (!(pMCTstat->GStatus & (1 << GSB_EnDIMMSpareNW))) { + printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Start\n"); + StartupDCT_D(pMCTstat, pDCTstat, dct); + printk(BIOS_DEBUG, "\t\tDCTFinalInit_D: StartupDCT_D Done\n"); + } + } + + if (pDCTstat->stopDCT[dct]) { dword = 1 << DisDramInterface; Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x94, dword); @@ -4358,6 +4381,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, /* Config. DCT0 for Ganged or unganged mode */ DCTInit_D(pMCTstat, pDCTstat, 0); + DCTFinalInit_D(pMCTstat, pDCTstat, 0); if (pDCTstat->ErrCode == SC_FatalErr) { /* Do nothing goto exitDCTInit; any fatal errors? */ } else { @@ -4367,6 +4391,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat, err_code = pDCTstat->ErrCode; /* save DCT0 errors */ pDCTstat->ErrCode = 0; DCTInit_D(pMCTstat, pDCTstat, 1); + DCTFinalInit_D(pMCTstat, pDCTstat, 1); if (pDCTstat->ErrCode == 2) /* DCT1 is not Running */ pDCTstat->ErrCode = err_code; /* Using DCT0 Error code to update pDCTstat.ErrCode */ } else { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index 8b8caca..b6256fa 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -334,7 +334,7 @@ struct DCTStatStruc { /* A per Node structure*/ u8 Node_ID; /* Node ID of current controller */ uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ - uint8_t stopDCT; /* Set if the DCT will be stopped */ + uint8_t stopDCT[2]; /* Set if the DCT will be stopped */ u8 ErrCode; /* Current error condition of Node 0= no error 1= Variance Error, DCT is running but not in an optimal configuration.

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12008 -gerrit commit a6e8650b1f18e9671c23cc973eb790a153db01ab Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 00:17:10 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Add additional debug trace statements Change-Id: Iacd789b3572dc8ee85e76d56c46685e6df31d1a6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 8 ++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 16 ++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index fa32901..9593d71 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5825,7 +5825,11 @@ static void mct_ResetDataStruct_D(struct MCTStatStruc *pMCTstat, static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { + printk(BIOS_DEBUG, "%s: Start\n", __func__); + mct_ProgramODT_D(pMCTstat, pDCTstat, dct); + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, @@ -5835,6 +5839,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, u32 dword; u32 dev = pDCTstat->dev_dct; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + /* FIXME * Mainboards need to be able to specify the maximum number of DIMMs installable per channel * For now assume a maximum of 2 DIMMs per channel can be installed @@ -6149,6 +6155,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, Set_NB32_index_wait_DCT(dev, i, 0xf0, 0x183, odt_pattern_2); } } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static void mct_EnDllShutdownSR(struct MCTStatStruc *pMCTstat, diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 46a0684..09f86ea 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -188,9 +188,13 @@ static void mct_DCTAccessDone(struct DCTStatStruc *pDCTstat, u8 dct) u32 dev = pDCTstat->dev_dct; u32 val; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + do { val = Get_NB32_DCT(dev, dct, 0x98); } while (!(val & (1 << DctAccessDone))); + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static u32 swapAddrBits(struct DCTStatStruc *pDCTstat, u32 MR_register_setting, u8 MrsChipSel, u8 dct) @@ -235,6 +239,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS) u32 dev = pDCTstat->dev_dct; u32 val; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + val = Get_NB32_DCT(dev, dct, 0x7c); val &= ~0x00ffffff; val |= EMRS; @@ -244,6 +250,8 @@ static void mct_SendMrsCmd(struct DCTStatStruc *pDCTstat, u8 dct, u32 EMRS) do { val = Get_NB32_DCT(dev, dct, 0x7c); } while (val & (1 << SendMrsCmd)); + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } static u32 mct_MR2(struct MCTStatStruc *pMCTstat, @@ -553,6 +561,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) u32 dev = pDCTstat->dev_dct; u32 dword; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + /*1.Program MrsAddress[10]=1 2.Set SendZQCmd=1 */ @@ -569,6 +579,8 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct) /* 4.Wait 512 MEMCLKs */ mct_Wait(300); + + printk(BIOS_DEBUG, "%s: Done\n", __func__); } void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, @@ -578,6 +590,8 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, u32 dword; u32 dev = pDCTstat->dev_dct; + printk(BIOS_DEBUG, "%s: Start\n", __func__); + if (pDCTstat->DIMMAutoSpeed == mhz_to_memclk_config(mctGet_NVbits(NV_MIN_MEMCLK))) { /* 3.Program F2x[1,0]7C[EnDramInit]=1 */ dword = Get_NB32_DCT(dev, dct, 0x7c); @@ -659,4 +673,6 @@ void mct_DramInit_Sw_D(struct MCTStatStruc *pMCTstat, Set_NB32_DCT(dev, dct, 0x7C, dword); mct_DCTAccessDone(pDCTstat, dct); } + + printk(BIOS_DEBUG, "%s: Done\n", __func__); }

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12009 -gerrit commit 0648a834594ba1a97489c45269f9732d3a28bbd1 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Jun 26 12:17:48 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Fix null pointer access and related hangs Change-Id: Iaf826b6a0c8e929372519f6d97933515a80f0b39 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 58 +++++++++++++++------------- src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 8 ++-- 2 files changed, 34 insertions(+), 32 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 9593d71..033f07b 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -832,7 +832,7 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT /* RDIMM */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 74 */ if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (MemClkFreq == 0x4) { /* DDR3-667 */ @@ -856,8 +856,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT calibration_code |= 0x22 << 16; } } else if (MaxDimmsInstallable == 2) { - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (dimm_count == 1) { /* 1 DIMM detected */ @@ -881,8 +881,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT } } else if (dimm_count == 2) { /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (MemClkFreq == 0x4) { /* DDR3-667 */ @@ -949,8 +949,8 @@ static uint32_t fam15h_output_driver_compensation_code(struct DCTStatStruc *pDCT } } else if (dimm_count == 2) { /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (MemClkFreq == 0x4) { /* DDR3-667 */ @@ -1071,7 +1071,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC /* UDIMM */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (MemClkFreq == 0x4) { /* DDR3-667 */ @@ -1104,7 +1104,7 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC } else if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (MemClkFreq == 0x4) { /* DDR3-667 */ @@ -1133,8 +1133,8 @@ static uint32_t fam15h_address_timing_compensation_code(struct DCTStatStruc *pDC } } else if (dimm_count == 2) { /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (MemClkFreq == 0x4) { /* DDR3-667 */ @@ -1202,7 +1202,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc /* UDIMM */ /* Fam15h BKDG Rev. 3.14 section 2.10.5.3.4 Table 73 */ if (MaxDimmsInstallable == 1) { - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { @@ -1218,7 +1218,7 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc } else if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(1 * 2) + dct]; if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) || (MemClkFreq == 0xa) | (MemClkFreq == 0xe)) { @@ -1233,8 +1233,8 @@ static uint8_t fam15h_slow_access_mode(struct DCTStatStruc *pDCTstat, uint8_t dc } } else if (dimm_count == 2) { /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if ((MemClkFreq == 0x4) || (MemClkFreq == 0x6) || (MemClkFreq == 0xa)) { @@ -5861,14 +5861,18 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, uint8_t write_odt_delay; uint8_t read_odt_delay; + /* NOTE + * Rank count per DIMM and DCT is encoded by pDCTstat->DimmRanks[(<dimm number> * 2) + dct] + */ + /* Select appropriate ODT pattern for installed DIMMs * Refer to the Fam15h BKDG Rev. 3.14, page 149 onwards */ - if (pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_REGISTERED]) { + if (pDCTstat->Status & (1 << SB_Registered)) { if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; @@ -5893,8 +5897,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, } } else { /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[dct]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + dct]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x01010202; @@ -5932,7 +5936,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, odt_pattern_2 = 0x00000000; odt_pattern_3 = 0x00000000; } - } else if (pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_LOAD_REDUCED]) { + } else if (pDCTstat->Status & (1 << SB_LoadReduced)) { /* TODO * Load reduced dimms UNIMPLEMENTED */ @@ -5944,7 +5948,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->C_DCTPtr[dct]->DimmRanks[1]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + dct]; if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; @@ -5980,7 +5984,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, } } - if (pDCTstat->C_DCTPtr[dct]->Status[DCT_STATUS_LOAD_REDUCED]) { + if (pDCTstat->Status & (1 << SB_LoadReduced)) { /* TODO * Load reduced dimms UNIMPLEMENTED */ @@ -6040,11 +6044,11 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, /* Select appropriate ODT pattern for installed DIMMs * Refer to the Fam10h BKDG Rev. 3.62, page 120 onwards */ - if (pDCTstat->C_DCTPtr[i]->Status[DCT_STATUS_REGISTERED]) { + if (pDCTstat->Status & (1 << SB_Registered)) { if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->C_DCTPtr[i]->DimmRanks[1]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + i]; if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; @@ -6069,8 +6073,8 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, } } else { /* 2 DIMMs detected */ - rank_count_dimm0 = pDCTstat->C_DCTPtr[i]->DimmRanks[0]; - rank_count_dimm1 = pDCTstat->C_DCTPtr[i]->DimmRanks[1]; + rank_count_dimm0 = pDCTstat->DimmRanks[(0 * 2) + i]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + i]; if ((rank_count_dimm0 < 4) && (rank_count_dimm1 < 4)) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x01010202; @@ -6112,7 +6116,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat, if (MaxDimmsInstallable == 2) { if (dimm_count == 1) { /* 1 DIMM detected */ - rank_count_dimm1 = pDCTstat->C_DCTPtr[i]->DimmRanks[1]; + rank_count_dimm1 = pDCTstat->DimmRanks[(1 * 2) + i]; if (rank_count_dimm1 == 1) { odt_pattern_0 = 0x00000000; odt_pattern_1 = 0x00000000; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c index 09f86ea..3b53b11 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c @@ -34,10 +34,9 @@ static uint8_t fam15_dimm_dic(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) { uint8_t term = 0; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint8_t number_of_dimms = pDCTData->MaxDimmsInstalled; + uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; uint8_t frequency_index; - uint8_t rank_count = pDCTData->DimmRanks[dimm]; + uint8_t rank_count = pDCTstat->DimmRanks[(dimm * 2) + dct]; if (is_fam15h()) frequency_index = Get_NB32_DCT(pDCTstat->dev_dct, dct, 0x94) & 0x1f; @@ -97,8 +96,7 @@ static uint8_t fam15_rttwr(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t d static uint8_t fam15_rttnom(struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t rank, uint8_t package_type) { uint8_t term = 0; - sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; - uint8_t number_of_dimms = pDCTData->MaxDimmsInstalled; + uint8_t number_of_dimms = pDCTstat->MAdimms[dct]; uint8_t frequency_index; if (is_fam15h())

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12006 -gerrit commit a72db4e9f33a0bfaeef8dcd7e2f2ac1969de4c30 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 18:08:53 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Attempt to recover from phy training errors AMD's automatic phy phase detection hardware is very fragile and often produces incorrect results. Attempt to recover from obvious phase locking errors by retrying phy training on the failing link. Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c | 68 +++++++++++++++++++++------ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 36 +++++++++++--- 2 files changed, 83 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c index 5107fee..b3572b1 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mcthwl.c @@ -14,11 +14,11 @@ * GNU General Public License for more details. */ -static void AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, +static uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -static void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, +static uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); -static void AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, +static uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass); static void EnableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); static void DisableZQcalibration(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -96,11 +96,12 @@ static void DisableAutoRefresh_D(struct MCTStatStruc *pMCTstat, } -static void PhyWLPass1(struct MCTStatStruc *pMCTstat, +static uint8_t PhyWLPass1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 dimm; u16 DIMMValid; + uint8_t status = 0; void *DCTPtr; dct &= 1; @@ -117,19 +118,22 @@ static void PhyWLPass1(struct MCTStatStruc *pMCTstat, PrepareC_DCT(pMCTstat, pDCTstat, dct); for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm ++) { if (DIMMValid & (1 << (dimm << 1))) { - AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, FirstPass); - AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, FirstPass); - AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, FirstPass); + status |= AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, FirstPass); + status |= AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, FirstPass); + status |= AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, FirstPass); } } } + + return status; } -static void PhyWLPass2(struct MCTStatStruc *pMCTstat, +static uint8_t PhyWLPass2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { u8 dimm; u16 DIMMValid; + uint8_t status = 0; void *DCTPtr; dct &= 1; @@ -159,12 +163,14 @@ static void PhyWLPass2(struct MCTStatStruc *pMCTstat, DisableAutoRefresh_D(pMCTstat, pDCTstat); for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm ++) { if (DIMMValid & (1 << (dimm << 1))) { - AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, SecondPass); - AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, SecondPass); - AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, SecondPass); + status |= AgesaHwWlPhase1(pMCTstat, pDCTstat, dct, dimm, SecondPass); + status |= AgesaHwWlPhase2(pMCTstat, pDCTstat, dct, dimm, SecondPass); + status |= AgesaHwWlPhase3(pMCTstat, pDCTstat, dct, dimm, SecondPass); } } } + + return status; } static uint16_t fam15h_next_highest_memclk_freq(uint16_t memclk_freq) @@ -179,6 +185,8 @@ static uint16_t fam15h_next_highest_memclk_freq(uint16_t memclk_freq) static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t Pass) { + uint8_t status; + uint8_t timeout; uint16_t final_target_freq; pDCTstat->C_MCTPtr = &(pDCTstat->s_C_MCTPtr); @@ -197,8 +205,21 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, } if (Pass == FirstPass) { - PhyWLPass1(pMCTstat, pDCTstat, 0); - PhyWLPass1(pMCTstat, pDCTstat, 1); + timeout = 0; + do { + status = 0; + timeout++; + status |= PhyWLPass1(pMCTstat, pDCTstat, 0); + status |= PhyWLPass1(pMCTstat, pDCTstat, 1); + if (status) + printk(BIOS_INFO, + "%s: Retrying write levelling due to invalid value(s) detected in first phase\n", + __func__); + } while (status && (timeout < 8)); + if (status) + printk(BIOS_INFO, + "%s: Uncorrectable invalid value(s) detected in first phase of write levelling\n", + __func__); } if (Pass == SecondPass) { @@ -207,6 +228,7 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, * NOTE: BIOS must program both DCTs to the same frequency. * NOTE: Fam15h steps the frequency, Fam10h slams the frequency. */ + uint8_t global_phy_training_status = 0; final_target_freq = pDCTstat->TargetFreq; while (pDCTstat->Speed != final_target_freq) { @@ -215,12 +237,28 @@ static void WriteLevelization_HW(struct MCTStatStruc *pMCTstat, else pDCTstat->TargetFreq = final_target_freq; SetTargetFreq(pMCTstat, pDCTstat); - PhyWLPass2(pMCTstat, pDCTstat, 0); - PhyWLPass2(pMCTstat, pDCTstat, 1); + timeout = 0; + do { + status = 0; + timeout++; + status |= PhyWLPass2(pMCTstat, pDCTstat, 0); + status |= PhyWLPass2(pMCTstat, pDCTstat, 1); + if (status) + printk(BIOS_INFO, + "%s: Retrying write levelling due to invalid value(s) detected in last phase\n", + __func__); + } while (status && (timeout < 8)); + global_phy_training_status |= status; } pDCTstat->TargetFreq = final_target_freq; + if (global_phy_training_status) + printk(BIOS_WARNING, + "%s: Uncorrectable invalid value(s) detected in second phase of write levelling; " + "continuing but system may be unstable!\n", + __func__); + uint8_t dct; for (dct = 0; dct < 2; dct++) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 48b72ca..496803e 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -50,7 +50,7 @@ static int32_t abs(int32_t val) { */ /*----------------------------------------------------------------------------- - * void AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, + * uint8_t AgesaHwWlPhase1(SPDStruct *SPDData,MCTStruct *MCTData, DCTStruct *DCTData, * u8 Dimm, u8 Pass) * * Description: @@ -67,7 +67,7 @@ static int32_t abs(int32_t val) { * OUT *----------------------------------------------------------------------------- */ -void AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, +uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass) { u8 ByteLane; @@ -170,12 +170,15 @@ void AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta } pDCTData->WLCriticalGrossDelayPrevPass = 0x1f; + + return 0; } -void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, +uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass) { u8 ByteLane; + uint8_t status = 0; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; if (is_fam15h()) { @@ -202,19 +205,38 @@ void AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta /* Compensate for occasional noise/instability causing sporadic training failure */ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + uint8_t faulty_value_detected = 0; uint16_t total_delay_seed = ((pDCTData->WLSeedGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLSeedFineDelay[index+ByteLane] & 0x1f); uint16_t total_delay_phy = ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f); - if (abs(total_delay_phy - total_delay_seed) > 0x20) { - printk(BIOS_DEBUG, "%s: overriding faulty phy value (seed: %04x phy: %04x step: %04x)\n", __func__, + if (pass == FirstPass) { + /* Allow a somewhat higher step threshold on the first pass + * For the most part, as long as the phy isn't stepping + * several clocks at once the values are probably valid. + */ + if (abs(total_delay_phy - total_delay_seed) > 0x30) + faulty_value_detected = 1; + } else { + /* Stepping memory clocks between adjacent allowed frequencies + * should not yield large phy value differences... + */ + + if (abs(total_delay_phy - total_delay_seed) > 0x20) + faulty_value_detected = 1; + } + if (faulty_value_detected) { + printk(BIOS_INFO, "%s: overriding faulty phy value (seed: %04x phy: %04x step: %04x)\n", __func__, total_delay_seed, total_delay_phy, abs(total_delay_phy - total_delay_seed)); pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; + status = 1; } } } + + return status; } -void AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, +uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, u8 pass) { u8 ByteLane; @@ -281,6 +303,8 @@ void AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTsta * to the normal operating termination: */ prepareDimms(pMCTstat, pDCTstat, dct, dimm, FALSE); + + return 0; } /*----------------------------------------------------------------------------

1 0

Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12007 -gerrit commit f3b9333f5c941ae5137790def10a725a26ebc108 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 18:37:45 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Work around strange phy training issue AMD Opteron processors contain a very fragile phy phase detection circuit. Additionally, the algorithm given in the BKDG does not function as intended; this was verified both on real hardware via execution trace and on paper with values read back from multiple CPUs and DIMMs. As a result, the phy training algorithm given in the BKDG has been replaced with a phy training algorithm developed at Raptor Engineering. This particular patch is the first part of that algorithm; the code is updated in future patches but this should exist in the historical record in case something breaks down in the later sections of code. Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 496803e..dfddb60 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -203,6 +203,22 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT pDCTData->WLCriticalGrossDelayPrevPass = cgd; + if (pDCTstat->Speed != pDCTstat->TargetFreq) { + /* FIXME + * Using the Pass 1 training values causes major phy training problems on + * all Family 15h processors I tested (Pass 1 values are randomly too high, + * and Pass 2 cannot lock). + * Figure out why this is and fix it, then remove the bypass code below... + */ + if (pass == FirstPass) { + for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; + pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; + } + return 0; + } + } + /* Compensate for occasional noise/instability causing sporadic training failure */ for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { uint8_t faulty_value_detected = 0;

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables
by Timothy Pearson 12 Nov '15

12 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12004 -gerrit commit b855319a7ad5d7a29a6cbc47ad79a7a895a69e8c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Jun 25 15:28:23 2015 -0500 northbridge/amd/amdfam10: Properly indicate node and channel in SMBIOS tables Change-Id: Ie7278745358daf0c78cdb9c579db5291a1a2a0cb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 7 ++++++- src/northbridge/amd/amdmct/mct/mct_d.c | 12 ++++++++++++ src/northbridge/amd/amdmct/mct/mct_d.h | 7 +++++-- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 12 ++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 8 +++++--- 5 files changed, 40 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 0c1971b..a922496 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1203,7 +1203,12 @@ static int amdfam10_get_smbios_data17(int* count, int handle, int parent_handle, t->attributes = 0; t->attributes |= ranks & 0xf; /* rank number is stored in the lowest 4 bits of the attributes field */ t->form_factor = MEMORY_FORMFACTOR_DIMM; - snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); + if (mem_info->dct_stat[node].Dual_Node_Package) { + snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node >> 1, + (mem_info->dct_stat[node].Internal_Node_ID)?((slot & 0x1)?"D":"C"):((slot & 0x1)?"B":"A"), (slot >> 1) + 1); + } else { + snprintf(string_buffer, sizeof (string_buffer), "NODE %d DIMM_%s%d", node, (slot & 0x1)?"B":"A", (slot >> 1) + 1); + } t->device_locator = smbios_add_string(t->eos, string_buffer); if (IS_ENABLED(CONFIG_DIMM_DDR2)) t->memory_type = MEMORY_TYPE_DDR2; diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c index 91d929a..0e59e1d 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.c +++ b/src/northbridge/amd/amdmct/mct/mct_d.c @@ -232,6 +232,18 @@ restartinit: pDCTstat->dev_nbmisc = PA_NBMISC(Node); pDCTstat->NodeSysBase = node_sys_base; + if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) { + uint32_t dword; + pDCTstat->Dual_Node_Package = 1; + + /* Get the internal node number */ + dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); + dword = (dword >> 30) & 0x3; + pDCTstat->Internal_Node_ID = dword; + } else { + pDCTstat->Dual_Node_Package = 0; + } + print_tx("mctAutoInitMCT_D: mct_init Node ", Node); mct_init(pMCTstat, pDCTstat); mctNodeIDDebugPort_D(); diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h index 3845a87..552681f 100644 --- a/src/northbridge/amd/amdmct/mct/mct_d.h +++ b/src/northbridge/amd/amdmct/mct/mct_d.h @@ -287,8 +287,11 @@ struct MCTStatStruc { struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ - u8 Node_ID; /* Node ID of current controller*/ - u8 ErrCode; /* Current error condition of Node + u8 Node_ID; /* Node ID of current controller*/ + uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ + uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t stopDCT; /* Set if the DCT will be stopped */ + u8 ErrCode; /* Current error condition of Node 0= no error 1= Variance Error, DCT is running but not in an optimal configuration. 2= Stop Error, DCT is NOT running diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 229073b..de0a508 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1396,6 +1396,18 @@ restartinit: pDCTstat->dev_nbctl = PA_NBCTL(Node); pDCTstat->NodeSysBase = node_sys_base; + if (mctGet_NVbits(NV_PACK_TYPE) == PT_GR) { + uint32_t dword; + pDCTstat->Dual_Node_Package = 1; + + /* Get the internal node number */ + dword = Get_NB32(pDCTstat->dev_nbmisc, 0xe8); + dword = (dword >> 30) & 0x3; + pDCTstat->Internal_Node_ID = dword; + } else { + pDCTstat->Dual_Node_Package = 0; + } + printk(BIOS_DEBUG, "%s: mct_init Node %d\n", __func__, Node); mct_init(pMCTstat, pDCTstat); mctNodeIDDebugPort_D(); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h index ffbad2b..8b8caca 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h @@ -331,9 +331,11 @@ struct amd_spd_node_data { struct DCTStatStruc { /* A per Node structure*/ /* DCTStatStruct_F - start */ - u8 Node_ID; /* Node ID of current controller */ - uint8_t stopDCT; /* Set if the DCT will be stopped */ - u8 ErrCode; /* Current error condition of Node + u8 Node_ID; /* Node ID of current controller */ + uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */ + uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */ + uint8_t stopDCT; /* Set if the DCT will be stopped */ + u8 ErrCode; /* Current error condition of Node 0= no error 1= Variance Error, DCT is running but not in an optimal configuration. 2= Stop Error, DCT is NOT running

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coreboot-gerrit November 2015