coreboot-gerrit November 2015

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Patch set updated for coreboot: fsp1_0: Update rangeley to revision POSTGOLD 3
by Marcin Wojciechowski 13 Nov '15

13 Nov '15

Marcin Wojciechowski (marcin.wojciechowski(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12418 -gerrit commit 86866b39e26592d1c031aee6ce4da582b302080f Author: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> Date: Thu Nov 12 16:05:42 2015 +0100 fsp1_0: Update rangeley to revision POSTGOLD 3 Alligment of Intel Firmware Support Package 1.0 rangeley header and source files to the revision: POSTGOLD3 Although there is POSTGOLD4 already available there is no differences apart from VPD_IMAGE_REV in fspvpd.h Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2 Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski(a)intel.com> --- .../intel/fsp1_0/rangeley/include/fspguid.h | 69 +++++ .../intel/fsp1_0/rangeley/include/fspplatform.h | 3 +- .../intel/fsp1_0/rangeley/include/fspsupport.h | 95 +++++++ .../intel/fsp1_0/rangeley/include/fsptypes.h | 9 +- .../intel/fsp1_0/rangeley/include/fspvpd.h | 12 +- .../intel/fsp1_0/rangeley/srx/fsp_support.c | 288 +++++++++++++++++++++ 6 files changed, 468 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h new file mode 100644 index 0000000..b9a6183 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspguid.h @@ -0,0 +1,69 @@ +/** @file + +Copyright (C) 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_GUID_H__ +#define __FSP_GUID_H__ + +/** + + FSP specific GUID HOB definitions + + **/ +#define FSP_INFO_HEADER_GUID \ + { \ + 0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \ + } + +#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \ + { \ + 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0 } \ + } + +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { \ + 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_FSP_GUID \ + { \ + 0x69a79759, 0x1373, 0x4367, { 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e } \ + } + +#define FSP_HOB_RESOURCE_OWNER_TSEG_GUID \ + { \ + 0xd038747c, 0xd00c, 0x4980, { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 } \ + } + +#define FSP_HOB_RESOURCE_OWNER_GRAPHICS_GUID \ + { \ + 0x9c7c3aa7, 0x5332, 0x4917, { 0x82, 0xb9, 0x56, 0xa5, 0xf3, 0xe6, 0x2a, 0x07 } \ + } + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h index ce479bf..c35dca0 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspplatform.h @@ -1,6 +1,6 @@ /** -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013 - 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -74,6 +74,7 @@ typedef struct { UINT8 tRTPmin; // 27 Minimum Internal Read to Precharge Command Delay Time (tRTPmin) UINT8 UpperNibbleFortFAW; // 28 Upper Nibble for tFAW UINT8 tFAWmin; // 29 Minimum Four Activate Window Delay Time (tFAWmin) + UINT8 SdramThermalRefreshOption; // 31 SdramThermalRefreshOption UINT8 ModuleThermalSensor; // 32 ModuleThermalSensor UINT8 SDRAMDeviceType; // 33 SDRAM Device Type UINT8 tCKminFine; // 34 Fine Offset for SDRAM Minimum Cycle Time (tCKmin) diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h new file mode 100644 index 0000000..dbbbf77 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspsupport.h @@ -0,0 +1,95 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#ifndef __FSP_SUPPORT_H__ +#define __FSP_SUPPORT_H__ + +#include "fsptypes.h" +#include "fspfv.h" +#include "fspffs.h" +#include "fspapi.h" +#include "fsphob.h" +#include "fspguid.h" +#include "fspplatform.h" +#include "fspinfoheader.h" +#include "fspbootmode.h" +#include "fspvpd.h" + +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobListPtr + ); + +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobListPtr + ); + +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid + ); + +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *FspMemoryBase, + UINT64 *FspMemoryLength, + EFI_GUID *FspReservedMemoryGuid + ); + +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +); + +VOID* +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length + ); + + +#endif diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h index 5912e01..3d2e663 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fsptypes.h @@ -100,13 +100,18 @@ typedef struct { #define TRUE ((BOOLEAN)(1==1)) #define FALSE ((BOOLEAN)(0==1)) +static inline void DebugDeadLoop(void) { + for (;;); +} + #define FSPAPI __attribute__((cdecl)) #define EFIAPI __attribute__((cdecl)) +#define _ASSERT(Expression) DebugDeadLoop() #define ASSERT(Expression) \ do { \ if (!(Expression)) { \ - for (;;); \ + _ASSERT (Expression); \ } \ } while (FALSE) @@ -175,4 +180,4 @@ typedef UINT32 EFI_STATUS; #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ (SIGNATURE_32 (A, B, C, D) | ((UINT64) (SIGNATURE_32 (E, F, G, H)) << 32)) -#endif +#endif \ No newline at end of file diff --git a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h index fba38a0..eefdb94 100644 --- a/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp1_0/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013-2014 Intel Corporation +Copyright (C) 2015, Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -50,7 +50,8 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdSpdBaseAddress_0_1; /* Offset 0x0026 */ UINT8 PcdSpdBaseAddress_1_0; /* Offset 0x0027 */ UINT8 PcdSpdBaseAddress_1_1; /* Offset 0x0028 */ - UINT8 UnusedUpdSpace1[7]; /* Offset 0x0029 */ + UINT8 PcdExtendedTemperatureEnable; /* Offset 0x0029 */ + UINT8 UnusedUpdSpace1[6]; /* Offset 0x002A */ UINT8 PcdEnableLan; /* Offset 0x0030 */ UINT8 PcdEnableSata2; /* Offset 0x0031 */ UINT8 PcdEnableSata3; /* Offset 0x0032 */ @@ -65,13 +66,14 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT8 PcdSerialPortBaudRate; /* Offset 0x0043 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0044 */ + UINT8 UnusedUpdSpace3[12]; /* Offset 0x0064 */ UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000102 +#define VPD_IMAGE_REV 0x00000130 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */ diff --git a/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c new file mode 100644 index 0000000..6fe3eb0 --- /dev/null +++ b/src/vendorcode/intel/fsp1_0/rangeley/srx/fsp_support.c @@ -0,0 +1,288 @@ +/** @file + +Copyright (C) 2013 - 2014, Intel Corporation + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + +#include <types.h> +#include <string.h> +#include "fspsupport.h" + +/** + This function retrieves the top of usable low memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable low memory top. + +**/ +UINT32 +GetUsableLowMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT32 MemLen; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemLen = 0x100000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= 0x100000 && + Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemLen += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemLen; +} + +/** + This function retrieves the top of usable high memory. + + @param HobListPtr A HOB list pointer. + + @retval Usable high memory top. + +**/ +UINT64 +GetUsableHighMemTop ( + CONST VOID *HobStart +) +{ + EFI_PEI_HOB_POINTERS Hob; + UINT64 MemTop; + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobStart; + + /* + * Collect memory ranges + */ + MemTop = 0x100000000; + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) { + /* + * Need memory above 1MB to be collected here + */ + if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) 0x100000000) { + MemTop += (UINT32) (Hob.ResourceDescriptor->ResourceLength); + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } + + return MemTop; +} + +/** + This function retrieves a special reserved memory region. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the GUID HOB is + located, the length will be updated. + @param OwnerGuid A pointer to the owner guild. + @retval Reserved region start address. 0 if this region does not exist. + +**/ +VOID +GetFspReservedMemoryFromGuid ( + CONST VOID *HobListPtr, + EFI_PHYSICAL_ADDRESS *Base, + UINT64 *Length, + EFI_GUID *OwnerGuid +) +{ + EFI_PEI_HOB_POINTERS Hob; + + /* + * Get the HOB list for processing + */ + Hob.Raw = (VOID *)HobListPtr; + + /* + * Collect memory ranges + */ + while (!END_OF_HOB_LIST (Hob)) { + if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) { + if (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) { + if (CompareGuid(&Hob.ResourceDescriptor->Owner, OwnerGuid)) { + *Base = (EFI_PHYSICAL_ADDRESS) (Hob.ResourceDescriptor->PhysicalStart); + *Length = (UINT64) (Hob.ResourceDescriptor->ResourceLength); + break; + } + } + } + Hob.Raw = GET_NEXT_HOB (Hob); + } +} + +/** + This function retrieves the TSEG reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the TSEG reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the TSEG reserved memory. + @retval others TSEG reserved memory base. + +**/ +UINT32 +GetTsegReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID TsegOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_TSEG_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&TsegOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + +/** + This function retrieves the FSP reserved normal memory. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the FSP reserved memory length buffer. If the GUID HOB is + located, the length will be updated. + @param Guid A pointer to owner HOB GUID. + @retval NULL Failed to find the FSP reserved memory. + @retval others FSP reserved memory base. + +**/ +UINT32 +GetFspReservedMemory ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspOwnerHobGuid = FSP_HOB_RESOURCE_OWNER_FSP_GUID; + UINT64 Length64 = 0; + EFI_PHYSICAL_ADDRESS Base = 0; + + GetFspReservedMemoryFromGuid (HobListPtr, &Base, &Length64, (EFI_GUID *)&FspOwnerHobGuid); + if ((Length != NULL) && (Base != 0)) { + *Length = (UINT32)Length64; + } + return (UINT32)Base; +} + + +/** + This function retrieves a GUIDed HOB data buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the GUID HOB data buffer length. If the + GUID HOB is located, the length will be updated. + @param Guid A pointer to HOB GUID. + @retval NULL Failed to find the GUID HOB. + @retval others GUID HOB data buffer pointer. + +**/ +VOID * +GetGuidHobDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length, + EFI_GUID *Guid +) +{ + UINT8 *GuidHob; + + /* FSP NVS DATA HOB */ + GuidHob = GetNextGuidHob(Guid, HobListPtr); + if (GuidHob == NULL) { + return NULL; + } else { + if (Length) { + *Length = GET_GUID_HOB_DATA_SIZE (GuidHob); + } + return GET_GUID_HOB_DATA (GuidHob); + } +} + +/** + This function retrieves FSP Non-volatile Storage HOB buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the NVS data buffer length. If the FSP NVS + HOB is located, the length will be updated. + @retval NULL Failed to find the NVS HOB. + @retval others FSP NVS data buffer pointer. + +**/ +VOID * +GetFspNvsDataBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspNvsHobGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspNvsHobGuid); +} + + +/** + This function retrieves Bootloader temporary stack buffer and size. + + @param HobListPtr A HOB list pointer. + @param Length A pointer to the Bootloader temporary stack length. + If the HOB is located, the length will be updated. + @retval NULL Failed to find the Bootloader temporary stack HOB. + @retval others Bootloader temporary stackbuffer pointer. + +**/ +VOID * +GetBootloaderTempMemoryBuffer ( + CONST VOID *HobListPtr, + UINT32 *Length +) +{ + const EFI_GUID FspBootloaderTemporaryMemoryHobGuid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + return GetGuidHobDataBuffer (HobListPtr, Length, (EFI_GUID *)&FspBootloaderTemporaryMemoryHobGuid); +}

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New patch to review for coreboot: sconfig: remove warning about root_complex
by Patrick Georgi 13 Nov '15

13 Nov '15

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12429 -gerrit commit 4466265a695d40fa26be8bc3c3350ff6b3726236 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Nov 13 09:39:22 2015 +0100 sconfig: remove warning about root_complex It's not deprecated if it's still in active use. The code layout is just "funny" (and could warrant a chipset-side cleanup, but not today) Change-Id: I5f7776ceba0134f20364a0c4a1ca51382e9877e2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/sconfig/main.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 5eb74da..27027f5 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -164,10 +164,10 @@ struct device *new_chip(struct device *parent, struct device *bus, char *path) { char *chip_h = malloc(strlen(path)+18); sprintf(chip_h, "src/%s", path); if ((stat(chip_h, &st) == -1) && (errno == ENOENT)) { - if (strstr(path, "/root_complex")) { - fprintf(stderr, "WARNING: Use of deprecated chip component %s\n", - path); - } else { + /* root_complex gets away without a separate directory, but + * exists on on pretty much all AMD chipsets. + */ + if (!strstr(path, "/root_complex")) { fprintf(stderr, "ERROR: Chip component %s does not exist.\n", path); exit(1);

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Patch merged into coreboot/master: newisys: Remove mainboard directory and Kconfig files
by gerrit＠coreboot.org 13 Nov '15

13 Nov '15

the following patch was just integrated into master: commit 2035d9aa94187040cfd73b12cc94c34ac1326f16 Author: Martin Roth <martinroth(a)google.com> Date: Thu Nov 12 14:14:40 2015 -0700 newisys: Remove mainboard directory and Kconfig files Since there are no longer any newisys mainboards, remove the directory and Kconfig files. This removes the Kconfig warning: mainboard/newisys/Kconfig:3:warning: config symbol defined without type Change-Id: Icb2e782173166a26fa261f6cfb81b665a846931e Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12423 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12423 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: Add way to access entire backing data for a buffer
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 9b24f7ca9abddfb9df9c084995486f7b55695835 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Nov 11 18:43:11 2015 +0100 cbfstool: Add way to access entire backing data for a buffer This is required to handle certain relative-to-flash-start offsets. BUG=none BRANCH=tot TEST=none Change-Id: I8b30c7b532e330af5db4b8ed65b21774c6cbbd25 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 596ba1aaa62aedb2b214ca55444e3068b9cb1044 Original-Change-Id: Idc9a5279f16951befec4d84aab35117988f7edb7 Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312220 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12415 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12415 for details. -gerrit

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Patch merged into coreboot/master: cbfstool: Allows mixed-state fmap regions to work
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 7db2b6cacc237dda66d927ada3cecd634c89fdb4 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Nov 11 15:35:24 2015 +0100 cbfstool: Allows mixed-state fmap regions to work When using FMAP regions (with option -r) that were generated with a master header (as done by cbfstool copy, eg. in Chrome OS' build system), there were differences in interpretation of the master header's fields. Normalize for that by not sanity-checking the master header's size field (there are enough other tests) and by dealing with region offsets properly. BUG=chromium:445938 BRANCH=tot TEST=`cbfstool /build/veyron_minnie/firmware/image.dev.bin print -r FW_MAIN_A` shows that region's directory (instead of claiming that there's no CBFS at all, or showing an empty directory). Change-Id: Ia840c823739d4ca144a7f861573d6d1b4113d799 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0e5364d291f45e4705e83c0331e128e35ab226d3 Original-Change-Id: Ie28edbf55ec56b7c78160000290ef3c57fda0f0e Original-Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/312210 Original-Commit-Ready: Patrick Georgi <pgeorgi(a)chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12416 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12416 for details. -gerrit

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Patch merged into coreboot/master: libpayload: queue: Add a helper macro for checking singleton queue
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 1dcb10eeb6912824ddf257dab8121a2a87260a3d Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Nov 6 22:20:15 2015 -0800 libpayload: queue: Add a helper macro for checking singleton queue Check if the simple queue consists of only 1 element. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. Change-Id: Ib257a5e6b9042b42c549f8ad8b943e3b75fd8c9c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5435d6fec1c4fbb4c04ba5b8c15caff9ee4e50f0 Original-Change-Id: I7a8cb9c4e7e71956e85e65b3e7b8e0af4d354110 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311256 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12412 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12412 for details. -gerrit

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Patch merged into coreboot/master: libpayload: udc/dwc2: Ignore setup packet in check for queue empty during shutdown
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit fe35623f20c4e94e59630143e6a01717f69851e8 Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Nov 6 22:22:56 2015 -0800 libpayload: udc/dwc2: Ignore setup packet in check for queue empty during shutdown DWC2 UDC controller always requires an active packet to be present in EP0-OUT to ensure proper operation of control plane. Thus, during shutdown ignore EP0-OUT for queue empty check if only 1 packet is present. BUG=b:24676003 BRANCH=None TEST=Compiles successfully. "fastboot reboot-bootloader" reboots device without timeout in udc shutdown. Change-Id: Iafe46c80f58c4cd57f8d58f060d805b603506bbd Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4e7c27d849c0411aae58e60a24d8170a27ab8485 Original-Change-Id: Ifa493ce0e41964ee7ca8bb3a1f4bb8726fa11173 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311257 Original-Commit-Ready: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12413 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/12413 for details. -gerrit

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Patch merged into coreboot/master: intel/kunimitsu: This patch enables wakeup from S0ix using headset button.
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 66aae6d3ba15fd673ccadf94c014bba540a45260 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Mon Nov 2 16:15:51 2015 -0800 intel/kunimitsu: This patch enables wakeup from S0ix using headset button. Kernel needs to set Audio IRQ as wake capable. BUG=chrome-os-partner:47450 BRANCH=NONE TEST=System wakes up from S0ix by pressing headset buttons. Change-Id: I0f89d05b4c5449e5e3277dde938d941e4ad8cbea Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 65bf434f7c7e1662211f9c8bf61eeb4f41bdc675 Original-Change-Id: I7b5b564023044b4458eb0976488018b3226f4c70 Original-Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311793 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/12414 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12414 for details. -gerrit

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Patch merged into coreboot/master: intel/skylake: ensure the RTC time is set
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit 685ab2a2f2335a2366e2338f0425422dd3409403 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 6 15:24:20 2015 -0600 intel/skylake: ensure the RTC time is set In 2014 or so the RTC code was changed to assume the ALTCENTRY register (0x32) as always being utilized for creating an rtc_time. However, one needs to ensure it's set at least once otherwise the year field in rtc_time is not sane. In practice this doesn't matter unless somone wants to use the full year value. cmos_init() should do the same thing in the rtc fail case, but the machine I had never had that set correctly. BUG=chrome-os-partner:47388 BRANCH=None TEST=Booted glados w/ 0xff ALTCENTRY value. New value is 0x20. Change-Id: I028f801c5d717a0018ed00df82c25b466d64670c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7d5be5bc697bef60a264ddc7f67755aa96088d36 Original-Change-Id: I6e12a30c9e08d8c1002e4cef0f143f0f88009e92 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311264 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12411 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12411 for details. -gerrit

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Patch merged into coreboot/master: elog: fix improper assumption for year values
by gerrit＠coreboot.org 12 Nov '15

12 Nov '15

the following patch was just integrated into master: commit c41c6a44127620a61b0a36b3d9b55cc13429c5cd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 6 15:20:23 2015 -0600 elog: fix improper assumption for year values The elog format stores the year of the event in bcd format. Semi-recently rtc_get() started returning the full year, e.g. 2015. However, bin2bcd takes a uint8_t as a parameter. Converting a full year (2015 or 0x7df) to a uint8_t results in passing bad values (223 or 0xdf) to bin2bcd. In other words the input value of bin2bcd needs to be a number between 0 and 99. Therefore fix that mistake. BUG=chrome-os-partner:47388 BRANCH=None TEST=Events show up with correct year in eventlog now. Change-Id: I9209cb9175c0b4925337e2e5d4fea8316b30022a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 95a86013234dc999c988291f636e2db3803cc24a Original-Change-Id: I12734bc3a423ba9d739658b8edc402b8d445f22e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/311263 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/12410 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12410 for details. -gerrit

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coreboot-gerrit November 2015