coreboot-gerrit November 2015

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Patch set updated for coreboot: southbridge/amd/sr5650: Hide clock configuration device after setup is complete
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12045 -gerrit commit b2df37ff62bcc09919361655dca45d8121429ac0 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 13 17:45:12 2015 -0500 southbridge/amd/sr5650: Hide clock configuration device after setup is complete Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sr5650/early_setup.c | 16 ++++++++-------- src/southbridge/amd/sr5650/pcie.c | 3 +++ 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index 95e6ebf..1fc0427 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -410,14 +410,14 @@ static void sr5650_por_misc_index_init(device_t nb_dev) set_nbmisc_enable_bits(nb_dev, 0x01, 0xFFFFFFFF, 0x00000310); /* NBCFG (NBMISCIND 0x0): NB_CNTL - - * HIDE_NB_AGP_CAP ([0], default=1)HIDE - * HIDE_P2P_AGP_CAP ([1], default=1)HIDE - * HIDE_NB_GART_BAR ([2], default=1)HIDE - * HIDE_MMCFG_BAR ([3], default=1)SHOW - * AGPMODE30 ([4], default=0)DISABLE - * AGP30ENCHANCED ([5], default=0)DISABLE - * HIDE_AGP_CAP ([8], default=1)ENABLE */ - set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6); + * HIDE_NB_AGP_CAP ([0], default=1)HIDE + * HIDE_P2P_AGP_CAP ([1], default=1)HIDE + * HIDE_NB_GART_BAR ([2], default=1)HIDE + * HIDE_MMCFG_BAR ([3], default=1)SHOW + * AGPMODE30 ([4], default=0)DISABLE + * AGP30ENCHANCED ([5], default=0)DISABLE + * HIDE_CLKCFG_HEADER ([8], default=0)SHOW */ + set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6 | 0 << 8); /* IOC_LAT_PERF_CNTR_CNTL */ set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); diff --git a/src/southbridge/amd/sr5650/pcie.c b/src/southbridge/amd/sr5650/pcie.c index 4161c18..762e632 100644 --- a/src/southbridge/amd/sr5650/pcie.c +++ b/src/southbridge/amd/sr5650/pcie.c @@ -850,6 +850,9 @@ void sr56x0_lock_hwinitreg(void) /* Lock HWInit Register NBMISCIND:0x0 NBCNTL[7] HWINIT_WR_LOCK */ set_nbmisc_enable_bits(nb_dev, 0x00, 1 << 7, 1 << 7); + + /* Hide clock configuration PCI device HIDE_CLKCFG_HEADER */ + set_nbmisc_enable_bits(nb_dev, 0x00, 0x00000100, 1 << 8); } /*****************************************

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Patch set updated for coreboot: southbridge/amd/sr5650: Add IOMMU support
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12044 -gerrit commit b2657558af30da692884cd2cd406829e78cc3abd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:49:06 2015 -0500 southbridge/amd/sr5650: Add IOMMU support Change-Id: I2083d0c5653515c27d4626c62a6499b850f7547b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/include/device/pci_ids.h | 1 + src/mainboard/asus/kgpe-d16/acpi_tables.c | 37 ++ src/mainboard/supermicro/h8scm_fam10/acpi_tables.c | 37 ++ src/southbridge/amd/sr5650/cmn.h | 3 + src/southbridge/amd/sr5650/early_setup.c | 50 ++- src/southbridge/amd/sr5650/sr5650.c | 479 ++++++++++++++++++++- src/southbridge/amd/sr5650/sr5650.h | 14 + 7 files changed, 611 insertions(+), 10 deletions(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 664ac49..72f1ece 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -429,6 +429,7 @@ #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV12 0x5A20 #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV13 0x5A1E #define PCI_DEVICE_ID_AMD_SR5650_PCIE_DEV8 0x5A21 +#define PCI_DEVICE_ID_AMD_SR5650_IOMMU 0x5A23 #define PCI_DEVICE_ID_AMD_CZ_HDA 0x157A #define PCI_DEVICE_ID_AMD_CZ_LPC 0x790E diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 3a4e6d8..24c1724 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -69,3 +69,40 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + uint32_t apicid_sp5100; + uint32_t apicid_sr5650; + + apicid_sp5100 = 0x20; + apicid_sr5650 = apicid_sp5100 + 1; + + /* Describe NB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = apicid_sr5650; /* IOAPIC ID */ + p[5] = 0x1; /* Device 0 Function 1 */ + p[6] = 0x0; /* Northbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + /* Describe SB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = apicid_sp5100; /* IOAPIC ID */ + p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ + p[6] = 0x0; /* Southbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + return current; +} \ No newline at end of file diff --git a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c index 0421d57..08910cc 100644 --- a/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c +++ b/src/mainboard/supermicro/h8scm_fam10/acpi_tables.c @@ -62,3 +62,40 @@ unsigned long acpi_fill_madt(unsigned long current) return current; } + +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + uint32_t apicid_sp5100; + uint32_t apicid_sr5650; + + apicid_sp5100 = 0x20; + apicid_sr5650 = apicid_sp5100 + 1; + + /* Describe NB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = apicid_sr5650; /* IOAPIC ID */ + p[5] = 0x1; /* Device 0 Function 1 */ + p[6] = 0x0; /* Northbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + /* Describe SB IOAPIC */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = apicid_sp5100; /* IOAPIC ID */ + p[5] = 0x14 << 3; /* Device 0x14 Function 0 */ + p[6] = 0x0; /* Southbridge bus */ + p[7] = 0x1; /* Variety */ + current += 8; + + return current; +} diff --git a/src/southbridge/amd/sr5650/cmn.h b/src/southbridge/amd/sr5650/cmn.h index db27d4f..0c0fd29 100644 --- a/src/southbridge/amd/sr5650/cmn.h +++ b/src/southbridge/amd/sr5650/cmn.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,6 +23,8 @@ #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ #define NBMC_INDEX 0xE8 #define NBPCIE_INDEX 0xE0 +#define L2CFG_INDEX 0xF0 +#define L1CFG_INDEX 0xF8 #define EXT_CONF_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS #define TEMP_MMIO_BASE_ADDRESS 0xC0000000 diff --git a/src/southbridge/amd/sr5650/early_setup.c b/src/southbridge/amd/sr5650/early_setup.c index b7bd1ab..95e6ebf 100644 --- a/src/southbridge/amd/sr5650/early_setup.c +++ b/src/southbridge/amd/sr5650/early_setup.c @@ -20,6 +20,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> +#include <option.h> +#include <reset.h> #include "sr5650.h" #include "cmn.h" @@ -267,6 +269,34 @@ void sr5650_htinit(void) /* HT Buffer Allocation for Ganged Links!!! */ #endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */ } + +} + +/* Must be run immediately after HT setup is complete and first warm reset has occurred (if applicable) + * Attempting to switch the NB into isochronous mode before the CPUs have engaged isochronous mode + * will cause a system hard lockup... + */ +void sr5650_htinit_dect_and_enable_isochronous_link(void) +{ + device_t sr5650_f0; + unsigned char iommu; + + sr5650_f0 = PCI_DEV(0, 0, 0); + + iommu = 1; + get_option(&iommu, "iommu"); + + if (iommu) { + /* Enable isochronous mode */ + set_nbcfg_enable_bits(sr5650_f0, 0xc8, 1 << 12, 1 << 12); + + /* Apply pending changes */ + if (!((pci_read_config32(sr5650_f0, 0xc8) >> 12) & 0x1)) { + printk(BIOS_INFO, "...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } + } } #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 /* save some spaces */ @@ -331,8 +361,21 @@ static void sr5650_por_pcicfg_init(device_t nb_dev) *****************************************/ static void sr5650_por_misc_index_init(device_t nb_dev) { - /* disable IOMMU */ - set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x0); + unsigned char iommu; + + iommu = 1; + get_option(&iommu, "iommu"); + + if (iommu) { + /* enable IOMMU */ + printk(BIOS_DEBUG, "Enabling IOMMU\n"); + set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x1); + } else { + /* disable IOMMU */ + printk(BIOS_DEBUG, "Disabling IOMMU\n"); + set_nbmisc_enable_bits(nb_dev, 0x75, 0x1, 0x0); + } + /* NBMISCIND:0x75[29]= 1 Device ID for hotplug and PME message */ set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 29, 1 << 29); set_nbmisc_enable_bits(nb_dev, 0x75, 1 << 9, 1 << 9); /* no doc reference, comply with BTS */ @@ -370,10 +413,11 @@ static void sr5650_por_misc_index_init(device_t nb_dev) * HIDE_NB_AGP_CAP ([0], default=1)HIDE * HIDE_P2P_AGP_CAP ([1], default=1)HIDE * HIDE_NB_GART_BAR ([2], default=1)HIDE + * HIDE_MMCFG_BAR ([3], default=1)SHOW * AGPMODE30 ([4], default=0)DISABLE * AGP30ENCHANCED ([5], default=0)DISABLE * HIDE_AGP_CAP ([8], default=1)ENABLE */ - set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 6); + set_nbmisc_enable_bits(nb_dev, 0x00, 0x0000FFFF, 0 << 0 | 1 << 1 | 1 << 2 | 0 << 3 | 0 << 6); /* IOC_LAT_PERF_CNTR_CNTL */ set_nbmisc_enable_bits(nb_dev, 0x30, 0xFF, 0x00); diff --git a/src/southbridge/amd/sr5650/sr5650.c b/src/southbridge/amd/sr5650/sr5650.c index 514e654..07b4a02 100644 --- a/src/southbridge/amd/sr5650/sr5650.c +++ b/src/southbridge/amd/sr5650/sr5650.c @@ -22,7 +22,9 @@ #include <device/pci_ops.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> +#include <stdlib.h> #include <delay.h> +#include <option.h> #include "sr5650.h" #include "cmn.h" @@ -83,6 +85,26 @@ void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data) nb_write_index((nb_dev), NBPCIE_INDEX, (index), (data)); } +uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index) +{ + return nb_read_index((nb_dev), L2CFG_INDEX, (index)); +} + +void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data) +{ + nb_write_index((nb_dev), L2CFG_INDEX | (0x1 << 8), (index), (data)); +} + +uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index) +{ + return nb_read_index((nb_dev), L1CFG_INDEX, (index)); +} + +void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data) +{ + nb_write_index((nb_dev), L1CFG_INDEX | (0x1 << 31), (index), (data)); +} + /*********************************************************** * To access bar3 we need to program PCI MMIO 7 in K8. * in_out: @@ -282,6 +304,240 @@ u32 get_vid_did(device_t dev) return pci_read_config32(dev, 0); } +void detect_and_enable_iommu(device_t iommu_dev) { + uint32_t dword; + uint8_t l1_target; + unsigned char iommu; + void * mmio_base; + + iommu = 1; + get_option(&iommu, "iommu"); + + if (iommu) { + printk(BIOS_DEBUG, "Initializing IOMMU\n"); + + device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + + if (!nb_dev) { + printk(BIOS_WARNING, "Unable to find SR5690 device! IOMMU NOT initialized\n"); + return; + } + + mmio_base = (void*)(pci_read_config32(iommu_dev, 0x44) & 0xffffc000); + + // if (get_nb_rev(nb_dev) == REV_SR5650_A11) { + // dword = pci_read_config32(iommu_dev, 0x6c); + // dword &= ~(0x1 << 8); + // pci_write_config32(iommu_dev, 0x6c, dword); + // } + + dword = pci_read_config32(iommu_dev, 0x50); + dword &= ~(0x1 << 22); + pci_write_config32(iommu_dev, 0x50, dword); + + dword = pci_read_config32(iommu_dev, 0x44); + dword |= 0x1; + pci_write_config32(iommu_dev, 0x44, dword); + + write32((void*)(mmio_base + 0x8), 0x0); + write32((void*)(mmio_base + 0xc), 0x08000000); + write32((void*)(mmio_base + 0x10), 0x0); + write32((void*)(mmio_base + 0x2008), 0x0); + write32((void*)(mmio_base + 0x2010), 0x0); + + /* IOMMU L1 initialization */ + for (l1_target = 0; l1_target < 6; l1_target++) { + dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0xc); + dword |= (0x7 << 28); + l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0xc, dword); + + dword = l1cfg_ind_read_index(nb_dev, (l1_target << 16) + 0x7); + dword |= (0x1 << 5); + l1cfg_ind_write_index(nb_dev, (l1_target << 16) + 0x7, dword); + } + + /* IOMMU L2 initialization */ + dword = l2cfg_ind_read_index(nb_dev, 0xc); + dword |= (0x7 << 29); + l2cfg_ind_write_index(nb_dev, 0xc, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x10); + dword &= ~(0x3 << 8); + dword |= (0x2 << 8); + l2cfg_ind_write_index(nb_dev, 0x10, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x14); + dword &= ~(0x3 << 8); + dword |= (0x2 << 8); + l2cfg_ind_write_index(nb_dev, 0x14, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x18); + dword &= ~(0x3 << 8); + dword |= (0x2 << 8); + l2cfg_ind_write_index(nb_dev, 0x18, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x1c); + dword &= ~(0x3 << 8); + dword |= (0x2 << 8); + l2cfg_ind_write_index(nb_dev, 0x1c, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x50); + dword &= ~(0x3 << 8); + dword |= (0x2 << 8); + l2cfg_ind_write_index(nb_dev, 0x50, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x10); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x10, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x14); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x14, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x18); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x18, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x1c); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x1c, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x50); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x50, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x6); + dword |= (0x1 << 7); + l2cfg_ind_write_index(nb_dev, 0x6, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x44); + dword |= (0x1 << 0); + l2cfg_ind_write_index(nb_dev, 0x44, dword); + +// if (get_nb_rev(nb_dev) == REV_SR5650_A21) { + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 1); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x44); + dword |= (0x1 << 1); + l2cfg_ind_write_index(nb_dev, 0x44, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 2); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 3); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x44); + dword |= (0x1 << 3); + l2cfg_ind_write_index(nb_dev, 0x44, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x6); + dword |= (0x1 << 5); + l2cfg_ind_write_index(nb_dev, 0x6, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x6); + dword |= (0x1 << 6); + l2cfg_ind_write_index(nb_dev, 0x6, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 5); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x44); + dword |= (0x1 << 4); + l2cfg_ind_write_index(nb_dev, 0x44, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 6); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x7); + dword |= (0x1 << 7); + l2cfg_ind_write_index(nb_dev, 0x7, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x6); + dword |= (0x1 << 8); + l2cfg_ind_write_index(nb_dev, 0x6, dword); +// } + + l2cfg_ind_write_index(nb_dev, 0x52, 0xf0000002); + + dword = l2cfg_ind_read_index(nb_dev, 0x80); + dword |= (0x1 << 0); + l2cfg_ind_write_index(nb_dev, 0x80, dword); + + dword = l2cfg_ind_read_index(nb_dev, 0x30); + dword |= (0x1 << 0); + l2cfg_ind_write_index(nb_dev, 0x30, dword); + } +} + +void sr5650_iommu_read_resources(device_t dev) +{ + unsigned char iommu; + struct resource *res; + + iommu = 1; + get_option(&iommu, "iommu"); + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + if (iommu) { + /* Request MMIO range allocation */ + res = new_resource(dev, 0x44); /* IOMMU */ + res->base = 0x0; + res->size = 0x4000; + res->limit = 0xFFFFFFFFUL; /* res->base + res->size -1; */ + res->align = 14; /* 16k alignment */ + res->gran = 14; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; + } + + compact_resources(dev); +} + +void sr5650_iommu_set_resources(device_t dev) +{ + unsigned char iommu; + struct resource *res; + + iommu = 1; + get_option(&iommu, "iommu"); + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); + + if (iommu) { + /* Get the allocated range */ + res = find_resource(dev, 0x44); + + if (res->base == 0) { + printk(BIOS_WARNING, "Unable to allocate MMIO range to IOMMU\n"); + } + + /* Assign the range to hardware */ + pci_write_config32(dev, 0x44, res->base & 0xffffc000); + pci_write_config32(dev, 0x48, 0x0); + } + + /* Run standard resource set routine */ + pci_dev_set_resources(dev); +} + +void sr5650_iommu_enable_resources(device_t dev) +{ + detect_and_enable_iommu(dev); +} + void sr5650_nb_pci_table(device_t nb_dev) { /* NBPOR_InitPOR function. */ u8 temp8; @@ -361,13 +617,23 @@ void sr5650_enable(device_t dev) dev_ind = dev->path.pci.devfn >> 3; switch (dev_ind) { case 0: /* bus0, dev0, fun0; */ - printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); - enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ - - config_gpp_core(nb_dev, sb_dev); - sr5650_gpp_sb_init(nb_dev, sb_dev, 8); - - sr5650_nb_pci_table(nb_dev); + switch (dev->path.pci.devfn & 0x7) { + case 0: + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-0.\n"); + enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ + + config_gpp_core(nb_dev, sb_dev); + sr5650_gpp_sb_init(nb_dev, sb_dev, 8); + + sr5650_nb_pci_table(nb_dev); + break; + case 1: + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-1.\n"); + break; + case 2: + printk(BIOS_INFO, "Bus-0, Dev-0, Fun-2.\n"); + break; + } break; case 2: /* bus0, dev2,3 GPP1 */ @@ -434,6 +700,205 @@ void sr5650_enable(device_t dev) } } +static void add_ivrs_device_entries(struct device *parent, struct device *dev, int depth, int linknum, int8_t *root_level, unsigned long *current, uint16_t *length) +{ + uint8_t *p; + struct device *sibling; + struct bus *link; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } + + if (dev->path.type == DEVICE_PATH_PCI) { + if ((dev->bus->secondary == 0x0) && (dev->path.pci.devfn == 0x0)) + *root_level = depth; + + if (*root_level != -1) { + if (depth >= *root_level) { + if (dev->enabled) { + if (depth == *root_level) { + if (dev->path.pci.devfn < (0x1 << 3)) { + /* SR5690 control device */ + } else if ((dev->path.pci.devfn >= (0x1 << 3)) && (dev->path.pci.devfn < (0xe << 3))) { + /* SR5690 PCIe bridge device */ + } else { + if (dev->path.pci.devfn == (0x14 << 3)) { + /* SMBUS controller */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x97; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Other southbridge device */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } + } + } else { + if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_NORMAL) { + /* Device behind bridge */ + if (pci_find_capability(dev, PCI_CAP_ID_PCIE)) { + /* Device is PCIe */ + p = (uint8_t *) *current; + p[0] = 0x2; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Padding */ + p[5] = 0x0; /* Padding */ + p[6] = 0x0; /* Padding */ + p[7] = 0x0; /* Padding */ + *length += 8; + *current += 8; + } else { + /* Device is legacy PCI or PCI-X */ + p = (uint8_t *) *current; + p[0] = 0x42; /* Entry type */ + p[1] = dev->path.pci.devfn; /* Device */ + p[2] = dev->bus->secondary; /* Bus */ + p[3] = 0x0; /* Data */ + p[4] = 0x0; /* Reserved */ + p[5] = parent->path.pci.devfn; /* Device */ + p[6] = parent->bus->secondary; /* Bus */ + p[7] = 0x0; /* Reserved */ + *length += 8; + *current += 8; + } + } + } + } + } + } + } + + for (link = dev->link_list; link; link = link->next) + for (sibling = link->children; sibling; sibling = sibling->sibling) + add_ivrs_device_entries(dev, sibling, depth + 1, depth, root_level, current, length); + + free(root_level); +} + +static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current) +{ + uint8_t *p; + + device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (!nb_dev) { + printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 device! IVRS table not generated...\n"); + return (unsigned long)ivrs; + } + + device_t iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2)); + if (!iommu_dev) { + printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 IOMMU device! IVRS table not generated...\n"); + return (unsigned long)ivrs; + } + + ivrs->iv_info = 0x0; + ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */ + ivrs->iv_info |= (0x34 << 8); /* Maximum supported physical address size */ + + ivrs->ivhd.type = 0x10; + ivrs->ivhd.flags = 0x0e; + // if (get_nb_rev(nb_dev) != REV_SR5650_A11) { + ivrs->ivhd.flags |= 0x10; /* Enable ATS support on all revisions except A11 */ + // } + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */ + ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */ + ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; + ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); + ivrs->ivhd.pci_segment_group = 0x0; + ivrs->ivhd.iommu_info = 0x0; + ivrs->ivhd.iommu_info |= (0x14 << 8); + ivrs->ivhd.efr = 0x0; + + /* Describe HPET */ + p = (uint8_t *)current; + p[0] = 0x48; /* Entry type */ + p[1] = 0; /* Device */ + p[2] = 0; /* Bus */ + p[3] = 0xd7; /* Data */ + p[4] = 0x0; /* HPET number */ + p[5] = 0x14 << 3; /* HPET device */ + p[6] = nb_dev->bus->secondary; /* HPET bus */ + p[7] = 0x2; /* Variety */ + ivrs->ivhd.length += 8; + current += 8; + + /* Describe PCI devices */ + add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); + + /* Describe IOAPICs */ + unsigned long prev_current = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivrs->ivhd.length += (current - prev_current); + + return current; +} + +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + unsigned char iommu; + + iommu = 1; + get_option(&iommu, "iommu"); + + if (iommu) { + acpi_ivrs_t *ivrs; + + /* IVRS */ + current = ALIGN(current, 8); + printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); + } + + return current; +} + +static struct pci_operations iommu_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations iommu_ops = { + .read_resources = sr5650_iommu_read_resources, + .set_resources = sr5650_iommu_set_resources, + .enable_resources = sr5650_iommu_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, + .init = 0, + .scan_bus = 0, + .ops_pci = &iommu_ops_pci, +}; + +static const struct pci_driver ht_driver_sr5690 __pci_driver = { + .ops = &iommu_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_AMD_SR5650_IOMMU, +}; + struct chip_operations southbridge_amd_sr5650_ops = { CHIP_NAME("ATI SR5650") .enable_dev = sr5650_enable, diff --git a/src/southbridge/amd/sr5650/sr5650.h b/src/southbridge/amd/sr5650/sr5650.h index 21acca3..bad3529 100644 --- a/src/southbridge/amd/sr5650/sr5650.h +++ b/src/southbridge/amd/sr5650/sr5650.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,6 +18,7 @@ #define __SR5650_H__ #include <stdint.h> +#include <arch/acpi.h> #include <device/pci_ids.h> #include "chip.h" #include "rev.h" @@ -91,16 +93,24 @@ u32 nbpcie_p_read_index(device_t dev, u32 index); void nbpcie_p_write_index(device_t dev, u32 index, u32 data); u32 nbpcie_ind_read_index(device_t nb_dev, u32 index); void nbpcie_ind_write_index(device_t nb_dev, u32 index, u32 data); +uint32_t l2cfg_ind_read_index(device_t nb_dev, uint32_t index); +void l2cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data); +uint32_t l1cfg_ind_read_index(device_t nb_dev, uint32_t index); +void l1cfg_ind_write_index(device_t nb_dev, uint32_t index, uint32_t data); u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg); void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg, u32 mask, u32 val); void sr5650_set_tom(device_t nb_dev); +unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, + struct acpi_rsdp *rsdp); + void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add); void enable_pcie_bar3(device_t nb_dev); void disable_pcie_bar3(device_t nb_dev); void enable_sr5650_dev8(void); void sr5650_htinit(void); +void sr5650_htinit_dect_and_enable_isochronous_link(void); void sr5650_early_setup(void); void sr5650_before_pci_init(void); void sr5650_enable(device_t dev); @@ -114,6 +124,10 @@ void pcie_config_misc_clk(device_t nb_dev); void fam10_optimization(void); void sr5650_disable_pcie_bridge(void); u32 get_vid_did(device_t dev); +void detect_and_enable_iommu(device_t iommu_dev); +void sr5650_iommu_read_resources(device_t dev); +void sr5650_iommu_set_resources(device_t dev); +void sr5650_iommu_enable_resources(device_t dev); void sr5650_nb_pci_table(device_t nb_dev); void init_gen2(device_t nb_dev, device_t dev, u8 port); void sr56x0_lock_hwinitreg(void);

1 0

New patch to review for coreboot: iwave/IWRainBowG6: Fix IASL warning and remark
by Martin Roth 23 Nov '15

23 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12515 -gerrit commit 66ac7f01b91311348904bcc820fb978394bcd345 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 11:21:25 2015 -0700 iwave/IWRainBowG6: Fix IASL warning and remark - Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes IASL Warning: dsdt.aml 1362: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Fixes IASL remark: dsdt.aml 1353: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/iwave/iWRainbowG6/Kconfig | 4 ---- src/mainboard/iwave/iWRainbowG6/acpi/ec.asl | 8 +++++++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index fbcfb17..5e92cfb 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -28,10 +28,6 @@ config IRQ_SLOT_COUNT int default 10 -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - # This mainboard might have a higher clocked UART or might not be able to run # serial output at 115200 baud diff --git a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl b/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl index 1de2ef4..63abc00 100644 --- a/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl +++ b/src/mainboard/iwave/iWRainbowG6/acpi/ec.asl @@ -19,7 +19,13 @@ Device(EC0) Name (_HID, EISAID("PNP0C09")) Name (_UID, 1) - Method (_CRS, 0) + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() {

1 0

New patch to review for coreboot: intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS method
by Martin Roth 23 Nov '15

23 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12514 -gerrit commit 75a62d9c7ae0886a869e57e820049485e5dd13ba Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 10:38:10 2015 -0700 intel/soc/baytrail: Move MCRS ResourceTemplate out of _CRS method Fixes these remarks: Object is not referenced (Name is within method [_CRS]) The ACPI compiler is trying to be helpful in letting us know that we're not using various fields in the MCRS ResourceTemplate when we define it inside of the _CRS method. Since we're not intending to use those objects in the method, it shouldn't be an issue, but the warning is annoying and can mask real issues. Moving the creation of the MCRS object to outside of the CRS method and referencing it from there solves this problem. Change-Id: I54ab3ad9ed148fdd24e8615d83bc8ae668d1dbff Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/soc/intel/baytrail/acpi/southcluster.asl | 233 ++++++++++++++------------- 1 file changed, 117 insertions(+), 116 deletions(-) diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index f111544..834f6ad 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -50,126 +50,127 @@ Name(_CID,EISAID("PNP0A03")) // PCI Name(_ADR, 0) Name(_BBN, 0) +Name (MCRS, ResourceTemplate() +{ + // Bus Numbers + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) + + // IO Region 0 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) + + // PCI Config Space + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + // IO Region 1 + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) + + // VGA memory (0xa0000-0xbffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,, ASEG) + + // OPROM reserved (0xc0000-0xc3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000,,, OPR0) + + // OPROM reserved (0xc4000-0xc7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000,,, OPR1) + + // OPROM reserved (0xc8000-0xcbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000,,, OPR2) + + // OPROM reserved (0xcc000-0xcffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000,,, OPR3) + + // OPROM reserved (0xd0000-0xd3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000,,, OPR4) + + // OPROM reserved (0xd4000-0xd7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000,,, OPR5) + + // OPROM reserved (0xd8000-0xdbfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000,,, OPR6) + + // OPROM reserved (0xdc000-0xdffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000,,, OPR7) + + // BIOS Extension (0xe0000-0xe3fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000,,, ESG0) + + // BIOS Extension (0xe4000-0xe7fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000,,, ESG1) + + // BIOS Extension (0xe8000-0xebfff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000,,, ESG2) + + // BIOS Extension (0xec000-0xeffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000,,, ESG3) + + // System BIOS (0xf0000-0xfffff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000,,, FSEG) + + // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PMEM) + + // TPM Area (0xfed40000-0xfed44fff) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, + 0x00005000,,, TPMR) +}) + Method (_CRS, 0, Serialized) { - Name (MCRS, ResourceTemplate() - { - // Bus Numbers - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,, PB00) - - // IO Region 0 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,, PI00) - - // PCI Config Space - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - // IO Region 1 - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300,,, PI01) - - // VGA memory (0xa0000-0xbffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,, ASEG) - - // OPROM reserved (0xc0000-0xc3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, - 0x00004000,,, OPR0) - - // OPROM reserved (0xc4000-0xc7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, - 0x00004000,,, OPR1) - - // OPROM reserved (0xc8000-0xcbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, - 0x00004000,,, OPR2) - - // OPROM reserved (0xcc000-0xcffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, - 0x00004000,,, OPR3) - - // OPROM reserved (0xd0000-0xd3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, - 0x00004000,,, OPR4) - - // OPROM reserved (0xd4000-0xd7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, - 0x00004000,,, OPR5) - - // OPROM reserved (0xd8000-0xdbfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, - 0x00004000,,, OPR6) - - // OPROM reserved (0xdc000-0xdffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, - 0x00004000,,, OPR7) - - // BIOS Extension (0xe0000-0xe3fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, - 0x00004000,,, ESG0) - - // BIOS Extension (0xe4000-0xe7fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, - 0x00004000,,, ESG1) - - // BIOS Extension (0xe8000-0xebfff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, - 0x00004000,,, ESG2) - - // BIOS Extension (0xec000-0xeffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000ec000, 0x000effff, 0x00000000, - 0x00004000,,, ESG3) - - // System BIOS (0xf0000-0xfffff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, - 0x00010000,,, FSEG) - - // PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PMEM) - - // TPM Area (0xfed40000-0xfed44fff) - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, - 0x00005000,,, TPMR) - }) // Update PCI resource area - CreateDwordField(MCRS, PMEM._MIN, PMIN) - CreateDwordField(MCRS, PMEM._MAX, PMAX) - CreateDwordField(MCRS, PMEM._LEN, PLEN) + CreateDwordField(MCRS, ^PMEM._MIN, PMIN) + CreateDwordField(MCRS, ^PMEM._MAX, PMAX) + CreateDwordField(MCRS, ^PMEM._LEN, PLEN) // TOLM is BMBOUND accessible from IOSF so is saved in NVS Store (\TOLM, PMIN)

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New patch to review for coreboot: ec/quanta/ene_kb3940q: Fix ACPI Notice
by Martin Roth 23 Nov '15

23 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12513 -gerrit commit 632dc740fc696b9b632fa18b4fc1d4657a711cec Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 10:35:11 2015 -0700 ec/quanta/ene_kb3940q: Fix ACPI Notice Affects these mainboards: - lenovo/g505s - google/parrot - hp/pavilion_m6_1035dx Fixes IASL notice for this specific instance: dsdt.aml 1952: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) Change-Id: Id297cdea35d43f51887f798a9983629343c2313a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/ec/quanta/ene_kb3940q/acpi/ec.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/ec/quanta/ene_kb3940q/acpi/ec.asl b/src/ec/quanta/ene_kb3940q/acpi/ec.asl index 0195a31..8d3ff81 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/ec.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/ec.asl @@ -116,7 +116,7 @@ Device (EC0) BCNT, 8, // SMBus Block Count ; E4h } - Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() {

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Patch merged into coreboot/master: fsp1_0: Update Kconfig for symbols not depending on FSP binary
by gerrit＠coreboot.org 23 Nov '15

23 Nov '15

the following patch was just integrated into master: commit c5bb7bd957f57428760edf26d41a6626b10a894e Author: Martin Roth <martinroth(a)google.com> Date: Wed Nov 18 16:07:54 2015 -0700 fsp1_0: Update Kconfig for symbols not depending on FSP binary There were several symbols that were inside the 'if HAVE_FSP_BIN' that don't really depend on having the FSP binary. In theory, we should be able to build a coreboot rom and add the FSP binary later. This doesn't always work in practice, but this is a step in that direction. This also fixes a Kconfig warning for Rangeley. Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12461 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12461 for details. -gerrit

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Patch merged into coreboot/master: google/rambi: Fix end comment in Kconfig
by gerrit＠coreboot.org 23 Nov '15

23 Nov '15

the following patch was just integrated into master: commit 40d073c3c5d17aa877dc08f8ec600979ed155363 Author: Martin Roth <martinroth(a)google.com> Date: Fri Nov 20 08:52:28 2015 -0700 google/rambi: Fix end comment in Kconfig Change-Id: I3963d145f6d209e32256268259e93103c62809c5 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: http://review.coreboot.org/12504 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc(a)marcjonesconsulting.com> See http://review.coreboot.org/12504 for details. -gerrit

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Patch merged into coreboot/master: IASL: Enable warnings as errors
by gerrit＠coreboot.org 23 Nov '15

23 Nov '15

the following patch was just integrated into master: commit 77c67b3d30d070aa0ddb016d99ce2f1a28cac633 Author: Martin Roth <gaumless(a)gmail.com> Date: Thu Jun 25 09:36:27 2015 -0600 IASL: Enable warnings as errors We've actually got more warnings now than when I first tested IASL warnings as errors. Because of this, I'm adding it with the option to have it disabled, in hopes that things won't get any worse as we work on fixing the IASL warnings that are currently in the codebase. - Enable IASL warnings as errors - Disable warnings as errors in mainboards that currently have warnings. - Print a really obnoxious message on those platforms when they build. ***** WARNING: IASL warnings as errors is disabled! ***** ***** Please fix the ASL for this platform. ***** Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: http://review.coreboot.org/10663 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/10663 for details. -gerrit

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Patch merged into coreboot/master: amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs
by gerrit＠coreboot.org 23 Nov '15

23 Nov '15

the following patch was just integrated into master: commit 845b00ce3344d1483d98cddcf59f317a1b96da64 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 7 19:05:29 2015 -0500 amd/amdmct/mct_ddr3: Fix poor performance on Family 15h CPUs Change-Id: Ib6bc197e43e40ba2b923b1eb1229bacafc8be360 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12029 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/12029 for details. -gerrit

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Patch set updated for coreboot: northbridge/amd/amdfam10: Fix invalid NUMA table
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12035 -gerrit commit 47ae50935982ec78da349cf74d997fed846b05f3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Aug 8 02:40:58 2015 -0500 northbridge/amd/amdfam10: Fix invalid NUMA table The existing code generated an invalid NUMA table that was rejected by Linux, leading to poor resource allocation. This was due to system I/O resources being inserted into the table when the table should only contain DRAM resources. Do not include system I/O resources (i.e. resources with an index less than 0x10) in the NUMA table. Change-Id: I99c200382b52a99687daf266a84873d9ae2df025 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/acpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index ad54abd..25df6b3 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -102,7 +102,8 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) } // need to figure out NV - state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); + if (res->index > 0xf) + state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); } static unsigned long acpi_fill_srat(unsigned long current)

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coreboot-gerrit November 2015