coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: cpu/amd/fam15h: Set up Link Base Channel Buffer Count registers
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12038 -gerrit commit 2092a2c7c820ca82b397d4dca45880993f02cdb4 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Aug 8 20:30:36 2015 -0500 cpu/amd/fam15h: Set up Link Base Channel Buffer Count registers Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 131 +++++++++++++++++++++++++- 1 file changed, 127 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 439e4fa..55df7a4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1201,6 +1201,133 @@ static void cpuSetAMDPCI(u8 node) dword |= (compute_unit_buffer_count << 4); pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); + uint8_t link; + uint8_t ganged; + uint8_t iolink; + uint8_t probe_filter_enabled = !!dual_node; + + /* Set up the Link Base Channel Buffer Count */ + uint8_t isoc_rsp_data; + uint8_t isoc_np_req_data; + uint8_t isoc_rsp_cmd; + uint8_t isoc_preq; + uint8_t isoc_np_req_cmd; + uint8_t free_data; + uint8_t free_cmd; + uint8_t rsp_data; + uint8_t np_req_data; + uint8_t probe_cmd; + uint8_t rsp_cmd; + uint8_t preq; + uint8_t np_req_cmd; + + /* Common settings for all links and system configurations */ + isoc_rsp_data = 0; + isoc_np_req_data = 0; + isoc_rsp_cmd = 0; + isoc_preq = 0; + isoc_np_req_cmd = 1; + free_cmd = 8; + + for (link = 0; link < 4; link++) { + if (AMD_CpuFindCapability(node, link, &offset)) { + ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); + iolink = (AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); + + if (!iolink && ganged) { + if (probe_filter_enabled) { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 4; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 8; + } else { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 8; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 4; + } + } else if (!iolink && !ganged) { + if (probe_filter_enabled) { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 4; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 8; + } else { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 8; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 4; + } + } else if (iolink && ganged) { + free_data = 0; + rsp_data = 1; + np_req_data = 0; + probe_cmd = 0; + rsp_cmd = 2; + preq = 7; + np_req_cmd = 14; + } else { + /* FIXME + * This is an educated guess as the BKDG does not specify + * the appropriate buffer counts for this case! + */ + free_data = 1; + rsp_data = 1; + np_req_data = 1; + probe_cmd = 0; + rsp_cmd = 2; + preq = 4; + np_req_cmd = 12; + } + + dword = pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x94); + dword &= ~(0x3 << 27); /* IsocRspData = isoc_rsp_data */ + dword |= ((isoc_rsp_data & 0x3) << 27); + dword &= ~(0x3 << 25); /* IsocNpReqData = isoc_np_req_data */ + dword |= ((isoc_np_req_data & 0x3) << 25); + dword &= ~(0x7 << 22); /* IsocRspCmd = isoc_rsp_cmd */ + dword |= ((isoc_rsp_cmd & 0x7) << 22); + dword &= ~(0x7 << 19); /* IsocPReq = isoc_preq */ + dword |= ((isoc_preq & 0x7) << 19); + dword &= ~(0x7 << 16); /* IsocNpReqCmd = isoc_np_req_cmd */ + dword |= ((isoc_np_req_cmd & 0x7) << 16); + pci_write_config32(NODE_PCI(node, 0), (link * 0x20) + 0x94, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x90); + dword &= ~(0x1 << 31); /* LockBc = 0x1 */ + dword |= ((0x1 & 0x1) << 31); + dword &= ~(0x7 << 25); /* FreeData = free_data */ + dword |= ((free_data & 0x7) << 25); + dword &= ~(0x1f << 20); /* FreeCmd = free_cmd */ + dword |= ((free_cmd & 0x1f) << 20); + dword &= ~(0x3 << 18); /* RspData = rsp_data */ + dword |= ((rsp_data & 0x3) << 18); + dword &= ~(0x3 << 16); /* NpReqData = np_req_data */ + dword |= ((np_req_data & 0x3) << 16); + dword &= ~(0xf << 12); /* ProbeCmd = probe_cmd */ + dword |= ((probe_cmd & 0xf) << 12); + dword &= ~(0xf << 8); /* RspCmd = rsp_cmd */ + dword |= ((rsp_cmd & 0xf) << 8); + dword &= ~(0x7 << 5); /* PReq = preq */ + dword |= ((preq & 0x7) << 5); + dword &= ~(0x1f << 0); /* NpReqCmd = np_req_cmd */ + dword |= ((np_req_cmd & 0x1f) << 0); + pci_write_config32(NODE_PCI(node, 0), (link * 0x20) + 0x90, dword); + } + } + /* Set up the Link to XCS Token Counts */ uint8_t isoc_rsp_tok_1; uint8_t isoc_preq_tok_1; @@ -1218,10 +1345,6 @@ static void cpuSetAMDPCI(u8 node) uint8_t preq_tok_0; uint8_t req_tok_0; - uint8_t link; - uint8_t ganged; - uint8_t iolink; - uint8_t probe_filter_enabled = !!dual_node; for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1);

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Patch set updated for coreboot: northbridge/amd/amdfam10: Fix invalid NUMA table
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12035 -gerrit commit 616bb984f2f665e9a0dcb31d1bd52a7d8faf4577 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Aug 8 02:40:58 2015 -0500 northbridge/amd/amdfam10: Fix invalid NUMA table The existing code generated an invalid NUMA table that was rejected by Linux, leading to poor resource allocation. This was due to system MMIO resources being inserted into the table when the table should only contain DRAM resources. Do not include system MMIO resources (i.e. resources with an index less than 0x10) in the NUMA table. Change-Id: I99c200382b52a99687daf266a84873d9ae2df025 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/acpi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdfam10/acpi.c b/src/northbridge/amd/amdfam10/acpi.c index ad54abd..960d468 100644 --- a/src/northbridge/amd/amdfam10/acpi.c +++ b/src/northbridge/amd/amdfam10/acpi.c @@ -102,7 +102,8 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res) } // need to figure out NV - state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); + if (res->index > 0xf) /* Exclude MMIO resources, e.g. as set in northbridge.c amdfam10_domain_read_resources() */ + state->current += acpi_create_srat_mem((acpi_srat_mem_t *)state->current, (res->index & 0xf), basek, sizek, 1); } static unsigned long acpi_fill_srat(unsigned long current)

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add several nvram configuration options
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12048 -gerrit commit f53aca8d1892061c4e344c75996ae1fa907c9119 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:53:45 2015 -0500 mainboard/asus/kgpe-d16: Add several nvram configuration options Change-Id: I45b04e8fbdfc65603e1057f7b0e5a13d073fe348 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 7 ++++--- src/mainboard/asus/kgpe-d16/devicetree.cb | 1 + src/mainboard/asus/kgpe-d16/romstage.c | 2 ++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 9e36690..b5e9f07 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -3,7 +3,7 @@ debug_level = Spew multi_core = Enable slow_cpu = off compute_unit_siblings = Enable -iommu = Disable +iommu = Enable nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 @@ -23,6 +23,7 @@ maximum_p_state_limit = 0xf probe_filter = Auto l3_cache_partitioning = Disable ieee1394_controller = Enable +gart = Disable experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index a34547a..d1c0702 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -46,9 +46,10 @@ entries 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning -477 1 e 1 experimental_memory_speed_boost -478 1 r 0 allow_spd_nvram_cache_restore -479 1 e 1 ieee1394_controller +477 1 e 1 ieee1394_controller +478 1 e 1 iommu +479 1 e 1 experimental_memory_speed_boost +480 1 r 0 allow_spd_nvram_cache_restore 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index ef7277d..014a35f 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -15,6 +15,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex chip southbridge/amd/sr5650 # Primary southbridge device pci 0.0 on end # HT Root Complex 0x9600 device pci 0.1 on end # CLKCONFIG + device pci 0.2 on end # IOMMU device pci 2.0 on # PCIE P2P bridge 0x9603 (GPP1 Port0) # Slot # PCI E 1 / PCI E 2 end diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 6503b90..ccb85f4 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -458,6 +458,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) die("After soft_reset_x - shouldn't see this message!!!\n"); } + sr5650_htinit_dect_and_enable_isochronous_link(); + /* Set default DDR memory voltage * This will be overridden later during RAM initialization */

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Patch set updated for coreboot: cpu/amd/family_10h-family_15h: Set up Family 15h Link Base Channel Buffer Count registers
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12038 -gerrit commit 5976e9f0d62d6a84c83b73bc90fd5bc7fdaacbe3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Aug 8 20:30:36 2015 -0500 cpu/amd/family_10h-family_15h: Set up Family 15h Link Base Channel Buffer Count registers Change-Id: I8d616a64a5a9cf0b51288535f5050c6866d0996b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 131 +++++++++++++++++++++++++- 1 file changed, 127 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 439e4fa..55df7a4 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1201,6 +1201,133 @@ static void cpuSetAMDPCI(u8 node) dword |= (compute_unit_buffer_count << 4); pci_write_config32(NODE_PCI(node, 3), 0x1a0, dword); + uint8_t link; + uint8_t ganged; + uint8_t iolink; + uint8_t probe_filter_enabled = !!dual_node; + + /* Set up the Link Base Channel Buffer Count */ + uint8_t isoc_rsp_data; + uint8_t isoc_np_req_data; + uint8_t isoc_rsp_cmd; + uint8_t isoc_preq; + uint8_t isoc_np_req_cmd; + uint8_t free_data; + uint8_t free_cmd; + uint8_t rsp_data; + uint8_t np_req_data; + uint8_t probe_cmd; + uint8_t rsp_cmd; + uint8_t preq; + uint8_t np_req_cmd; + + /* Common settings for all links and system configurations */ + isoc_rsp_data = 0; + isoc_np_req_data = 0; + isoc_rsp_cmd = 0; + isoc_preq = 0; + isoc_np_req_cmd = 1; + free_cmd = 8; + + for (link = 0; link < 4; link++) { + if (AMD_CpuFindCapability(node, link, &offset)) { + ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1); + iolink = (AMD_checkLinkType(node, link, offset) & HTPHY_LINKTYPE_NONCOHERENT); + + if (!iolink && ganged) { + if (probe_filter_enabled) { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 4; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 8; + } else { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 8; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 4; + } + } else if (!iolink && !ganged) { + if (probe_filter_enabled) { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 4; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 8; + } else { + free_data = 0; + rsp_data = 3; + np_req_data = 3; + probe_cmd = 8; + rsp_cmd = 9; + preq = 2; + np_req_cmd = 4; + } + } else if (iolink && ganged) { + free_data = 0; + rsp_data = 1; + np_req_data = 0; + probe_cmd = 0; + rsp_cmd = 2; + preq = 7; + np_req_cmd = 14; + } else { + /* FIXME + * This is an educated guess as the BKDG does not specify + * the appropriate buffer counts for this case! + */ + free_data = 1; + rsp_data = 1; + np_req_data = 1; + probe_cmd = 0; + rsp_cmd = 2; + preq = 4; + np_req_cmd = 12; + } + + dword = pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x94); + dword &= ~(0x3 << 27); /* IsocRspData = isoc_rsp_data */ + dword |= ((isoc_rsp_data & 0x3) << 27); + dword &= ~(0x3 << 25); /* IsocNpReqData = isoc_np_req_data */ + dword |= ((isoc_np_req_data & 0x3) << 25); + dword &= ~(0x7 << 22); /* IsocRspCmd = isoc_rsp_cmd */ + dword |= ((isoc_rsp_cmd & 0x7) << 22); + dword &= ~(0x7 << 19); /* IsocPReq = isoc_preq */ + dword |= ((isoc_preq & 0x7) << 19); + dword &= ~(0x7 << 16); /* IsocNpReqCmd = isoc_np_req_cmd */ + dword |= ((isoc_np_req_cmd & 0x7) << 16); + pci_write_config32(NODE_PCI(node, 0), (link * 0x20) + 0x94, dword); + + dword = pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x90); + dword &= ~(0x1 << 31); /* LockBc = 0x1 */ + dword |= ((0x1 & 0x1) << 31); + dword &= ~(0x7 << 25); /* FreeData = free_data */ + dword |= ((free_data & 0x7) << 25); + dword &= ~(0x1f << 20); /* FreeCmd = free_cmd */ + dword |= ((free_cmd & 0x1f) << 20); + dword &= ~(0x3 << 18); /* RspData = rsp_data */ + dword |= ((rsp_data & 0x3) << 18); + dword &= ~(0x3 << 16); /* NpReqData = np_req_data */ + dword |= ((np_req_data & 0x3) << 16); + dword &= ~(0xf << 12); /* ProbeCmd = probe_cmd */ + dword |= ((probe_cmd & 0xf) << 12); + dword &= ~(0xf << 8); /* RspCmd = rsp_cmd */ + dword |= ((rsp_cmd & 0xf) << 8); + dword &= ~(0x7 << 5); /* PReq = preq */ + dword |= ((preq & 0x7) << 5); + dword &= ~(0x1f << 0); /* NpReqCmd = np_req_cmd */ + dword |= ((np_req_cmd & 0x1f) << 0); + pci_write_config32(NODE_PCI(node, 0), (link * 0x20) + 0x90, dword); + } + } + /* Set up the Link to XCS Token Counts */ uint8_t isoc_rsp_tok_1; uint8_t isoc_preq_tok_1; @@ -1218,10 +1345,6 @@ static void cpuSetAMDPCI(u8 node) uint8_t preq_tok_0; uint8_t req_tok_0; - uint8_t link; - uint8_t ganged; - uint8_t iolink; - uint8_t probe_filter_enabled = !!dual_node; for (link = 0; link < 4; link++) { if (AMD_CpuFindCapability(node, link, &offset)) { ganged = !!(pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170) & 0x1);

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Patch set updated for coreboot: northbridge/amd/amdfam10: Add Family 15h cache partitioning support
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12036 -gerrit commit 0caa25c08b3c46ade8e800eae4b2e98d8abc6e13 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sat Aug 8 20:29:27 2015 -0500 northbridge/amd/amdfam10: Add Family 15h cache partitioning support Certain workloads may evict too many lines of other cores from the L3 cache if configured as one monolithic shared cache region. Forcibly partition L3 cache to improve performance. Change-Id: Ie4e28dd886aaa1c586b0919c5fe87ef1696f47e9 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 94 ++++++++++++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 17dabae..ced64aa 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1805,9 +1805,103 @@ static void detect_and_enable_probe_filter(device_t dev) } } +static void detect_and_enable_cache_partitioning(device_t dev) +{ + uint8_t i; + uint32_t dword; + + if (is_fam15h()) { + printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n"); + + uint32_t f5x80; + uint8_t cu_enabled; + uint8_t compute_unit_count = 0; + + uint32_t f3xe8; + uint8_t dual_node = 0; + + for (i = 0; i < sysconf.nodes; i++) { + device_t f3x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 3)); + device_t f4x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 4)); + device_t f5x_dev = dev_find_slot(0, PCI_DEVFN(0x18 + i, 5)); + + f3xe8 = pci_read_config32(f3x_dev, 0xe8); + + /* Check for dual node capability */ + if (f3xe8 & 0x20000000) + dual_node = 1; + + /* Determine the number of active compute units on this node */ + f5x80 = pci_read_config32(f5x_dev, 0x80); + cu_enabled = f5x80 & 0xf; + if (cu_enabled == 0x1) + compute_unit_count = 1; + if (cu_enabled == 0x3) + compute_unit_count = 2; + if (cu_enabled == 0x7) + compute_unit_count = 3; + if (cu_enabled == 0xf) + compute_unit_count = 4; + + /* Disable BAN mode */ + dword = pci_read_config32(f3x_dev, 0x1b8); + dword &= ~(0x7 << 19); /* L3BanMode = 0x0 */ + pci_write_config32(f3x_dev, 0x1b8, dword); + + /* Set up cache mapping */ + dword = pci_read_config32(f4x_dev, 0x1d4); + if (compute_unit_count == 1) { + dword |= 0xf; /* ComputeUnit0SubCacheEn = 0xf */ + } + if (compute_unit_count == 2) { + dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0xc */ + dword |= (0xc << 4); + dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x3 */ + dword |= 0x3; + } + if (compute_unit_count == 3) { + dword &= ~(0xf << 8); /* ComputeUnit2SubCacheEn = 0x8 */ + dword |= (0x8 << 8); + dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0x4 */ + dword |= (0x4 << 4); + dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x3 */ + dword |= 0x3; + } + if (compute_unit_count == 4) { + dword &= ~(0xf << 12); /* ComputeUnit3SubCacheEn = 0x8 */ + dword |= (0x8 << 12); + dword &= ~(0xf << 8); /* ComputeUnit2SubCacheEn = 0x4 */ + dword |= (0x4 << 8); + dword &= ~(0xf << 4); /* ComputeUnit1SubCacheEn = 0x2 */ + dword |= (0x2 << 4); + dword &= ~0xf; /* ComputeUnit0SubCacheEn = 0x1 */ + dword |= 0x1; + } + pci_write_config32(f4x_dev, 0x1d4, dword); + + /* Enable cache partitioning */ + pci_write_config32(f4x_dev, 0x1d4, dword); + if (compute_unit_count == 1) { + dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x1 */ + dword |= (0x1 << 26); + } else if (compute_unit_count == 2) { + dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x3 */ + dword |= (0x3 << 26); + } else if (compute_unit_count == 3) { + dword &= ~(0xf << 26); /* MaskUpdateForComputeUnit = 0x7 */ + dword |= (0x7 << 26); + } else if (compute_unit_count == 4) { + dword |= (0xf << 26); /* MaskUpdateForComputeUnit = 0xf */ + } + pci_write_config32(f4x_dev, 0x1d4, dword); + } + } +} + static void cpu_bus_init(device_t dev) { detect_and_enable_probe_filter(dev); + detect_and_enable_cache_partitioning(dev); initialize_cpus(dev->link_list); #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init();

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Patch set updated for coreboot: arch/x86/acpi: Add IVRS table generation routines
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12043 -gerrit commit a77119ea5ba47ea6b37f3dd92e3fd60f456f61a2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:48:32 2015 -0500 arch/x86/acpi: Add IVRS table generation routines Change-Id: Ia5d97d01dc9ddc45f81d998d126d592a915b4a75 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/arch/x86/acpi.c | 25 +++++++++++++++++++++++++ src/arch/x86/include/arch/acpi.h | 31 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index c540b5c..ccaab9e 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -6,6 +6,7 @@ * * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2005-2009 coresystems GmbH + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * * ACPI FADT, FACS, and DSDT table support added by * Nick Barker <nick.barker9(a)btinternet.com>, and those portions @@ -531,6 +532,30 @@ void acpi_create_hpet(acpi_hpet_t *hpet) header->checksum = acpi_checksum((void *)hpet, sizeof(acpi_hpet_t)); } +void acpi_create_ivrs(acpi_ivrs_t *ivrs, + unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)) +{ + acpi_header_t *header = &(ivrs->header); + unsigned long current = (unsigned long)ivrs + sizeof(acpi_ivrs_t); + + memset((void *)ivrs, 0, sizeof(acpi_ivrs_t)); + + /* Fill out header fields. */ + memcpy(header->signature, "IVRS", 4); + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + + header->length = sizeof(acpi_ivrs_t); + header->revision = 1; /* ACPI 1.0: N/A, ACPI 2.0/3.0/4.0: 1 */ + + current = acpi_fill_ivrs(ivrs, current); + + /* (Re)calculate length and checksum. */ + header->length = current - (unsigned long)ivrs; + header->checksum = acpi_checksum((void *)ivrs, header->length); +} + unsigned long acpi_write_hpet(device_t device, unsigned long current, acpi_rsdp_t *rsdp) { acpi_hpet_t *hpet; diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 87810b6..79ae7ed 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -4,6 +4,7 @@ * Copyright (C) 2004 SUSE LINUX AG * Copyright (C) 2004 Nick Barker * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * (Written by Stefan Reinauer <stepan(a)coresystems.de>) * * This program is free software; you can redistribute it and/or modify @@ -190,6 +191,32 @@ typedef struct acpi_madt { u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; +typedef struct acpi_ivrs_info { +} __attribute__ ((packed)) acpi_ivrs_info_t; + +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) */ +typedef struct acpi_ivrs_ivhd { + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + uint32_t efr; + uint8_t entry[0]; +} __attribute__ ((packed)) acpi_ivrs_ivhd_t; + +/* IVRS (I/O Virtualization Reporting Structure) */ +typedef struct acpi_ivrs { + struct acpi_table_header header; + uint32_t iv_info; + uint32_t reserved[2]; + struct acpi_ivrs_ivhd ivhd; +} __attribute__ ((packed)) acpi_ivrs_t; + enum dev_scope_type { SCOPE_PCI_ENDPOINT = 1, SCOPE_PCI_SUB = 2, @@ -498,6 +525,7 @@ unsigned long fw_cfg_acpi_tables(unsigned long start); unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_mcfg(unsigned long current); +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); #if IS_ENABLED(CONFIG_COMMON_FADT) @@ -536,6 +564,9 @@ void acpi_create_srat(acpi_srat_t *srat, void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)); +void acpi_create_ivrs(acpi_ivrs_t *ivrs, + unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t* ivrs_struct, unsigned long current)); + #if ENV_RAMSTAGE void acpi_create_hpet(acpi_hpet_t *hpet); unsigned long acpi_write_hpet(device_t device, unsigned long start, acpi_rsdp_t *rsdp);

1 0

Patch set updated for coreboot: northbridge/amd/amdht: Add isochronous setup support for coherent fabric
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12042 -gerrit commit 453c24e4bc26c19611287f01b9bbeba784062605 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:47:48 2015 -0500 northbridge/amd/amdht: Add isochronous setup support for coherent fabric Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 61 +++++++++++++++++++++++++++ src/northbridge/amd/amdht/h3ffeat.h | 3 ++ src/northbridge/amd/amdht/h3finit.c | 35 ++++++++++++++- src/northbridge/amd/amdht/h3finit.h | 4 +- src/northbridge/amd/amdht/h3ncmn.c | 30 ++++++++++++- 5 files changed, 129 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index da45888..635f357 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1666,6 +1666,67 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), 0x140, dword); } + uint8_t link; + uint8_t isochronous; + uint8_t isochronous_link_present; + + /* Set up isochronous buffers if needed */ + isochronous_link_present = 0; + if (revision & AMD_FAM15_ALL) { + for (link = 0; link < 4; link++) { + if (AMD_CpuFindCapability(node, link, &offset)) { + isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; + + if (isochronous) + isochronous_link_present = 1; + } + } + } + + uint8_t free_tok; + uint8_t up_rsp_cbc; + uint8_t isoc_preq_cbc; + uint8_t isoc_preq_tok; + uint8_t xbar_to_sri_free_list_cbc; + if (isochronous_link_present) { + /* Adjust buffer counts */ + dword = pci_read_config32(NODE_PCI(node, 3), 0x70); + isoc_preq_cbc = (dword >> 24) & 0x7; + up_rsp_cbc = (dword >> 16) & 0x7; + up_rsp_cbc--; + isoc_preq_cbc++; + dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */ + dword |= ((isoc_preq_cbc & 0x7) << 24); + dword &= ~(0x7 << 16); /* UpRspCBC = up_rsp_cbc */ + dword |= ((up_rsp_cbc & 0x7) << 16); + pci_write_config32(NODE_PCI(node, 3), 0x70, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0x74); + isoc_preq_cbc = (dword >> 24) & 0x7; + isoc_preq_cbc++; + dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */ + dword |= (isoc_preq_cbc & 0x7) << 24; + pci_write_config32(NODE_PCI(node, 3), 0x74, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0x7c); + xbar_to_sri_free_list_cbc = dword & 0x1f; + xbar_to_sri_free_list_cbc--; + dword &= ~0x1f; /* Xbar2SriFreeListCBC = xbar_to_sri_free_list_cbc */ + dword |= xbar_to_sri_free_list_cbc & 0x1f; + pci_write_config32(NODE_PCI(node, 3), 0x7c, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0x140); + free_tok = (dword >> 20) & 0xf; + isoc_preq_tok = (dword >> 14) & 0x3; + free_tok--; + isoc_preq_tok++; + dword &= ~(0xf << 20); /* FreeTok = free_tok */ + dword |= ((free_tok & 0xf) << 20); + dword &= ~(0x3 << 14); /* IsocPreqTok = isoc_preq_tok */ + dword |= ((isoc_preq_tok & 0x3) << 14); + pci_write_config32(NODE_PCI(node, 3), 0x140, dword); + } + printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index 628b86e..bcd4c10 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -75,6 +75,7 @@ #define HTSLAVE_LINK01_OFFSET 4 #define HTSLAVE_LINK_CONTROL_0_REG 4 #define HTSLAVE_FREQ_REV_0_REG 0xC +#define HTSLAVE_FEATURE_CAP_REG 0x10 /* HT3 gen Capability */ #define IS_HT_GEN3_CAPABILITY(reg) \ @@ -122,10 +123,12 @@ typedef struct u8 SelWidthIn; u8 SelWidthOut; u8 SelFrequency; + uint8_t enable_isochronous_mode; /* This section is for keeping track of capabilities and possible configurations */ BOOL RegangCap; uint32_t PrvFrequencyCap; + uint32_t PrvFeatureCap; u8 PrvWidthInCap; u8 PrvWidthOutCap; uint32_t CompositeFrequencyCap; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index e4ce768..6a45f10 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1415,6 +1415,38 @@ static void regangLinks(sMainData *pDat) #endif /* HT_BUILD_NC_ONLY */ } +static void detectIoLinkIsochronousCapable(sMainData *pDat) +{ + uint8_t i; + unsigned char iommu; + uint8_t isochronous_capable = 0; + + iommu = 1; + get_option(&iommu, "iommu"); + + for (i = 0; i < pDat->TotalLinks*2; i += 2) { + if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_IO)) { + if ((pDat->PortList[i].PrvFeatureCap & 0x1) && (pDat->PortList[i+1].PrvFeatureCap & 0x1)) { + pDat->PortList[i].enable_isochronous_mode = 1; + pDat->PortList[i+1].enable_isochronous_mode = 1; + isochronous_capable = 1; + } else { + pDat->PortList[i].enable_isochronous_mode = 0; + pDat->PortList[i+1].enable_isochronous_mode = 0; + } + } + } + + if (isochronous_capable && iommu) { + printk(BIOS_DEBUG, "Forcing HT links to isochronous mode due to enabled IOMMU\n"); + /* Isochronous mode must be set on all links if the IOMMU is enabled */ + for (i = 0; i < pDat->TotalLinks*2; i += 2) { + pDat->PortList[i].enable_isochronous_mode = 1; + pDat->PortList[i+1].enable_isochronous_mode = 1; + } + } +} + /*---------------------------------------------------------------------------------------- * void * selectOptimalWidthAndFrequency(sMainData *pDat) @@ -1535,7 +1567,6 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) temp = cbPCBBAUpstreamWidth; pDat->PortList[i].SelWidthIn = (u8)temp; pDat->PortList[i+1].SelWidthOut = (u8)temp; - } } @@ -1697,6 +1728,8 @@ static void linkOptimization(sMainData *pDat) { pDat->nb->gatherLinkData(pDat, pDat->nb); regangLinks(pDat); + if (is_fam15h()) + detectIoLinkIsochronousCapable(pDat); selectOptimalWidthAndFrequency(pDat); hammerSublinkFixup(pDat); pDat->nb->setLinkData(pDat, pDat->nb); diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index 1bd8616..ab2dace 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -227,6 +227,7 @@ typedef struct { * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out * @param[in,out] u32* FreqCap = modify to change the link's frequency capability + * @param[in,out] u32* FeatureCap = modify to change the link's feature capability * * --------------------------------------------------------------------------------------- */ @@ -241,7 +242,8 @@ typedef struct { u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut, - u32 *FreqCap + u32 *FreqCap, + u32 *FeatureCap ); /**---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index c97d592..7937c6e 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1429,12 +1429,15 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) temp &= 0x7; /* Mask off reserved values */ pDat->PortList[i].PrvFrequencyCap |= (temp << 17); } + + AmdPCIReadBits(linkBase + HTHOST_FEATURE_CAP_REG, 9, 0, &temp); + pDat->PortList[i].PrvFeatureCap = (u16)temp; } else { linkBase = pDat->PortList[i].Pointer; if (pDat->PortList[i].Link == 1) - linkBase += HTSLAVE_LINK01_OFFSET; + linkBase += HTSLAVE_LINK01_OFFSET; AmdPCIReadBits(linkBase + HTSLAVE_LINK_CONTROL_0_REG, 22, 20, &temp); pDat->PortList[i].PrvWidthOutCap = convertBitsToWidth((u8)temp, pDat->nb); @@ -1445,6 +1448,9 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) AmdPCIReadBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 31, 16, &temp); pDat->PortList[i].PrvFrequencyCap = (u16)temp; + AmdPCIReadBits(linkBase + HTSLAVE_FEATURE_CAP_REG, 7, 0, &temp); + pDat->PortList[i].PrvFeatureCap = (u16)temp; + if (pDat->HtBlock->AMD_CB_DeviceCapOverride) { linkBase &= 0xFFFFF000; @@ -1461,7 +1467,8 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) pDat->PortList[i].Link, &(pDat->PortList[i].PrvWidthInCap), &(pDat->PortList[i].PrvWidthOutCap), - &(pDat->PortList[i].PrvFrequencyCap)); + &(pDat->PortList[i].PrvFrequencyCap), + &(pDat->PortList[i].PrvFeatureCap)); } } } @@ -1562,6 +1569,16 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) if (is_gt_rev_d()) AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); + + /* Enable isochronous flow control mode if supported by chipset */ + if (is_fam15h()) { + if (pDat->PortList[i].enable_isochronous_mode) + temp = 1; + else + temp = 0; + setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 12, 12, &temp); + } + if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */ { /* Enable for Gen3 frequencies */ @@ -1579,6 +1596,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) CPU_HTNB_FUNC_00, REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), 0, 0, &temp); + /* and Scrambling enable / disable */ AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), makePCIBusFromNode(pDat->PortList[i].NodeID), @@ -1617,6 +1635,14 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) bits = 0; } + /* Enable isochronous flow control mode if supported by chipset */ + if (is_fam15h()) { + if (pDat->PortList[i].enable_isochronous_mode) + temp = 1; + else + temp = 0; + } + /* Retry Enable */ isFound = FALSE; currentPtr = linkBase & (u32)0xFFFFF000; /* Set PCI Offset to 0 */

1 0

Patch set updated for coreboot: amd/amdfam10: Control Family 15h cache partitioning and memory performance via nvram
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12041 -gerrit commit 053da50233c70a655ed61818524eeedcd49f2685 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 9 02:47:51 2015 -0500 amd/amdfam10: Control Family 15h cache partitioning and memory performance via nvram Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 5 ++--- src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 ++++++++++++++-- src/mainboard/asus/kgpe-d16/cmos.default | 3 +++ src/mainboard/asus/kgpe-d16/cmos.layout | 9 +++++++-- src/northbridge/amd/amdfam10/northbridge.c | 22 ++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 ++++++++++- 6 files changed, 58 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index d4999b9..7fd115c 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -135,9 +135,8 @@ static const struct { 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ { BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL, - (0x3 << 20) | (0x1 << 22), 0x00000000, - (0x3 << 20) | (0x1 << 22), 0x00000000}, /* C0 or above [PfcDoubleStride]=1, - PfcStrideMul]=0x3 */ + 1 << 22, 0x00000000, + 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, 0x00000000, 1 << (54-32), diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 55df7a4..da45888 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -953,6 +953,7 @@ void cpuSetAMDMSR(uint8_t node_id) */ msr_t msr; u8 i; + uint8_t nvram; u32 platform; uint64_t revision; uint8_t enable_c_states; @@ -977,6 +978,13 @@ void cpuSetAMDMSR(uint8_t node_id) /* Revision C0 and above */ if (revision & AMD_OR_C0) { + uint8_t enable_experimental_memory_speed_boost; + + /* Check to see if cache partitioning is allowed */ + enable_experimental_memory_speed_boost = 0; + if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) + enable_experimental_memory_speed_boost = !!nvram; + uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); msr = rdmsr(FP_CFG); msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */ @@ -996,11 +1004,15 @@ void cpuSetAMDMSR(uint8_t node_id) msr.lo &= ~(0x1 << 16); /* DiDtMode */ msr.lo |= ((f3x1fc & 0x1) << 16); wrmsr(FP_CFG, msr); + + if (enable_experimental_memory_speed_boost) { + msr = rdmsr(BU_CFG3); + msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */ + wrmsr(BU_CFG3, msr); + } } #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) - uint8_t nvram; - if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ msr = rdmsr(0xc0010055); diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 9994dad..9e36690 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -20,6 +20,9 @@ cpu_cc6_state = Enable sata_ahci_mode = Enable sata_alpm = Disable maximum_p_state_limit = 0xf +probe_filter = Auto +l3_cache_partitioning = Disable ieee1394_controller = Enable +experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index e17fec6..648091a 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -44,8 +44,11 @@ entries 468 1 e 1 sata_alpm 469 4 h 0 maximum_p_state_limit 473 2 e 13 dimm_spd_checksum -475 1 r 0 allow_spd_nvram_cache_restore -477 1 e 1 ieee1394_controller +475 1 e 14 probe_filter +476 1 e 1 l3_cache_partitioning +477 1 e 1 experimental_memory_speed_boost +478 1 r 0 allow_spd_nvram_cache_restore +479 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -142,6 +145,8 @@ enumerations 13 0 Enforce 13 1 Ignore 13 2 Override +14 0 Disable +14 1 Auto checksums diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index ced64aa..600fdf8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1650,6 +1650,17 @@ static void detect_and_enable_probe_filter(device_t dev) { uint32_t dword; + uint8_t nvram; + uint8_t enable_probe_filter; + + /* Check to see if the probe filter is allowed */ + enable_probe_filter = 1; + if (get_option(&nvram, "probe_filter") == CB_SUCCESS) + enable_probe_filter = !!nvram; + + if (!enable_probe_filter) + return; + uint8_t fam15h = 0; uint8_t rev_gte_d = 0; uint8_t dual_node = 0; @@ -1810,6 +1821,17 @@ static void detect_and_enable_cache_partitioning(device_t dev) uint8_t i; uint32_t dword; + uint8_t nvram; + uint8_t enable_l3_cache_partitioning; + + /* Check to see if cache partitioning is allowed */ + enable_l3_cache_partitioning = 0; + if (get_option(&nvram, "l3_cache_partitioning") == CB_SUCCESS) + enable_l3_cache_partitioning = !!nvram; + + if (!enable_l3_cache_partitioning) + return; + if (is_fam15h()) { printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n"); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index aad813a..a6cc70f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5559,6 +5559,14 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, mct_ExtMCTConfig_Dx(pDCTstat); } else { /* Family 15h CPUs */ + uint8_t nvram; + uint8_t enable_experimental_memory_speed_boost; + + /* Check to see if cache partitioning is allowed */ + enable_experimental_memory_speed_boost = 0; + if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) + enable_experimental_memory_speed_boost = !!nvram; + val = 0x0ce00f00; /* FlushWrOnStpGnt = 0x0 */ val |= 0x10 << 2; /* MctWrLimit = 0x10 */ val |= 0x1; /* DctWrLimit = 0x1 */ @@ -5572,7 +5580,8 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ val |= (0x1 << 8); val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ - val |= (0x1 << 20); /* DblPrefEn = 0x1 */ + if (enable_experimental_memory_speed_boost) + val |= (0x1 << 20); /* DblPrefEn = 0x1 */ val |= (0x7 << 22); /* PrefFourConf = 0x7 */ val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Fix gart setup not working on Family 15h processors
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12047 -gerrit commit efd5eacd1067a27e89fc546e31bc41be8e1bc2f5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:52:31 2015 -0500 northbridge/amd/amdfam10: Fix gart setup not working on Family 15h processors Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 34 ++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index ed932a9..0b312b1 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -73,7 +73,7 @@ static void mcf3_read_resources(device_t dev) } } -static void set_agp_aperture(device_t dev) +static void set_agp_aperture(device_t dev, uint32_t pci_id) { struct resource *resource; @@ -93,7 +93,7 @@ static void set_agp_aperture(device_t dev) /* Update the other northbriges */ pdev = 0; - while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1203, pdev))) { + while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, pci_id, pdev))) { /* Store the GART size but don't enable it */ pci_write_config32(pdev, 0x90, gart_acr); @@ -109,10 +109,19 @@ static void set_agp_aperture(device_t dev) } } -static void mcf3_set_resources(device_t dev) +static void mcf3_set_resources_fam10h(device_t dev) { /* Set the gart apeture */ - set_agp_aperture(dev); + set_agp_aperture(dev, 0x1203); + + /* Set the generic PCI resources */ + pci_dev_set_resources(dev); +} + +static void mcf3_set_resources_fam15h(device_t dev) +{ + /* Set the gart apeture */ + set_agp_aperture(dev, 0x1603); /* Set the generic PCI resources */ pci_dev_set_resources(dev); @@ -151,9 +160,18 @@ static void misc_control_init(struct device *dev) } -static struct device_operations mcf3_ops = { +static struct device_operations mcf3_ops_fam10h = { + .read_resources = mcf3_read_resources, + .set_resources = mcf3_set_resources_fam10h, + .enable_resources = pci_dev_enable_resources, + .init = misc_control_init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static struct device_operations mcf3_ops_fam15h = { .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources, + .set_resources = mcf3_set_resources_fam15h, .enable_resources = pci_dev_enable_resources, .init = misc_control_init, .scan_bus = 0, @@ -161,13 +179,13 @@ static struct device_operations mcf3_ops = { }; static const struct pci_driver mcf3_driver __pci_driver = { - .ops = &mcf3_ops, + .ops = &mcf3_ops_fam10h, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1203, }; static const struct pci_driver mcf3_driver_fam15 __pci_driver = { - .ops = &mcf3_ops, + .ops = &mcf3_ops_fam15h, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1603, };

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12046 -gerrit commit 07050f67a514f37707829621b048d45f835da47c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:52:03 2015 -0500 northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/advansus/a785e-i/cmos.layout | 2 +- src/mainboard/amd/bimini_fam10/cmos.layout | 2 +- src/mainboard/amd/mahogany_fam10/cmos.layout | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout | 2 +- src/mainboard/amd/tilapia_fam10/cmos.layout | 2 +- src/mainboard/asus/kfsn4-dre/cmos.layout | 2 +- src/mainboard/asus/kgpe-d16/cmos.layout | 2 +- src/mainboard/asus/m4a78-em/cmos.layout | 2 +- src/mainboard/asus/m4a785-m/cmos.layout | 2 +- src/mainboard/asus/m4a785t-m/cmos.layout | 2 +- src/mainboard/asus/m5a88-v/cmos.layout | 2 +- src/mainboard/avalue/eax-785e/cmos.layout | 2 +- src/mainboard/gigabyte/ma785gm/cmos.layout | 2 +- src/mainboard/gigabyte/ma785gmt/cmos.layout | 2 +- src/mainboard/gigabyte/ma78gm/cmos.layout | 2 +- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 2 +- src/mainboard/iei/kino-780am2-fam10/cmos.layout | 2 +- src/mainboard/jetway/pa78vm5/cmos.layout | 2 +- src/mainboard/msi/ms9652_fam10/cmos.layout | 2 +- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 2 +- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 2 +- src/mainboard/supermicro/h8scm_fam10/cmos.layout | 2 +- src/mainboard/tyan/s2912_fam10/cmos.layout | 2 +- src/northbridge/amd/amdfam10/misc_control.c | 12 ++++++------ 24 files changed, 29 insertions(+), 29 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/cmos.layout b/src/mainboard/advansus/a785e-i/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/advansus/a785e-i/cmos.layout +++ b/src/mainboard/advansus/a785e-i/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/amd/bimini_fam10/cmos.layout b/src/mainboard/amd/bimini_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/amd/bimini_fam10/cmos.layout +++ b/src/mainboard/amd/bimini_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/amd/mahogany_fam10/cmos.layout b/src/mainboard/amd/mahogany_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/amd/mahogany_fam10/cmos.layout +++ b/src/mainboard/amd/mahogany_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/amd/tilapia_fam10/cmos.layout b/src/mainboard/amd/tilapia_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/amd/tilapia_fam10/cmos.layout +++ b/src/mainboard/amd/tilapia_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 66bc3a0..bd5fdbe 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 648091a..a34547a 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 2 e 3 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/asus/m4a78-em/cmos.layout b/src/mainboard/asus/m4a78-em/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m4a78-em/cmos.layout +++ b/src/mainboard/asus/m4a78-em/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/m4a785-m/cmos.layout b/src/mainboard/asus/m4a785-m/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m4a785-m/cmos.layout +++ b/src/mainboard/asus/m4a785-m/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m4a785t-m/cmos.layout +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/m5a88-v/cmos.layout b/src/mainboard/asus/m5a88-v/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m5a88-v/cmos.layout +++ b/src/mainboard/asus/m5a88-v/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/avalue/eax-785e/cmos.layout b/src/mainboard/avalue/eax-785e/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/avalue/eax-785e/cmos.layout +++ b/src/mainboard/avalue/eax-785e/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ma785gm/cmos.layout b/src/mainboard/gigabyte/ma785gm/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/gigabyte/ma785gm/cmos.layout +++ b/src/mainboard/gigabyte/ma785gm/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ma785gmt/cmos.layout b/src/mainboard/gigabyte/ma785gmt/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/gigabyte/ma785gmt/cmos.layout +++ b/src/mainboard/gigabyte/ma785gmt/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ma78gm/cmos.layout b/src/mainboard/gigabyte/ma78gm/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/gigabyte/ma78gm/cmos.layout +++ b/src/mainboard/gigabyte/ma78gm/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 73d53af..5602c70 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection 728 256 h 0 user_data diff --git a/src/mainboard/iei/kino-780am2-fam10/cmos.layout b/src/mainboard/iei/kino-780am2-fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/iei/kino-780am2-fam10/cmos.layout +++ b/src/mainboard/iei/kino-780am2-fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/jetway/pa78vm5/cmos.layout b/src/mainboard/jetway/pa78vm5/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/jetway/pa78vm5/cmos.layout +++ b/src/mainboard/jetway/pa78vm5/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/supermicro/h8scm_fam10/cmos.layout b/src/mainboard/supermicro/h8scm_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/supermicro/h8scm_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8scm_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 847b599..ed932a9 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -38,7 +38,7 @@ * * @param dev * - * There is only one AGP aperture resource needed. The resoruce is added to + * There is only one AGP aperture resource needed. The resource is added to * the northbridge of BSP. * * The same trick can be used to augment legacy VGA resources which can @@ -50,7 +50,7 @@ static void mcf3_read_resources(device_t dev) { struct resource *resource; - unsigned char iommu; + unsigned char gart; /* Read the generic PCI resources */ pci_dev_read_resources(dev); @@ -59,13 +59,13 @@ static void mcf3_read_resources(device_t dev) return; } - iommu = 1; - get_option(&iommu, "iommu"); + gart = 1; + get_option(&gart, "gart"); - if (iommu) { + if (gart) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; + resource->size = gart?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */

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coreboot-gerrit November 2015