coreboot-gerrit November 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: southbridge/amd/sb700: Fix drifting system clock
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12052 -gerrit commit 4188b53af25faafd931fd73a1b2bdca015a664ec Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 28 15:31:31 2015 -0500 southbridge/amd/sb700: Fix drifting system clock Change-Id: I1698c9b9b1840d254115821f3c0e76b7211e9056 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index f109896..f7e9120 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -427,10 +427,10 @@ static void sb700_devices_por_init(void) /* Configure HPET Counter CLK period */ byte = pci_read_config8(dev, 0x43); - byte &= 0xF7; /* unhide HPET regs */ + byte &= 0xF7; /* Unhide HPET regs */ pci_write_config8(dev, 0x43, byte); - pci_write_config32(dev, 0x34, 0x0429B17E ); /* Counter CLK period */ - byte |= 0x08; /* hide HPET regs */ + pci_write_config32(dev, 0x34, 0x0429b17e); /* Counter CLK period */ + byte |= 0x08; /* Hide HPET regs */ pci_write_config8(dev, 0x43, byte); /* Features Enable */ @@ -661,6 +661,14 @@ static void sb700_pmio_por_init(void) byte = pmio_read(0xbb); byte |= 0xc0; pmio_write(0xbb, byte); + +#if CONFIG_SOUTHBRIDGE_AMD_SUBTYPE_SP5100 + /* Work around system clock drift issues */ + byte = pmio_read(0xd4); + byte |= 0x1 << 6; /* Enable alternate 14MHz clock source */ + byte |= 0x1 << 7; /* Disable 25MHz oscillator buffer */ + pmio_write(0xd4, byte); +#endif } /*

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Patch set updated for coreboot: northbridge/amd/amdmct/mct_ddr3: Add cc6 setup information messages
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12053 -gerrit commit 5d4e91c3b176f6823436674c4d5ed53942cdbccf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 20 12:49:49 2015 -0500 northbridge/amd/amdmct/mct_ddr3: Add cc6 setup information messages Change-Id: I17660ce5429431e08476b7bba15e381636b64c7d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index a6cc70f..f8f9ab4 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -1502,6 +1502,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, if (pMCTstat->GStatus & (1 << GSB_NodeIntlv)) interleaved = 1; + printk(BIOS_INFO, "%s: Initializing CC6 DRAM storage area for node %d (interleaved: %d)\n", __func__, pDCTstat->Node_ID, interleaved); + /* Find highest DRAM range (DramLimitAddr) */ max_node = 0; max_range = -1; @@ -1525,6 +1527,9 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, } if (max_range >= 0) { + printk(BIOS_INFO, "%s:\toriginal (node %d) max_range_limit: %16llx DRAM limit: %16llx\n", __func__, max_node, max_range_limit, + (((uint64_t)(Get_NB32(pDCTstat->dev_map, 0x124) & 0x1fffff)) << 27) | 0x7ffffff); + if (interleaved) /* Move upper limit down by 16M * the number of nodes */ max_range_limit -= (0x1000000 * num_nodes); @@ -1532,6 +1537,8 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, /* Move upper limit down by 16M */ max_range_limit -= 0x1000000; + printk(BIOS_INFO, "%s:\tnew max_range_limit: %16llx\n", __func__, max_range_limit); + /* Disable the range */ dword = Get_NB32(pDCTstat->dev_map, 0x40 + (max_range * 0x8)); byte = dword & 0x3; @@ -1566,6 +1573,10 @@ static void set_up_cc6_storage_fam15(struct MCTStatStruc *pMCTstat, dword &= ~(0x3f << 12); /* CoreSaveStateDestNode = destination_node */ dword |= (destination_node & 0x3f) << 12; Set_NB32(pDCTstat->dev_link, 0x128, dword); + + printk(BIOS_INFO, "%s:\tTarget node: %d\n", __func__, destination_node); + + printk(BIOS_INFO, "%s:\tDone\n", __func__); } static void lock_dram_config(struct MCTStatStruc *pMCTstat,

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Patch set updated for coreboot: northbridge/amd/amdht: Add isochronous setup support for coherent fabric
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12042 -gerrit commit 04207d430df06ce58cee0f892ad05362a6b8219e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:47:48 2015 -0500 northbridge/amd/amdht: Add isochronous setup support for coherent fabric Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 61 +++++++++++++++++++++++++++ src/northbridge/amd/amdht/h3ffeat.h | 3 ++ src/northbridge/amd/amdht/h3finit.c | 35 ++++++++++++++- src/northbridge/amd/amdht/h3finit.h | 4 +- src/northbridge/amd/amdht/h3ncmn.c | 30 ++++++++++++- 5 files changed, 129 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index da45888..635f357 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -1666,6 +1666,67 @@ static void cpuSetAMDPCI(u8 node) pci_write_config32(NODE_PCI(node, 3), 0x140, dword); } + uint8_t link; + uint8_t isochronous; + uint8_t isochronous_link_present; + + /* Set up isochronous buffers if needed */ + isochronous_link_present = 0; + if (revision & AMD_FAM15_ALL) { + for (link = 0; link < 4; link++) { + if (AMD_CpuFindCapability(node, link, &offset)) { + isochronous = (pci_read_config32(NODE_PCI(node, 0), (link * 0x20) + 0x84) >> 12) & 0x1; + + if (isochronous) + isochronous_link_present = 1; + } + } + } + + uint8_t free_tok; + uint8_t up_rsp_cbc; + uint8_t isoc_preq_cbc; + uint8_t isoc_preq_tok; + uint8_t xbar_to_sri_free_list_cbc; + if (isochronous_link_present) { + /* Adjust buffer counts */ + dword = pci_read_config32(NODE_PCI(node, 3), 0x70); + isoc_preq_cbc = (dword >> 24) & 0x7; + up_rsp_cbc = (dword >> 16) & 0x7; + up_rsp_cbc--; + isoc_preq_cbc++; + dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */ + dword |= ((isoc_preq_cbc & 0x7) << 24); + dword &= ~(0x7 << 16); /* UpRspCBC = up_rsp_cbc */ + dword |= ((up_rsp_cbc & 0x7) << 16); + pci_write_config32(NODE_PCI(node, 3), 0x70, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0x74); + isoc_preq_cbc = (dword >> 24) & 0x7; + isoc_preq_cbc++; + dword &= ~(0x7 << 24); /* IsocPreqCBC = isoc_preq_cbc */ + dword |= (isoc_preq_cbc & 0x7) << 24; + pci_write_config32(NODE_PCI(node, 3), 0x74, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0x7c); + xbar_to_sri_free_list_cbc = dword & 0x1f; + xbar_to_sri_free_list_cbc--; + dword &= ~0x1f; /* Xbar2SriFreeListCBC = xbar_to_sri_free_list_cbc */ + dword |= xbar_to_sri_free_list_cbc & 0x1f; + pci_write_config32(NODE_PCI(node, 3), 0x7c, dword); + + dword = pci_read_config32(NODE_PCI(node, 3), 0x140); + free_tok = (dword >> 20) & 0xf; + isoc_preq_tok = (dword >> 14) & 0x3; + free_tok--; + isoc_preq_tok++; + dword &= ~(0xf << 20); /* FreeTok = free_tok */ + dword |= ((free_tok & 0xf) << 20); + dword &= ~(0x3 << 14); /* IsocPreqTok = isoc_preq_tok */ + dword |= ((isoc_preq_tok & 0x3) << 14); + pci_write_config32(NODE_PCI(node, 3), 0x140, dword); + } + printk(BIOS_DEBUG, " done\n"); } diff --git a/src/northbridge/amd/amdht/h3ffeat.h b/src/northbridge/amd/amdht/h3ffeat.h index 628b86e..bcd4c10 100644 --- a/src/northbridge/amd/amdht/h3ffeat.h +++ b/src/northbridge/amd/amdht/h3ffeat.h @@ -75,6 +75,7 @@ #define HTSLAVE_LINK01_OFFSET 4 #define HTSLAVE_LINK_CONTROL_0_REG 4 #define HTSLAVE_FREQ_REV_0_REG 0xC +#define HTSLAVE_FEATURE_CAP_REG 0x10 /* HT3 gen Capability */ #define IS_HT_GEN3_CAPABILITY(reg) \ @@ -122,10 +123,12 @@ typedef struct u8 SelWidthIn; u8 SelWidthOut; u8 SelFrequency; + uint8_t enable_isochronous_mode; /* This section is for keeping track of capabilities and possible configurations */ BOOL RegangCap; uint32_t PrvFrequencyCap; + uint32_t PrvFeatureCap; u8 PrvWidthInCap; u8 PrvWidthOutCap; uint32_t CompositeFrequencyCap; diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index e4ce768..6a45f10 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -1415,6 +1415,38 @@ static void regangLinks(sMainData *pDat) #endif /* HT_BUILD_NC_ONLY */ } +static void detectIoLinkIsochronousCapable(sMainData *pDat) +{ + uint8_t i; + unsigned char iommu; + uint8_t isochronous_capable = 0; + + iommu = 1; + get_option(&iommu, "iommu"); + + for (i = 0; i < pDat->TotalLinks*2; i += 2) { + if ((pDat->PortList[i].Type == PORTLIST_TYPE_CPU) && (pDat->PortList[i+1].Type == PORTLIST_TYPE_IO)) { + if ((pDat->PortList[i].PrvFeatureCap & 0x1) && (pDat->PortList[i+1].PrvFeatureCap & 0x1)) { + pDat->PortList[i].enable_isochronous_mode = 1; + pDat->PortList[i+1].enable_isochronous_mode = 1; + isochronous_capable = 1; + } else { + pDat->PortList[i].enable_isochronous_mode = 0; + pDat->PortList[i+1].enable_isochronous_mode = 0; + } + } + } + + if (isochronous_capable && iommu) { + printk(BIOS_DEBUG, "Forcing HT links to isochronous mode due to enabled IOMMU\n"); + /* Isochronous mode must be set on all links if the IOMMU is enabled */ + for (i = 0; i < pDat->TotalLinks*2; i += 2) { + pDat->PortList[i].enable_isochronous_mode = 1; + pDat->PortList[i+1].enable_isochronous_mode = 1; + } + } +} + /*---------------------------------------------------------------------------------------- * void * selectOptimalWidthAndFrequency(sMainData *pDat) @@ -1535,7 +1567,6 @@ static void selectOptimalWidthAndFrequency(sMainData *pDat) temp = cbPCBBAUpstreamWidth; pDat->PortList[i].SelWidthIn = (u8)temp; pDat->PortList[i+1].SelWidthOut = (u8)temp; - } } @@ -1697,6 +1728,8 @@ static void linkOptimization(sMainData *pDat) { pDat->nb->gatherLinkData(pDat, pDat->nb); regangLinks(pDat); + if (is_fam15h()) + detectIoLinkIsochronousCapable(pDat); selectOptimalWidthAndFrequency(pDat); hammerSublinkFixup(pDat); pDat->nb->setLinkData(pDat, pDat->nb); diff --git a/src/northbridge/amd/amdht/h3finit.h b/src/northbridge/amd/amdht/h3finit.h index 1bd8616..ab2dace 100644 --- a/src/northbridge/amd/amdht/h3finit.h +++ b/src/northbridge/amd/amdht/h3finit.h @@ -227,6 +227,7 @@ typedef struct { * @param[in,out] u8* LinkWidthIn = modify to change the Link Witdh In * @param[in,out] u8* LinkWidthOut = modify to change the Link Witdh Out * @param[in,out] u32* FreqCap = modify to change the link's frequency capability + * @param[in,out] u32* FeatureCap = modify to change the link's feature capability * * --------------------------------------------------------------------------------------- */ @@ -241,7 +242,8 @@ typedef struct { u8 Link, u8 *LinkWidthIn, u8 *LinkWidthOut, - u32 *FreqCap + u32 *FreqCap, + u32 *FeatureCap ); /**---------------------------------------------------------------------------------------- diff --git a/src/northbridge/amd/amdht/h3ncmn.c b/src/northbridge/amd/amdht/h3ncmn.c index c97d592..7937c6e 100644 --- a/src/northbridge/amd/amdht/h3ncmn.c +++ b/src/northbridge/amd/amdht/h3ncmn.c @@ -1429,12 +1429,15 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) temp &= 0x7; /* Mask off reserved values */ pDat->PortList[i].PrvFrequencyCap |= (temp << 17); } + + AmdPCIReadBits(linkBase + HTHOST_FEATURE_CAP_REG, 9, 0, &temp); + pDat->PortList[i].PrvFeatureCap = (u16)temp; } else { linkBase = pDat->PortList[i].Pointer; if (pDat->PortList[i].Link == 1) - linkBase += HTSLAVE_LINK01_OFFSET; + linkBase += HTSLAVE_LINK01_OFFSET; AmdPCIReadBits(linkBase + HTSLAVE_LINK_CONTROL_0_REG, 22, 20, &temp); pDat->PortList[i].PrvWidthOutCap = convertBitsToWidth((u8)temp, pDat->nb); @@ -1445,6 +1448,9 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) AmdPCIReadBits(linkBase + HTSLAVE_FREQ_REV_0_REG, 31, 16, &temp); pDat->PortList[i].PrvFrequencyCap = (u16)temp; + AmdPCIReadBits(linkBase + HTSLAVE_FEATURE_CAP_REG, 7, 0, &temp); + pDat->PortList[i].PrvFeatureCap = (u16)temp; + if (pDat->HtBlock->AMD_CB_DeviceCapOverride) { linkBase &= 0xFFFFF000; @@ -1461,7 +1467,8 @@ static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) pDat->PortList[i].Link, &(pDat->PortList[i].PrvWidthInCap), &(pDat->PortList[i].PrvWidthOutCap), - &(pDat->PortList[i].PrvFrequencyCap)); + &(pDat->PortList[i].PrvFrequencyCap), + &(pDat->PortList[i].PrvFeatureCap)); } } } @@ -1562,6 +1569,16 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) if (is_gt_rev_d()) AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG_2, 0, 0, &temp2); AmdPCIWriteBits(linkBase + HTHOST_FREQ_REV_REG, 11, 8, &temp); + + /* Enable isochronous flow control mode if supported by chipset */ + if (is_fam15h()) { + if (pDat->PortList[i].enable_isochronous_mode) + temp = 1; + else + temp = 0; + setHtControlRegisterBits(linkBase + HTHOST_LINK_CONTROL_REG, 12, 12, &temp); + } + if (frequency_index > HT_FREQUENCY_1000M) /* Gen1 = 200MHz -> 1000MHz, Gen3 = 1200MHz -> 3200MHz */ { /* Enable for Gen3 frequencies */ @@ -1579,6 +1596,7 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) CPU_HTNB_FUNC_00, REG_HT_LINK_RETRY0_0X130 + 4*pDat->PortList[i].Link), 0, 0, &temp); + /* and Scrambling enable / disable */ AmdPCIWriteBits(MAKE_SBDFO(makePCISegmentFromNode(pDat->PortList[i].NodeID), makePCIBusFromNode(pDat->PortList[i].NodeID), @@ -1617,6 +1635,14 @@ static void setLinkData(sMainData *pDat, cNorthBridge *nb) bits = 0; } + /* Enable isochronous flow control mode if supported by chipset */ + if (is_fam15h()) { + if (pDat->PortList[i].enable_isochronous_mode) + temp = 1; + else + temp = 0; + } + /* Retry Enable */ isFound = FALSE; currentPtr = linkBase & (u32)0xFFFFF000; /* Set PCI Offset to 0 */

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Patch set updated for coreboot: amd/amdfam10: Control Fam15h cache partitioning via nvram
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12041 -gerrit commit d1ec117105d3a91890557eba981d4e10b68702a3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Aug 9 02:47:51 2015 -0500 amd/amdfam10: Control Fam15h cache partitioning via nvram Add options to control cache partitioning and overall memory performance via nvram. Change-Id: I3dd5d7f3640aee0395a68645c0242307605d3ce7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/defaults.h | 5 ++--- src/cpu/amd/family_10h-family_15h/init_cpus.c | 16 ++++++++++++++-- src/mainboard/asus/kgpe-d16/cmos.default | 3 +++ src/mainboard/asus/kgpe-d16/cmos.layout | 9 +++++++-- src/northbridge/amd/amdfam10/northbridge.c | 22 ++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 ++++++++++- 6 files changed, 58 insertions(+), 8 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/defaults.h b/src/cpu/amd/family_10h-family_15h/defaults.h index d4999b9..7fd115c 100644 --- a/src/cpu/amd/family_10h-family_15h/defaults.h +++ b/src/cpu/amd/family_10h-family_15h/defaults.h @@ -135,9 +135,8 @@ static const struct { 0x00000000, 1 << (42-32)}, /* Bx [PwcDisableWalkerSharing]=1 */ { BU_CFG3, AMD_OR_C0, AMD_PTYPE_ALL, - (0x3 << 20) | (0x1 << 22), 0x00000000, - (0x3 << 20) | (0x1 << 22), 0x00000000}, /* C0 or above [PfcDoubleStride]=1, - PfcStrideMul]=0x3 */ + 1 << 22, 0x00000000, + 1 << 22, 0x00000000}, /* C0 or above [PfcDoubleStride]=1 */ { EX_CFG, AMD_OR_C0, AMD_PTYPE_ALL, 0x00000000, 1 << (54-32), diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 55df7a4..da45888 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -953,6 +953,7 @@ void cpuSetAMDMSR(uint8_t node_id) */ msr_t msr; u8 i; + uint8_t nvram; u32 platform; uint64_t revision; uint8_t enable_c_states; @@ -977,6 +978,13 @@ void cpuSetAMDMSR(uint8_t node_id) /* Revision C0 and above */ if (revision & AMD_OR_C0) { + uint8_t enable_experimental_memory_speed_boost; + + /* Check to see if cache partitioning is allowed */ + enable_experimental_memory_speed_boost = 0; + if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) + enable_experimental_memory_speed_boost = !!nvram; + uint32_t f3x1fc = pci_read_config32(NODE_PCI(node_id, 3), 0x1fc); msr = rdmsr(FP_CFG); msr.hi &= ~(0x7 << (42-32)); /* DiDtCfg4 */ @@ -996,11 +1004,15 @@ void cpuSetAMDMSR(uint8_t node_id) msr.lo &= ~(0x1 << 16); /* DiDtMode */ msr.lo |= ((f3x1fc & 0x1) << 16); wrmsr(FP_CFG, msr); + + if (enable_experimental_memory_speed_boost) { + msr = rdmsr(BU_CFG3); + msr.lo |= (0x3 << 20); /* PfcStrideMul = 0x3 */ + wrmsr(BU_CFG3, msr); + } } #if IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700) || IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB800) - uint8_t nvram; - if (revision & (AMD_DR_GT_D0 | AMD_FAM15_ALL)) { /* Set up message triggered C1E */ msr = rdmsr(0xc0010055); diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 9994dad..9e36690 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -20,6 +20,9 @@ cpu_cc6_state = Enable sata_ahci_mode = Enable sata_alpm = Disable maximum_p_state_limit = 0xf +probe_filter = Auto +l3_cache_partitioning = Disable ieee1394_controller = Enable +experimental_memory_speed_boost = Disable power_on_after_fail = On boot_option = Fallback diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index e17fec6..648091a 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -44,8 +44,11 @@ entries 468 1 e 1 sata_alpm 469 4 h 0 maximum_p_state_limit 473 2 e 13 dimm_spd_checksum -475 1 r 0 allow_spd_nvram_cache_restore -477 1 e 1 ieee1394_controller +475 1 e 14 probe_filter +476 1 e 1 l3_cache_partitioning +477 1 e 1 experimental_memory_speed_boost +478 1 r 0 allow_spd_nvram_cache_restore +479 1 e 1 ieee1394_controller 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers @@ -142,6 +145,8 @@ enumerations 13 0 Enforce 13 1 Ignore 13 2 Override +14 0 Disable +14 1 Auto checksums diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index ced64aa..600fdf8 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1650,6 +1650,17 @@ static void detect_and_enable_probe_filter(device_t dev) { uint32_t dword; + uint8_t nvram; + uint8_t enable_probe_filter; + + /* Check to see if the probe filter is allowed */ + enable_probe_filter = 1; + if (get_option(&nvram, "probe_filter") == CB_SUCCESS) + enable_probe_filter = !!nvram; + + if (!enable_probe_filter) + return; + uint8_t fam15h = 0; uint8_t rev_gte_d = 0; uint8_t dual_node = 0; @@ -1810,6 +1821,17 @@ static void detect_and_enable_cache_partitioning(device_t dev) uint8_t i; uint32_t dword; + uint8_t nvram; + uint8_t enable_l3_cache_partitioning; + + /* Check to see if cache partitioning is allowed */ + enable_l3_cache_partitioning = 0; + if (get_option(&nvram, "l3_cache_partitioning") == CB_SUCCESS) + enable_l3_cache_partitioning = !!nvram; + + if (!enable_l3_cache_partitioning) + return; + if (is_fam15h()) { printk(BIOS_DEBUG, "Enabling L3 cache partitioning\n"); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index aad813a..a6cc70f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -5559,6 +5559,14 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, mct_ExtMCTConfig_Dx(pDCTstat); } else { /* Family 15h CPUs */ + uint8_t nvram; + uint8_t enable_experimental_memory_speed_boost; + + /* Check to see if cache partitioning is allowed */ + enable_experimental_memory_speed_boost = 0; + if (get_option(&nvram, "experimental_memory_speed_boost") == CB_SUCCESS) + enable_experimental_memory_speed_boost = !!nvram; + val = 0x0ce00f00; /* FlushWrOnStpGnt = 0x0 */ val |= 0x10 << 2; /* MctWrLimit = 0x10 */ val |= 0x1; /* DctWrLimit = 0x1 */ @@ -5572,7 +5580,8 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat, val &= ~(0x7 << 8); /* CohPrefPrbLmt = 0x1 */ val |= (0x1 << 8); val |= (0x1 << 12); /* EnSplitDctLimits = 0x1 */ - val |= (0x1 << 20); /* DblPrefEn = 0x1 */ + if (enable_experimental_memory_speed_boost) + val |= (0x1 << 20); /* DblPrefEn = 0x1 */ val |= (0x7 << 22); /* PrefFourConf = 0x7 */ val |= (0x7 << 25); /* PrefFiveConf = 0x7 */ val &= ~(0xf << 28); /* DcqBwThrotWm = 0x0 */

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Fix gart setup not working on Family 15h processors
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12047 -gerrit commit 12c06916f0d531afb713c2825884d37622e8cc1c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:52:31 2015 -0500 northbridge/amd/amdfam10: Fix gart setup not working on Family 15h processors Change-Id: Ib78620c30502df6add9cc2ea1dbd4fb6dc89203e Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/misc_control.c | 34 ++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 8 deletions(-) diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index ed932a9..0b312b1 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -73,7 +73,7 @@ static void mcf3_read_resources(device_t dev) } } -static void set_agp_aperture(device_t dev) +static void set_agp_aperture(device_t dev, uint32_t pci_id) { struct resource *resource; @@ -93,7 +93,7 @@ static void set_agp_aperture(device_t dev) /* Update the other northbriges */ pdev = 0; - while((pdev = dev_find_device(PCI_VENDOR_ID_AMD, 0x1203, pdev))) { + while ((pdev = dev_find_device(PCI_VENDOR_ID_AMD, pci_id, pdev))) { /* Store the GART size but don't enable it */ pci_write_config32(pdev, 0x90, gart_acr); @@ -109,10 +109,19 @@ static void set_agp_aperture(device_t dev) } } -static void mcf3_set_resources(device_t dev) +static void mcf3_set_resources_fam10h(device_t dev) { /* Set the gart apeture */ - set_agp_aperture(dev); + set_agp_aperture(dev, 0x1203); + + /* Set the generic PCI resources */ + pci_dev_set_resources(dev); +} + +static void mcf3_set_resources_fam15h(device_t dev) +{ + /* Set the gart apeture */ + set_agp_aperture(dev, 0x1603); /* Set the generic PCI resources */ pci_dev_set_resources(dev); @@ -151,9 +160,18 @@ static void misc_control_init(struct device *dev) } -static struct device_operations mcf3_ops = { +static struct device_operations mcf3_ops_fam10h = { + .read_resources = mcf3_read_resources, + .set_resources = mcf3_set_resources_fam10h, + .enable_resources = pci_dev_enable_resources, + .init = misc_control_init, + .scan_bus = 0, + .ops_pci = 0, +}; + +static struct device_operations mcf3_ops_fam15h = { .read_resources = mcf3_read_resources, - .set_resources = mcf3_set_resources, + .set_resources = mcf3_set_resources_fam15h, .enable_resources = pci_dev_enable_resources, .init = misc_control_init, .scan_bus = 0, @@ -161,13 +179,13 @@ static struct device_operations mcf3_ops = { }; static const struct pci_driver mcf3_driver __pci_driver = { - .ops = &mcf3_ops, + .ops = &mcf3_ops_fam10h, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1203, }; static const struct pci_driver mcf3_driver_fam15 __pci_driver = { - .ops = &mcf3_ops, + .ops = &mcf3_ops_fam15h, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1603, };

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart
by Timothy Pearson 23 Nov '15

23 Nov '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12046 -gerrit commit b8a75dfffbe759c6199dbe4670c5b89181f8ebec Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Aug 11 17:52:03 2015 -0500 northbridge/amd/amdfam10: Rename mislabeled iommu nvram option to gart Change-Id: Ia24102e164eb5753ade3f9b5ab21eba2fa60836b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/advansus/a785e-i/cmos.layout | 2 +- src/mainboard/amd/bimini_fam10/cmos.layout | 2 +- src/mainboard/amd/mahogany_fam10/cmos.layout | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout | 2 +- src/mainboard/amd/tilapia_fam10/cmos.layout | 2 +- src/mainboard/asus/kfsn4-dre/cmos.layout | 2 +- src/mainboard/asus/kgpe-d16/cmos.default | 2 +- src/mainboard/asus/kgpe-d16/cmos.layout | 2 +- src/mainboard/asus/m4a78-em/cmos.layout | 2 +- src/mainboard/asus/m4a785-m/cmos.layout | 2 +- src/mainboard/asus/m4a785t-m/cmos.default | 2 +- src/mainboard/asus/m4a785t-m/cmos.layout | 2 +- src/mainboard/asus/m5a88-v/cmos.layout | 2 +- src/mainboard/avalue/eax-785e/cmos.layout | 2 +- src/mainboard/gigabyte/ma785gm/cmos.layout | 2 +- src/mainboard/gigabyte/ma785gmt/cmos.layout | 2 +- src/mainboard/gigabyte/ma78gm/cmos.layout | 2 +- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 2 +- src/mainboard/iei/kino-780am2-fam10/cmos.layout | 2 +- src/mainboard/jetway/pa78vm5/cmos.layout | 2 +- src/mainboard/msi/ms9652_fam10/cmos.layout | 2 +- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 2 +- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 2 +- src/mainboard/supermicro/h8scm_fam10/cmos.layout | 2 +- src/mainboard/tyan/s2912_fam10/cmos.layout | 2 +- src/northbridge/amd/amdfam10/misc_control.c | 12 ++++++------ 26 files changed, 31 insertions(+), 31 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/cmos.layout b/src/mainboard/advansus/a785e-i/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/advansus/a785e-i/cmos.layout +++ b/src/mainboard/advansus/a785e-i/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/amd/bimini_fam10/cmos.layout b/src/mainboard/amd/bimini_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/amd/bimini_fam10/cmos.layout +++ b/src/mainboard/amd/bimini_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/amd/mahogany_fam10/cmos.layout b/src/mainboard/amd/mahogany_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/amd/mahogany_fam10/cmos.layout +++ b/src/mainboard/amd/mahogany_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/amd/tilapia_fam10/cmos.layout b/src/mainboard/amd/tilapia_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/amd/tilapia_fam10/cmos.layout +++ b/src/mainboard/amd/tilapia_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 66bc3a0..bd5fdbe 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index 9e36690..3319497 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -3,7 +3,7 @@ debug_level = Spew multi_core = Enable slow_cpu = off compute_unit_siblings = Enable -iommu = Disable +gart = Disable nmi = Disable hypertransport_speed_limit = Auto max_mem_clock = DDR3-1600 diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 648091a..a34547a 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 2 e 3 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/asus/m4a78-em/cmos.layout b/src/mainboard/asus/m4a78-em/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m4a78-em/cmos.layout +++ b/src/mainboard/asus/m4a78-em/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/m4a785-m/cmos.layout b/src/mainboard/asus/m4a785-m/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m4a785-m/cmos.layout +++ b/src/mainboard/asus/m4a785-m/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/m4a785t-m/cmos.default b/src/mainboard/asus/m4a785t-m/cmos.default index 1686102..f336bd3 100644 --- a/src/mainboard/asus/m4a785t-m/cmos.default +++ b/src/mainboard/asus/m4a785t-m/cmos.default @@ -9,4 +9,4 @@ power_on_after_fail=Disable debug_level=Spew slow_cpu=off nmi=Enable -iommu=Enable +gart=Enable diff --git a/src/mainboard/asus/m4a785t-m/cmos.layout b/src/mainboard/asus/m4a785t-m/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m4a785t-m/cmos.layout +++ b/src/mainboard/asus/m4a785t-m/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/asus/m5a88-v/cmos.layout b/src/mainboard/asus/m5a88-v/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/asus/m5a88-v/cmos.layout +++ b/src/mainboard/asus/m5a88-v/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/avalue/eax-785e/cmos.layout b/src/mainboard/avalue/eax-785e/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/avalue/eax-785e/cmos.layout +++ b/src/mainboard/avalue/eax-785e/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ma785gm/cmos.layout b/src/mainboard/gigabyte/ma785gm/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/gigabyte/ma785gm/cmos.layout +++ b/src/mainboard/gigabyte/ma785gm/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ma785gmt/cmos.layout b/src/mainboard/gigabyte/ma785gmt/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/gigabyte/ma785gmt/cmos.layout +++ b/src/mainboard/gigabyte/ma785gmt/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ma78gm/cmos.layout b/src/mainboard/gigabyte/ma78gm/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/gigabyte/ma78gm/cmos.layout +++ b/src/mainboard/gigabyte/ma78gm/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 73d53af..5602c70 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection 728 256 h 0 user_data diff --git a/src/mainboard/iei/kino-780am2-fam10/cmos.layout b/src/mainboard/iei/kino-780am2-fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/iei/kino-780am2-fam10/cmos.layout +++ b/src/mainboard/iei/kino-780am2-fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/jetway/pa78vm5/cmos.layout b/src/mainboard/jetway/pa78vm5/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/jetway/pa78vm5/cmos.layout +++ b/src/mainboard/jetway/pa78vm5/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/mainboard/supermicro/h8scm_fam10/cmos.layout b/src/mainboard/supermicro/h8scm_fam10/cmos.layout index 0ad18a2..bf58aac 100644 --- a/src/mainboard/supermicro/h8scm_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8scm_fam10/cmos.layout @@ -12,7 +12,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 456 1 e 1 ECC_memory 728 256 h 0 user_data 984 16 h 0 check_sum diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index 14e45ef..3c0a4ed 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -31,7 +31,7 @@ entries 412 4 e 6 debug_level 440 4 e 9 slow_cpu 444 1 e 1 nmi -445 1 e 1 iommu +445 1 e 1 gart 446 1 e 1 power_on_after_fail 456 1 e 1 ECC_memory 457 1 e 1 ECC_redirection diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 847b599..ed932a9 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -38,7 +38,7 @@ * * @param dev * - * There is only one AGP aperture resource needed. The resoruce is added to + * There is only one AGP aperture resource needed. The resource is added to * the northbridge of BSP. * * The same trick can be used to augment legacy VGA resources which can @@ -50,7 +50,7 @@ static void mcf3_read_resources(device_t dev) { struct resource *resource; - unsigned char iommu; + unsigned char gart; /* Read the generic PCI resources */ pci_dev_read_resources(dev); @@ -59,13 +59,13 @@ static void mcf3_read_resources(device_t dev) return; } - iommu = 1; - get_option(&iommu, "iommu"); + gart = 1; + get_option(&gart, "gart"); - if (iommu) { + if (gart) { /* Add a Gart apeture resource */ resource = new_resource(dev, 0x94); - resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; + resource->size = gart?CONFIG_AGP_APERTURE_SIZE:1; resource->align = log2(resource->size); resource->gran = log2(resource->size); resource->limit = 0xffffffff; /* 4G */

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New patch to review for coreboot: intel/d945gclf: Fix IASL warning and remark
by Martin Roth 23 Nov '15

23 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12523 -gerrit commit 2aac1b916d4e87f5e60f9e4c3b50e8054c3193c4 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 16:34:10 2015 -0700 intel/d945gclf: Fix IASL warning and remark - Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors dsdt.aml 1445: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1454: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/d945gclf/Kconfig | 4 ---- src/mainboard/intel/d945gclf/acpi/ec.asl | 8 +++++++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 2023216..429a304 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -50,8 +50,4 @@ config MAX_CPUS int default 4 -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - endif # BOARD_INTEL_D945GCLF diff --git a/src/mainboard/intel/d945gclf/acpi/ec.asl b/src/mainboard/intel/d945gclf/acpi/ec.asl index 45e2bd1..5362bb2 100644 --- a/src/mainboard/intel/d945gclf/acpi/ec.asl +++ b/src/mainboard/intel/d945gclf/acpi/ec.asl @@ -18,7 +18,13 @@ Device(EC0) Name (_HID, EISAID("PNP0C09")) Name (_UID, 1) - Method (_CRS, 0) + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() {

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New patch to review for coreboot: intel/eagleheights: Fix IASL warning _OSC must return a value
by Martin Roth 23 Nov '15

23 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12522 -gerrit commit e788e4892e5cb9a80620130a5c43ad07be03403a Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 16:27:53 2015 -0700 intel/eagleheights: Fix IASL warning _OSC must return a value Not all the paths through the _OSC method returned a value. Fortunately this is very common code, and was easy to copy from another file. copied from src/soc/intel/baytrail/acpi/southcluster.asl dsdt.aml 140: Method (_OSC, 4) Warning 3115 - ^ Not all control paths return a value (_OSC) dsdt.aml 140: Method (_OSC, 4) Warning 3107 - ^ Reserved method must return a value (Buffer required for _OSC) - Remove Kconfig default disabling IASL warnings as errors. Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/eagleheights/Kconfig | 4 ---- src/mainboard/intel/eagleheights/dsdt.asl | 7 +++++++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index bfcb4ce..702e2af 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -35,8 +35,4 @@ config MAX_CPUS int default 4 -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - endif # BOARD_INTEL_EAGLEHEIGHTS diff --git a/src/mainboard/intel/eagleheights/dsdt.asl b/src/mainboard/intel/eagleheights/dsdt.asl index 6ad320b..0e572f7 100644 --- a/src/mainboard/intel/eagleheights/dsdt.asl +++ b/src/mainboard/intel/eagleheights/dsdt.asl @@ -179,6 +179,13 @@ DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001) /* Let OS control everything */ Return (Arg3) } + Else + { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } } /* End _OSC */ Method (_PRT, 0, NotSerialized)

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New patch to review for coreboot: kontron/986lcd-m: Fix IASL warning and remark
by Martin Roth 23 Nov '15

23 Nov '15

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12521 -gerrit commit 4eaded80f7eb1052676d7203da068e49c87ce2b7 Author: Martin Roth <martinroth(a)google.com> Date: Mon Nov 23 16:14:13 2015 -0700 kontron/986lcd-m: Fix IASL warning and remark - Add an empty Operating Region for the empty _REG method - Serialize _CRS Method - Remove Kconfig default disabling IASL warnings as errors Fixes IASL Warning and remark: dsdt.aml 1451: Method (_CRS, 0) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 1460: Method (_REG, 2) Warning 3079 - ^ _REG has no corresponding Operation Region Change-Id: I4aa59468a89c4013146ab34004476a0968c60707 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/kontron/986lcd-m/Kconfig | 4 ---- src/mainboard/kontron/986lcd-m/acpi/ec.asl | 8 +++++++- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index a589b46..2a3cfe2 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -42,8 +42,4 @@ config VGA_BIOS_FILE string default "amipci_01.20" -# TODO: Remove this when platform ASL is fixed -config IASL_WARNINGS_ARE_ERRORS - def_bool n - endif # BOARD_KONTRON_986LCD_M diff --git a/src/mainboard/kontron/986lcd-m/acpi/ec.asl b/src/mainboard/kontron/986lcd-m/acpi/ec.asl index 4decb5d..cd882d1 100644 --- a/src/mainboard/kontron/986lcd-m/acpi/ec.asl +++ b/src/mainboard/kontron/986lcd-m/acpi/ec.asl @@ -18,7 +18,13 @@ Device(EC0) Name (_HID, EISAID("PNP0C09")) Name (_UID, 1) - Method (_CRS, 0) + // _REG method requires that an operation region be defined. + OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff) + Field (ERAM, ByteAcc, Lock, Preserve) + { + } + + Method (_CRS, 0, Serialized) { Name (ECMD, ResourceTemplate() {

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Patch merged into coreboot/master: southbridge/amd/sr5650: Hide clock configuration device after setup is complete
by gerrit＠coreboot.org 23 Nov '15

23 Nov '15

the following patch was just integrated into master: commit a8c6c7f30c2793aff4f1ab8d01954bbaced2b4ae Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Aug 13 17:45:12 2015 -0500 southbridge/amd/sr5650: Hide clock configuration device after setup is complete Change-Id: I043f2eb0993660d0a9351867eca1e73e0b2c37f1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12045 Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See http://review.coreboot.org/12045 for details. -gerrit

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coreboot-gerrit November 2015