coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: b6fe0df No need to specify '1' in define of header guard
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8103 -gerrit commit b6fe0dfb02ce5bf6f3526e6d0d63994360dd1d11 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 02:48:57 2015 +1100 No need to specify '1' in define of header guard Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ++-- src/northbridge/intel/gm45/delay.h | 4 ++-- src/northbridge/intel/gm45/gm45.h | 4 ++-- src/northbridge/intel/haswell/haswell.h | 4 ++-- src/northbridge/intel/nehalem/gma.h | 4 ++-- src/northbridge/intel/nehalem/nehalem.h | 4 ++-- src/northbridge/intel/sandybridge/sandybridge.h | 4 ++-- src/northbridge/intel/sch/sch.h | 4 ++-- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index abce07a..dab5a9c 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index 9a0cf42..d67d696 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ /* Chipset types */ #define SANDYBRIDGE_MOBILE 0 @@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h index dda6cf4..a28a3f1 100644 --- a/src/northbridge/intel/gm45/delay.h +++ b/src/northbridge/intel/gm45/delay.h @@ -18,11 +18,11 @@ */ #ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__ -#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ 1 +#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ #include <delay.h> void ns100delay(u32); void udelay_from_reset(u32); -#endif +#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 673160b..5bdf9e4 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ 1 +#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ #include "southbridge/intel/i82801ix/i82801ix.h" @@ -434,4 +434,4 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 55f6f28..d8221a9 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ -#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1 +#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ /* Chipset types */ #define HASWELL_MOBILE 0 @@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index f0e1c53..baf12f2 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ 1 +#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ /* mailbox 0: header */ typedef struct { @@ -118,4 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -#endif +#endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 60cafdf..73137b2 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1 +#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ #ifndef __ASSEMBLER__ @@ -623,4 +623,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d38bf0b..0790ae8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ /* Chipset types */ #define SANDYBRIDGE_MOBILE 0 @@ -240,4 +240,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 5700842..3eb0825 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -20,7 +20,7 @@ */ #ifndef __SCH_PULSBO_H__ -#define __SCH_PULSBO_H__ 1 +#define __SCH_PULSBO_H__ int sch_port_access_read(int port, int reg, int bytes); void sch_port_access_write(int port, int reg, int bytes, long data); @@ -51,4 +51,4 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); /* FIXME: should probably be in southbridge, but is setup in romstage, too */ #define CMC_SHADOW 0x3faf0000 -#endif +#endif /* __SCH_PULSBO_H__ */

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Patch set updated for coreboot: d1e5231 inteltool: add `-s` to dump spi bar and bios_cntl registers
by Alexander Couzens 05 Jan '15

05 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8049 -gerrit commit d1e5231a01efb5ba8756dd34968a9a849e16a4a4 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Jan 3 02:52:10 2015 +0100 inteltool: add `-s` to dump spi bar and bios_cntl registers Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/inteltool/Makefile | 2 +- util/inteltool/inteltool.8 | 3 + util/inteltool/inteltool.c | 15 +++- util/inteltool/inteltool.h | 1 + util/inteltool/spi.c | 219 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 237 insertions(+), 3 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 98848b1..f846672 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -27,7 +27,7 @@ PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -W LDFLAGS += -lpci -lz -OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o +OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o spi.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 9db4df7..5956bcd 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -29,6 +29,9 @@ Dump I/O Controller Hub (ICH) southbridge GPIO registers. .B "\-r, \-\-rcba" Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP +.B "\-s, \-\-spi" +Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +.TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge PMBASE registers. .TP diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index ffed606..38ab061 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -209,10 +209,11 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMa]\n", name); + printf("usage: %s [-vh?gGrpmedPMas]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" + " -s | --spi: dump southbridge spi and bios_cntrl registers\n" " -g | --gpio: dump southbridge GPIO registers\n" " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump southbridge RCBA registers\n" @@ -240,6 +241,7 @@ int main(int argc, char *argv[]) int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; + int dump_spi = 0; int show_gpio_diffs = 0; static struct option long_options[] = { @@ -255,11 +257,12 @@ int main(int argc, char *argv[]) {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, {"ambs", 0, 0, 'A'}, + {"spi", 0, 0, 's'}, {"all", 0, 0, 'a'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaA", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAs", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -304,10 +307,14 @@ int main(int argc, char *argv[]) dump_pciexbar = 1; dump_coremsrs = 1; dump_ambs = 1; + dump_spi = 1; break; case 'A': dump_ambs = 1; break; + case 's': + dump_spi = 1; + break; case 'h': case '?': default: @@ -454,6 +461,10 @@ int main(int argc, char *argv[]) if (dump_ambs) { print_ambs(nb, pacc); } + + if (dump_spi) { + print_spi(sb); + } /* Clean up */ pci_free_dev(nb); // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1db9e63..3f22641 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -203,4 +203,5 @@ int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); int print_ambs(struct pci_dev *nb, struct pci_access *pacc); +int print_spi(struct pci_dev *sb); void ivybridge_dump_timings(void); diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c new file mode 100644 index 0000000..3d5ddc3 --- /dev/null +++ b/util/inteltool/spi.c @@ -0,0 +1,219 @@ + +#include <stdio.h> +#include <stdlib.h> +#include "inteltool.h" + +static const io_register_t pch_bios_cntl_registers[] = { + { 0x0, 1, "BIOSWE - write enable" }, + { 0x1, 1, "BLE - lock enable" }, + { 0x2, 2, "SPI Read configuration" }, + { 0x4, 1, "TopSwapStatus" }, + { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x6, 2, "reserved" }, +}; + +#define SPIBAR 0x3800 + +static const io_register_t spi_bar_registers[] = { + { SPIBAR + 0x00, 4, "BFPR - BIOS Flash primary region" }, + { SPIBAR + 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" }, + { SPIBAR + 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" }, + { SPIBAR + 0x08, 4, "FADDR - Flash Address" }, + { SPIBAR + 0x0c, 4, "Reserved" }, + { SPIBAR + 0x10, 4, "FDATA0" }, + /* 0x10 .. 0x4f are filled with data */ + { SPIBAR + 0x50, 4, "FRACC - Flash Region Access Permissions" }, + { SPIBAR + 0x54, 4, "Flash Region 0" }, + { SPIBAR + 0x58, 4, "Flash Region 1" }, + { SPIBAR + 0x5c, 4, "Flash Region 2" }, + { SPIBAR + 0x60, 4, "Flash Region 3" }, + { SPIBAR + 0x64, 4, "Flash Region 4" }, + { SPIBAR + 0x74, 4, "FPR0 Flash Protected Range 0" }, + { SPIBAR + 0x78, 4, "FPR0 Flash Protected Range 1" }, + { SPIBAR + 0x7c, 4, "FPR0 Flash Protected Range 2" }, + { SPIBAR + 0x80, 4, "FPR0 Flash Protected Range 3" }, + { SPIBAR + 0x84, 4, "FPR0 Flash Protected Range 4" }, + { SPIBAR + 0x90, 1, "SSFSTS - Software Sequencing Flash Status" }, + { SPIBAR + 0x91, 3, "SSFSTS - Software Sequencing Flash Status" }, + { SPIBAR + 0x94, 2, "PREOP - Prefix opcode Configuration" }, + { SPIBAR + 0x96, 2, "OPTYPE - Opcode Type Configuration" }, + { SPIBAR + 0x98, 8, "OPMENU - Opcode Menu Configuration" }, + { SPIBAR + 0xa0, 1, "BBAR - BIOS Base Address Configuration" }, + { SPIBAR + 0xb0, 4, "FDOC - Flash Descriptor Observability Control" }, + { SPIBAR + 0xb8, 4, "Reserved" }, + { SPIBAR + 0xc0, 4, "AFC - Additional Flash Control" }, + { SPIBAR + 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" }, + { SPIBAR + 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" }, + { SPIBAR + 0xd0, 4, "FPB - Flash Partition Boundary" }, +}; + +int print_bioscntl(struct pci_dev *sb) +{ + int i, size = 0; + unsigned char bios_cntl = 0xff; + const io_register_t *bios_cntl_register = NULL; + + printf("\n============= SPI / BIOS CNTL =============\n\n"); + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: + bios_cntl = pci_read_byte(sb, 0xdc); + bios_cntl_register = pch_bios_cntl_registers; + size = ARRAY_SIZE(pch_bios_cntl_registers); + break; + default: + printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n"); + return 1; + } + + printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl); + + if (bios_cntl_register) { + for (i = 0; i < size; i++) { + unsigned int val = bios_cntl >> bios_cntl_register[i].addr; + val &= ((1 << bios_cntl_register[i].size) -1); + printf("0x%04x = %s\n", val, bios_cntl_register[i].name); + } + } + + return 0; +} + +int print_spibar(struct pci_dev *sb) { + int i, size = 0, rcba_size = 0x4000; + volatile uint8_t *rcba; + uint32_t rcba_phys; + const io_register_t *spi_register = NULL; + + printf("\n============= SPI Bar ==============\n\n"); + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH6: + case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7M: + case PCI_DEVICE_ID_INTEL_ICH7DH: + case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8: + case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + case PCI_DEVICE_ID_INTEL_ICH10R: + case PCI_DEVICE_ID_INTEL_NM10: + case PCI_DEVICE_ID_INTEL_I63XX: + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: + case PCI_DEVICE_ID_INTEL_Z68: + case PCI_DEVICE_ID_INTEL_P67: + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_H67: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_Q65: + case PCI_DEVICE_ID_INTEL_QS67: + case PCI_DEVICE_ID_INTEL_Q67: + case PCI_DEVICE_ID_INTEL_QM67: + case PCI_DEVICE_ID_INTEL_B65: + case PCI_DEVICE_ID_INTEL_C202: + case PCI_DEVICE_ID_INTEL_C204: + case PCI_DEVICE_ID_INTEL_C206: + case PCI_DEVICE_ID_INTEL_H61: + case PCI_DEVICE_ID_INTEL_Z77: + case PCI_DEVICE_ID_INTEL_Z75: + case PCI_DEVICE_ID_INTEL_Q77: + case PCI_DEVICE_ID_INTEL_Q75: + case PCI_DEVICE_ID_INTEL_B75: + case PCI_DEVICE_ID_INTEL_H77: + case PCI_DEVICE_ID_INTEL_C216: + case PCI_DEVICE_ID_INTEL_QM77: + case PCI_DEVICE_ID_INTEL_QS77: + case PCI_DEVICE_ID_INTEL_HM77: + case PCI_DEVICE_ID_INTEL_UM77: + case PCI_DEVICE_ID_INTEL_HM76: + case PCI_DEVICE_ID_INTEL_HM75: + case PCI_DEVICE_ID_INTEL_HM70: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; + size = ARRAY_SIZE(spi_bar_registers); + spi_register = spi_bar_registers; + break; + case PCI_DEVICE_ID_INTEL_ICH: + case PCI_DEVICE_ID_INTEL_ICH0: + case PCI_DEVICE_ID_INTEL_ICH2: + case PCI_DEVICE_ID_INTEL_ICH4: + case PCI_DEVICE_ID_INTEL_ICH4M: + case PCI_DEVICE_ID_INTEL_ICH5: + printf("This southbridge does not have RCBA.\n"); + return 1; + default: + printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n"); + return 1; + } + + rcba = map_physical(rcba_phys, rcba_size); + if (rcba == NULL) { + perror("Error mapping RCBA"); + exit(1); + } + + for (i = 0; i < size; i++) { + switch(spi_register[i].size) { + case 1: + printf("0x%08x = %s\n", *(uint8_t *)(rcba + spi_register[i].addr), spi_register[i].name); + break; + case 2: + printf("0x%08x = %s\n", *(uint16_t *)(rcba + spi_register[i].addr), spi_register[i].name); + break; + case 4: + printf("0x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), spi_register[i].name); + break; + case 8: + printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), *(uint32_t *)(rcba + spi_register[i].addr + 4), spi_register[i].name); + break; + } + } + + unmap_physical((void *)rcba, rcba_size); + return 0; +} + +int print_spi(struct pci_dev *sb) { + return (print_bioscntl(sb) || print_spibar(sb)); +} +

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Patch merged into coreboot/master: c800199 northbridge/via/vx800/examples: Remove rotting source
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit c800199007757656aa3a3c6e712117ecc96ff25e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:29:36 2015 +1100 northbridge/via/vx800/examples: Remove rotting source This is just bit-rotting and its likely this will continue to rot by the time someone notices it exits it will be too late (i.e., today). Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8087 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8087 for details. -gerrit

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Patch set updated for coreboot: 252d815 superio/smsc/lpc47n207: Hook into build system
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8084 -gerrit commit 252d815a2415b7566e1fd555f61a8d6af6e66649 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 17:21:52 2015 +1100 superio/smsc/lpc47n207: Hook into build system Provide proper Makefile and Kconfig components so that this superio is built as object code. Select superio component in mainboard Kconfig's to bring in the link-time symbols and thereby removing the need for .c inclusion. N.B. The LPC47N207 Super I/O does not physically exist on these boards. The Super I/O is found on external LPC debug card hardware and so should really be made selectable. However, this is beyond the scope of this specific fix, that rids us of .c inclusions in romstage.c Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/lumpy/Kconfig | 3 +++ src/mainboard/samsung/lumpy/romstage.c | 1 - src/mainboard/samsung/stumpy/Kconfig | 3 +++ src/mainboard/samsung/stumpy/romstage.c | 1 - src/superio/smsc/Kconfig | 2 ++ src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/lpc47n207/Makefile.inc | 21 +++++++++++++++++++++ src/superio/smsc/lpc47n207/early_serial.c | 6 ++++++ src/superio/smsc/lpc47n207/lpc47n207.h | 11 +++++++---- 9 files changed, 43 insertions(+), 6 deletions(-) diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index baf0eee..1b20452 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -13,6 +13,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 +# LPC47N207 selected for external LPC card +# not on board, should be made selectable. + select SUPERIO_SMSC_LPC47N207 select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 select HAVE_MRC diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index b356fa8..8568f84 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -45,7 +45,6 @@ #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> -#include "superio/smsc/lpc47n207/early_serial.c" #endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 17484a9..1b65eae 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -11,6 +11,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F +# LPC47N207 selected for external LPC card +# not on board, should be made selectable. + select SUPERIO_SMSC_LPC47N207 select HAVE_MRC select INTEL_INT15 diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 1462132..2ed185b 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -45,7 +45,6 @@ #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> -#include "superio/smsc/lpc47n207/early_serial.c" #endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 6aaa112..34bc60c 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -30,6 +30,8 @@ config SUPERIO_SMSC_LPC47M10X bool config SUPERIO_SMSC_LPC47M15X bool +config SUPERIO_SMSC_LPC47N207 + bool config SUPERIO_SMSC_LPC47N217 bool config SUPERIO_SMSC_LPC47N227 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index a89b6ac..caa2c72 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -24,6 +24,7 @@ subdirs-y += lpc47b272 subdirs-y += lpc47b397 subdirs-y += lpc47m10x subdirs-y += lpc47m15x +subdirs-y += lpc47n207 subdirs-y += lpc47n217 subdirs-y += lpc47n227 subdirs-y += sio10n268 diff --git a/src/superio/smsc/lpc47n207/Makefile.inc b/src/superio/smsc/lpc47n207/Makefile.inc new file mode 100644 index 0000000..08e1387 --- /dev/null +++ b/src/superio/smsc/lpc47n207/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SMSC_LPC47N207) += early_serial.c diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index e2ae49d..847fe97 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -17,6 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include <stdlib.h> +#include "lpc47n207.h" + /* * This code tries to discover the SMSC LPC47N207 superio chip which can be * connected over an LPC dongle. The chip could be bootstrap mapped to one of diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h index 69689a4..a122465 100644 --- a/src/superio/smsc/lpc47n207/lpc47n207.h +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -17,9 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H -#define SUPERIO_SMSC_LPC47N207_LPC47N207_H +#ifndef SUPERIO_SMSC_LPC47N207_H +#define SUPERIO_SMSC_LPC47N207_H -extern void try_enabling_LPC47N207_uart(void); +#include <arch/io.h> +#include <stdint.h> -#endif +void try_enabling_LPC47N207_uart(void); + +#endif /* SUPERIO_SMSC_LPC47N207_H */

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New patch to review for coreboot: 05066db superio/smsc/lpc47n207: Remove poorly implemented SIO support
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8102 -gerrit commit 05066db0da9f7474a9e327dce024487c82627431 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 21:21:16 2015 +1100 superio/smsc/lpc47n207: Remove poorly implemented SIO support We remove the final superio .c includes here. The 'lpc47n207' was never properly hooked into the build system and the corresponding boards do not actually contain this superio necessarily. The support was for add-on lpc debug cards however we have better ways to handle this now. Change-Id: I9e2bc4677fe2198123a0f4c3e0ad8928cae97296 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/lumpy/romstage.c | 15 ----- src/mainboard/samsung/stumpy/romstage.c | 15 ----- src/superio/smsc/lpc47n207/early_serial.c | 97 ------------------------------- src/superio/smsc/lpc47n207/lpc47n207.h | 25 -------- 4 files changed, 152 deletions(-) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 93cc068..85553fd 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -43,10 +43,6 @@ #include <halt.h> #include "option_table.h" #include "gpio.h" -#if CONFIG_DRIVERS_UART_8250IO -#include <superio/smsc/lpc47n207/lpc47n207.h> -#include "superio/smsc/lpc47n207/early_serial.c" -#endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -56,20 +52,9 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_DRIVERS_UART_8250IO - /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | - KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); - - /* map full 256 bytes at 0x1600 to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); - - try_enabling_LPC47N207_uart(); -#else /* Enable SuperIO + EC + KBC */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); -#endif } static void rcba_config(void) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index abaf48e..bbbefc3 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -43,10 +43,6 @@ #include <cpu/x86/msr.h> #include <halt.h> #include "gpio.h" -#if CONFIG_DRIVERS_UART_8250IO -#include <superio/smsc/lpc47n207/lpc47n207.h> -#include "superio/smsc/lpc47n207/early_serial.c" -#endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #endif @@ -69,19 +65,8 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_DRIVERS_UART_8250IO - /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ - pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ - CNF2_LPC_EN | COMA_LPC_EN); - - /* map full 256 bytes at 0x1600 to the LPC bus */ - pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0xfc1601); - - try_enabling_LPC47N207_uart(); -#else /* Enable SuperIO + PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); -#endif } static void rcba_config(void) diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c deleted file mode 100644 index e2ae49d..0000000 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ /dev/null @@ -1,97 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* - * This code tries to discover the SMSC LPC47N207 superio chip which can be - * connected over an LPC dongle. The chip could be bootstrap mapped to one of - * four LPC addresses: 0x2e, 0x4e, 0x162e, and 0x164e. - * - * Initializing the UART requires accesses to a few control registers. This - * structure includes the register offset and the value to write (along with - * the mask). - */ -typedef struct { - u8 conf_reg; - u8 value; - u8 mask; -} uart_conf; - -/* All regs/values to write to initialize the LPC47N207 UART */ -static const uart_conf uart_conf_data [] = { - {2, (1 << 3), (1 << 3)}, /* cr02, enable Primary UART power */ - {0xc, (1 << 6), (1 << 6)}, /* cr0c, enable Primary UART high speed */ - {0x24, (CONFIG_TTYS0_BASE >> 3) << 1, 0xff}, /* cr24, base addr */ -}; - -void try_enabling_LPC47N207_uart(void) -{ - u8 reg_value; - const uart_conf* conf_item; - u16 lpc_ports[] = {0x2e, 0x4e, 0x162e, 0x164e}; - u16 lpc_port; - int i, j; - -#define CONFIG_ENABLE 0x55 -#define CONFIG_DISABLE 0xaa - - for (j = 0; j < ARRAY_SIZE(lpc_ports); j++) { - lpc_port = lpc_ports[j]; - - /* enable CONFIG mode */ - outb(CONFIG_ENABLE, lpc_port); - reg_value=inb(lpc_port); - if (reg_value != CONFIG_ENABLE) { - continue; /* There is no LPC device at this address */ - } - - do { - /* - * Registers 12 and 13 hold config address, look for a - * match. - */ - outb(0x12, lpc_port); - reg_value=inb(lpc_port + 1); - if (reg_value != (lpc_port & 0xff)) - break; - - outb(0x13, lpc_port); - reg_value=inb(lpc_port + 1); - if (reg_value != (lpc_port >> 8)) - break; - - /* This must be the SMSC LPC 47N207, enable the UART. */ - for (i = 0; i < ARRAY_SIZE(uart_conf_data); i++) { - u8 reg, value, mask; - - conf_item = uart_conf_data + i; - - reg = conf_item->conf_reg; - value = conf_item->value; - mask = conf_item->mask; - - outb(reg, lpc_port); - reg_value = inb(lpc_port + 1); - reg_value &= ~mask; - reg_value |= (value & mask); - outb(reg_value, lpc_port + 1); - } - } while (0); - outb(CONFIG_DISABLE, lpc_port); - } -} diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h deleted file mode 100644 index 69689a4..0000000 --- a/src/superio/smsc/lpc47n207/lpc47n207.h +++ /dev/null @@ -1,25 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H -#define SUPERIO_SMSC_LPC47N207_LPC47N207_H - -extern void try_enabling_LPC47N207_uart(void); - -#endif

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Patch set updated for coreboot: dcdc433 cbmem: make do_car_migrate_variables external, add pointer
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8095 -gerrit commit dcdc433c9eee2e3e998bbdf8a6a707b8cd65e20a Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jan 4 11:23:13 2015 -0700 cbmem: make do_car_migrate_variables external, add pointer This is for the FSP migration. The pointer to the saved CAR data needs to be passed in for the car migration. Instead of creating special functions just for the FSP, or changing everything to pass the pointer all the way through from cbmem_recovery(), keep the BROKEN_CAR_MIGRATE in place for FSP platforms so that do_car_migrate_variables doesn't get called in the standard cbmem_recovery() path. After it returns, call do_car_migrate_variables() directly, passing in the pointer to the saved data. Change-Id: I4967eef097bf41b033ab82fafd1fd0d4144fd5d2 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/arch/arm/include/arch/early_variables.h | 1 + src/arch/arm64/include/arch/early_variables.h | 1 + src/arch/riscv/include/arch/early_variables.h | 1 + src/arch/x86/include/arch/early_variables.h | 2 ++ src/cpu/x86/car.c | 9 ++++++--- 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 5b58baa..edddc7c 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -27,5 +27,6 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..779515a 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -31,5 +31,6 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index 3a1f20d..2487c82 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -31,5 +31,6 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index f76c048..fbbbc6b 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -55,8 +55,10 @@ static inline void *car_get_var_ptr(void *var) { return var; } #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) /* Migrate the CAR variables to memory. */ void car_migrate_variables(void); +void do_car_migrate_variables(void *var); #else static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif #endif diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index c9cc6d6..eb04d0c 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -73,7 +73,7 @@ void *car_get_var_ptr(void *var) return &migrated_base[offset]; } -static void do_car_migrate_variables(void) +void do_car_migrate_variables(void * saved_car) { void *migrated_base; car_migration_func_t *migrate_func; @@ -90,7 +90,10 @@ static void do_car_migrate_variables(void) return; } - memcpy(migrated_base, &_car_data_start[0], car_data_size); + if (saved_car == NULL) + memcpy(migrated_base, &_car_data_start[0], car_data_size); + else + memcpy(migrated_base, saved_car, car_data_size); /* Mark that the data has been moved. */ car_migrated = ~0; @@ -106,5 +109,5 @@ static void do_car_migrate_variables(void) void car_migrate_variables(void) { if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) - do_car_migrate_variables(); + do_car_migrate_variables(NULL); }

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Patch set updated for coreboot: a1aa953 fsp_baytrail: Do the CAR CBMRM transition
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8096 -gerrit commit a1aa9531823e806e252d1bb5dec66d057f8dd925 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jan 4 17:44:35 2015 -0700 fsp_baytrail: Do the CAR CBMRM transition - Add FSP driver routine to find and return a pointer to the saved CAR data. - Add the TEMPORARY_MEMORY_HOB_GUID, used to find the saved CAR data. - Move the cbmem_recovery call from romstage.c into chipset_fsp_util.c so that it's completed by the time we get back to romstage. - Clear area in the stack in early romstage for CBMEM - Remove printk from chipset_prev_sleep_state - this gets called multiple times, including at a point when CBMEM could have been initialized as a console device, but before it's been reinitialized after the CAR->memory transition. Change-Id: Ie3b6797cbcc9bbc6b7c9185a5fc9a85096c40ff6 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/drivers/intel/fsp/fsp_util.c | 25 +++++++++++++++++++++++ src/drivers/intel/fsp/fsp_util.h | 7 +++++++ src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 20 +++++++++++++++--- src/soc/intel/fsp_baytrail/romstage/romstage.c | 7 ++----- 4 files changed, 51 insertions(+), 8 deletions(-) diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index d0ed9cf..8f9b7aa 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -177,6 +177,31 @@ volatile u8 * find_fsp () return (fsp_ptr); } +/** finds the saved temporary memory information in the FSP HOB list + * + * @param[in] hob_list_ptr pointer to the start of the hob list + * @param[out] location ptr to ptr gets filled in with stack location + * @param[in] length ptr gets filled in with stack length + * @return 1 if stack was found, 0 if stack was not found + */ +uint8_t find_saved_temp_mem(void *hob_list_ptr, void **location, + uint32_t *length) +{ + EFI_GUID temp_hob_guid = FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID; + + EFI_HOB_GUID_TYPE *saved_mem_hob; + saved_mem_hob = (EFI_HOB_GUID_TYPE *) find_hob_by_guid(hob_list_ptr, + &temp_hob_guid); + + if (saved_mem_hob == NULL) + return 0; + + *length = saved_mem_hob->Header.HobLength; + *location =(void *) ((char *) saved_mem_hob + + sizeof(EFI_HOB_GUID_TYPE)); + return 1; +} + #ifndef __PRE_RAM__ /* Only parse HOB data in ramstage */ void print_fsp_info(void) { diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index cb667dc..a8b89b3 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -37,6 +37,7 @@ void print_fsp_info(void); void chipset_fsp_early_init(FSP_INIT_PARAMS *FspInitParams, FSP_INFO_HEADER *fsp_ptr); void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); +uint8_t find_saved_temp_mem(void *hob_list_ptr, void **location, uint32_t *length); /* functions in hob.c */ void print_hob_mem_attributes(void *Hobptr); @@ -120,4 +121,10 @@ extern void *FspHobListPtr; UpdData->member?"Enabled":"Disabled"); \ break; + +#ifndef FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID +#define FSP_BOOTLOADER_TEMPORARY_MEMORY_HOB_GUID \ + { 0xbbcff46c, 0xc8d3, 0x4113, { 0x89, 0x85, 0xb9, 0xd4, 0xf3, 0xb3, 0xf6, 0x4e } }; +#endif + #endif /* FSP_UTIL_H */ diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index c6b5f9c..b645682 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -34,6 +34,7 @@ #include <baytrail/acpi.h> #include <baytrail/iomap.h> #include <baytrail/smm.h> +#include <arch/early_variables.h> #ifdef __PRE_RAM__ #include <baytrail/romstage.h> @@ -326,12 +327,25 @@ void chipset_fsp_early_init(FSP_INIT_PARAMS *pFspInitParams, } /* The FSP returns here after the fsp_early_init call */ -void ChipsetFspReturnPoint(EFI_STATUS Status, - VOID *HobListPtr) +void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr) { - if (Status == 0xFFFFFFFF) { + void *saved_tmp_mem_location; + uint32_t saved_tmp_mem_length; + + if (Status == 0xFFFFFFFF) warm_reset(); + + /* find the saved temp memory so we can recover cbmem */ + find_saved_temp_mem(HobListPtr, &saved_tmp_mem_location, + &saved_tmp_mem_length); + cbmem_recovery(chipset_prev_sleep_state(0) == 3); + + if (saved_tmp_mem_location != NULL) { + do_car_migrate_variables(saved_tmp_mem_location); + } else { + printk(BIOS_DEBUG, "Skipping CBMEM variable migration.\n"); } + romstage_main_continue(Status, HobListPtr); } diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 2619c96..1529850 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -59,9 +59,6 @@ uint32_t chipset_prev_sleep_state(uint32_t clear) pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); - printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n", - pm1_sts, pm1_cnt, gen_pmcon1); - if (pm1_sts & WAK_STS) { switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { #if CONFIG_HAVE_ACPI_RESUME @@ -159,6 +156,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) uint32_t fd_mask = 0; uint32_t fd2_mask = 0; + /* Clear stack area for CBMEM */ + memset((void *)CONFIG_DCACHE_RAM_BASE,0,0x3000); post_code(0x40); program_base_addresses(); @@ -215,7 +214,6 @@ void main(FSP_INFO_HEADER *fsp_info_header) * Memory is setup and the stack is set by the FSP. */ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { - int cbmem_was_initted; void *cbmem_hob_ptr; uint32_t prev_sleep_state; struct romstage_handoff *handoff; @@ -258,7 +256,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { post_code(0x4d); } - cbmem_was_initted = !cbmem_recovery(prev_sleep_state == 3); /* Save the HOB pointer in CBMEM to be used in ramstage*/ cbmem_hob_ptr = cbmem_add (CBMEM_ID_HOB_POINTER, sizeof(*hob_list_ptr));

1 0

Patch set updated for coreboot: 25bc49a drivers/intel/fsp: Add HOB tools to work with GUIDs
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8066 -gerrit commit 25bc49a1db0256ee89b5d490c014ef67a7b395e7 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sat Jan 3 17:18:58 2015 -0700 drivers/intel/fsp: Add HOB tools to work with GUIDs Add new functions to: - Compare two GUIDs - Find a hob based on its GUID - Print information about GUID_EXTENSION type HOBs - Print a GUID's address and value Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/drivers/intel/fsp/fsp_util.h | 4 ++ src/drivers/intel/fsp/hob.c | 97 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index a8b89b3..ff6daca 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -43,7 +43,11 @@ uint8_t find_saved_temp_mem(void *hob_list_ptr, void **location, uint32_t *lengt void print_hob_mem_attributes(void *Hobptr); void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); void print_hob_resource_attributes(void *Hobptr); +void print_guid_type_attributes(void *Hobptr); const char * get_hob_type_string(void *Hobptr); +void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); +uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2); +void printguid(EFI_GUID *guid); /* Additional HOB types not included in the FSP: * #define EFI_HOB_TYPE_HANDOFF 0x0001 diff --git a/src/drivers/intel/fsp/hob.c b/src/drivers/intel/fsp/hob.c index 4537ffb..99c4ba1 100644 --- a/src/drivers/intel/fsp/hob.c +++ b/src/drivers/intel/fsp/hob.c @@ -20,8 +20,26 @@ #include <types.h> #include <string.h> #include <console/console.h> +#include <lib.h> // hexdump #include "fsp_util.h" + +/** Displays a GUID's address and value + * + * @param guid pointer to the GUID to display + */ +void printguid(EFI_GUID *guid) +{ + printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-", + guid, (unsigned long)guid->Data1, + guid->Data2, guid->Data3); + printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n", + guid->Data4[0], guid->Data4[1], + guid->Data4[2], guid->Data4[3], + guid->Data4[4], guid->Data4[5], + guid->Data4[6], guid->Data4[7] ); +} + void print_hob_mem_attributes(void *Hobptr) { EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr; @@ -118,6 +136,27 @@ const char * get_hob_type_string(void *Hobptr) return Hobtypestring; } +/** Displays the length, location, and GUID value of a GUID extension + * + * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard + * HOB header containing the HOB type and length, and a GUID for + * identification. The rest of the data is undefined and must be known + * based on the GUID. + * + * This displays the entire HOB length, and the location of the start + * of the HOB, *NOT* the length of or the start of the data inside the HOB. + * + * @param Hobptr + */ +void print_guid_type_attributes(void *Hobptr) +{ + printk(BIOS_SPEW, " at location %p with length0x%0lx\n ", + Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \ + Hobptr)->Guid->Header.HobLength)); + printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name)); + +} + /* Print out a structure of all the HOBs * that match a certain type: * Print all types (0x0000) @@ -159,6 +198,8 @@ void print_hob_type_structure(u16 Hobtype, void *Hoblistptr) print_hob_mem_attributes(Currenthob); break; case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: print_hob_resource_attributes(Currenthob); break; + case EFI_HOB_TYPE_GUID_EXTENSION: + print_guid_type_attributes(Currenthob); break; } } @@ -170,3 +211,59 @@ void print_hob_type_structure(u16 Hobtype, void *Hoblistptr) } while (!Lasthob); printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n"); } + + +/** Finds a HOB entry based on type and guid + * + * @param current_hob pointer to the start of the HOB list + * @param guid the GUID of the HOB entry to find + * @return pointer to the start of the requested HOB or NULL if not found. + */ +void * find_hob_by_guid(void *current_hob, EFI_GUID *guid) +{ + do { + switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) { + + case EFI_HOB_TYPE_MEMORY_ALLOCATION: + if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \ + current_hob)->AllocDescriptor.Name))) + return current_hob; + break; + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + if (guids_are_equal(guid, + &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \ + current_hob)->Owner))) + return current_hob; + break; + case EFI_HOB_TYPE_GUID_EXTENSION: + if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \ + current_hob)->Name))) + return current_hob; + break; + } + + if (!END_OF_HOB_LIST(current_hob)) + current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */ + } while (!END_OF_HOB_LIST(current_hob)); + + return NULL; +} + +/** Compares a pair of GUIDs to see if they are equal + * + * GUIDs are 128 bits long, so compare them as pairs of quadwords. + * + * @param guid1 pointer to the first of the GUIDs to compare + * @param guid2 pointer to the second of the GUIDs to compare + * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal + */ +uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2) +{ + uint64_t* guid_1 = (void *) guid1; + uint64_t* guid_2 = (void *) guid2; + + if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1))) + return 0; + + return 1; +}

1 0

Patch set updated for coreboot: 2a4da33 cbmem: make do_car_migrate_variables external, add pointer
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8095 -gerrit commit 2a4da33782deaebbc69f12efc83d1ee8cecf02a8 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jan 4 11:23:13 2015 -0700 cbmem: make do_car_migrate_variables external, add pointer This is for the FSP migration. The pointer to the saved CAR data needs to be passed in for the car migration. Instead of creating special functions just for the FSP, or changing everything to pass the pointer all the way through from cbmem_recovery(), keep the BROKEN_CAR_MIGRATE in place for FSP platforms so that do_car_migrate_variables doesn't get called in the standard cbmem_recovery() path. After it returns, call do_car_migrate_variables() directly, passing in the pointer to the saved data. Change-Id: I4967eef097bf41b033ab82fafd1fd0d4144fd5d2 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/arch/arm/include/arch/early_variables.h | 1 + src/arch/arm64/include/arch/early_variables.h | 1 + src/arch/riscv/include/arch/early_variables.h | 1 + src/arch/x86/include/arch/early_variables.h | 2 ++ src/cpu/x86/car.c | 9 ++++++--- 5 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 5b58baa..edddc7c 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -27,5 +27,6 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..779515a 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -31,5 +31,6 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index 3a1f20d..2487c82 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -31,5 +31,6 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index f76c048..fbbbc6b 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -55,8 +55,10 @@ static inline void *car_get_var_ptr(void *var) { return var; } #if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) /* Migrate the CAR variables to memory. */ void car_migrate_variables(void); +void do_car_migrate_variables(void *var); #else static inline void car_migrate_variables(void) { } +static inline void do_car_migrate_variables(void *var) { } #endif #endif diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index c9cc6d6..eb04d0c 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -73,7 +73,7 @@ void *car_get_var_ptr(void *var) return &migrated_base[offset]; } -static void do_car_migrate_variables(void) +void do_car_migrate_variables(void * saved_car) { void *migrated_base; car_migration_func_t *migrate_func; @@ -90,7 +90,10 @@ static void do_car_migrate_variables(void) return; } - memcpy(migrated_base, &_car_data_start[0], car_data_size); + if (saved_car == NULL) + memcpy(migrated_base, &_car_data_start[0], car_data_size); + else + memcpy(migrated_base, saved_car, car_data_size); /* Mark that the data has been moved. */ car_migrated = ~0; @@ -106,5 +109,5 @@ static void do_car_migrate_variables(void) void car_migrate_variables(void) { if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) - do_car_migrate_variables(); + do_car_migrate_variables(NULL); }

1 0

Patch set updated for coreboot: 75e2707 drivers/intel/fsp: Add HOB tools to work with GUIDs
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8066 -gerrit commit 75e2707e43b66e8402901a0c927bcfd652f36212 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sat Jan 3 17:18:58 2015 -0700 drivers/intel/fsp: Add HOB tools to work with GUIDs Add new functions to: - Compare two GUIDs - Find a hob based on its GUID - Print information about GUID_EXTENSION type HOBs - Print a GUID's address and value Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/drivers/intel/fsp/fsp_util.h | 4 ++ src/drivers/intel/fsp/hob.c | 97 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h index cb667dc..3c72f24 100644 --- a/src/drivers/intel/fsp/fsp_util.h +++ b/src/drivers/intel/fsp/fsp_util.h @@ -42,7 +42,11 @@ void ChipsetFspReturnPoint(EFI_STATUS Status, VOID *HobListPtr); void print_hob_mem_attributes(void *Hobptr); void print_hob_type_structure(u16 Hobtype, void *Hoblistptr); void print_hob_resource_attributes(void *Hobptr); +void print_guid_type_attributes(void *Hobptr); const char * get_hob_type_string(void *Hobptr); +void * find_hob_by_guid(void *Hoblistptr, EFI_GUID *guid1); +uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2); +void printguid(EFI_GUID *guid); /* Additional HOB types not included in the FSP: * #define EFI_HOB_TYPE_HANDOFF 0x0001 diff --git a/src/drivers/intel/fsp/hob.c b/src/drivers/intel/fsp/hob.c index 4537ffb..fbb6868 100644 --- a/src/drivers/intel/fsp/hob.c +++ b/src/drivers/intel/fsp/hob.c @@ -20,8 +20,26 @@ #include <types.h> #include <string.h> #include <console/console.h> +#include <lib.h> // hexdump #include "fsp_util.h" + +/** Displays a GUID's address and value + * + * @param guid pointer to the GUID to display + */ +void printguid(EFI_GUID *guid) +{ + printk(BIOS_SPEW,"Address: %p Guid: %08lx-%04x-%04x-", + guid, (unsigned long)guid->Data1, + guid->Data2, guid->Data3, + printk(BIOS_SPEW,"%02x%02x%02x%02x%02x%02x%02x%02x\n", + guid->Data4[0], guid->Data4[1]); + guid->Data4[2], guid->Data4[3], + guid->Data4[4], guid->Data4[5], + guid->Data4[6], guid->Data4[7] ); +} + void print_hob_mem_attributes(void *Hobptr) { EFI_HOB_MEMORY_ALLOCATION *HobMemoryPtr = (EFI_HOB_MEMORY_ALLOCATION *)Hobptr; @@ -118,6 +136,27 @@ const char * get_hob_type_string(void *Hobptr) return Hobtypestring; } +/** Displays the length, location, and GUID value of a GUID extension + * + * The EFI_HOB_GUID_TYPE is very basic - it just contains the standard + * HOB header containing the HOB type and length, and a GUID for + * identification. The rest of the data is undefined and must be known + * based on the GUID. + * + * This displays the entire HOB length, and the location of the start + * of the HOB, *NOT* the length of or the start of the data inside the HOB. + * + * @param Hobptr + */ +void print_guid_type_attributes(void *Hobptr) +{ + printk(BIOS_SPEW, " at location %p with length0x%0lx\n ", + Hobptr, (unsigned long)(((EFI_PEI_HOB_POINTERS *) \ + Hobptr)->Guid->Header.HobLength)); + printguid(&(((EFI_HOB_GUID_TYPE *)Hobptr)->Name)); + +} + /* Print out a structure of all the HOBs * that match a certain type: * Print all types (0x0000) @@ -159,6 +198,8 @@ void print_hob_type_structure(u16 Hobtype, void *Hoblistptr) print_hob_mem_attributes(Currenthob); break; case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: print_hob_resource_attributes(Currenthob); break; + case EFI_HOB_TYPE_GUID_EXTENSION: + print_guid_type_attributes(Currenthob); break; } } @@ -170,3 +211,59 @@ void print_hob_type_structure(u16 Hobtype, void *Hoblistptr) } while (!Lasthob); printk(BIOS_DEBUG, "=== End of FSP HOB Data Structure ===\n\n"); } + + +/** Finds a HOB entry based on type and guid + * + * @param current_hob pointer to the start of the HOB list + * @param guid the GUID of the HOB entry to find + * @return pointer to the start of the requested HOB or NULL if not found. + */ +void * find_hob_by_guid(void *current_hob, EFI_GUID *guid) +{ + do { + switch (((EFI_HOB_GENERIC_HEADER *)current_hob)->HobType) { + + case EFI_HOB_TYPE_MEMORY_ALLOCATION: + if (guids_are_equal(guid, &(((EFI_HOB_MEMORY_ALLOCATION *) \ + current_hob)->AllocDescriptor.Name))) + return current_hob; + break; + case EFI_HOB_TYPE_RESOURCE_DESCRIPTOR: + if (guids_are_equal(guid, + &(((EFI_HOB_RESOURCE_DESCRIPTOR *) \ + current_hob)->Owner))) + return current_hob; + break; + case EFI_HOB_TYPE_GUID_EXTENSION: + if (guids_are_equal(guid, &(((EFI_HOB_GUID_TYPE *) \ + current_hob)->Name))) + return current_hob; + break; + } + + if (!END_OF_HOB_LIST(current_hob)) + current_hob = GET_NEXT_HOB(current_hob); /* Get next HOB pointer */ + } while (!END_OF_HOB_LIST(current_hob)); + + return NULL; +} + +/** Compares a pair of GUIDs to see if they are equal + * + * GUIDs are 128 bits long, so compare them as pairs of quadwords. + * + * @param guid1 pointer to the first of the GUIDs to compare + * @param guid2 pointer to the second of the GUIDs to compare + * @return 1 if the GUIDs were equal, 0 if GUIDs were not equal + */ +uint8_t guids_are_equal(EFI_GUID *guid1, EFI_GUID *guid2) +{ + uint64_t* guid_1 = (void *) guid1; + uint64_t* guid_2 = (void *) guid2; + + if ((*(guid_1) != *(guid_2)) || (*(guid_1 + 1) != *(guid_2 + 1))) + return 0; + + return 1; +}

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coreboot-gerrit January 2015