coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 680b261 Drop duplicate API from spi_flash.h
by Stefan Reinauer 05 Jan '15

05 Jan '15

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8108 -gerrit commit 680b261399307f142d2c0f9b7a50a0d165d1ba63 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Jan 5 11:06:29 2015 -0800 Drop duplicate API from spi_flash.h This convenience API was never used. Change-Id: If2a99967e7f8c02e9029f7766aeef1e1a1f3dd16 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/include/spi_flash.h | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 70ca784..7cf0229 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -58,22 +58,4 @@ struct spi_flash { struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs); -static inline int spi_flash_read(struct spi_flash *flash, u32 offset, - size_t len, void *buf) -{ - return flash->read(flash, offset, len, buf); -} - -static inline int spi_flash_write(struct spi_flash *flash, u32 offset, - size_t len, const void *buf) -{ - return flash->write(flash, offset, len, buf); -} - -static inline int spi_flash_erase(struct spi_flash *flash, u32 offset, - size_t len) -{ - return flash->erase(flash, offset, len); -} - #endif /* _SPI_FLASH_H_ */

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Patch set updated for coreboot: 7abd0c5 intel/rangeley: update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 05 Jan '15

05 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit 7abd0c5753ca873aaeba79e53ac152d73a98981d Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h old mode 100644 new mode 100755 index 12ac2be..fba38a0 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

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New patch to review for coreboot: d643856 intel/rangeley: update UPD_DATA_REGION to support POST-GOLD 2 FSP
by York Yang 05 Jan '15

05 Jan '15

York Yang (york.yang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8107 -gerrit commit d6438565c5b717864375c1226967e1552b457598 Author: York Yang <york.yang(a)intel.com> Date: Mon Jan 5 10:04:45 2015 -0700 intel/rangeley: update UPD_DATA_REGION to support POST-GOLD 2 FSP Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration by UPD input. Update UPD_DATA_REGION structure for matching up this FSP change. Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b Signed-off-by: York Yang <york.yang(a)intel.com> --- src/vendorcode/intel/fsp/rangeley/include/fspvpd.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h old mode 100644 new mode 100755 index 12ac2be..59d2f35 --- a/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h +++ b/src/vendorcode/intel/fsp/rangeley/include/fspvpd.h @@ -1,6 +1,6 @@ /** @file -Copyright (C) 2013, Intel Corporation +Copyright (C) 2013-2014 Intel Corporation Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: @@ -57,16 +57,21 @@ typedef struct _UPD_DATA_REGION { UINT8 PcdEnableIQAT; /* Offset 0x0033 */ UINT8 PcdEnableUsb20; /* Offset 0x0034 */ UINT8 PcdBifurcation; /* Offset 0x0035 */ - UINT8 UnusedUpdSpace2[10]; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort1DeEmphasis; /* Offset 0x0036 */ + UINT8 PcdPcieRootPort2DeEmphasis; /* Offset 0x0037 */ + UINT8 PcdPcieRootPort3DeEmphasis; /* Offset 0x0038 */ + UINT8 PcdPcieRootPort4DeEmphasis; /* Offset 0x0039 */ + UINT8 UnusedUpdSpace2[6]; /* Offset 0x003A */ UINT8 PcdPrintDebugMessages; /* Offset 0x0040 */ UINT8 PcdFastboot; /* Offset 0x0041 */ UINT8 PcdEccSupport; /* Offset 0x0042 */ - UINT8 UnusedUpdSpace3[13]; /* Offset 0x0043 */ - UINT16 PcdRegionTerminator; /* Offset 0x0050 */ + UINT8 PcdCustomerRevision[32]; /* Offset 0x0043 */ + UINT8 UnusedUpdSpace3[13]; /* Offset 0x0063 */ + UINT16 PcdRegionTerminator; /* Offset 0x0070 */ } UPD_DATA_REGION; #define VPD_IMAGE_ID 0x562D474E524E5641 /* 'AVNRNG-V' */ -#define VPD_IMAGE_REV 0x00000101 +#define VPD_IMAGE_REV 0x00000102 typedef struct _VPD_DATA_REGION { UINT64 PcdVpdRegionSign; /* Offset 0x0000 */

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New patch to review for coreboot: 2be75de arch/x86/include/stdint.h: Don't let header wind up in ASL files
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8106 -gerrit commit 2be75de76c1af560fdd24351eab71838d740d16b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 04:15:47 2015 +1100 arch/x86/include/stdint.h: Don't let header wind up in ASL files Push '#ifndef __ACPI__' guard into system header so that it does not wind up in ASL files DSDT builds. Change-Id: I59800b2f75196ff1c80a29f104ea9fa6706e51fb Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/include/stdint.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/arch/x86/include/stdint.h b/src/arch/x86/include/stdint.h index c491f4b..eed22e0 100644 --- a/src/arch/x86/include/stdint.h +++ b/src/arch/x86/include/stdint.h @@ -1,6 +1,8 @@ #ifndef I386_STDINT_H #define I386_STDINT_H +#ifndef __ACPI__ + #if defined(__GNUC__) #define __HAVE_LONG_LONG__ 1 #else @@ -89,7 +91,8 @@ typedef int32_t s32; #define PRIu64 "llu" #endif - #undef __HAVE_LONG_LONG__ +#endif /* __ACPI__ */ + #endif /* I386_STDINT_H */

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Patch set updated for coreboot: 421feb6 cpu/amd/model_10xxx/*: Trivial - Fix indent style
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8105 -gerrit commit 421feb623cb05198b08aef09f5a2f11b790a86dd Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 04:06:44 2015 +1100 cpu/amd/model_10xxx/*: Trivial - Fix indent style Change-Id: I54df9ed04a5100fe514d15bf82d0b58a3d9668f7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/model_10xxx/fidvid.c | 512 ++++++++++++++--------------- src/cpu/amd/model_10xxx/model_10xxx_init.c | 1 - 2 files changed, 249 insertions(+), 264 deletions(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index d3c67a9..8f34ffe 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -146,121 +146,121 @@ static void enable_fid_change(u8 fid) dword |= (u32) fid & 0x1F; dword |= 1 << 5; // enable pci_write_config32(dev, 0xd4, dword); - printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, - dword); + printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword); } } static void applyBoostFIDOffset( device_t dev ) { - // BKDG 2.4.2.8 - // revision E only, but E is apparently not supported yet, therefore untested - if ((cpuid_edx(0x80000007) & CPB_MASK) - && ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) { - u32 core = get_node_core_id_x().coreid; - u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; - msr_t msr = rdmsr(PS_REG_BASE); - u32 cpuFid = msr.lo & PS_CPU_FID_MASK; - cpuFid = cpuFid + asymetricBoostThisCore; - msr.lo &= ~PS_CPU_FID_MASK; - msr.lo |= cpuFid ; - wrmsr(PS_REG_BASE , msr); - - } + // BKDG 2.4.2.8 + // revision E only, but E is apparently not supported yet, therefore untested + if ((cpuid_edx(0x80000007) & CPB_MASK) && ((cpuid_ecx(0x80000008) & NC_MASK) == 5)) { + u32 core = get_node_core_id_x().coreid; + u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; + msr_t msr = rdmsr(PS_REG_BASE); + u32 cpuFid = msr.lo & PS_CPU_FID_MASK; + cpuFid = cpuFid + asymetricBoostThisCore; + msr.lo &= ~PS_CPU_FID_MASK; + msr.lo |= cpuFid ; + wrmsr(PS_REG_BASE , msr); + } } -static void enableNbPState1( device_t dev ) { - u32 cpuRev = mctGetLogicalCPUID(0xFF); - if (cpuRev & AMD_FAM10_C3) { - u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); - if ( nbPState){ - u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; - u32 i; - for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_EN_MASK ) { - msr.hi |= NB_DID_M_ON; - msr.lo &= NB_VID_MASK_OFF; - msr.lo |= ( nbVid1 << NB_VID_POS); - wrmsr(PS_REG_BASE + i, msr); - } - } - } - } +static void enableNbPState1(device_t dev) { + u32 cpuRev = mctGetLogicalCPUID(0xFF); + if (cpuRev & AMD_FAM10_C3) { + u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); + if (nbPState) { + u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; + u32 i; + for (i = nbPState; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; + msr.lo |= ( nbVid1 << NB_VID_POS); + wrmsr(PS_REG_BASE + i, msr); + } + } + } + } } -static u8 setPStateMaxVal( device_t dev ) { - u8 i,maxpstate=0; - for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_IDD_VALUE_MASK) { - msr.hi |= PS_EN_MASK ; - wrmsr(PS_REG_BASE + i, msr); - } - if (msr.hi & PS_EN_MASK) { - maxpstate = i; - } - } - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u32 reg = pci_read_config32(dev, CPTC2); - reg &= PS_MAX_VAL_MASK; - reg |= (maxpstate << PS_MAX_VAL_POS); - pci_write_config32(dev, CPTC2,reg); - return maxpstate; +static u8 setPStateMaxVal(device_t dev) { + u8 i, maxpstate = 0; + + for (i = 0; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_IDD_VALUE_MASK) { + msr.hi |= PS_EN_MASK ; + wrmsr(PS_REG_BASE + i, msr); + } + if (msr.hi & PS_EN_MASK) { + maxpstate = i; + } + } + + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u32 reg = pci_read_config32(dev, CPTC2); + reg &= PS_MAX_VAL_MASK; + reg |= (maxpstate << PS_MAX_VAL_POS); + pci_write_config32(dev, CPTC2,reg); + + return maxpstate; } -static void dualPlaneOnly( device_t dev ) { - // BKDG 2.4.2.7 - - u32 cpuRev = mctGetLogicalCPUID(0xFF); - if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) - && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E - if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) - && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){ - if (cpuid_edx(0x80000007) & CPB_MASK) { - // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(0xC0010065); - wrmsr(0xC0010065, rdmsr(0xC0010068) ); - wrmsr(0xC0010068,minPstate); - } else { - msr_t msr; - msr.lo=0; msr.hi=0; - wrmsr(0xC0010064, rdmsr(0xC0010068) ); - wrmsr(0xC0010068, msr ); - } - - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u8 maxpstate = setPStateMaxVal(dev); - - u32 reg = pci_read_config32(dev, HTC_REG); - reg &= HTC_PS_LMT_MASK; - reg |= (maxpstate << PS_LIMIT_POS); - pci_write_config32(dev, HTC_REG,reg); - - } - } +static void dualPlaneOnly(device_t dev) { +// BKDG 2.4.2.7 + u32 cpuRev = mctGetLogicalCPUID(0xFF); + + // should be rev C or rev E but there's no constant for E + if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) && (cpuRev & AMD_DR_Cx)) { + if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) && (pci_read_config32(dev, 0xA0) & PVI_MODE)) { + if (cpuid_edx(0x80000007) & CPB_MASK) { + // revision E only, but E is apparently not supported yet, therefore untested + msr_t minPstate = rdmsr(0xC0010065); + wrmsr(0xC0010065, rdmsr(0xC0010068)); + wrmsr(0xC0010068,minPstate); + } else { + msr_t msr; + msr.lo=0; + msr.hi=0; + wrmsr(0xC0010064, rdmsr(0xC0010068)); + wrmsr(0xC0010068, msr ); + } + + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u8 maxpstate = setPStateMaxVal(dev); + + u32 reg = pci_read_config32(dev, HTC_REG); + reg &= HTC_PS_LMT_MASK; + reg |= (maxpstate << PS_LIMIT_POS); + pci_write_config32(dev, HTC_REG,reg); + } + } } static int vidTo100uV(u8 vid) -{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV - // BKDG #31116 rev 3.48 2.4.1.6 - int voltage; - if (vid >= 0x7c) { - voltage = 0; - } else { - voltage = (15500 - (125*vid)); - } - return voltage; +{ + // returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV + // BKDG #31116 rev 3.48 2.4.1.6 + int voltage; + if (vid >= 0x7c) { + voltage = 0; + } else { + voltage = (15500 - (125*vid)); + } + return voltage; } static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] - * If this field accepts 8 values between 10 and 500 us why - * does page 324 say "BIOS should set this field to 001b." - * (20 us) ? - * Shouldn't it depend on the voltage regulators, mainboard - * or something ? - */ - u32 dword; + * If this field accepts 8 values between 10 and 500 us why + * does page 324 say "BIOS should set this field to 001b." + * (20 us) ? + * Shouldn't it depend on the voltage regulators, mainboard + * or something ? + */ + u32 dword; dword = pci_read_config32(dev, 0xd8); dword &= VSRAMP_MASK; dword |= VSRAMP_VALUE; @@ -278,12 +278,12 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* This function calculates the VsSlamTime using the range of possible * voltages instead of a hardcoded 200us. - * Note: his function is called only from prep_fid_change, - * and that from init_cpus.c finalize_node_setup() - * (after set AMD MSRs and init ht ) + * Note: his function is called only from prep_fid_change, + * and that from init_cpus.c finalize_node_setup() + * (after set AMD MSRs and init ht ) */ - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Calculate Slam Time * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV * In our case, we will scale the values by 100 to avoid @@ -299,16 +299,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pviModeFlag = 0; /* Get P0's voltage */ - /* MSRC001_00[68:64] are not programmed yet when called from - prep_fid_change, one might use F4x1[F0:E0] instead, but - theoretically MSRC001_00[68:64] are equal to them after - reset. */ + /* MSRC001_00[68:64] are not programmed yet when called from + * prep_fid_change, one might use F4x1[F0:E0] instead, but + * theoretically MSRC001_00[68:64] are equal to them after + * reset. + */ msr = rdmsr(0xC0010064); highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { - printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); - highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) - >> PS_CPU_VID_SHFT) & 0x7F); + if (!(msr.hi & 0x80000000)) { + printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); + highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) >> PS_CPU_VID_SHFT) & 0x7F); } /* If SVI, we only care about CPU VID. @@ -336,7 +336,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* If SVI, we only care about CPU VID. * If PVI, determine the higher voltage b/t NB and CPU * BKDG 2.4.1.7 (a) - */ + */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); if (lowVoltageVid > bValue) @@ -351,7 +351,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) if (lowVoltageVid < bValue) lowVoltageVid = bValue; - u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; + u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */ @@ -372,23 +372,23 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) } static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { - u8 link0isGen3 = 0; - u8 offset; - if (AMD_CpuFindCapability(node, 0, &offset)) { - link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); + u8 link0isGen3 = 0; + u8 offset; + + if (AMD_CpuFindCapability(node, 0, &offset)) { + link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); + } + /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package + * S1g3 in link Gen3 mode, but I don't know how to tell + * package S1g3 from S1g4 + */ + if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) && link0isGen3) { + return 5 ; /* divide clk by 128*/ + } else { + return 4 ; /* divide clk by 16 */ } - /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package - S1g3 in link Gen3 mode, but I don't know how to tell - package S1g3 from S1g4 */ - if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) - && link0isGen3) { - return 5 ; /* divide clk by 128*/ - } else { - return 4 ; /* divide clk by 16 */ - } } - static u32 power_up_down(int node, u8 procPkg) { u32 dword=0; /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ @@ -504,83 +504,79 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ - /* adjust FIFO between nb and core clocks to max allowed - values (min latency) */ + /* adjust FIFO between nb and core clocks to max allowed values (min latency) */ u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; - u8 nbSynPtrAdj; - if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) - || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { - nbSynPtrAdj = 5; + u8 nbSynPtrAdj; + + if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx)) || ((cpuRev & AMD_RB_C3) && (nbPstate!=0))) { + nbSynPtrAdj = 5; } else { - nbSynPtrAdj = 6; + nbSynPtrAdj = 6; } u32 dword = pci_read_config32(dev, 0xDc); - dword &= ~ NB_SYN_PTR_ADJ_MASK; + dword &= ~ NB_SYN_PTR_ADJ_MASK; dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; - /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ + /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); } static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { - /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ - u32 dword; - u32 c1= 1; - if (cpuRev & (AMD_DR_Bx)) { - // will coreboot ever enable cache scrubbing ? - // if it does, will it be enough to check the current state - // or should we configure for what we'll set up later ? - dword = pci_read_config32(dev, 0x58); - u32 scrubbingCache = dword & - ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub - if (scrubbingCache) { - c1 = 0x80; - } else { - c1 = 0xA0; - } + /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ + u32 dword; + u32 c1 = 1; + if (cpuRev & (AMD_DR_Bx)) { + // will coreboot ever enable cache scrubbing ? + // if it does, will it be enough to check the current state + // or should we configure for what we'll set up later ? + dword = pci_read_config32(dev, 0x58); + u32 scrubbingCache = dword & ((0x1F << 16) /* DCacheScrub */ | (0x1F << 8)); /* L2Scrub */ + if (scrubbingCache) { + c1 = 0x80; + } else { + c1 = 0xA0; + } } else { // rev C or later - // same doubt as cache scrubbing: ok to check current state ? - dword = pci_read_config32(dev, 0xDC); - u32 cacheFlushOnHalt = dword & (7 << 16); - if (!cacheFlushOnHalt) { - c1 = 0x80; - } - } - dword = (c1 << 24) | (0xE641E6); + // same doubt as cache scrubbing: ok to check current state ? + dword = pci_read_config32(dev, 0xDC); + u32 cacheFlushOnHalt = dword & (7 << 16); + if (!cacheFlushOnHalt) { + c1 = 0x80; + } + } + dword = (c1 << 24) | (0xE641E6); pci_write_config32(dev, 0x84, dword); - /* FIXME: BKDG Table 100 says if the link is at a Gen1 -frequency and the chipset does not support a 10us minimum LDTSTOP -assertion time, then { If ASB2 && SVI then smaf001 = F6h else -smaf001=87h. } else ... I hardly know what it means or how to check -it from here, so I bluntly assume it is false and code here the else, -which is easier */ - - u32 smaf001 = 0xE6; - if (cpuRev & AMD_DR_Bx ) { - smaf001 = 0xA6; - } else { - #if CONFIG_SVI_HIGH_FREQ - if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { - smaf001 = 0xF6; +/* FIXME: BKDG Table 100 says if the link is at a Gen1 + * frequency and the chipset does not support a 10us minimum LDTSTOP + * assertion time, then { If ASB2 && SVI then smaf001 = F6h else + * smaf001=87h. } else ... I hardly know what it means or how to check + * it from here, so I bluntly assume it is false and code here the else, + * which is easier + */ + + u32 smaf001 = 0xE6; + if (cpuRev & AMD_DR_Bx ) { + smaf001 = 0xA6; + } else { +#if CONFIG_SVI_HIGH_FREQ + if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { + smaf001 = 0xF6; } - #endif - } - u32 fidvidChange = 0; - if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) - || (cpuRev & AMD_RB_C3) ) { - fidvidChange=0x0B; - } - dword = (0xE6 << 24) | (fidvidChange << 16) - | (smaf001 << 8) | 0x81; +#endif + } + u32 fidvidChange = 0; + if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) || (cpuRev & AMD_RB_C3) ) { + fidvidChange = 0x0B; + } + dword = (0xE6 << 24) | (fidvidChange << 16) | (smaf001 << 8) | 0x81; pci_write_config32(dev, 0x80, dword); } static void prep_fid_change(void) { - u32 dword; + u32 dword; u32 nodes; device_t dev; int i; @@ -592,20 +588,20 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i, 3); - u32 cpuRev = mctGetLogicalCPUID(0xFF) ; - u8 procPkg = mctGetProcessorPackageType(); + u32 cpuRev = mctGetLogicalCPUID(0xFF) ; + u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev); - config_clk_power_ctrl_reg0(i,cpuRev,procPkg); + config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - config_power_ctrl_misc_reg(dev,cpuRev,procPkg); + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev,cpuRev); - config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); + config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword); @@ -617,54 +613,51 @@ static void prep_fid_change(void) printk(BIOS_DEBUG, " F3xD8: %08x \n", dword); dword = pci_read_config32(dev, 0xDC); printk(BIOS_DEBUG, " F3xDC: %08x \n", dword); - - } } static void waitCurrentPstate(u32 target_pstate){ - msr_t initial_msr = rdmsr(TSC_MSR); - msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); - msr_t tsc_msr; - u8 timedout ; - - /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a - * P1 that is a copy of P0, therefore has the same NB DID but the - * TSC will count twice per tick, so we have to wait for twice the - * count to achieve the desired timeout. But I'm likely to - * misunderstand this... - */ - u32 corrected_timeout = ( (pstate_msr.lo==1) - && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? - WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; - msr_t timeout; - - timeout.lo = initial_msr.lo + corrected_timeout ; - timeout.hi = initial_msr.hi; - if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { - timeout.hi++; - } - - // assuming TSC ticks at 1.25 ns per tick (800 MHz) - do { - pstate_msr = rdmsr(CUR_PSTATE_MSR); - tsc_msr = rdmsr(TSC_MSR); - timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; - - if (pstate_msr.lo != target_pstate) { - msr_t limit_msr = rdmsr(0xc0010061); - printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo); - - do { // should we just go on instead ? - pstate_msr = rdmsr(CUR_PSTATE_MSR); - } while ( pstate_msr.lo != target_pstate ) ; - } + msr_t initial_msr = rdmsr(TSC_MSR); + msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + msr_t tsc_msr; + msr_t timeout; + u8 timedout; + + /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a + * P1 that is a copy of P0, therefore has the same NB DID but the + * TSC will count twice per tick, so we have to wait for twice the + * count to achieve the desired timeout. But I'm likely to + * misunderstand this... + */ + u32 corrected_timeout = ((pstate_msr.lo==1) + && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; + + timeout.lo = initial_msr.lo + corrected_timeout ; + timeout.hi = initial_msr.hi; + if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { + timeout.hi++; + } + + // assuming TSC ticks at 1.25 ns per tick (800 MHz) + do { + pstate_msr = rdmsr(CUR_PSTATE_MSR); + tsc_msr = rdmsr(TSC_MSR); + timedout = (tsc_msr.hi > timeout.hi) || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); + } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; + + if (pstate_msr.lo != target_pstate) { + msr_t limit_msr = rdmsr(0xc0010061); + printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo); + + do { // should we just go on instead ? + pstate_msr = rdmsr(CUR_PSTATE_MSR); + } while ( pstate_msr.lo != target_pstate ) ; + } } -static void set_pstate(u32 nonBoostedPState) { - msr_t msr; +static void set_pstate(u32 nonBoostedPState) +{ + msr_t msr; // Transition P0 for calling core. msr = rdmsr(0xC0010062); @@ -673,12 +666,9 @@ static void set_pstate(u32 nonBoostedPState) { wrmsr(0xC0010062, msr); /* Wait for P0 to set. */ - waitCurrentPstate(nonBoostedPState); + waitCurrentPstate(nonBoostedPState); } - - - static void UpdateSinglePlaneNbVid(void) { u32 nbVid, cpuVid; @@ -704,23 +694,23 @@ static void UpdateSinglePlaneNbVid(void) } static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) - { - msr_t msr; - u8 startup_pstate; +{ + msr_t msr; + u8 startup_pstate; - /* This function sets NbVid before the warm reset. - * Get StartupPstate from MSRC001_0071. + /* This function sets NbVid before the warm reset. + * Get StartupPstate from MSRC001_0071. * Read Pstate register pointed by [StartupPstate]. - * and copy its content to P0 and P1 registers. - * Copy newNbVid to P0[NbVid]. - * transition to P1 on all cores, - * then transition to P0 on core 0. - * Wait for MSRC001_0063[CurPstate] = 000b on core 0. - * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems - */ - - msr = rdmsr(0xc0010071); + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. + * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems + */ + + msr = rdmsr(0xc0010071); startup_pstate = (msr.hi >> (32 - 32)) & 0x07; /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for @@ -731,13 +721,13 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr); - /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = - * max(1,F3xDC[PstateMaxVal] ) because it would take - * synchronization between cores and we don't think - * PstatMaxVal is going to be 0 on cold reset anyway ? + /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = + * max(1,F3xDC[PstateMaxVal] ) because it would take + * synchronization between cores and we don't think + * PstatMaxVal is going to be 0 on cold reset anyway ? */ - if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { - printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); + if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { + printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); }; msr.lo &= ~0xFE000000; // clear nbvid @@ -753,12 +743,11 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) if (coreid == 0) { set_pstate(0); - } + } /* missing step 7 (restore PstateMax to 0 if needed) because * we skipped step 2 */ - } static u32 needs_NB_COF_VID_update(void) @@ -888,7 +877,6 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) fvp->common_fid = calc_common_fid(fvp->common_fid, readback); print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid); - } static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) @@ -930,7 +918,6 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) /* Set and wait for StartupPstate to set. */ set_pstate(StartupPstate); - } static void finalPstateChange(void) @@ -979,9 +966,9 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp); - dualPlaneOnly(dev); - applyBoostFIDOffset(dev); - enableNbPState1(dev); + dualPlaneOnly(dev); + applyBoostFIDOffset(dev); + enableNbPState1(dev); finalPstateChange(); @@ -1002,7 +989,6 @@ struct ap_apicid_st { static void store_ap_apicid(unsigned ap_apicid, void *gp) { struct ap_apicid_st *p = gp; - p->apicid[p->num++] = ap_apicid; } diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..453684a 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -113,7 +113,6 @@ static void model_10xxx_init(device_t dev) msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); - } static struct device_operations cpu_dev_ops = {

1 0

Patch set updated for coreboot: 4e44642 {north, south}bridge/*: Use system include path syntax over relative local
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8104 -gerrit commit 4e44642b9421a726215cc46e07b7af764a98954e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 02:44:20 2015 +1100 {north,south}bridge/*: Use system include path syntax over relative local Change-Id: Ib7fe3a9d672a02c9a91e3b320fefdbd98fd16cff Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/northbridge.c | 2 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 2 +- src/northbridge/intel/gm45/gm45.h | 5 ++--- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/report_platform.c | 2 +- src/northbridge/intel/i945/i945.h | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit_native.c | 8 ++++---- src/northbridge/intel/sandybridge/report_platform.c | 2 +- src/northbridge/intel/sandybridge/romstage_native.c | 4 ++-- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cs5535/chipsetinit.c | 4 ++-- src/southbridge/dmp/vortex86ex/southbridge.c | 4 ++-- src/southbridge/intel/bd82x6x/early_pch_native.c | 2 +- src/southbridge/intel/bd82x6x/early_rcba.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- src/southbridge/intel/bd82x6x/nvs.h | 3 ++- src/southbridge/intel/bd82x6x/smi.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/nvs.h | 3 ++- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_rangeley/romstage.c | 8 ++++---- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/nvs.h | 3 ++- src/southbridge/intel/ibexpeak/smi.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/nvs.h | 3 ++- 29 files changed, 43 insertions(+), 41 deletions(-) diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..aa09e08 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> void print_conf(void); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..c4214ad 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -33,7 +33,7 @@ #include <cpu/amd/vr.h> #include <cpu/cpu.h> #include "northbridge.h" -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> /* here is programming for the various MSRs.*/ diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 7c95ab4..656c6e5 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,7 +22,7 @@ #include <cpu/amd/lxdef.h> #include <arch/io.h> #include <spd.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "raminit.h" #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5bdf9e4..4e50aba 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,12 +21,11 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <stdint.h> #ifndef __ACPI__ -#include <stdint.h> - typedef enum { FSB_CLOCK_1067MHz = 0, FSB_CLOCK_800MHz = 1, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..e366c3f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -30,7 +30,7 @@ #include <cpu/x86/mtrr.h> #include <kconfig.h> -#include "drivers/intel/gma/i915_reg.h" +#include <drivers/intel/gma/i915_reg.h> #include "chip.h" #include "gm45.h" #include <drivers/intel/gma/intel_bios.h> diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8bb4a05..33da3b5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/lynxpoint/pch.h" +#include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe59ebe..651b75a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -27,7 +27,7 @@ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9ca98d5..7d37cb8 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -55,7 +55,7 @@ typedef u32 device_t; #include "nehalem.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/me.h> #if REAL #include <delay.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f6c92db..0f13f01 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -34,7 +34,7 @@ #include "sandybridge.h" /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* * MRC scrambler seed offsets should be reserved in diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index de6dac7..77c4005 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -36,11 +36,11 @@ #include <lib.h> /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* For SPD. */ -#include "southbridge/intel/bd82x6x/smbus.h" -#include "arch/cpu.h" -#include "cpu/x86/msr.h" +#include <southbridge/intel/bd82x6x/smbus.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 8230729..f189697 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/bd82x6x/pch.h> #include <arch/io.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 737cd63..400a079 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -31,8 +31,8 @@ #include <cpu/intel/romstage.h> #include <halt.h> #include "raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> void main(unsigned long bist) { diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 59d89b0..1a618b5 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -156,7 +156,7 @@ typedef union _PCI_ADDR { #define cimFusionMsgCMultiCoreDefault FALSE #define cimFusionMsgCStageDefault FALSE -#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h> #if CONFIG_HAVE_ACPI_RESUME #include <spi-generic.h> diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index ab1b640..e6aec1d 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -7,11 +7,11 @@ #include <stdlib.h> #include <string.h> #include "chip.h" -#include "northbridge/amd/gx2/northbridge.h" +#include <northbridge/amd/gx2/northbridge.h> #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h> /* the structs in this file only set msr.lo. But ... that may not always be true */ diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 2fe1bc2..c8aeb56 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -26,10 +26,10 @@ #include <pc80/keyboard.h> #include <string.h> #include <delay.h> -#include "arch/io.h" +#include <arch/io.h> #include "chip.h" #include "southbridge.h" -#include "cpu/dmp/dmp_post_code.h" +#include <cpu/dmp/dmp_post_code.h> /* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */ static const unsigned char irq_to_int_routing[16] = { diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c index 0863f34..a16da96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_native.c +++ b/src/southbridge/intel/bd82x6x/early_pch_native.c @@ -30,7 +30,7 @@ #include "pch.h" /* For DMI bar. */ -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 114b174..d63b7b3 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -21,7 +21,7 @@ #include <stdint.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> void southbridge_configure_default_intmap(void) diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 02ec9a7..2328be3 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_206ax/model_206ax.h" +#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b1f8447..f4ce625 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */ +#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ #include "pch.h" void diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index a20232e..5bb153d 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> @@ -29,7 +28,7 @@ #include <cpu/x86/smm.h> #include <string.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 8557c02..dde07e2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 827b897..1847b22 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -31,7 +31,7 @@ #include "pch.h" #if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include "northbridge/intel/fsp_sandybridge/northbridge.h" +#include <northbridge/intel/fsp_sandybridge/northbridge.h> #endif extern unsigned char _binary_smm_start; diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e..d910498 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -30,10 +30,10 @@ #include <cbmem.h> #include <console/console.h> #include <drivers/intel/fsp/fsp_util.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" -#include "southbridge/intel/fsp_rangeley/soc.h" -#include "southbridge/intel/fsp_rangeley/gpio.h" -#include "southbridge/intel/fsp_rangeley/romstage.h" +#include <northbridge/intel/fsp_rangeley/northbridge.h> +#include <southbridge/intel/fsp_rangeley/soc.h> +#include <southbridge/intel/fsp_rangeley/gpio.h> +#include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> #include <arch/stages.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index d23749e..fee2269 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_2065x/model_2065x.h" +#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..d83cd0a 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -31,7 +31,7 @@ #include <string.h> #include "pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..39fc40c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -36,7 +36,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> #include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 81b2321..790953f 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */

1 0

New patch to review for coreboot: b7c44ba cpu/amd/model_10xxx/*: Trivial - Fix indent style
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8105 -gerrit commit b7c44bae0fcb0dc534bf9e6c52d85ec2064a8ae2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 04:06:44 2015 +1100 cpu/amd/model_10xxx/*: Trivial - Fix indent style Change-Id: I54df9ed04a5100fe514d15bf82d0b58a3d9668f7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/amd/model_10xxx/fidvid.c | 512 ++++++++++++++--------------- src/cpu/amd/model_10xxx/model_10xxx_init.c | 1 - 2 files changed, 249 insertions(+), 264 deletions(-) diff --git a/src/cpu/amd/model_10xxx/fidvid.c b/src/cpu/amd/model_10xxx/fidvid.c index d3c67a9..8f34ffe 100644 --- a/src/cpu/amd/model_10xxx/fidvid.c +++ b/src/cpu/amd/model_10xxx/fidvid.c @@ -146,121 +146,121 @@ static void enable_fid_change(u8 fid) dword |= (u32) fid & 0x1F; dword |= 1 << 5; // enable pci_write_config32(dev, 0xd4, dword); - printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, - dword); + printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword); } } static void applyBoostFIDOffset( device_t dev ) { - // BKDG 2.4.2.8 - // revision E only, but E is apparently not supported yet, therefore untested - if ((cpuid_edx(0x80000007) & CPB_MASK) - && ((cpuid_ecx(0x80000008) & NC_MASK) ==5) ) { - u32 core = get_node_core_id_x().coreid; - u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; - msr_t msr = rdmsr(PS_REG_BASE); - u32 cpuFid = msr.lo & PS_CPU_FID_MASK; - cpuFid = cpuFid + asymetricBoostThisCore; - msr.lo &= ~PS_CPU_FID_MASK; - msr.lo |= cpuFid ; - wrmsr(PS_REG_BASE , msr); - - } + // BKDG 2.4.2.8 + // revision E only, but E is apparently not supported yet, therefore untested + if ((cpuid_edx(0x80000007) & CPB_MASK) && ((cpuid_ecx(0x80000008) & NC_MASK) == 5)) { + u32 core = get_node_core_id_x().coreid; + u32 asymetricBoostThisCore = ((pci_read_config32(dev, 0x10C) >> (core*2))) & 3; + msr_t msr = rdmsr(PS_REG_BASE); + u32 cpuFid = msr.lo & PS_CPU_FID_MASK; + cpuFid = cpuFid + asymetricBoostThisCore; + msr.lo &= ~PS_CPU_FID_MASK; + msr.lo |= cpuFid ; + wrmsr(PS_REG_BASE , msr); + } } -static void enableNbPState1( device_t dev ) { - u32 cpuRev = mctGetLogicalCPUID(0xFF); - if (cpuRev & AMD_FAM10_C3) { - u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); - if ( nbPState){ - u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; - u32 i; - for (i = nbPState; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_EN_MASK ) { - msr.hi |= NB_DID_M_ON; - msr.lo &= NB_VID_MASK_OFF; - msr.lo |= ( nbVid1 << NB_VID_POS); - wrmsr(PS_REG_BASE + i, msr); - } - } - } - } +static void enableNbPState1(device_t dev) { + u32 cpuRev = mctGetLogicalCPUID(0xFF); + if (cpuRev & AMD_FAM10_C3) { + u32 nbPState = (pci_read_config32(dev, 0x1F0) & NB_PSTATE_MASK); + if (nbPState) { + u32 nbVid1 = (pci_read_config32(dev, 0x1F4) & NB_VID1_MASK) >> NB_VID1_SHIFT; + u32 i; + for (i = nbPState; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_EN_MASK ) { + msr.hi |= NB_DID_M_ON; + msr.lo &= NB_VID_MASK_OFF; + msr.lo |= ( nbVid1 << NB_VID_POS); + wrmsr(PS_REG_BASE + i, msr); + } + } + } + } } -static u8 setPStateMaxVal( device_t dev ) { - u8 i,maxpstate=0; - for (i = 0; i < NM_PS_REG; i++) { - msr_t msr = rdmsr(PS_REG_BASE + i); - if (msr.hi & PS_IDD_VALUE_MASK) { - msr.hi |= PS_EN_MASK ; - wrmsr(PS_REG_BASE + i, msr); - } - if (msr.hi & PS_EN_MASK) { - maxpstate = i; - } - } - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u32 reg = pci_read_config32(dev, CPTC2); - reg &= PS_MAX_VAL_MASK; - reg |= (maxpstate << PS_MAX_VAL_POS); - pci_write_config32(dev, CPTC2,reg); - return maxpstate; +static u8 setPStateMaxVal(device_t dev) { + u8 i, maxpstate = 0; + + for (i = 0; i < NM_PS_REG; i++) { + msr_t msr = rdmsr(PS_REG_BASE + i); + if (msr.hi & PS_IDD_VALUE_MASK) { + msr.hi |= PS_EN_MASK ; + wrmsr(PS_REG_BASE + i, msr); + } + if (msr.hi & PS_EN_MASK) { + maxpstate = i; + } + } + + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u32 reg = pci_read_config32(dev, CPTC2); + reg &= PS_MAX_VAL_MASK; + reg |= (maxpstate << PS_MAX_VAL_POS); + pci_write_config32(dev, CPTC2,reg); + + return maxpstate; } -static void dualPlaneOnly( device_t dev ) { - // BKDG 2.4.2.7 - - u32 cpuRev = mctGetLogicalCPUID(0xFF); - if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) - && (cpuRev & AMD_DR_Cx)) { // should be rev C or rev E but there's no constant for E - if ( (pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) - && (pci_read_config32(dev, 0xA0) & PVI_MODE) ){ - if (cpuid_edx(0x80000007) & CPB_MASK) { - // revision E only, but E is apparently not supported yet, therefore untested - msr_t minPstate = rdmsr(0xC0010065); - wrmsr(0xC0010065, rdmsr(0xC0010068) ); - wrmsr(0xC0010068,minPstate); - } else { - msr_t msr; - msr.lo=0; msr.hi=0; - wrmsr(0xC0010064, rdmsr(0xC0010068) ); - wrmsr(0xC0010068, msr ); - } - - //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? - u8 maxpstate = setPStateMaxVal(dev); - - u32 reg = pci_read_config32(dev, HTC_REG); - reg &= HTC_PS_LMT_MASK; - reg |= (maxpstate << PS_LIMIT_POS); - pci_write_config32(dev, HTC_REG,reg); - - } - } +static void dualPlaneOnly(device_t dev) { +// BKDG 2.4.2.7 + u32 cpuRev = mctGetLogicalCPUID(0xFF); + + // should be rev C or rev E but there's no constant for E + if ((mctGetProcessorPackageType() == AMD_PKGTYPE_AM3_2r2) && (cpuRev & AMD_DR_Cx)) { + if ((pci_read_config32(dev, 0x1FC) & DUAL_PLANE_ONLY_MASK) && (pci_read_config32(dev, 0xA0) & PVI_MODE)) { + if (cpuid_edx(0x80000007) & CPB_MASK) { + // revision E only, but E is apparently not supported yet, therefore untested + msr_t minPstate = rdmsr(0xC0010065); + wrmsr(0xC0010065, rdmsr(0xC0010068)); + wrmsr(0xC0010068,minPstate); + } else { + msr_t msr; + msr.lo=0; + msr.hi=0; + wrmsr(0xC0010064, rdmsr(0xC0010068)); + wrmsr(0xC0010068, msr ); + } + + //FIXME: CPTC2 and HTC_REG should get max per node, not per core ? + u8 maxpstate = setPStateMaxVal(dev); + + u32 reg = pci_read_config32(dev, HTC_REG); + reg &= HTC_PS_LMT_MASK; + reg |= (maxpstate << PS_LIMIT_POS); + pci_write_config32(dev, HTC_REG,reg); + } + } } static int vidTo100uV(u8 vid) -{// returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV - // BKDG #31116 rev 3.48 2.4.1.6 - int voltage; - if (vid >= 0x7c) { - voltage = 0; - } else { - voltage = (15500 - (125*vid)); - } - return voltage; +{ + // returns voltage corresponding to vid in tenths of mV, i.e. hundreds of uV + // BKDG #31116 rev 3.48 2.4.1.6 + int voltage; + if (vid >= 0x7c) { + voltage = 0; + } else { + voltage = (15500 - (125*vid)); + } + return voltage; } static void setVSRamp(device_t dev) { /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSRampTime] - * If this field accepts 8 values between 10 and 500 us why - * does page 324 say "BIOS should set this field to 001b." - * (20 us) ? - * Shouldn't it depend on the voltage regulators, mainboard - * or something ? - */ - u32 dword; + * If this field accepts 8 values between 10 and 500 us why + * does page 324 say "BIOS should set this field to 001b." + * (20 us) ? + * Shouldn't it depend on the voltage regulators, mainboard + * or something ? + */ + u32 dword; dword = pci_read_config32(dev, 0xd8); dword &= VSRAMP_MASK; dword |= VSRAMP_VALUE; @@ -278,12 +278,12 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* This function calculates the VsSlamTime using the range of possible * voltages instead of a hardcoded 200us. - * Note: his function is called only from prep_fid_change, - * and that from init_cpus.c finalize_node_setup() - * (after set AMD MSRs and init ht ) + * Note: his function is called only from prep_fid_change, + * and that from init_cpus.c finalize_node_setup() + * (after set AMD MSRs and init ht ) */ - /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ + /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Calculate Slam Time * Vslam = (mobileCPU?0.2:0.4)us/mV * (Vp0 - (lowest out of Vpmin or Valt)) mV * In our case, we will scale the values by 100 to avoid @@ -299,16 +299,16 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) pviModeFlag = 0; /* Get P0's voltage */ - /* MSRC001_00[68:64] are not programmed yet when called from - prep_fid_change, one might use F4x1[F0:E0] instead, but - theoretically MSRC001_00[68:64] are equal to them after - reset. */ + /* MSRC001_00[68:64] are not programmed yet when called from + * prep_fid_change, one might use F4x1[F0:E0] instead, but + * theoretically MSRC001_00[68:64] are equal to them after + * reset. + */ msr = rdmsr(0xC0010064); highVoltageVid = (u8) ((msr.lo >> PS_CPU_VID_SHFT) & 0x7F); - if (!(msr.hi & 0x80000000)) { - printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); - highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) - >> PS_CPU_VID_SHFT) & 0x7F); + if (!(msr.hi & 0x80000000)) { + printk(BIOS_ERR,"P-state info in MSRC001_0064 is invalid !!!\n"); + highVoltageVid = (u8) ((pci_read_config32(dev, 0x1E0) >> PS_CPU_VID_SHFT) & 0x7F); } /* If SVI, we only care about CPU VID. @@ -336,7 +336,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) /* If SVI, we only care about CPU VID. * If PVI, determine the higher voltage b/t NB and CPU * BKDG 2.4.1.7 (a) - */ + */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); if (lowVoltageVid > bValue) @@ -351,7 +351,7 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) if (lowVoltageVid < bValue) lowVoltageVid = bValue; - u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; + u8 mobileFlag = get_platform_type() & AMD_PTYPE_MOB; minimumSlamTime = (mobileFlag?2:4) * (vidTo100uV(highVoltageVid) - vidTo100uV(lowVoltageVid)); /* * 0.01 us */ @@ -372,23 +372,23 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) } static u32 nb_clk_did(int node, u32 cpuRev,u8 procPkg) { - u8 link0isGen3 = 0; - u8 offset; - if (AMD_CpuFindCapability(node, 0, &offset)) { - link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); + u8 link0isGen3 = 0; + u8 offset; + + if (AMD_CpuFindCapability(node, 0, &offset)) { + link0isGen3 = (AMD_checkLinkType(node, 0, offset) & HTPHY_LINKTYPE_HT3 ); + } + /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package + * S1g3 in link Gen3 mode, but I don't know how to tell + * package S1g3 from S1g4 + */ + if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) && link0isGen3) { + return 5 ; /* divide clk by 128*/ + } else { + return 4 ; /* divide clk by 16 */ } - /* FIXME: NB_CLKDID should be 101b for AMD_DA_C2 in package - S1g3 in link Gen3 mode, but I don't know how to tell - package S1g3 from S1g4 */ - if ((cpuRev & AMD_DA_C2) && (procPkg & AMD_PKGTYPE_S1gX) - && link0isGen3) { - return 5 ; /* divide clk by 128*/ - } else { - return 4 ; /* divide clk by 16 */ - } } - static u32 power_up_down(int node, u8 procPkg) { u32 dword=0; /* from CPU rev guide #41322 rev 3.74 June 2010 Table 26 */ @@ -504,83 +504,79 @@ static void config_nb_syn_ptr_adj(device_t dev, u32 cpuRev) { /* Note the following settings are additional from the ported * function setFidVidRegs() */ - /* adjust FIFO between nb and core clocks to max allowed - values (min latency) */ + /* adjust FIFO between nb and core clocks to max allowed values (min latency) */ u32 nbPstate = pci_read_config32(dev,0x1f0) & NB_PSTATE_MASK; - u8 nbSynPtrAdj; - if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx) ) - || ( (cpuRev & AMD_RB_C3) && (nbPstate!=0))) { - nbSynPtrAdj = 5; + u8 nbSynPtrAdj; + + if ((cpuRev & (AMD_DR_Bx|AMD_DA_Cx)) || ((cpuRev & AMD_RB_C3) && (nbPstate!=0))) { + nbSynPtrAdj = 5; } else { - nbSynPtrAdj = 6; + nbSynPtrAdj = 6; } u32 dword = pci_read_config32(dev, 0xDc); - dword &= ~ NB_SYN_PTR_ADJ_MASK; + dword &= ~ NB_SYN_PTR_ADJ_MASK; dword |= nbSynPtrAdj << NB_SYN_PTR_ADJ_POS; - /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ + /* NbsynPtrAdj set to 5 or 6 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); } static void config_acpi_pwr_state_ctrl_regs(device_t dev, u32 cpuRev, u8 procPkg) { - /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ - u32 dword; - u32 c1= 1; - if (cpuRev & (AMD_DR_Bx)) { - // will coreboot ever enable cache scrubbing ? - // if it does, will it be enough to check the current state - // or should we configure for what we'll set up later ? - dword = pci_read_config32(dev, 0x58); - u32 scrubbingCache = dword & - ( (0x1F << 16) // DCacheScrub - | (0x1F << 8) ); // L2Scrub - if (scrubbingCache) { - c1 = 0x80; - } else { - c1 = 0xA0; - } + /* step 1, chapter 2.4.2.6 of AMD Fam 10 BKDG #31116 Rev 3.48 22.4.2010 */ + u32 dword; + u32 c1 = 1; + if (cpuRev & (AMD_DR_Bx)) { + // will coreboot ever enable cache scrubbing ? + // if it does, will it be enough to check the current state + // or should we configure for what we'll set up later ? + dword = pci_read_config32(dev, 0x58); + u32 scrubbingCache = dword & ((0x1F << 16) /* DCacheScrub */ | (0x1F << 8)); /* L2Scrub */ + if (scrubbingCache) { + c1 = 0x80; + } else { + c1 = 0xA0; + } } else { // rev C or later - // same doubt as cache scrubbing: ok to check current state ? - dword = pci_read_config32(dev, 0xDC); - u32 cacheFlushOnHalt = dword & (7 << 16); - if (!cacheFlushOnHalt) { - c1 = 0x80; - } - } - dword = (c1 << 24) | (0xE641E6); + // same doubt as cache scrubbing: ok to check current state ? + dword = pci_read_config32(dev, 0xDC); + u32 cacheFlushOnHalt = dword & (7 << 16); + if (!cacheFlushOnHalt) { + c1 = 0x80; + } + } + dword = (c1 << 24) | (0xE641E6); pci_write_config32(dev, 0x84, dword); - /* FIXME: BKDG Table 100 says if the link is at a Gen1 -frequency and the chipset does not support a 10us minimum LDTSTOP -assertion time, then { If ASB2 && SVI then smaf001 = F6h else -smaf001=87h. } else ... I hardly know what it means or how to check -it from here, so I bluntly assume it is false and code here the else, -which is easier */ - - u32 smaf001 = 0xE6; - if (cpuRev & AMD_DR_Bx ) { - smaf001 = 0xA6; - } else { - #if CONFIG_SVI_HIGH_FREQ - if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { - smaf001 = 0xF6; +/* FIXME: BKDG Table 100 says if the link is at a Gen1 + * frequency and the chipset does not support a 10us minimum LDTSTOP + * assertion time, then { If ASB2 && SVI then smaf001 = F6h else + * smaf001=87h. } else ... I hardly know what it means or how to check + * it from here, so I bluntly assume it is false and code here the else, + * which is easier + */ + + u32 smaf001 = 0xE6; + if (cpuRev & AMD_DR_Bx ) { + smaf001 = 0xA6; + } else { +#if CONFIG_SVI_HIGH_FREQ + if (cpuRev & (AMD_RB_C3 | AMD_DA_C3)) { + smaf001 = 0xF6; } - #endif - } - u32 fidvidChange = 0; - if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) - || (cpuRev & AMD_RB_C3) ) { - fidvidChange=0x0B; - } - dword = (0xE6 << 24) | (fidvidChange << 16) - | (smaf001 << 8) | 0x81; +#endif + } + u32 fidvidChange = 0; + if (((cpuRev & AMD_DA_Cx) && (procPkg & AMD_PKGTYPE_S1gX)) || (cpuRev & AMD_RB_C3) ) { + fidvidChange = 0x0B; + } + dword = (0xE6 << 24) | (fidvidChange << 16) | (smaf001 << 8) | 0x81; pci_write_config32(dev, 0x80, dword); } static void prep_fid_change(void) { - u32 dword; + u32 dword; u32 nodes; device_t dev; int i; @@ -592,20 +588,20 @@ static void prep_fid_change(void) for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); dev = NODE_PCI(i, 3); - u32 cpuRev = mctGetLogicalCPUID(0xFF) ; - u8 procPkg = mctGetProcessorPackageType(); + u32 cpuRev = mctGetLogicalCPUID(0xFF) ; + u8 procPkg = mctGetProcessorPackageType(); setVSRamp(dev); /* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */ /* Figure out the value for VsSlamTime and program it */ recalculateVsSlamTimeSettingOnCorePre(dev); - config_clk_power_ctrl_reg0(i,cpuRev,procPkg); + config_clk_power_ctrl_reg0(i,cpuRev,procPkg); - config_power_ctrl_misc_reg(dev,cpuRev,procPkg); + config_power_ctrl_misc_reg(dev,cpuRev,procPkg); config_nb_syn_ptr_adj(dev,cpuRev); - config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); + config_acpi_pwr_state_ctrl_regs(dev,cpuRev,procPkg); dword = pci_read_config32(dev, 0x80); printk(BIOS_DEBUG, " F3x80: %08x \n", dword); @@ -617,54 +613,51 @@ static void prep_fid_change(void) printk(BIOS_DEBUG, " F3xD8: %08x \n", dword); dword = pci_read_config32(dev, 0xDC); printk(BIOS_DEBUG, " F3xDC: %08x \n", dword); - - } } static void waitCurrentPstate(u32 target_pstate){ - msr_t initial_msr = rdmsr(TSC_MSR); - msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); - msr_t tsc_msr; - u8 timedout ; - - /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a - * P1 that is a copy of P0, therefore has the same NB DID but the - * TSC will count twice per tick, so we have to wait for twice the - * count to achieve the desired timeout. But I'm likely to - * misunderstand this... - */ - u32 corrected_timeout = ( (pstate_msr.lo==1) - && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? - WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT ; - msr_t timeout; - - timeout.lo = initial_msr.lo + corrected_timeout ; - timeout.hi = initial_msr.hi; - if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { - timeout.hi++; - } - - // assuming TSC ticks at 1.25 ns per tick (800 MHz) - do { - pstate_msr = rdmsr(CUR_PSTATE_MSR); - tsc_msr = rdmsr(TSC_MSR); - timedout = (tsc_msr.hi > timeout.hi) - || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo )); - } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; - - if (pstate_msr.lo != target_pstate) { - msr_t limit_msr = rdmsr(0xc0010061); - printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo); - - do { // should we just go on instead ? - pstate_msr = rdmsr(CUR_PSTATE_MSR); - } while ( pstate_msr.lo != target_pstate ) ; - } + msr_t initial_msr = rdmsr(TSC_MSR); + msr_t pstate_msr = rdmsr(CUR_PSTATE_MSR); + msr_t tsc_msr; + msr_t timeout; + u8 timedout; + + /* paranoia ? I fear when we run fixPsNbVidBeforeWR we can enter a + * P1 that is a copy of P0, therefore has the same NB DID but the + * TSC will count twice per tick, so we have to wait for twice the + * count to achieve the desired timeout. But I'm likely to + * misunderstand this... + */ + u32 corrected_timeout = ((pstate_msr.lo==1) + && (!(rdmsr(0xC0010065).lo & NB_DID_M_ON)) ) ? WAIT_PSTATE_TIMEOUT*2 : WAIT_PSTATE_TIMEOUT; + + timeout.lo = initial_msr.lo + corrected_timeout ; + timeout.hi = initial_msr.hi; + if ( (((u32)0xffffffff) - initial_msr.lo) < corrected_timeout ) { + timeout.hi++; + } + + // assuming TSC ticks at 1.25 ns per tick (800 MHz) + do { + pstate_msr = rdmsr(CUR_PSTATE_MSR); + tsc_msr = rdmsr(TSC_MSR); + timedout = (tsc_msr.hi > timeout.hi) || ((tsc_msr.hi == timeout.hi) && (tsc_msr.lo > timeout.lo)); + } while ( (pstate_msr.lo != target_pstate) && (! timedout) ) ; + + if (pstate_msr.lo != target_pstate) { + msr_t limit_msr = rdmsr(0xc0010061); + printk(BIOS_ERR, "*** Time out waiting for P-state %01x. Current P-state %01x P-state current limit MSRC001_0061=%02x\n", target_pstate, pstate_msr.lo, limit_msr.lo); + + do { // should we just go on instead ? + pstate_msr = rdmsr(CUR_PSTATE_MSR); + } while ( pstate_msr.lo != target_pstate ) ; + } } -static void set_pstate(u32 nonBoostedPState) { - msr_t msr; +static void set_pstate(u32 nonBoostedPState) +{ + msr_t msr; // Transition P0 for calling core. msr = rdmsr(0xC0010062); @@ -673,12 +666,9 @@ static void set_pstate(u32 nonBoostedPState) { wrmsr(0xC0010062, msr); /* Wait for P0 to set. */ - waitCurrentPstate(nonBoostedPState); + waitCurrentPstate(nonBoostedPState); } - - - static void UpdateSinglePlaneNbVid(void) { u32 nbVid, cpuVid; @@ -704,23 +694,23 @@ static void UpdateSinglePlaneNbVid(void) } static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) - { - msr_t msr; - u8 startup_pstate; +{ + msr_t msr; + u8 startup_pstate; - /* This function sets NbVid before the warm reset. - * Get StartupPstate from MSRC001_0071. + /* This function sets NbVid before the warm reset. + * Get StartupPstate from MSRC001_0071. * Read Pstate register pointed by [StartupPstate]. - * and copy its content to P0 and P1 registers. - * Copy newNbVid to P0[NbVid]. - * transition to P1 on all cores, - * then transition to P0 on core 0. - * Wait for MSRC001_0063[CurPstate] = 000b on core 0. - * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration - * for SVI and Single-Plane PVI Systems - */ - - msr = rdmsr(0xc0010071); + * and copy its content to P0 and P1 registers. + * Copy newNbVid to P0[NbVid]. + * transition to P1 on all cores, + * then transition to P0 on core 0. + * Wait for MSRC001_0063[CurPstate] = 000b on core 0. + * see BKDG rev 3.48 2.4.2.9.1 BIOS NB COF and VID Configuration + * for SVI and Single-Plane PVI Systems + */ + + msr = rdmsr(0xc0010071); startup_pstate = (msr.hi >> (32 - 32)) & 0x07; /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for @@ -731,13 +721,13 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) wrmsr(0xC0010065, msr); wrmsr(0xC0010064, msr); - /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = - * max(1,F3xDC[PstateMaxVal] ) because it would take - * synchronization between cores and we don't think - * PstatMaxVal is going to be 0 on cold reset anyway ? + /* missing step 2 from BDKG , F3xDC[PstateMaxVal] = + * max(1,F3xDC[PstateMaxVal] ) because it would take + * synchronization between cores and we don't think + * PstatMaxVal is going to be 0 on cold reset anyway ? */ - if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { - printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); + if ( ! (pci_read_config32(dev, 0xDC) & (~ PS_MAX_VAL_MASK)) ) { + printk(BIOS_ERR,"F3xDC[PstateMaxVal] is zero. Northbridge voltage setting will fail. fixPsNbVidBeforeWR in fidvid.c needs fixing. See AMD # 31116 rev 3.48 BKDG 2.4.2.9.1 \n"); }; msr.lo &= ~0xFE000000; // clear nbvid @@ -753,12 +743,11 @@ static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid, u32 dev, u8 pviMode) if (coreid == 0) { set_pstate(0); - } + } /* missing step 7 (restore PstateMax to 0 if needed) because * we skipped step 2 */ - } static u32 needs_NB_COF_VID_update(void) @@ -888,7 +877,6 @@ static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) fvp->common_fid = calc_common_fid(fvp->common_fid, readback); print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid); - } static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) @@ -930,7 +918,6 @@ static void fixPsNbVidAfterWR(u32 newNbVid, u8 NbVidUpdatedAll,u8 pviMode) /* Set and wait for StartupPstate to set. */ set_pstate(StartupPstate); - } static void finalPstateChange(void) @@ -979,9 +966,9 @@ static void init_fidvid_stage2(u32 apicid, u32 nodeid) dtemp |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dtemp); - dualPlaneOnly(dev); - applyBoostFIDOffset(dev); - enableNbPState1(dev); + dualPlaneOnly(dev); + applyBoostFIDOffset(dev); + enableNbPState1(dev); finalPstateChange(); @@ -1002,7 +989,6 @@ struct ap_apicid_st { static void store_ap_apicid(unsigned ap_apicid, void *gp) { struct ap_apicid_st *p = gp; - p->apicid[p->num++] = ap_apicid; } diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c index c6cf64a..453684a 100644 --- a/src/cpu/amd/model_10xxx/model_10xxx_init.c +++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c @@ -113,7 +113,6 @@ static void model_10xxx_init(device_t dev) msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); - } static struct device_operations cpu_dev_ops = {

1 0

Patch merged into coreboot/master: 83405a1 hp/abm: Add new mainboard
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit 83405a1241f4b8f516f687bd00f8ea981f7c7d87 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jun 5 11:49:04 2014 -0600 hp/abm: Add new mainboard The hp/abm board is used in network/server applications. Notes: - The hp/abm board is headless and therefore does not define CONFIG_GFXUMA, and does not require a video bios. - The micro USB connector on the board edge is connected to COM4 (i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3. - If you are using SeaBIOS it would also need to be configured to use the UART at I/O=2E8h. - This board has been tested with headless installed versions of Ubuntu 12.10 and Fedora 19. Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6116 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/6116 for details. -gerrit

1 0

Patch merged into coreboot/master: e75deb6 Copy asrock/ibm-a180 to hp/abm
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit e75deb69cc9678248f2b3ad73bc75b5d5d164842 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jun 26 09:12:54 2014 +0300 Copy asrock/ibm-a180 to hp/abm Change-Id: I8dcb3912976d7381421dc41ee30e7c7652e6c28a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/6115 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/6115 for details. -gerrit

1 0

New patch to review for coreboot: 903ffbb {north, south}bridge/*: Use system include path syntax over relative local
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8104 -gerrit commit 903ffbbf01bcf4a10ac6db52a2ae0801653da5c5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 02:44:20 2015 +1100 {north,south}bridge/*: Use system include path syntax over relative local Change-Id: Ib7fe3a9d672a02c9a91e3b320fefdbd98fd16cff Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/northbridge.c | 2 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 2 +- src/northbridge/intel/gm45/gm45.h | 5 ++--- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/report_platform.c | 2 +- src/northbridge/intel/i945/i945.h | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit_native.c | 8 ++++---- src/northbridge/intel/sandybridge/report_platform.c | 2 +- src/northbridge/intel/sandybridge/romstage_native.c | 4 ++-- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cs5535/chipsetinit.c | 4 ++-- src/southbridge/dmp/vortex86ex/southbridge.c | 4 ++-- src/southbridge/intel/bd82x6x/early_pch_native.c | 2 +- src/southbridge/intel/bd82x6x/early_rcba.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- src/southbridge/intel/bd82x6x/nvs.h | 3 ++- src/southbridge/intel/bd82x6x/smi.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/nvs.h | 3 ++- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_rangeley/romstage.c | 8 ++++---- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/nvs.h | 3 ++- src/southbridge/intel/ibexpeak/smi.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/nvs.h | 3 ++- 29 files changed, 43 insertions(+), 41 deletions(-) diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..aa09e08 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> void print_conf(void); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..c4214ad 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -33,7 +33,7 @@ #include <cpu/amd/vr.h> #include <cpu/cpu.h> #include "northbridge.h" -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> /* here is programming for the various MSRs.*/ diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 7c95ab4..656c6e5 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,7 +22,7 @@ #include <cpu/amd/lxdef.h> #include <arch/io.h> #include <spd.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "raminit.h" #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 5bdf9e4..4e50aba 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,12 +21,11 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> +#include <stdint.h> #ifndef __ACPI__ -#include <stdint.h> - typedef enum { FSB_CLOCK_1067MHz = 0, FSB_CLOCK_800MHz = 1, diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..e366c3f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -30,7 +30,7 @@ #include <cpu/x86/mtrr.h> #include <kconfig.h> -#include "drivers/intel/gma/i915_reg.h" +#include <drivers/intel/gma/i915_reg.h> #include "chip.h" #include "gm45.h" #include <drivers/intel/gma/intel_bios.h> diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8bb4a05..33da3b5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/lynxpoint/pch.h" +#include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe59ebe..651b75a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -27,7 +27,7 @@ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9ca98d5..7d37cb8 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -55,7 +55,7 @@ typedef u32 device_t; #include "nehalem.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/me.h> #if REAL #include <delay.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f6c92db..0f13f01 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -34,7 +34,7 @@ #include "sandybridge.h" /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* * MRC scrambler seed offsets should be reserved in diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index de6dac7..77c4005 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -36,11 +36,11 @@ #include <lib.h> /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* For SPD. */ -#include "southbridge/intel/bd82x6x/smbus.h" -#include "arch/cpu.h" -#include "cpu/x86/msr.h" +#include <southbridge/intel/bd82x6x/smbus.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 8230729..f189697 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/bd82x6x/pch.h> #include <arch/io.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 737cd63..400a079 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -31,8 +31,8 @@ #include <cpu/intel/romstage.h> #include <halt.h> #include "raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> void main(unsigned long bist) { diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 59d89b0..1a618b5 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -156,7 +156,7 @@ typedef union _PCI_ADDR { #define cimFusionMsgCMultiCoreDefault FALSE #define cimFusionMsgCStageDefault FALSE -#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h> #if CONFIG_HAVE_ACPI_RESUME #include <spi-generic.h> diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index ab1b640..e6aec1d 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -7,11 +7,11 @@ #include <stdlib.h> #include <string.h> #include "chip.h" -#include "northbridge/amd/gx2/northbridge.h" +#include <northbridge/amd/gx2/northbridge.h> #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h> /* the structs in this file only set msr.lo. But ... that may not always be true */ diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 2fe1bc2..c8aeb56 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -26,10 +26,10 @@ #include <pc80/keyboard.h> #include <string.h> #include <delay.h> -#include "arch/io.h" +#include <arch/io.h> #include "chip.h" #include "southbridge.h" -#include "cpu/dmp/dmp_post_code.h" +#include <cpu/dmp/dmp_post_code.h> /* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */ static const unsigned char irq_to_int_routing[16] = { diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c index 0863f34..a16da96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_native.c +++ b/src/southbridge/intel/bd82x6x/early_pch_native.c @@ -30,7 +30,7 @@ #include "pch.h" /* For DMI bar. */ -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 114b174..d63b7b3 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -21,7 +21,7 @@ #include <stdint.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> void southbridge_configure_default_intmap(void) diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 02ec9a7..2328be3 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_206ax/model_206ax.h" +#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b1f8447..f4ce625 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */ +#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ #include "pch.h" void diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index a20232e..5bb153d 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> @@ -29,7 +28,7 @@ #include <cpu/x86/smm.h> #include <string.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 8557c02..dde07e2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 827b897..1847b22 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -31,7 +31,7 @@ #include "pch.h" #if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include "northbridge/intel/fsp_sandybridge/northbridge.h" +#include <northbridge/intel/fsp_sandybridge/northbridge.h> #endif extern unsigned char _binary_smm_start; diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e..d910498 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -30,10 +30,10 @@ #include <cbmem.h> #include <console/console.h> #include <drivers/intel/fsp/fsp_util.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" -#include "southbridge/intel/fsp_rangeley/soc.h" -#include "southbridge/intel/fsp_rangeley/gpio.h" -#include "southbridge/intel/fsp_rangeley/romstage.h" +#include <northbridge/intel/fsp_rangeley/northbridge.h> +#include <southbridge/intel/fsp_rangeley/soc.h> +#include <southbridge/intel/fsp_rangeley/gpio.h> +#include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> #include <arch/stages.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index d23749e..fee2269 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_2065x/model_2065x.h" +#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..d83cd0a 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -31,7 +31,7 @@ #include <string.h> #include "pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..39fc40c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -36,7 +36,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> #include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 81b2321..790953f 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */

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coreboot-gerrit January 2015