New patch to review for coreboot: 4c1ad84 cpu: Drop print_ implementation from non-romcc boards
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8114
-gerrit
commit 4c1ad843edbcc3450e14418264221b1687af1503
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 13:07:39 2015 -0800
cpu: Drop print_ implementation from non-romcc boards
Because we have no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the cpu code to use printk() on all non-ROMCC
boards.
Change-Id: I233c53300f9a74bce4b828fc4074501a77f7b593
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/cpu/amd/car/post_cache_as_ram.c | 2 +-
src/cpu/amd/geode_lx/cpureginit.c | 20 ++++++++++----------
src/cpu/via/c7/c7_init.c | 2 +-
src/include/cpu/x86/bist.h | 6 ------
4 files changed, 12 insertions(+), 18 deletions(-)
diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 61874a9..8bc5cd3 100644
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -17,7 +17,7 @@
#define PRINTK_IN_CAR 1
#if PRINTK_IN_CAR
-#define print_car_debug(x) print_debug(x)
+#define print_car_debug(x) printk(BIOS_DEBUG, x)
#else
#define print_car_debug(x)
#endif
diff --git a/src/cpu/amd/geode_lx/cpureginit.c b/src/cpu/amd/geode_lx/cpureginit.c
index 282fa7e..9c0a8d9 100644
--- a/src/cpu/amd/geode_lx/cpureginit.c
+++ b/src/cpu/amd/geode_lx/cpureginit.c
@@ -170,7 +170,7 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
/* Castle 2.0 BTM periodic sync period. */
/* [40:37] 1 sync record per 256 bytes */
- print_debug("Castle 2.0 BTM periodic sync period.\n");
+ printk(BIOS_DEBUG, "Castle 2.0 BTM periodic sync period.\n");
msrnum = CPU_PF_CONF;
msr = rdmsr(msrnum);
msr.hi |= (0x8 << 5);
@@ -180,7 +180,7 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
* LX performance setting.
* Enable Quack for fewer re-RAS on the MC
*/
- print_debug("Enable Quack for fewer re-RAS on the MC\n");
+ printk(BIOS_DEBUG, "Enable Quack for fewer re-RAS on the MC\n");
msrnum = GLIU0_ARB;
msr = rdmsr(msrnum);
msr.hi &= ~ARB_UPPER_DACK_EN_SET;
@@ -196,25 +196,25 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
/* GLIU port active enable, limit south pole masters
* (AES and PCI) to one outstanding transaction.
*/
- print_debug(" GLIU port active enable\n");
+ printk(BIOS_DEBUG, " GLIU port active enable\n");
msrnum = GLIU1_PORT_ACTIVE;
msr = rdmsr(msrnum);
msr.lo &= ~0x880;
wrmsr(msrnum, msr);
/* Set the Delay Control in GLCP */
- print_debug("Set the Delay Control in GLCP\n");
+ printk(BIOS_DEBUG, "Set the Delay Control in GLCP\n");
SetDelayControl(dimm0, dimm1, terminated);
/* Enable RSDC */
- print_debug("Enable RSDC\n");
+ printk(BIOS_DEBUG, "Enable RSDC\n");
msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
msr.lo |= SMM_INST_EN_SET;
wrmsr(msrnum, msr);
/* FPU imprecise exceptions bit */
- print_debug("FPU imprecise exceptions bit\n");
+ printk(BIOS_DEBUG, "FPU imprecise exceptions bit\n");
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
@@ -222,14 +222,14 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
/* Power Savers (Do after BIST) */
/* Enable Suspend on HLT & PAUSE instructions */
- print_debug("Enable Suspend on HLT & PAUSE instructions\n");
+ printk(BIOS_DEBUG, "Enable Suspend on HLT & PAUSE instructions\n");
msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT | XC_CONFIG_SUSP_ON_PAUSE;
wrmsr(msrnum, msr);
/* Enable SUSP and allow TSC to run in Suspend (keep speed detection happy) */
- print_debug("Enable SUSP and allow TSC to run in Suspend\n");
+ printk(BIOS_DEBUG, "Enable SUSP and allow TSC to run in Suspend\n");
msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
@@ -247,10 +247,10 @@ void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated)
}
/* Setup throttling delays to proper mode if it is ever enabled. */
- print_debug("Setup throttling delays to proper mode\n");
+ printk(BIOS_DEBUG, "Setup throttling delays to proper mode\n");
msrnum = GLCP_TH_OD;
msr.hi = 0;
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
- print_debug("Done cpuRegInit\n");
+ printk(BIOS_DEBUG, "Done cpuRegInit\n");
}
diff --git a/src/cpu/via/c7/c7_init.c b/src/cpu/via/c7/c7_init.c
index 7f22e59..054a874 100644
--- a/src/cpu/via/c7/c7_init.c
+++ b/src/cpu/via/c7/c7_init.c
@@ -122,7 +122,7 @@ static void set_c7_speed(int model) {
}
break;
default:
- print_info("CPU type not known, multiplier unchanged.\n");
+ printk(BIOS_INFO, "CPU type not known, multiplier unchanged.\n");
}
msr.lo = new;
diff --git a/src/include/cpu/x86/bist.h b/src/include/cpu/x86/bist.h
index d1646bf..08aca2f 100644
--- a/src/include/cpu/x86/bist.h
+++ b/src/include/cpu/x86/bist.h
@@ -4,14 +4,8 @@
static void report_bist_failure(u32 bist)
{
if (bist != 0) {
-#if CONFIG_CACHE_AS_RAM
printk(BIOS_EMERG, "BIST failed: %08x", bist);
-#else
- print_emerg("BIST failed: ");
- print_emerg_hex32(bist);
-#endif
die("\n");
-
}
}
1
0
New patch to review for coreboot: c232f7e superio: Drop print_ implementation from non-romcc boards
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8113
-gerrit
commit c232f7e3de9abae02a9e4d0eed454a33bcf4a766
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 13:05:44 2015 -0800
superio: Drop print_ implementation from non-romcc boards
Because we have no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the superio code to use printk() on all non-ROMCC
boards.
Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/superio/serverengines/pilot/early_init.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c
index 6635645..b609572 100644
--- a/src/superio/serverengines/pilot/early_init.c
+++ b/src/superio/serverengines/pilot/early_init.c
@@ -36,11 +36,9 @@ void pilot_early_init(pnp_devfn_t dev)
{
u16 port = dev >> 8;
- print_debug("Using port: ");
- print_debug_hex16(port);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Using port: %04x\n", port);
pilot_disable_serial(PNP_DEV(port, 0x1));
- print_debug("disable serial 1\n");
+ printk(BIOS_DEBUG, "disable serial 1\n");
pnp_enter_ext_func_mode(dev);
pnp_set_logical_device(PNP_DEV(port, 0x3));
1
0
New patch to review for coreboot: 79a9123 superio/smsc/lpc47n217: Drop dead code
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8112
-gerrit
commit 79a91233f3c802e1c1077b5c664abe679973d465
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 13:03:43 2015 -0800
superio/smsc/lpc47n217: Drop dead code
This code is unused, and the same functionality is in superiotool
already.
Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/superio/smsc/lpc47n217/superio.c | 40 ------------------------------------
1 file changed, 40 deletions(-)
diff --git a/src/superio/smsc/lpc47n217/superio.c b/src/superio/smsc/lpc47n217/superio.c
index 96dd4e2..85de359 100644
--- a/src/superio/smsc/lpc47n217/superio.c
+++ b/src/superio/smsc/lpc47n217/superio.c
@@ -276,43 +276,3 @@ static void pnp_exit_conf_state(struct device *dev)
{
outb(0xaa, dev->path.pnp.port);
}
-
-#if 0
-/**
- * Print the values of all of the LPC47N217's configuration registers.
- *
- * NOTE: The LPC47N217 must be in config mode when this function is called.
- *
- * @param dev Pointer to structure describing a Super I/O device.
- */
-static void dump_pnp_device(struct device *dev)
-{
- int i;
- print_debug("\n");
-
- for (i = 0; i <= LPC47N217_MAX_CONFIG_REGISTER; i++) {
- u8 register_value;
-
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
-
- /*
- * Skip over 'register' that would cause exit from
- * configuration mode.
- */
- if (i == 0xaa)
- register_value = 0xaa;
- else
- register_value = pnp_read_config(dev, i);
-
- print_debug_char(' ');
- print_debug_hex8(register_value);
- if ((i & 0x0f) == 0x0f)
- print_debug("\n");
- }
-
- print_debug("\n");
-}
-#endif
1
0
New patch to review for coreboot: e2e0ebb mainboard: Drop print_ implementation from non-romcc boards
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8111
-gerrit
commit e2e0ebb65a459cbef6aced20ca2e952903209a0b
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 13:02:32 2015 -0800
mainboard: Drop print_ implementation from non-romcc boards
Because we have no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the mainboard code to use printk() on all non-ROMCC
boards.
Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/mainboard/advansus/a785e-i/romstage.c | 2 +-
src/mainboard/amd/bimini_fam10/romstage.c | 2 +-
src/mainboard/amd/dbm690t/romstage.c | 2 +-
src/mainboard/amd/dinar/romstage.c | 4 +-
src/mainboard/amd/mahogany/romstage.c | 2 +-
src/mainboard/amd/mahogany_fam10/romstage.c | 2 +-
src/mainboard/amd/pistachio/romstage.c | 2 +-
src/mainboard/amd/rumba/romstage.c | 2 +-
src/mainboard/amd/serengeti_cheetah/romstage.c | 10 +--
.../amd/serengeti_cheetah_fam10/romstage.c | 4 +-
src/mainboard/amd/tilapia_fam10/romstage.c | 2 +-
src/mainboard/arima/hdama/debug.c | 77 -------------------
src/mainboard/arima/hdama/romstage.c | 2 +-
src/mainboard/artecgroup/dbe61/romstage.c | 25 +------
src/mainboard/asrock/939a785gmh/romstage.c | 2 +-
src/mainboard/asus/a8n_e/romstage.c | 2 +-
src/mainboard/asus/a8v-e_deluxe/romstage.c | 10 +--
src/mainboard/asus/a8v-e_se/romstage.c | 10 +--
src/mainboard/asus/k8v-x/romstage.c | 10 +--
src/mainboard/asus/m2n-e/romstage.c | 2 +-
src/mainboard/asus/m2v-mx_se/romstage.c | 14 ++--
src/mainboard/asus/m2v/romstage.c | 10 +--
src/mainboard/asus/m4a78-em/romstage.c | 2 +-
src/mainboard/asus/m4a785-m/romstage.c | 2 +-
src/mainboard/asus/m5a88-v/romstage.c | 2 +-
src/mainboard/avalue/eax-785e/romstage.c | 2 +-
src/mainboard/bifferos/bifferboard/romstage.c | 1 +
src/mainboard/broadcom/blast/romstage.c | 10 +--
src/mainboard/digitallogic/msm800sev/romstage.c | 2 +-
src/mainboard/dmp/vortex86ex/romstage.c | 1 +
src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 8 +-
src/mainboard/gigabyte/m57sli/romstage.c | 11 ++-
src/mainboard/gigabyte/ma785gm/romstage.c | 2 +-
src/mainboard/gigabyte/ma785gmt/romstage.c | 2 +-
src/mainboard/gigabyte/ma78gm/romstage.c | 2 +-
src/mainboard/hp/dl145_g1/romstage.c | 14 ++--
src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +-
src/mainboard/ibm/e325/romstage.c | 2 +-
src/mainboard/ibm/e326/romstage.c | 2 +-
src/mainboard/iei/kino-780am2-fam10/romstage.c | 2 +-
src/mainboard/intel/eagleheights/debug.c | 86 ++++++++--------------
src/mainboard/intel/eagleheights/romstage.c | 6 +-
src/mainboard/iwill/dk8_htx/romstage.c | 8 +-
src/mainboard/iwill/dk8s2/romstage.c | 8 +-
src/mainboard/iwill/dk8x/romstage.c | 8 +-
src/mainboard/jetway/pa78vm5/romstage.c | 2 +-
src/mainboard/kontron/kt690/romstage.c | 2 +-
src/mainboard/lippert/frontrunner/romstage.c | 23 +++---
src/mainboard/lippert/hurricane-lx/romstage.c | 4 +-
src/mainboard/lippert/literunner-lx/romstage.c | 12 +--
src/mainboard/lippert/spacerunner-lx/romstage.c | 9 +--
src/mainboard/msi/ms7135/romstage.c | 2 +-
src/mainboard/msi/ms7260/romstage.c | 16 +---
src/mainboard/msi/ms9185/romstage.c | 8 +-
src/mainboard/msi/ms9282/romstage.c | 2 +-
src/mainboard/msi/ms9652_fam10/romstage.c | 2 +-
src/mainboard/newisys/khepri/romstage.c | 2 +-
src/mainboard/nvidia/l1_2pvv/romstage.c | 8 +-
src/mainboard/pcengines/alix1c/romstage.c | 16 ++--
src/mainboard/pcengines/alix2d/romstage.c | 16 ++--
src/mainboard/sunw/ultra40/romstage.c | 2 +-
src/mainboard/supermicro/h8dme/romstage.c | 16 +---
src/mainboard/supermicro/h8dmr/romstage.c | 4 +-
src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +-
src/mainboard/supermicro/h8qgi/romstage.c | 8 +-
src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +-
src/mainboard/supermicro/h8scm/romstage.c | 8 +-
src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +-
src/mainboard/technexion/tim5690/romstage.c | 2 +-
src/mainboard/technexion/tim8690/romstage.c | 2 +-
src/mainboard/tyan/s2850/romstage.c | 2 +-
src/mainboard/tyan/s2875/romstage.c | 2 +-
src/mainboard/tyan/s2880/romstage.c | 2 +-
src/mainboard/tyan/s2881/romstage.c | 2 +-
src/mainboard/tyan/s2882/romstage.c | 2 +-
src/mainboard/tyan/s2885/romstage.c | 2 +-
src/mainboard/tyan/s2912/romstage.c | 8 +-
src/mainboard/tyan/s2912_fam10/romstage.c | 2 +-
src/mainboard/tyan/s4880/romstage.c | 2 +-
src/mainboard/tyan/s4882/romstage.c | 2 +-
src/mainboard/tyan/s8226/romstage.c | 8 +-
src/mainboard/via/epia-m700/romstage.c | 20 ++---
src/mainboard/via/epia-m850/mainboard.c | 2 +-
src/mainboard/via/epia-m850/romstage.c | 4 +-
src/mainboard/wyse/s50/romstage.c | 4 +-
85 files changed, 231 insertions(+), 388 deletions(-)
diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c
index 1167bf5..37bd416 100644
--- a/src/mainboard/advansus/a785e-i/romstage.c
+++ b/src/mainboard/advansus/a785e-i/romstage.c
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c
index ef85df2..41bc343 100644
--- a/src/mainboard/amd/bimini_fam10/romstage.c
+++ b/src/mainboard/amd/bimini_fam10/romstage.c
@@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c
index c9a04f5..83a13bf 100644
--- a/src/mainboard/amd/dbm690t/romstage.c
+++ b/src/mainboard/amd/dbm690t/romstage.c
@@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c
index ad6bce3..aa1191a 100644
--- a/src/mainboard/amd/dinar/romstage.c
+++ b/src/mainboard/amd/dinar/romstage.c
@@ -98,9 +98,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x43);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x44);
copy_and_run();
diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c
index 00223ae..7e653b2 100644
--- a/src/mainboard/amd/mahogany/romstage.c
+++ b/src/mainboard/amd/mahogany/romstage.c
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index b940be0..8023f9d 100644
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index af4253d..f083e1b 100644
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x06);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c
index 248baa0..ef4b2f0 100644
--- a/src/mainboard/amd/rumba/romstage.c
+++ b/src/mainboard/amd/rumba/romstage.c
@@ -50,7 +50,7 @@ void main(unsigned long bist)
pll_reset();
cpuRegInit();
- print_err("done cpuRegInit\n");
+ printk(BIOS_ERR, "done cpuRegInit\n");
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index ec0682a..6e17393 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -160,11 +160,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
} else {
- print_debug("Changing FIDVID not supported\n");
+ printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
#endif
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
#endif
diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
index df968c3..f923e0b 100644
--- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
@@ -283,7 +283,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
die("After soft_reset_x - shouldn't see this message!!!\n");
}
@@ -292,7 +292,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* FIXME: Move this to chipset init.
enable cf9 for hard reset */
- print_debug("enable_cf9_x()\n");
+ printk(BIOS_DEBUG, "enable_cf9_x()\n");
enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn);
post_code(0x3C);
diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index c4ccc70..9fdb4f0 100644
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/arima/hdama/debug.c b/src/mainboard/arima/hdama/debug.c
deleted file mode 100644
index bcb918e..0000000
--- a/src/mainboard/arima/hdama/debug.c
+++ /dev/null
@@ -1,77 +0,0 @@
-
-static void dump_spd_registers(int controllers, const struct mem_controller *ctrl)
-{
- int n;
- for(n = 0; n < controllers; n++) {
- int i;
- print_debug("\n");
- activate_spd_rom(&ctrl[n]);
- for(i = 0; i < 4; i++) {
- unsigned device;
- device = ctrl[n].channel0[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(n);
- print_debug_char('.');
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = spd_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\n");
- break;
- }
-#if 0
- byte = status & 0xff;
- print_debug_hex8(byte);
-#else
- print_debug_hex8(status & 0xff);
-#endif
- print_debug_char(' ');
- }
- print_debug("\n");
- }
- device = ctrl[n].channel1[i];
- if (device) {
- int j;
- print_debug("dimm: ");
- print_debug_hex8(n);
- print_debug_char('.');
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
- for(j = 0; j < 256; j++) {
- int status;
- unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
- status = spd_read_byte(device, j);
- if (status < 0) {
- print_debug("bad device\n");
- break;
- }
-#if 0
- byte = status & 0xff;
- print_debug_hex8(byte);
-#else
- print_debug_hex8(status & 0xff);
-#endif
- print_debug_char(' ');
- }
- print_debug("\n");
- }
- }
- }
-}
diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c
index 137d3eb..cb91ded 100644
--- a/src/mainboard/arima/hdama/romstage.c
+++ b/src/mainboard/arima/hdama/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c
index 63f89f1..a5a47c7 100644
--- a/src/mainboard/artecgroup/dbe61/romstage.c
+++ b/src/mainboard/artecgroup/dbe61/romstage.c
@@ -95,31 +95,12 @@ void main(unsigned long bist)
/* Dump memory configuration. */
#if 0
msr = rdmsr(MC_CF07_DATA);
- print_debug("MC_CF07_DATA: ");
- print_debug_hex32(MC_CF07_DATA);
- print_debug(" value is: ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MC_CF07_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
msr = rdmsr(MC_CF1017_DATA);
- print_debug("MC_CF1017_DATA: ");
- print_debug_hex32(MC_CF1017_DATA);
- print_debug(" value is: ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MC_CF1017_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
msr = rdmsr(MC_CF8F_DATA);
- print_debug("MC_CF8F_DATA: ");
- print_debug_hex32(MC_CF8F_DATA);
- print_debug(" value is: ");
- print_debug_hex32(msr.hi);
- print_debug(":");
- print_debug_hex32(msr.lo);
- msr = rdmsr(MC_CF8F_DATA);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MC_CF8F_DATA: %08x value is: %08x:%08x\n", MC_CF07_DATA, msr.hi, msr.lo);
#endif
}
diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index 417f9a7..ca6296a 100644
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -199,7 +199,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c
index c0fa6a5..e5893e0 100644
--- a/src/mainboard/asus/a8n_e/romstage.c
+++ b/src/mainboard/asus/a8n_e/romstage.c
@@ -128,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c
index 0d55e53..42c3ae5 100644
--- a/src/mainboard/asus/a8v-e_deluxe/romstage.c
+++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c
@@ -65,7 +65,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... romstage\n");
+ printk(BIOS_INFO, "now booting... romstage\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c
index 3ed2491..5226c93 100644
--- a/src/mainboard/asus/a8v-e_se/romstage.c
+++ b/src/mainboard/asus/a8v-e_se/romstage.c
@@ -65,7 +65,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... fallback\n");
+ printk(BIOS_INFO, "now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -165,7 +165,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -192,7 +192,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c
index dab3193..aec1b03 100644
--- a/src/mainboard/asus/k8v-x/romstage.c
+++ b/src/mainboard/asus/k8v-x/romstage.c
@@ -63,7 +63,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -111,7 +111,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
console_init();
enable_rom_decode();
- print_info("now booting... fallback\n");
+ printk(BIOS_INFO, "now booting... fallback\n");
/* Is this a CPU only reset? Or is this a secondary CPU? */
if (!cpu_init_detectedx && boot_cpu()) {
@@ -120,7 +120,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
enumerate_ht_chain();
}
- print_info("now booting... real_main\n");
+ printk(BIOS_INFO, "now booting... real_main\n");
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
@@ -132,7 +132,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain();
wait_all_core0_started();
- print_info("now booting... Core0 started\n");
+ printk(BIOS_INFO, "now booting... Core0 started\n");
#if CONFIG_LOGICAL_CPUS
/* It is said that we should start core1 after all core0 launched. */
@@ -147,7 +147,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= k8t890_early_setup_ht();
if (needs_reset) {
- print_debug("ht reset -\n");
+ printk(BIOS_DEBUG, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c
index d12b77c..e7191b1 100644
--- a/src/mainboard/asus/m2n-e/romstage.c
+++ b/src/mainboard/asus/m2n-e/romstage.c
@@ -149,7 +149,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
* effective too.
*/
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c
index 42b03c8..ca8a82d 100644
--- a/src/mainboard/asus/m2v-mx_se/romstage.c
+++ b/src/mainboard/asus/m2v-mx_se/romstage.c
@@ -70,7 +70,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void ldtstop_sb(void)
{
- print_debug("toggle LDTSTP#\n");
+ printk(BIOS_DEBUG, "toggle LDTSTP#\n");
/* fix errata #181, disable DRAM controller it will get enabled later */
u8 tmp = pci_read_config8(PCI_DEV(0, 0x18, 2), 0x94);
@@ -81,7 +81,7 @@ static void ldtstop_sb(void)
reg = reg ^ (1 << 0);
outb(reg, VT8237R_ACPI_IO_BASE + 0x5c);
reg = inb(VT8237R_ACPI_IO_BASE + 0x15);
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
}
#include "cpu/amd/model_fxx/fidvid.c"
@@ -92,7 +92,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -154,11 +154,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= k8t890_early_setup_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
vt8237_early_network_init(NULL);
vt8237_early_spi_init();
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_sb_enable_fid_vid();
enable_fid_change();
- print_debug("after enable_fid_change\n");
+ printk(BIOS_DEBUG, "after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c
index f776351..fffcba8 100644
--- a/src/mainboard/asus/m2v/romstage.c
+++ b/src/mainboard/asus/m2v/romstage.c
@@ -76,7 +76,7 @@ void soft_reset(void)
uint8_t tmp;
set_bios_reset();
- print_debug("soft reset\n");
+ printk(BIOS_DEBUG, "soft reset\n");
/* PCI reset */
tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f);
@@ -254,11 +254,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */
needs_reset = optimize_link_coherent_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= optimize_link_incoherent_ht(sysinfo);
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
needs_reset |= k8t890_early_setup_ht();
- print_debug_hex8(needs_reset);
+ printk(BIOS_DEBUG, "%02x", needs_reset);
if (needs_reset) {
printk(BIOS_DEBUG, "ht reset -\n");
@@ -271,7 +271,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
vt8237_sb_enable_fid_vid();
enable_fid_change();
- print_debug("after enable_fid_change\n");
+ printk(BIOS_DEBUG, "after enable_fid_change\n");
init_fidvid_bsp(bsp_apicid);
diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c
index 9da8c6c..290445a 100644
--- a/src/mainboard/asus/m4a78-em/romstage.c
+++ b/src/mainboard/asus/m4a78-em/romstage.c
@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c
index dcf2b22..7764091 100644
--- a/src/mainboard/asus/m4a785-m/romstage.c
+++ b/src/mainboard/asus/m4a785-m/romstage.c
@@ -185,7 +185,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c
index a2fceda..0a3ecff 100644
--- a/src/mainboard/asus/m5a88-v/romstage.c
+++ b/src/mainboard/asus/m5a88-v/romstage.c
@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c
index 36ce1de..bf681b1 100644
--- a/src/mainboard/avalue/eax-785e/romstage.c
+++ b/src/mainboard/avalue/eax-785e/romstage.c
@@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/bifferos/bifferboard/romstage.c b/src/mainboard/bifferos/bifferboard/romstage.c
index 574e9a6..3bbc73a 100644
--- a/src/mainboard/bifferos/bifferboard/romstage.c
+++ b/src/mainboard/bifferos/bifferboard/romstage.c
@@ -23,6 +23,7 @@
#include <arch/io.h>
#include <device/pnp_def.h>
#include <pc80/mc146818rtc.h>
+#include "arch/x86/lib/romcc_console.c"
#include <console/console.h>
#include <cpu/x86/cache.h>
diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c
index a97c3b8..367540a 100644
--- a/src/mainboard/broadcom/blast/romstage.c
+++ b/src/mainboard/broadcom/blast/romstage.c
@@ -79,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_blast_resource_map();
@@ -101,10 +101,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
bcm5785_early_setup();
- if (needs_reset) {
- print_info("ht reset -\n");
- soft_reset();
- }
+ if (needs_reset) {
+ printk(BIOS_INFO, "ht reset -\n");
+ soft_reset();
+ }
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c
index 4df217f..6b05174 100644
--- a/src/mainboard/digitallogic/msm800sev/romstage.c
+++ b/src/mainboard/digitallogic/msm800sev/romstage.c
@@ -73,7 +73,7 @@ void main(unsigned long bist)
*/
post_code(0x02);
__asm__("wbinvd\n");
- print_err("Past wbinvd\n");
+ printk(BIOS_ERR, "Past wbinvd\n");
/* we are finding the return does not work on this board. Explicitly call the label that is
* after the call to us. This is gross, but sometimes at this level it is the only way out
*/
diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c
index d43df8d..117bd35 100644
--- a/src/mainboard/dmp/vortex86ex/romstage.c
+++ b/src/mainboard/dmp/vortex86ex/romstage.c
@@ -21,6 +21,7 @@
#include <stdint.h>
#include <arch/io.h>
#include <stdlib.h>
+#include "arch/x86/lib/romcc_console.c"
#include <console/console.h>
#include <cpu/x86/cache.h>
#include <halt.h>
diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
index 10bbb6f..284536d 100644
--- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
+++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -179,7 +179,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c
index b2e1d70..4e5e2ed 100644
--- a/src/mainboard/gigabyte/m57sli/romstage.c
+++ b/src/mainboard/gigabyte/m57sli/romstage.c
@@ -144,9 +144,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
-
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo+1);
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -169,7 +168,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -178,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -190,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c
index 75090d9..e08d27b 100644
--- a/src/mainboard/gigabyte/ma785gm/romstage.c
+++ b/src/mainboard/gigabyte/ma785gm/romstage.c
@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c
index 87778c6..35647f5 100644
--- a/src/mainboard/gigabyte/ma785gmt/romstage.c
+++ b/src/mainboard/gigabyte/ma785gmt/romstage.c
@@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c
index b3ae326..5687bab 100644
--- a/src/mainboard/gigabyte/ma78gm/romstage.c
+++ b/src/mainboard/gigabyte/ma78gm/romstage.c
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c
index 2b42e73..85d2e58 100644
--- a/src/mainboard/hp/dl145_g1/romstage.c
+++ b/src/mainboard/hp/dl145_g1/romstage.c
@@ -64,14 +64,14 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl)
static inline void change_i2c_mux(unsigned device)
{
int ret, i;
- print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n");
+ printk(BIOS_DEBUG, "change_i2c_mux i=%02x\n", device);
i=2;
do {
ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
- print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n");
+ printk(BIOS_DEBUG, "change_i2c_mux 1 ret=%08x\n", ret);
} while ((ret!=0) && (i-->0));
ret = smbus_write_byte(SMBUS_HUB, 0x03, 0);
- print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n");
+ printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret);
}
static inline int spd_read_byte(unsigned device, unsigned address)
@@ -143,7 +143,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
@@ -154,11 +154,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
} else {
- print_debug("Changing FIDVID not supported\n");
+ printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
#endif
@@ -166,7 +166,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c
index e22ed1c..7193f0d 100644
--- a/src/mainboard/hp/dl165_g6_fam10/romstage.c
+++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c
@@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c
index 4e1e925..5c6c507 100644
--- a/src/mainboard/ibm/e325/romstage.c
+++ b/src/mainboard/ibm/e325/romstage.c
@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c
index 2ac90ab..0cc350e 100644
--- a/src/mainboard/ibm/e326/romstage.c
+++ b/src/mainboard/ibm/e326/romstage.c
@@ -106,7 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c
index 2182a7e..ecd5e54 100644
--- a/src/mainboard/iei/kino-780am2-fam10/romstage.c
+++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c
@@ -183,7 +183,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/intel/eagleheights/debug.c b/src/mainboard/intel/eagleheights/debug.c
index d2c3d58..b1346c1 100644
--- a/src/mainboard/intel/eagleheights/debug.c
+++ b/src/mainboard/intel/eagleheights/debug.c
@@ -28,11 +28,7 @@ static void print_reg(unsigned char index)
outb(index, 0x2e);
data = inb(0x2f);
- print_debug("0x");
- print_debug_hex8(index);
- print_debug(": 0x");
- print_debug_hex8(data);
- print_debug("\n");
+ printk(BIOS_DEBUG, "0x%02x: 0x%02x\n", index, data);
return;
}
@@ -69,52 +65,49 @@ static inline void siodump(void)
int i;
unsigned char data;
- print_debug("\n*** SERVER I/O REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** SERVER I/O REGISTERS ***\n");
for (i=0x10; i<=0x2d; i++) {
print_reg((unsigned char)i);
}
#if 0
- print_debug("\n*** XBUS REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** XBUS REGISTERS ***\n");
setup_func(0x0f);
for (i=0xf0; i<=0xff; i++) {
print_reg((unsigned char)i);
}
- print_debug("\n*** SERIAL 1 CONFIG REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** SERIAL 1 CONFIG REGISTERS ***\n");
setup_func(0x03);
print_reg(0xf0);
- print_debug("\n*** SERIAL 2 CONFIG REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** SERIAL 2 CONFIG REGISTERS ***\n");
setup_func(0x02);
print_reg(0xf0);
#endif
- print_debug("\n*** GPIO REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** GPIO REGISTERS ***\n");
setup_func(0x07);
for (i=0xf0; i<=0xf8; i++) {
print_reg((unsigned char)i);
}
- print_debug("\n*** GPIO VALUES ***\n");
+ printk(BIOS_DEBUG, "\n*** GPIO VALUES ***\n");
data = inb(0x68a);
- print_debug("\nGPDO 4: 0x");
- print_debug_hex8(data);
+ printk(BIOS_DEBUG, "\nGPDO 4: 0x%02x", data);
data = inb(0x68b);
- print_debug("\nGPDI 4: 0x");
- print_debug_hex8(data);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\nGPDI 4: 0x%02x\n", data);
#if 0
- print_debug("\n*** WATCHDOG TIMER REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** WATCHDOG TIMER REGISTERS ***\n");
setup_func(0x0a);
print_reg(0xf0);
- print_debug("\n*** FAN CONTROL REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** FAN CONTROL REGISTERS ***\n");
setup_func(0x09);
print_reg(0xf0);
print_reg(0xf1);
- print_debug("\n*** RTC REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** RTC REGISTERS ***\n");
setup_func(0x10);
print_reg(0xf0);
print_reg(0xf1);
@@ -124,7 +117,7 @@ static inline void siodump(void)
print_reg(0xfe);
print_reg(0xff);
- print_debug("\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
+ printk(BIOS_DEBUG, "\n*** HEALTH MONITORING & CONTROL REGISTERS ***\n");
setup_func(0x14);
print_reg(0xf0);
#endif
@@ -136,27 +129,21 @@ static inline void dump_bar14(unsigned dev)
int i;
unsigned long bar;
- print_debug("BAR 14 Dump\n");
+ printk(BIOS_DEBUG, "BAR 14 Dump\n");
bar = pci_read_config32(dev, 0x14);
for(i = 0; i <= 0x300; i+=4) {
#if 0
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x:", i);
val = pci_read_config8(dev, i);
#endif
- if((i%4)==0) {
- print_debug("\n");
- print_debug_hex16(i);
- print_debug_char(' ');
- }
- print_debug_hex32(read32(bar + i));
- print_debug_char(' ');
+ if((i%4)==0)
+ printk(BIOS_DEBUG, "\n%04x ", i);
+ printk(BIOS_DEBUG, "%08x ", read32(bar + i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_spd_registers(void)
@@ -166,28 +153,20 @@ static inline void dump_spd_registers(void)
while(device <= DIMM7) {
int status = 0;
int i;
- print_debug("\n");
- print_debug("dimm ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "\ndimm %02x", device);
for(i = 0; (i < 256) ; i++) {
- if ((i % 16) == 0) {
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
+ if ((i % 16) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
status = smbus_read_byte(device, i);
if (status < 0) {
- print_debug("bad device: ");
- print_debug_hex8(-status);
- print_debug("\n");
+ printk(BIOS_DEBUG, "bad device: %d\n", -status);
break;
}
- print_debug_hex8(status);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", status);
}
device++;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -198,22 +177,17 @@ static inline void dump_ipmi_registers(void)
while(device <= 0x42) {
int status = 0;
int i;
- print_debug("\n");
- print_debug("ipmi ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "\nipmi %02x", device);
for(i = 0; (i < 8) ; i++) {
status = smbus_read_byte(device, 2);
if (status < 0) {
- print_debug("bad device: ");
- print_debug_hex8(-status);
- print_debug("\n");
+ printk(BIOS_DEBUG, "bad device: %d\n", -status);
break;
}
- print_debug_hex8(status);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", status);
}
device++;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c
index b41e0c5..18c36cd 100644
--- a/src/mainboard/intel/eagleheights/romstage.c
+++ b/src/mainboard/intel/eagleheights/romstage.c
@@ -20,14 +20,16 @@
* MA 02110-1301 USA
*/
-#include <delay.h>
#include <stdint.h>
-#include <arch/io.h>
+#include <stdlib.h>
#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
+#include <delay.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/speedstep.h>
#include "southbridge/intel/i3100/early_smbus.c"
diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c
index a429568..ef54c7e 100644
--- a/src/mainboard/iwill/dk8_htx/romstage.c
+++ b/src/mainboard/iwill/dk8_htx/romstage.c
@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_coherent_ht_domain(); // routing table and start other core0
@@ -115,7 +115,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -124,7 +124,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -133,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c
index d2371b5..df69121 100644
--- a/src/mainboard/iwill/dk8s2/romstage.c
+++ b/src/mainboard/iwill/dk8s2/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_default_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_coherent_ht_domain(); // routing table and start other core0
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c
index 50869f7..cf8aa9f 100644
--- a/src/mainboard/iwill/dk8x/romstage.c
+++ b/src/mainboard/iwill/dk8x/romstage.c
@@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_default_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_coherent_ht_domain(); // routing table and start other core0
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
}
diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c
index 87af979..247a6dc 100644
--- a/src/mainboard/jetway/pa78vm5/romstage.c
+++ b/src/mainboard/jetway/pa78vm5/romstage.c
@@ -188,7 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c
index 24cae41..9013eaf 100644
--- a/src/mainboard/kontron/kt690/romstage.c
+++ b/src/mainboard/kontron/kt690/romstage.c
@@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c
index 3be4eb3..daff6af 100644
--- a/src/mainboard/lippert/frontrunner/romstage.c
+++ b/src/mainboard/lippert/frontrunner/romstage.c
@@ -52,9 +52,8 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
#if CONFIG_DEBUG_SMBUS
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
- print_err("ERROR: spd_read_byte(DIMM0, 0x");
- print_err_hex8(address);
- print_err(") returns 0xff\n");
+ printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
+ "returns 0xff\n", address);
}
#endif
@@ -85,29 +84,29 @@ void main(unsigned long bist)
console_init();
cs5535_early_setup();
- print_err("done cs5535 early\n");
+ printk(BIOS_ERR, "done cs5535 early\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
- print_err("done pll_reset\n");
+ printk(BIOS_ERR, "done pll_reset\n");
cpuRegInit();
- print_err("done cpuRegInit\n");
+ printk(BIOS_ERR, "done cpuRegInit\n");
sdram_initialize(1, memctrl);
- print_err("Done sdram_initialize\n");
- print_err("Disable watchdog\n");
+ printk(BIOS_ERR, "Done sdram_initialize\n");
+ printk(BIOS_ERR, "Disable watchdog\n");
outb( 0x87, 0x4E); //enter SuperIO configuration mode
outb( 0x87, 0x4E);
outb(0x20, 0x4e);
temp = inb(0x4f);
- print_debug_hex8(temp);
+ printk(BIOS_DEBUG, "%02x", temp);
if (temp != 0x52){
- print_err("CAN NOT READ SUPERIO VID\n");
+ printk(BIOS_ERR, "CAN NOT READ SUPERIO VID\n");
}
outb(0x29, 0x4e);
@@ -121,9 +120,9 @@ void main(unsigned long bist)
outb( 0xC7, 0x4F);
outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
- print_debug_hex8(temp);print_debug(":");
+ printk(BIOS_DEBUG, "%02x:", temp);
temp = temp & ~8;
outb( temp, 0x4F);
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
- print_debug_hex8(temp);print_debug("\n");
+ printk(BIOS_DEBUG, "%02x\n", temp);
}
diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c
index 416a8fb..a218d45 100644
--- a/src/mainboard/lippert/hurricane-lx/romstage.c
+++ b/src/mainboard/lippert/hurricane-lx/romstage.c
@@ -141,9 +141,7 @@ void main(unsigned long bist)
int err;
/* bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {
- print_err("ERROR ");
- print_err_char('0'+err);
- print_err(" sending config data to SMC\n");
+ printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
}
#endif
diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c
index 8b48640..9a38a63 100644
--- a/src/mainboard/lippert/literunner-lx/romstage.c
+++ b/src/mainboard/lippert/literunner-lx/romstage.c
@@ -84,11 +84,9 @@ int spd_read_byte(unsigned int device, unsigned int address)
return 0xFF; /* No DIMM1, don't even try. */
#if CONFIG_DEBUG_SMBUS
- if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
- print_err("ERROR: spd_read_byte(DIMM0, 0x");
- print_err_hex8(address);
- print_err(") returns 0xff\n");
- }
+ if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF)
+ printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
+ "returns 0xff\n", address);
#endif
/* Fake SPD ROM value */
@@ -182,9 +180,7 @@ void main(unsigned long bist)
/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {
- print_err("ERROR ");
- print_err_char('0'+err);
- print_err(" sending config data to SMC\n");
+ printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
}
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c
index 3c25c08..02b61ea 100644
--- a/src/mainboard/lippert/spacerunner-lx/romstage.c
+++ b/src/mainboard/lippert/spacerunner-lx/romstage.c
@@ -85,9 +85,8 @@ int spd_read_byte(unsigned int device, unsigned int address)
#if CONFIG_DEBUG_SMBUS
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
- print_err("ERROR: spd_read_byte(DIMM0, 0x");
- print_err_hex8(address);
- print_err(") returns 0xff\n");
+ printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
+ "returns 0xff\n", address);
}
#endif
@@ -179,9 +178,7 @@ void main(unsigned long bist)
/* bit1 = on-board IDE is slave, bit0 = Spread Spectrum */
if ((err = smc_send_config(SMC_CONFIG))) {
- print_err("ERROR ");
- print_err_char('0'+err);
- print_err(" sending config data to SMC\n");
+ printk(BIOS_ERR, "ERROR %d sending config data to SMC\n", err);
}
sdram_initialize(1, memctrl);
diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c
index 15c02f5..12c2f3b 100644
--- a/src/mainboard/msi/ms7135/romstage.c
+++ b/src/mainboard/msi/ms7135/romstage.c
@@ -146,7 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c
index fd8fbfb..0f91067 100644
--- a/src/mainboard/msi/ms7260/romstage.c
+++ b/src/mainboard/msi/ms7260/romstage.c
@@ -131,9 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist); /* Halt upon BIST failure. */
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid=");
- print_debug_hex8(bsp_apicid);
- print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
/* In BSP so could hold all AP until sysinfo is in RAM. */
set_sysinfo_in_ram(0);
@@ -158,20 +156,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
#if CONFIG_SET_FIDVID
{
msr_t msr = rdmsr(0xc0010042);
- print_debug("begin msr fid, vid ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
{
msr_t msr = rdmsr(0xc0010042);
- print_debug("end msr fid, vid ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -183,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* fidvid change will issue one LDTSTOP and the HT change will be effective too. */
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c
index bd82436..22c3842 100644
--- a/src/mainboard/msi/ms9185/romstage.c
+++ b/src/mainboard/msi/ms9185/romstage.c
@@ -123,7 +123,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
setup_coherent_ht_domain();
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -162,7 +162,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -172,7 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
#endif
diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c
index 9a6e21f..1b84d30 100644
--- a/src/mainboard/msi/ms9282/romstage.c
+++ b/src/mainboard/msi/ms9282/romstage.c
@@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c
index 722122d..15702c3 100644
--- a/src/mainboard/msi/ms9652_fam10/romstage.c
+++ b/src/mainboard/msi/ms9652_fam10/romstage.c
@@ -209,7 +209,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c
index b34882e..99804ff 100644
--- a/src/mainboard/newisys/khepri/romstage.c
+++ b/src/mainboard/newisys/khepri/romstage.c
@@ -109,7 +109,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c
index df78a0c..afac008 100644
--- a/src/mainboard/nvidia/l1_2pvv/romstage.c
+++ b/src/mainboard/nvidia/l1_2pvv/romstage.c
@@ -131,7 +131,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
report_bist_failure(bist);
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -154,7 +154,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -175,7 +175,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
allow_all_aps_stop(bsp_apicid);
diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c
index f4bbc31..5cf8d7a 100644
--- a/src/mainboard/pcengines/alix1c/romstage.c
+++ b/src/mainboard/pcengines/alix1c/romstage.c
@@ -83,19 +83,15 @@ static const u8 spdbytes[] = {
int spd_read_byte(unsigned int device, unsigned int address)
{
- print_debug("spd_read_byte dev ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);
if (device != DIMM0) {
- print_debug(" returns 0xff\n");
+ printk(BIOS_DEBUG, " returns 0xff\n");
return 0xff;
}
- print_debug(" addr ");
- print_debug_hex8(address);
- print_debug(" returns ");
- print_debug_hex8(spdbytes[address]);
- print_debug("\n");
+ printk(BIOS_DEBUG, " addr %02x returns %02x\n",
+ address, spdbytes[address]);
return spdbytes[address];
}
@@ -156,9 +152,9 @@ void main(unsigned long bist)
* We use method 1 on Norwich and on this board too.
*/
post_code(0x02);
- print_err("POST 02\n");
+ printk(BIOS_ERR, "POST 02\n");
__asm__("wbinvd\n");
- print_err("Past wbinvd\n");
+ printk(BIOS_ERR, "Past wbinvd\n");
/* We are finding the return does not work on this board. Explicitly
* call the label that is after the call to us. This is gross, but
diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c
index 1316d5e..96d6fb1 100644
--- a/src/mainboard/pcengines/alix2d/romstage.c
+++ b/src/mainboard/pcengines/alix2d/romstage.c
@@ -81,19 +81,15 @@ static const u8 spdbytes[] = {
int spd_read_byte(unsigned int device, unsigned int address)
{
- print_debug("spd_read_byte dev ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "spd_read_byte dev %02x", device);
if (device != DIMM0) {
- print_debug(" returns 0xff\n");
+ printk(BIOS_DEBUG, " returns 0xff\n");
return 0xff;
}
- print_debug(" addr ");
- print_debug_hex8(address);
- print_debug(" returns ");
- print_debug_hex8(spdbytes[address]);
- print_debug("\n");
+ printk(BIOS_DEBUG, " addr %02x returns %02x\n",
+ address, spdbytes[address]);
return spdbytes[address];
}
@@ -179,9 +175,9 @@ void main(unsigned long bist)
* We use method 1 on Norwich and on this board too.
*/
post_code(0x02);
- print_err("POST 02\n");
+ printk(BIOS_ERR, "POST 02\n");
__asm__("wbinvd\n");
- print_err("Past wbinvd\n");
+ printk(BIOS_ERR, "Past wbinvd\n");
/* We are finding the return does not work on this board. Explicitly
* call the label that is after the call to us. This is gross, but
diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c
index 99d0dfb..10bdb0b 100644
--- a/src/mainboard/sunw/ultra40/romstage.c
+++ b/src/mainboard/sunw/ultra40/romstage.c
@@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c
index e3e7386..810a708 100644
--- a/src/mainboard/supermicro/h8dme/romstage.c
+++ b/src/mainboard/supermicro/h8dme/romstage.c
@@ -146,9 +146,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map();
- print_debug("bsp_apicid=");
- print_debug_hex8(bsp_apicid);
- print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
#if CONFIG_DEBUG_SMBUS
@@ -174,10 +172,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr = rdmsr(0xc0010042);
- print_debug("begin msr fid, vid ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -186,10 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr = rdmsr(0xc0010042);
- print_debug("end msr fid, vid ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -201,7 +193,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c
index 7d1f834..f4b25f5 100644
--- a/src/mainboard/supermicro/h8dmr/romstage.c
+++ b/src/mainboard/supermicro/h8dmr/romstage.c
@@ -126,7 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_mb_resource_map();
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
index 08c7d2b..290e915 100644
--- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c
@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c
index c231e31..849258f 100644
--- a/src/mainboard/supermicro/h8qgi/romstage.c
+++ b/src/mainboard/supermicro/h8qgi/romstage.c
@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -107,14 +107,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
- print_debug("should not be here -\n");
+ printk(BIOS_DEBUG, "should not be here -\n");
post_code(0x54);
}
diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c
index f46b2e6..c23ed13 100644
--- a/src/mainboard/supermicro/h8qme_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c
@@ -269,7 +269,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c
index 0bbd8bc..9e06036 100644
--- a/src/mainboard/supermicro/h8scm/romstage.c
+++ b/src/mainboard/supermicro/h8scm/romstage.c
@@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -101,14 +101,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
- print_debug("should not be here -\n");
+ printk(BIOS_DEBUG, "should not be here -\n");
post_code(0x54);
}
diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c
index 350ab16..c22b255 100644
--- a/src/mainboard/supermicro/h8scm_fam10/romstage.c
+++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c
@@ -196,7 +196,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c
index 68373b9..260f170 100644
--- a/src/mainboard/technexion/tim5690/romstage.c
+++ b/src/mainboard/technexion/tim5690/romstage.c
@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c
index 0ba0fce..eaedc39 100644
--- a/src/mainboard/technexion/tim8690/romstage.c
+++ b/src/mainboard/technexion/tim8690/romstage.c
@@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset);
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 952b19d..8e0d7d1 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -93,7 +93,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 8f87257..656a3e0 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -102,7 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c
index 873652b..1f9dccb 100644
--- a/src/mainboard/tyan/s2880/romstage.c
+++ b/src/mainboard/tyan/s2880/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c
index c020f3e..1716133 100644
--- a/src/mainboard/tyan/s2881/romstage.c
+++ b/src/mainboard/tyan/s2881/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c
index 873652b..1f9dccb 100644
--- a/src/mainboard/tyan/s2882/romstage.c
+++ b/src/mainboard/tyan/s2882/romstage.c
@@ -103,7 +103,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c
index df602ea..57669f4 100644
--- a/src/mainboard/tyan/s2885/romstage.c
+++ b/src/mainboard/tyan/s2885/romstage.c
@@ -98,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 55cb95e..bd0bfc5 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -129,7 +129,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n");
+ printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid);
set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
setup_coherent_ht_domain(); // routing table and start other core0
@@ -152,7 +152,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
@@ -161,7 +161,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
msr_t msr;
msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
+ printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo);
}
#endif
@@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
// fidvid change will issue one LDTSTOP and the HT change will be effective too
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 3e0f8f3..79eb906 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -205,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
}
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index c106b1c..5d8f9f5 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -138,7 +138,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c
index 17379b5..aa58a6f 100644
--- a/src/mainboard/tyan/s4882/romstage.c
+++ b/src/mainboard/tyan/s4882/romstage.c
@@ -116,7 +116,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
needs_reset |= ht_setup_chains_x();
if (needs_reset) {
- print_info("ht reset -\n");
+ printk(BIOS_INFO, "ht reset -\n");
soft_reset();
}
diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c
index ac28874..d4b91f7 100644
--- a/src/mainboard/tyan/s8226/romstage.c
+++ b/src/mainboard/tyan/s8226/romstage.c
@@ -96,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x3D);
/* Reset for HT, FIDVID, PLL and ucode patch(errata) changes to take affect. */
if (!warm_reset_detect(0)) {
- print_info("...WARM RESET...\n\n\n");
+ printk(BIOS_INFO, "...WARM RESET...\n\n\n");
distinguish_cpu_resets(0);
soft_reset();
die("After soft_reset_x - shouldn't see this message!!!\n");
@@ -110,14 +110,14 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x42);
post_code(0x50);
- print_debug("Disabling cache as ram ");
+ printk(BIOS_DEBUG, "Disabling cache as ram ");
disable_cache_as_ram();
- print_debug("done\n");
+ printk(BIOS_DEBUG, "done\n");
post_code(0x51);
copy_and_run();
/* We will not return, Should never see this message and post code. */
- print_debug("should not be here -\n");
+ printk(BIOS_DEBUG, "should not be here -\n");
post_code(0x54);
}
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c
index c9b1e8b..9e3a16a 100644
--- a/src/mainboard/via/epia-m700/romstage.c
+++ b/src/mainboard/via/epia-m700/romstage.c
@@ -57,7 +57,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
device_t dev;
u16 tmp, result;
- print_debug("In acpi_is_wakeup_early_via_vx800\n");
+ printk(BIOS_DEBUG, "In acpi_is_wakeup_early_via_vx800\n");
/* Power management controller */
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855_LPC), 0);
@@ -73,9 +73,7 @@ static int acpi_is_wakeup_early_via_vx800(void)
tmp = inw(VX800_ACPI_IO_BASE + 0x04);
result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0;
- print_debug(" boot_mode=");
- print_debug_hex16(result);
- print_debug("\n");
+ printk(BIOS_DEBUG, " boot_mode=%04x\n", result);
return result;
}
@@ -116,7 +114,7 @@ static void enable_mainboard_devices(void)
pci_write_config8(dev, 0x5b, 0x01);
#endif
- print_debug("In enable_mainboard_devices\n");
+ printk(BIOS_DEBUG, "In enable_mainboard_devices\n");
/* Enable P2P Bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
@@ -451,7 +449,7 @@ void main(unsigned long bist)
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n");
+ printk(BIOS_DEBUG, "Enabling mainboard devices\n");
enable_mainboard_devices();
/*
@@ -460,9 +458,7 @@ void main(unsigned long bist)
*/
device = PCI_DEV(0, 0, 4);
Data = pci_read_config8(device, 0xf6);
- print_debug("NB chip revision =");
- print_debug_hex8(Data);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NB chip revision = %02x\n", Data);
/* Make NB ready before DRAM init. */
via_pci_inittable(Data, mNbStage1InitTbl);
@@ -479,7 +475,7 @@ void main(unsigned long bist)
u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
DRAM_SYS_ATTR DramAttr;
- print_debug("This is an S3 wakeup\n");
+ printk(BIOS_DEBUG, "This is an S3 wakeup\n");
memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR));
/*
@@ -514,7 +510,7 @@ void main(unsigned long bist)
/* Just copy this function from draminit to here! */
SetUMARam();
- print_debug("Resume from S3, RAM init was ignored\n");
+ printk(BIOS_DEBUG, "Resume from S3, RAM init was ignored\n");
} else {
ddr2_ram_setup();
ram_check(0, 640 * 1024);
@@ -634,7 +630,7 @@ void main(unsigned long bist)
);
#endif
/* This can have function call, because no variable used before this. */
- print_debug("Copy memory to high memory to protect s3 wakeup vector code\n");
+ printk(BIOS_DEBUG, "Copy memory to high memory to protect s3 wakeup vector code\n");
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
0x100000), (unsigned char *)0, 0xa0000);
memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 -
diff --git a/src/mainboard/via/epia-m850/mainboard.c b/src/mainboard/via/epia-m850/mainboard.c
index dbe682c..9cd69a2 100644
--- a/src/mainboard/via/epia-m850/mainboard.c
+++ b/src/mainboard/via/epia-m850/mainboard.c
@@ -100,7 +100,7 @@ static void mainboard_enable(device_t dev)
(void)dev;
#if CONFIG_VGA_ROM_RUN
- print_debug("Installing INT15 handler...\n");
+ printk(BIOS_DEBUG, "Installing INT15 handler...\n");
mainboard_interrupt_handlers(0x15, &vx900_int15_handler);
#endif
}
diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c
index 899c5a6..bea5300 100644
--- a/src/mainboard/via/epia-m850/romstage.c
+++ b/src/mainboard/via/epia-m850/romstage.c
@@ -55,7 +55,7 @@ void main(unsigned long bist)
/* Serial console is easy to take care of */
fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
- print_debug("Console initialized.\n");
+ printk(BIOS_DEBUG, "Console initialized.\n");
vx900_cpu_bus_interface_setup();
@@ -91,7 +91,7 @@ void main(unsigned long bist)
if (tolm > (2 * (u32) GiB))
ram_check(2048 << 20, 0x80);
- print_debug("We passed RAM verify\n");
+ printk(BIOS_DEBUG, "We passed RAM verify\n");
/* We got RAM working, now we can write the timestamps to RAM */
#if CONFIG_EARLY_CBMEM_INIT
diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c
index 6283c9c..8674dd6 100644
--- a/src/mainboard/wyse/s50/romstage.c
+++ b/src/mainboard/wyse/s50/romstage.c
@@ -70,10 +70,10 @@ void main(unsigned long bist)
pll_reset();
cpuRegInit();
- print_err("done cpuRegInit\n");
+ printk(BIOS_ERR, "done cpuRegInit\n");
sdram_initialize(1, memctrl);
- print_err("ram setup done\n");
+ printk(BIOS_ERR, "ram setup done\n");
msr_init();
}
1
0
New patch to review for coreboot: b931f2c southbridge: Drop print_ implementation from non-romcc boards
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8110
-gerrit
commit b931f2c685d3fb2baa1e8919972fc2fdd27e4ee5
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 13:01:01 2015 -0800
southbridge: Drop print_ implementation from non-romcc boards
Because we have no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the southbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I312406257e66bbdc3940e206b5256460559a2c98
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/southbridge/amd/amd8111/early_smbus.c | 2 +-
src/southbridge/amd/cs5535/early_setup.c | 12 +++++------
src/southbridge/amd/cs5536/early_setup.c | 12 +++++------
src/southbridge/amd/cs5536/smbus.c | 6 +-----
src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +-
src/southbridge/intel/bd82x6x/early_smbus.c | 2 +-
src/southbridge/intel/esb6300/early_smbus.c | 4 ++--
src/southbridge/intel/fsp_bd82x6x/early_smbus.c | 2 +-
src/southbridge/intel/fsp_rangeley/early_smbus.c | 2 +-
src/southbridge/intel/i3100/early_smbus.c | 2 +-
src/southbridge/intel/i82371eb/smbus.h | 4 +---
src/southbridge/intel/i82801ax/early_smbus.c | 2 +-
src/southbridge/intel/i82801bx/early_smbus.c | 2 +-
src/southbridge/intel/i82801cx/early_smbus.c | 2 +-
src/southbridge/intel/i82801dx/early_smbus.c | 14 ++++++-------
src/southbridge/intel/i82801ex/early_smbus.c | 8 ++++----
src/southbridge/intel/i82801gx/early_smbus.c | 2 +-
src/southbridge/intel/i82801ix/early_smbus.c | 2 +-
src/southbridge/intel/ibexpeak/early_smbus.c | 2 +-
src/southbridge/intel/lynxpoint/early_smbus.c | 2 +-
src/southbridge/intel/sch/early_smbus.c | 2 +-
src/southbridge/nvidia/ck804/early_smbus.c | 2 +-
src/southbridge/nvidia/mcp55/early_setup_car.c | 4 +---
src/southbridge/sis/sis966/aza.c | 17 +++++++---------
src/southbridge/sis/sis966/early_smbus.c | 22 ++++++++++----------
src/southbridge/sis/sis966/ide.c | 20 ++++++++----------
src/southbridge/sis/sis966/nic.c | 20 ++++++++----------
src/southbridge/sis/sis966/sata.c | 20 ++++++++----------
src/southbridge/sis/sis966/usb.c | 20 ++++++++----------
src/southbridge/sis/sis966/usb2.c | 20 ++++++++----------
src/southbridge/via/k8t890/bridge.c | 2 +-
src/southbridge/via/k8t890/ctrl.c | 8 ++++----
src/southbridge/via/k8t890/dram.c | 2 +-
src/southbridge/via/k8t890/early_car.c | 25 ++++++++++-------------
src/southbridge/via/k8t890/error.c | 6 +++---
src/southbridge/via/k8t890/host.c | 2 +-
src/southbridge/via/k8t890/host_ctrl.c | 2 +-
src/southbridge/via/vt8237r/ctrl.c | 4 ++--
src/southbridge/via/vt8237r/early_smbus.c | 26 ++++++++++++------------
src/southbridge/via/vt8237r/vt8237r.c | 10 +++------
src/southbridge/via/vt8237r/vt8237r.h | 4 ++--
41 files changed, 143 insertions(+), 181 deletions(-)
diff --git a/src/southbridge/amd/amd8111/early_smbus.c b/src/southbridge/amd/amd8111/early_smbus.c
index e236286..aed4ebb 100644
--- a/src/southbridge/amd/amd8111/early_smbus.c
+++ b/src/southbridge/amd/amd8111/early_smbus.c
@@ -23,7 +23,7 @@ static void enable_smbus(void)
/* clear any lingering errors, so the transaction will run */
outw(inw(SMBUS_IO_BASE + SMBGSTATUS), SMBUS_IO_BASE + SMBGSTATUS);
- print_spew("SMBus controller enabled\n");
+ printk(BIOS_SPEW, "SMBus controller enabled\n");
}
static inline int smbus_recv_byte(unsigned device)
diff --git a/src/southbridge/amd/cs5535/early_setup.c b/src/southbridge/amd/cs5535/early_setup.c
index 4a2e1b4..1030aa0 100644
--- a/src/southbridge/amd/cs5535/early_setup.c
+++ b/src/southbridge/amd/cs5535/early_setup.c
@@ -127,19 +127,19 @@ static void cs5535_early_setup(void)
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
- print_debug("reboot from BIOS reset\n");
+ printk(BIOS_DEBUG, "reboot from BIOS reset\n");
return;
}
- print_debug("Setup idsel\n");
+ printk(BIOS_DEBUG, "Setup idsel\n");
cs5535_setup_idsel();
- print_debug("Setup iobase\n");
+ printk(BIOS_DEBUG, "Setup iobase\n");
cs5535_usb_swapsif();
cs5535_setup_iobase();
- print_debug("Setup gpio\n");
+ printk(BIOS_DEBUG, "Setup gpio\n");
cs5535_setup_gpio();
- print_debug("Setup cis_mode\n");
+ printk(BIOS_DEBUG, "Setup cis_mode\n");
cs5535_setup_cis_mode();
- print_debug("Setup smbus\n");
+ printk(BIOS_DEBUG, "Setup smbus\n");
cs5535_enable_smbus();
dummy();
}
diff --git a/src/southbridge/amd/cs5536/early_setup.c b/src/southbridge/amd/cs5536/early_setup.c
index e6ef8ad..ea8b5e0 100644
--- a/src/southbridge/amd/cs5536/early_setup.c
+++ b/src/southbridge/amd/cs5536/early_setup.c
@@ -258,18 +258,18 @@ static void cs5536_early_setup(void)
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
- //print_debug("reboot from BIOS reset\n");
+ //printk(BIOS_DEBUG, "reboot from BIOS reset\n");
return;
}
- //print_debug("Setup idsel\n");
+ //printk(BIOS_DEBUG, "Setup idsel\n");
cs5536_setup_idsel();
- //print_debug("Setup iobase\n");
+ //printk(BIOS_DEBUG, "Setup iobase\n");
cs5536_usb_swapsif();
cs5536_setup_iobase();
- //print_debug("Setup gpio\n");
+ //printk(BIOS_DEBUG, "Setup gpio\n");
cs5536_setup_gpio();
- //print_debug("Setup smbus\n");
+ //printk(BIOS_DEBUG, "Setup smbus\n");
cs5536_enable_smbus();
- //print_debug("Setup power button\n");
+ //printk(BIOS_DEBUG, "Setup power button\n");
cs5536_setup_power_button();
}
diff --git a/src/southbridge/amd/cs5536/smbus.c b/src/southbridge/amd/cs5536/smbus.c
index 31c5bf1..3da8389 100644
--- a/src/southbridge/amd/cs5536/smbus.c
+++ b/src/southbridge/amd/cs5536/smbus.c
@@ -182,11 +182,7 @@ unsigned char do_smbus_read_byte(unsigned smbus_io_base,
return smbus_get_result(smbus_io_base);
err:
- print_debug("SMBUS READ ERROR:");
- print_debug_hex8(error);
- print_debug(" device:");
- print_debug_hex8(device);
- print_debug("\n");
+ printk(BIOS_DEBUG, "SMBUS READ ERROR: %02x device: %02x\n", error, device);
/* stop, clean up the error, and leave */
smbus_stop_condition(smbus_io_base);
outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c
index 38e58f8..636da2e 100644
--- a/src/southbridge/broadcom/bcm5785/early_smbus.c
+++ b/src/southbridge/broadcom/bcm5785/early_smbus.c
@@ -31,7 +31,7 @@ static void enable_smbus(void)
die("SMBUS controller not found\n");
}
- print_debug("SMBus controller enabled\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, 0x90, SMBUS_IO_BASE | 1);
/* Set smbus iospace enable */
diff --git a/src/southbridge/intel/bd82x6x/early_smbus.c b/src/southbridge/intel/bd82x6x/early_smbus.c
index 616e7c3..7ba2e88 100644
--- a/src/southbridge/intel/bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/bd82x6x/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/intel/esb6300/early_smbus.c b/src/southbridge/intel/esb6300/early_smbus.c
index fbbf4d9..9ad4f65 100644
--- a/src/southbridge/intel/esb6300/early_smbus.c
+++ b/src/southbridge/intel/esb6300/early_smbus.c
@@ -6,7 +6,7 @@ static void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\n");
+ printk(BIOS_SPEW, "SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
pci_write_config8(dev, 0x40, 1);
pci_write_config8(dev, 0x4, 1);
@@ -91,7 +91,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
SMBUS_IO_BASE + SMBHSTSTAT);
}
- print_debug("SMBUS Block complete\n");
+ printk(BIOS_DEBUG, "SMBUS Block complete\n");
return 0;
}
#endif
diff --git a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c
index 3d347b4..c5459cb 100644
--- a/src/southbridge/intel/fsp_bd82x6x/early_smbus.c
+++ b/src/southbridge/intel/fsp_bd82x6x/early_smbus.c
@@ -97,7 +97,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
/** \brief generic smbus helper function to read & write to the smbus
diff --git a/src/southbridge/intel/fsp_rangeley/early_smbus.c b/src/southbridge/intel/fsp_rangeley/early_smbus.c
index c89d176..c1da54b 100644
--- a/src/southbridge/intel/fsp_rangeley/early_smbus.c
+++ b/src/southbridge/intel/fsp_rangeley/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/intel/i3100/early_smbus.c b/src/southbridge/intel/i3100/early_smbus.c
index f06947c..484627c 100644
--- a/src/southbridge/intel/i3100/early_smbus.c
+++ b/src/southbridge/intel/i3100/early_smbus.c
@@ -26,7 +26,7 @@ static void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\n");
+ printk(BIOS_SPEW, "SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
pci_write_config8(dev, 0x40, 1);
pci_write_config8(dev, 0x4, 1);
diff --git a/src/southbridge/intel/i82371eb/smbus.h b/src/southbridge/intel/i82371eb/smbus.h
index 6c7c6f4..fd02217 100644
--- a/src/southbridge/intel/i82371eb/smbus.h
+++ b/src/southbridge/intel/i82371eb/smbus.h
@@ -104,9 +104,7 @@ int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address
if (status_register & 0x04) {
#if 0
- print_debug("Read fail ");
- print_debug_hex16(status_register);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Read fail %04x\n", status_register);
#endif
return SMBUS_ERROR;
}
diff --git a/src/southbridge/intel/i82801ax/early_smbus.c b/src/southbridge/intel/i82801ax/early_smbus.c
index 878d5f6..104875a 100644
--- a/src/southbridge/intel/i82801ax/early_smbus.c
+++ b/src/southbridge/intel/i82801ax/early_smbus.c
@@ -50,7 +50,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
}
int smbus_read_byte(u8 device, u8 address)
diff --git a/src/southbridge/intel/i82801bx/early_smbus.c b/src/southbridge/intel/i82801bx/early_smbus.c
index 26c9e85..a87a4a7 100644
--- a/src/southbridge/intel/i82801bx/early_smbus.c
+++ b/src/southbridge/intel/i82801bx/early_smbus.c
@@ -50,7 +50,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
}
int smbus_read_byte(u8 device, u8 address)
diff --git a/src/southbridge/intel/i82801cx/early_smbus.c b/src/southbridge/intel/i82801cx/early_smbus.c
index b62db80..5be6353 100644
--- a/src/southbridge/intel/i82801cx/early_smbus.c
+++ b/src/southbridge/intel/i82801cx/early_smbus.c
@@ -5,7 +5,7 @@ static void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_debug("SMBus controller enabled\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, SMB_BASE, SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
/* Set smbus enable */
diff --git a/src/southbridge/intel/i82801dx/early_smbus.c b/src/southbridge/intel/i82801dx/early_smbus.c
index 6f4d4f8..c61de85 100644
--- a/src/southbridge/intel/i82801dx/early_smbus.c
+++ b/src/southbridge/intel/i82801dx/early_smbus.c
@@ -28,7 +28,7 @@ void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_debug("SMBus controller enabled\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
/* Set smbus enable */
@@ -104,9 +104,9 @@ int smbus_read_byte(unsigned device, unsigned address)
unsigned char global_status_register;
unsigned char byte;
- /* print_err("smbus_read_byte\n"); */
+ /* printk(BIOS_ERR, "smbus_read_byte\n"); */
if (smbus_wait_until_ready() < 0) {
- print_err("SMBUS not ready (-2)\n");
+ printk(BIOS_ERR, "SMBUS not ready (-2)\n");
return -2;
}
@@ -132,13 +132,13 @@ int smbus_read_byte(unsigned device, unsigned address)
SMBUS_IO_BASE + SMBHSTCTL);
/* poll for it to start */
if (smbus_wait_until_active() < 0) {
- print_err("SMBUS not active (-4)\n");
+ printk(BIOS_ERR, "SMBUS not active (-4)\n");
return -4;
}
/* poll for transaction completion */
if (smbus_wait_until_done() < 0) {
- print_err("SMBUS not completed (-3)\n");
+ printk(BIOS_ERR, "SMBUS not completed (-3)\n");
return -3;
}
@@ -148,10 +148,10 @@ int smbus_read_byte(unsigned device, unsigned address)
byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
if (global_status_register != 2) {
- //print_spew("%s: no device (%02x, %02x)\n", __func__, device, address);
+ //printk(BIOS_SPEW, "%s: no device (%02x, %02x)\n", __func__, device, address);
return -1;
}
- //print_debug("%s: %02x@%02x = %02x\n", __func__, device, address, byte);
+ //printk(BIOS_DEBUG, "%s: %02x@%02x = %02x\n", __func__, device, address, byte);
return byte;
}
diff --git a/src/southbridge/intel/i82801ex/early_smbus.c b/src/southbridge/intel/i82801ex/early_smbus.c
index cdf1f62..979b842 100644
--- a/src/southbridge/intel/i82801ex/early_smbus.c
+++ b/src/southbridge/intel/i82801ex/early_smbus.c
@@ -6,10 +6,10 @@ static void enable_smbus(void)
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x3);
- print_spew("SMBus controller enabled\n");
+ printk(BIOS_SPEW, "SMBus controller enabled\n");
pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1);
- print_debug_hex32(pci_read_config32(dev, 0x20));
+ printk(BIOS_DEBUG, "%08x", pci_read_config32(dev, 0x20));
/* Set smbus enable */
pci_write_config8(dev, 0x40, 1);
/* Set smbus iospace enable */
@@ -36,7 +36,7 @@ static void smbus_write_byte(unsigned device, unsigned address, unsigned char va
return;
}
- print_debug("Unimplemented smbus_write_byte() called.\n");
+ printk(BIOS_DEBUG, "Unimplemented smbus_write_byte() called.\n");
#if 0
/* setup transaction */
@@ -124,7 +124,7 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd,
SMBUS_IO_BASE + SMBHSTSTAT);
}
- print_debug("SMBUS Block complete\n");
+ printk(BIOS_DEBUG, "SMBUS Block complete\n");
return 0;
}
#endif
diff --git a/src/southbridge/intel/i82801gx/early_smbus.c b/src/southbridge/intel/i82801gx/early_smbus.c
index 8adc04d..32eccae 100644
--- a/src/southbridge/intel/i82801gx/early_smbus.c
+++ b/src/southbridge/intel/i82801gx/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/intel/i82801ix/early_smbus.c b/src/southbridge/intel/i82801ix/early_smbus.c
index 981ae5e..0393c3d 100644
--- a/src/southbridge/intel/i82801ix/early_smbus.c
+++ b/src/southbridge/intel/i82801ix/early_smbus.c
@@ -53,7 +53,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/intel/ibexpeak/early_smbus.c b/src/southbridge/intel/ibexpeak/early_smbus.c
index f518f28..cf02b9e 100644
--- a/src/southbridge/intel/ibexpeak/early_smbus.c
+++ b/src/southbridge/intel/ibexpeak/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/intel/lynxpoint/early_smbus.c b/src/southbridge/intel/lynxpoint/early_smbus.c
index 616e7c3..7ba2e88 100644
--- a/src/southbridge/intel/lynxpoint/early_smbus.c
+++ b/src/southbridge/intel/lynxpoint/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/intel/sch/early_smbus.c b/src/southbridge/intel/sch/early_smbus.c
index 8adc04d..32eccae 100644
--- a/src/southbridge/intel/sch/early_smbus.c
+++ b/src/southbridge/intel/sch/early_smbus.c
@@ -52,7 +52,7 @@ void enable_smbus(void)
/* Clear any lingering errors, so transactions can run. */
outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
- print_debug("SMBus controller enabled.\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
}
int smbus_read_byte(unsigned device, unsigned address)
diff --git a/src/southbridge/nvidia/ck804/early_smbus.c b/src/southbridge/nvidia/ck804/early_smbus.c
index a8c12a2..e0f8648 100644
--- a/src/southbridge/nvidia/ck804/early_smbus.c
+++ b/src/southbridge/nvidia/ck804/early_smbus.c
@@ -54,7 +54,7 @@ void enable_smbus(void)
outb(inb(SMBUS_BASE(0) + SMBHSTSTAT), SMBUS_BASE(0) + SMBHSTSTAT);
outb(inb(SMBUS_BASE(1) + SMBHSTSTAT), SMBUS_BASE(1) + SMBHSTSTAT);
- print_debug("SMBus controller enabled\n");
+ printk(BIOS_DEBUG, "SMBus controller enabled\n");
}
int ck804_smbus_read_byte(unsigned bus, unsigned device, unsigned address)
diff --git a/src/southbridge/nvidia/mcp55/early_setup_car.c b/src/southbridge/nvidia/mcp55/early_setup_car.c
index 4b1443c..2e03d6b 100644
--- a/src/southbridge/nvidia/mcp55/early_setup_car.c
+++ b/src/southbridge/nvidia/mcp55/early_setup_car.c
@@ -392,9 +392,7 @@ static int mcp55_early_setup_x(void)
}
out:
- print_debug("mcp55_num:");
- print_debug_hex8(mcp55_num);
- print_debug("\n");
+ printk(BIOS_DEBUG, "mcp55_num: %02x\n", mcp55_num);
mcp55_early_set_port(mcp55_num, busn, devn, io_base);
mcp55_early_setup(mcp55_num, busn, devn, io_base, pci_e_x);
diff --git a/src/southbridge/sis/sis966/aza.c b/src/southbridge/sis/sis966/aza.c
index 7e148cf..1a9462b 100644
--- a/src/southbridge/sis/sis966/aza.c
+++ b/src/southbridge/sis/sis966/aza.c
@@ -244,7 +244,7 @@ static void aza_init(struct device *dev)
struct resource *res;
u32 codec_mask;
- print_debug("AZALIA_INIT:---------->\n");
+ printk(BIOS_DEBUG, "AZALIA_INIT:---------->\n");
//-------------- enable AZA (SiS7502) -------------------------
{
@@ -269,19 +269,16 @@ static void aza_init(struct device *dev)
{
int i;
- print_debug("****** Azalia PCI config ******");
- print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** Azalia PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
if((i%16)==0){
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%02x: ", i);
}
- print_debug_hex32(pci_read_config32(dev,i));
- print_debug(" ");
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
@@ -299,7 +296,7 @@ static void aza_init(struct device *dev)
codecs_init(base, codec_mask);
}
- print_debug("AZALIA_INIT:<----------\n");
+ printk(BIOS_DEBUG, "AZALIA_INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/early_smbus.c b/src/southbridge/sis/sis966/early_smbus.c
index 06130db..079e4b0 100644
--- a/src/southbridge/sis/sis966/early_smbus.c
+++ b/src/southbridge/sis/sis966/early_smbus.c
@@ -138,23 +138,23 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un
outb(0x12, smbus_io_base + 0x03);
smbus_delay();
-int i,j;
-for(i=0;i<0x1000;i++)
-{
- if (inb(smbus_io_base + 0x00) != 0x08)
- { smbus_delay();
- for(j=0;j<0xFFFF;j++);
+ int i, j;
+ for(i = 0;i < 0x1000; i++)
+ {
+ if (inb(smbus_io_base + 0x00) != 0x08)
+ { smbus_delay();
+ for(j=0;j<0xFFFF;j++);
+ }
}
-};
global_status_register = inb(smbus_io_base + 0x00);
byte = inb(smbus_io_base + 0x08);
if (global_status_register != 0x08) { // lose check, otherwise it should be 0
- print_debug("Fail");print_debug("\r\t");
- return -1;
+ printk(BIOS_DEBUG, "Fail\r\t");
+ return -1;
}
- print_debug("Success");print_debug("\r\t");
+ printk(BIOS_DEBUG, "Success\r\t");
return byte;
}
@@ -706,7 +706,7 @@ static void sis_init_stage2(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_SATA), 0);
if (!dev)
- print_debug("SiS 1183 does not exist !!");
+ printk(BIOS_DEBUG, "SiS 1183 does not exist !!");
// SATA Set Mode
pci_write_config8(dev, 0x90, (pci_read_config8(dev, 0x90)&0x3F) | 0x40);
diff --git a/src/southbridge/sis/sis966/ide.c b/src/southbridge/sis/sis966/ide.c
index ddfcead..5300b7e 100644
--- a/src/southbridge/sis/sis966/ide.c
+++ b/src/southbridge/sis/sis966/ide.c
@@ -100,7 +100,7 @@ static void ide_init(struct device *dev)
-print_debug("IDE_INIT:---------->\n");
+printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
//-------------- enable IDE (SiS5513) -------------------------
@@ -149,22 +149,18 @@ print_debug("IDE_INIT:---------->\n");
{
int i;
- print_debug("****** IDE PCI config ******");
- print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** IDE PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
- if((i%16)==0){
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
- print_debug_hex32(pci_read_config32(dev,i));
- print_debug(" ");
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
-print_debug("IDE_INIT:<----------\n");
+printk(BIOS_DEBUG, "IDE_INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/nic.c b/src/southbridge/sis/sis966/nic.c
index 18ed75e..b12c831 100644
--- a/src/southbridge/sis/sis966/nic.c
+++ b/src/southbridge/sis/sis966/nic.c
@@ -241,7 +241,7 @@ static void nic_init(struct device *dev)
u32 base;
struct resource *res;
- print_debug("NIC_INIT:---------->\n");
+ printk(BIOS_DEBUG, "NIC_INIT:---------->\n");
//-------------- enable NIC (SiS19x) -------------------------
{
@@ -312,19 +312,15 @@ static void nic_init(struct device *dev)
{
int i;
- print_debug("****** NIC PCI config ******");
- print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** NIC PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
- if((i%16)==0){
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
- print_debug_hex32(pci_read_config32(dev,i));
- print_debug(" ");
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
@@ -332,7 +328,7 @@ static void nic_init(struct device *dev)
}
-print_debug("NIC_INIT:<----------\n");
+printk(BIOS_DEBUG, "NIC_INIT:<----------\n");
return;
diff --git a/src/southbridge/sis/sis966/sata.c b/src/southbridge/sis/sis966/sata.c
index 3f8c28f..ade8c1c 100644
--- a/src/southbridge/sis/sis966/sata.c
+++ b/src/southbridge/sis/sis966/sata.c
@@ -116,7 +116,7 @@ static void sata_init(struct device *dev)
conf = dev->chip_info;
- print_debug("SATA_INIT:---------->\n");
+ printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
//-------------- enable IDE (SiS1183) -------------------------
{
@@ -151,23 +151,19 @@ for (i=0;i<10;i++){
{
int i;
- print_debug("****** SATA PCI config ******");
- print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** SATA PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
- if((i%16)==0){
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
- print_debug_hex32(pci_read_config32(dev,i));
- print_debug(" ");
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
- print_debug("SATA_INIT:<----------\n");
+ printk(BIOS_DEBUG, "SATA_INIT:<----------\n");
}
diff --git a/src/southbridge/sis/sis966/usb.c b/src/southbridge/sis/sis966/usb.c
index c33f0fc..5aedefb 100644
--- a/src/southbridge/sis/sis966/usb.c
+++ b/src/southbridge/sis/sis966/usb.c
@@ -55,7 +55,7 @@ uint8_t SiS_SiS7001_init[16][3]={
static void usb_init(struct device *dev)
{
- print_debug("USB 1.1 INIT:---------->\n");
+ printk(BIOS_DEBUG, "USB 1.1 INIT:---------->\n");
//-------------- enable USB1.1 (SiS7001) -------------------------
{
@@ -76,22 +76,18 @@ static void usb_init(struct device *dev)
{
int i;
- print_debug("****** USB 1.1 PCI config ******");
- print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** USB 1.1 PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
- if((i%16)==0){
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
- print_debug_hex32(pci_read_config32(dev,i));
- print_debug(" ");
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
- print_debug("USB 1.1 INIT:<----------\n");
+ printk(BIOS_DEBUG, "USB 1.1 INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/sis/sis966/usb2.c b/src/southbridge/sis/sis966/usb2.c
index e2112eb..c6f4027 100644
--- a/src/southbridge/sis/sis966/usb2.c
+++ b/src/southbridge/sis/sis966/usb2.c
@@ -71,7 +71,7 @@ static void usb2_init(struct device *dev)
int i;
u8 temp8;
- print_debug("USB 2.0 INIT:---------->\n");
+ printk(BIOS_DEBUG, "USB 2.0 INIT:---------->\n");
//-------------- enable USB2.0 (SiS7002) ----------------------
@@ -95,21 +95,17 @@ static void usb2_init(struct device *dev)
//-------------------------------------------------------------
#if DEBUG_USB2
- print_debug("****** USB 2.0 PCI config ******");
- print_debug("\n 03020100 07060504 0B0A0908 0F0E0D0C");
+ printk(BIOS_DEBUG, "****** USB 2.0 PCI config ******");
+ printk(BIOS_DEBUG, "\n 03020100 07060504 0B0A0908 0F0E0D0C");
for(i=0;i<0xff;i+=4){
- if((i%16)==0){
- print_debug("\n");
- print_debug_hex8(i);
- print_debug(": ");
- }
- print_debug_hex32(pci_read_config32(dev,i));
- print_debug(" ");
+ if((i%16)==0)
+ printk(BIOS_DEBUG, "\n%02x: ", i);
+ printk(BIOS_DEBUG, "%08x ", pci_read_config32(dev,i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
- print_debug("USB 2.0 INIT:<----------\n");
+ printk(BIOS_DEBUG, "USB 2.0 INIT:<----------\n");
}
static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
diff --git a/src/southbridge/via/k8t890/bridge.c b/src/southbridge/via/k8t890/bridge.c
index 2da31f4..fdf5b9d 100644
--- a/src/southbridge/via/k8t890/bridge.c
+++ b/src/southbridge/via/k8t890/bridge.c
@@ -26,7 +26,7 @@
static void bridge_enable(struct device *dev)
{
u8 tmp;
- print_debug("B188 device dump\n");
+ printk(BIOS_DEBUG, "B188 device dump\n");
/* VIA recommends this, sorry no known info. */
diff --git a/src/southbridge/via/k8t890/ctrl.c b/src/southbridge/via/k8t890/ctrl.c
index a918f01..782c547 100644
--- a/src/southbridge/via/k8t890/ctrl.c
+++ b/src/southbridge/via/k8t890/ctrl.c
@@ -152,7 +152,7 @@ static void vt8237r_vlink_init(struct device *dev)
static void ctrl_init(struct device *dev)
{
- print_debug("K8x8xx: Initializing V-Link to VT8237R sb: ");
+ printk(BIOS_DEBUG, "K8x8xx: Initializing V-Link to VT8237R sb: ");
/* TODO: Fix some ordering issue for V-link set Rx77[6] and PCI1_Rx4F[0]
should to 1 */
@@ -172,11 +172,11 @@ static void ctrl_init(struct device *dev)
vt8237r_vlink_init(dev);
k8x8xx_vt8237r_cfg(dev, devsb);
} else {
- print_debug("VT8237R LPC not found !\n");
+ printk(BIOS_DEBUG, "VT8237R LPC not found !\n");
return;
}
- print_debug(" Done\n");
- print_debug(" VIA_X_7 device dump:\n");
+ printk(BIOS_DEBUG, " Done\n");
+ printk(BIOS_DEBUG, " VIA_X_7 device dump:\n");
dump_south(dev);
}
diff --git a/src/southbridge/via/k8t890/dram.c b/src/southbridge/via/k8t890/dram.c
index 07a34b7..04184b7 100644
--- a/src/southbridge/via/k8t890/dram.c
+++ b/src/southbridge/via/k8t890/dram.c
@@ -66,7 +66,7 @@ static void dram_enable(struct device *dev)
/* The Address Next to the Last Valid DRAM Address */
pci_write_config16(dev, 0x88, reg | mregs.shadow_mem_ctrl);
- print_debug(" VIA_X_3 device dump:\n");
+ printk(BIOS_DEBUG, " VIA_X_3 device dump:\n");
dump_south(dev);
}
diff --git a/src/southbridge/via/k8t890/early_car.c b/src/southbridge/via/k8t890/early_car.c
index d7049ae..7eba967 100644
--- a/src/southbridge/via/k8t890/early_car.c
+++ b/src/southbridge/via/k8t890/early_car.c
@@ -80,23 +80,23 @@ u8 k8t890_early_setup_ht(void)
}
#if CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M800
- print_debug("K8M800 found at LDT ");
+ printk(BIOS_DEBUG, "K8M800 found at LDT ");
#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800
- print_debug("K8T800 found at LDT ");
+ printk(BIOS_DEBUG, "K8T800 found at LDT ");
#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800_OLD
- print_debug("K8T800_OLD found at LDT ");
+ printk(BIOS_DEBUG, "K8T800_OLD found at LDT ");
pci_write_config8(PCI_DEV(0, 0x0, 0), 0x64, 0x00);
pci_write_config8(PCI_DEV(0, 0x0, 0), 0xdd, 0x50);
#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T800PRO
- print_debug("K8T800 Pro found at LDT ");
+ printk(BIOS_DEBUG, "K8T800 Pro found at LDT ");
#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8M890
- print_debug("K8M890 found at LDT ");
+ printk(BIOS_DEBUG, "K8M890 found at LDT ");
/* K8M890 fix HT delay */
pci_write_config8(PCI_DEV(0, 0x0, 2), 0xab, 0x22);
#elif CONFIG_SOUTHBRIDGE_VIA_SUBTYPE_K8T890
- print_debug("K8T890 found at LDT ");
+ printk(BIOS_DEBUG, "K8T890 found at LDT ");
#endif
- print_debug_hex8(ldtnr);
+ printk(BIOS_DEBUG, "%02x", ldtnr);
/* get the maximum widths for both sides */
cldtwidth_in = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr]) & 0x7;
@@ -105,8 +105,7 @@ u8 k8t890_early_setup_ht(void)
vldtwidth_out = (pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x6) >> 4) & 0x7;
width = MIN(MIN(MIN(cldtwidth_out, cldtwidth_in), vldtwidth_out), vldtwidth_in);
- print_debug(" Agreed on width: ");
- print_debug_hex8(width);
+ printk(BIOS_DEBUG, " Agreed on width: %02x", width);
awidth = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0x7);
@@ -117,12 +116,10 @@ u8 k8t890_early_setup_ht(void)
/* Get programmed HT freq at base 0x89 */
cldtfreq = pci_read_config8(PCI_DEV(0, 0x18, 0), ldtreg[ldtnr] + 3) & 0xf;
- print_debug(" CPU programmed to HT freq: ");
- print_debug_hex8(cldtfreq);
+ printk(BIOS_DEBUG, " CPU programmed to HT freq: %02x", cldtfreq);
- print_debug(" VIA HT caps: ");
vldtcaps = pci_read_config16(PCI_DEV(0, 0, 0), K8X8XX_HT_CFG_BASE + 0xe);
- print_debug_hex16(vldtcaps);
+ printk(BIOS_DEBUG, " VIA HT caps: %04x", vldtcaps);
if (!(vldtcaps & (1 << cldtfreq ))) {
die("Chipset does not support desired HT frequency\n");
@@ -130,7 +127,7 @@ u8 k8t890_early_setup_ht(void)
afreq = pci_read_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd);
pci_write_config8(PCI_DEV(0, 0x0, 0), K8X8XX_HT_CFG_BASE + 0xd, cldtfreq);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
/* no reset needed */
if ((width == awidth) && (afreq == cldtfreq)) {
diff --git a/src/southbridge/via/k8t890/error.c b/src/southbridge/via/k8t890/error.c
index 0870288..2c1b5b6 100644
--- a/src/southbridge/via/k8t890/error.c
+++ b/src/southbridge/via/k8t890/error.c
@@ -26,7 +26,7 @@
static void error_enable(struct device *dev)
{
- print_debug(" K8x8xx: Enabling NB error reporting: ");
+ printk(BIOS_DEBUG, " K8x8xx: Enabling NB error reporting: ");
/*
* bit0 - Enable V-link parity error reporting in 0x50 bit0 (RWC)
* bit6 - Parity Error/SERR# Report Through V-Link to SB
@@ -34,10 +34,10 @@ static void error_enable(struct device *dev)
*/
pci_write_config8(dev, 0x58, 0x81);
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* TODO: enable AGP errors reporting on K8M890 */
- print_debug(" VIA_X_1 device dump:\n");
+ printk(BIOS_DEBUG, " VIA_X_1 device dump:\n");
dump_south(dev);
}
diff --git a/src/southbridge/via/k8t890/host.c b/src/southbridge/via/k8t890/host.c
index aa1b748..878ee9a 100644
--- a/src/southbridge/via/k8t890/host.c
+++ b/src/southbridge/via/k8t890/host.c
@@ -60,7 +60,7 @@ static void host_enable(struct device *dev)
/* Multiple function control */
pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01);
- print_debug(" VIA_X_0 device dump:\n");
+ printk(BIOS_DEBUG, " VIA_X_0 device dump:\n");
dump_south(dev);
}
diff --git a/src/southbridge/via/k8t890/host_ctrl.c b/src/southbridge/via/k8t890/host_ctrl.c
index 74351bc..2f4bca7 100644
--- a/src/southbridge/via/k8t890/host_ctrl.c
+++ b/src/southbridge/via/k8t890/host_ctrl.c
@@ -84,7 +84,7 @@ static void host_ctrl_enable_k8t8xx(struct device *dev)
writeback(dev, 0xc4, 0x50);
writeback(dev, 0xc5, 0x50);
- print_debug(" VIA_X_2 device dump:\n");
+ printk(BIOS_DEBUG, " VIA_X_2 device dump:\n");
dump_south(dev);
}
diff --git a/src/southbridge/via/vt8237r/ctrl.c b/src/southbridge/via/vt8237r/ctrl.c
index 3d856a8..f951afa 100644
--- a/src/southbridge/via/vt8237r/ctrl.c
+++ b/src/southbridge/via/vt8237r/ctrl.c
@@ -130,7 +130,7 @@ static void vt8237s_vlink_init(struct device *dev)
/* No pairing NB was found. */
if (!devfun7)
{
- print_debug("vt8237s_vlink_init: No pairing NB was found.\n");
+ printk(BIOS_DEBUG, "vt8237s_vlink_init: No pairing NB was found.\n");
return;
}
@@ -205,7 +205,7 @@ static void vt8237a_vlink_init(struct device *dev)
/* No pairing NB was found. */
if (!devfun7)
{
- print_debug("vt8237a_vlink_init: No pairing NB was found.\n");
+ printk(BIOS_DEBUG, "vt8237a_vlink_init: No pairing NB was found.\n");
return;
}
diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c
index 747dc5c..bb06322 100644
--- a/src/southbridge/via/vt8237r/early_smbus.c
+++ b/src/southbridge/via/vt8237r/early_smbus.c
@@ -42,17 +42,17 @@ static void smbus_print_error(u8 host_status, int loops)
return;
if (loops >= SMBUS_TIMEOUT)
- print_err("SMBus timeout\n");
+ printk(BIOS_ERR, "SMBus timeout\n");
if (host_status & (1 << 4))
- print_err("Interrupt/SMI# was Failed Bus Transaction\n");
+ printk(BIOS_ERR, "Interrupt/SMI# was Failed Bus Transaction\n");
if (host_status & (1 << 3))
- print_err("Bus error\n");
+ printk(BIOS_ERR, "Bus error\n");
if (host_status & (1 << 2))
- print_err("Device error\n");
+ printk(BIOS_ERR, "Device error\n");
if (host_status & (1 << 1))
- print_debug("Interrupt/SMI# completed successfully\n");
+ printk(BIOS_DEBUG, "Interrupt/SMI# completed successfully\n");
if (host_status & (1 << 0))
- print_err("Host busy\n");
+ printk(BIOS_ERR, "Host busy\n");
}
/**
@@ -229,7 +229,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
ram_slots = ARRAY_SIZE(ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\n");
+ printk(BIOS_ERR, "smbus_fixup() thinks there are no RAM slots!\n");
return;
}
@@ -253,7 +253,7 @@ void smbus_fixup(const struct mem_controller *ctrl)
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\n");
+ printk(BIOS_ERR, "SMBus timed out while warming up\n");
else
PRINT_DEBUG("Done\n");
}
@@ -336,7 +336,7 @@ int acpi_is_wakeup_early(void)
device_t dev;
u16 tmp;
- print_debug("IN TEST WAKEUP\n");
+ printk(BIOS_DEBUG, "IN TEST WAKEUP\n");
/* Power management controller */
dev = get_vt8237_lpc();
@@ -351,7 +351,7 @@ int acpi_is_wakeup_early(void)
tmp = inw(VT8237R_ACPI_IO_BASE + 0x04);
- print_debug_hex8(tmp);
+ printk(BIOS_DEBUG, "%02x", tmp);
return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ;
}
#endif
@@ -426,7 +426,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_8233_7), 0);
if (dev == PCI_DEV_INVALID) {
- print_err("Network is disabled, please enable\n");
+ printk(BIOS_ERR, "Network is disabled, please enable\n");
return 0;
}
@@ -441,7 +441,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom)
return 0;
if (rom == NULL) {
- print_err("No config data specified, using default MAC!\n");
+ printk(BIOS_ERR, "No config data specified, using default MAC!\n");
n.mac_address[0] = 0x0;
n.mac_address[1] = 0x0;
n.mac_address[2] = 0xde;
@@ -503,7 +503,7 @@ int vt8237_early_network_init(struct vt8237_network_rom *rom)
}
if (loops >= LAN_TIMEOUT) {
- print_err("Timeout - LAN controller didn't accept config\n");
+ printk(BIOS_ERR, "Timeout - LAN controller didn't accept config\n");
return 0;
}
diff --git a/src/southbridge/via/vt8237r/vt8237r.c b/src/southbridge/via/vt8237r/vt8237r.c
index 5f2449a..d392512 100644
--- a/src/southbridge/via/vt8237r/vt8237r.c
+++ b/src/southbridge/via/vt8237r/vt8237r.c
@@ -37,13 +37,9 @@ void writeback(struct device *dev, u16 where, u8 what)
pci_write_config8(dev, where, what);
regval = pci_read_config8(dev, where);
- if (regval != what) {
- print_debug("Writeback to ");
- print_debug_hex8(where);
- print_debug(" failed ");
- print_debug_hex8(regval);
- print_debug("\n");
- }
+ if (regval != what)
+ printk(BIOS_DEBUG, "Writeback to %02x failed %02x\n",
+ where, regval);
}
#else
void writeback(struct device *dev, u16 where, u8 what)
diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h
index ee5cc82..8c7ae45 100644
--- a/src/southbridge/via/vt8237r/vt8237r.h
+++ b/src/southbridge/via/vt8237r/vt8237r.h
@@ -94,8 +94,8 @@
#define CLOCK_SLAVE_ADDRESS 0x69
#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
+#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
#else
#define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX16(x)
1
0
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7883
-gerrit
commit 39baecbebbc6f7306c944782dfdee86c9938890b
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Fri Dec 19 13:45:24 2014 -0800
Drop VIA VT8235 southbridge
It's unused.
Change-Id: Iad3e7aa0f777392c9d65b9fcdd3c1666af31723a
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/mainboard/via/epia-cn/romstage.c | 4 +-
src/southbridge/via/Kconfig | 1 -
src/southbridge/via/Makefile.inc | 1 -
src/southbridge/via/vt8235/Kconfig | 22 ---
src/southbridge/via/vt8235/Makefile.inc | 24 ---
src/southbridge/via/vt8235/chip.h | 19 ---
src/southbridge/via/vt8235/early_serial.c | 77 ---------
src/southbridge/via/vt8235/early_smbus.c | 247 ---------------------------
src/southbridge/via/vt8235/ide.c | 113 -------------
src/southbridge/via/vt8235/lpc.c | 261 -----------------------------
src/southbridge/via/vt8235/nic.c | 36 ----
src/southbridge/via/vt8235/usb.c | 43 -----
src/southbridge/via/vt8235/vt8235.c | 89 ----------
src/southbridge/via/vt8237r/early_serial.c | 77 +++++++++
14 files changed, 79 insertions(+), 935 deletions(-)
diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c
index 8a0d384..8422ec0 100644
--- a/src/mainboard/via/epia-cn/romstage.c
+++ b/src/mainboard/via/epia-cn/romstage.c
@@ -31,7 +31,7 @@
#include "drivers/pc80/udelay_io.c"
#include "lib/delay.c"
#include "southbridge/via/vt8237r/early_smbus.c"
-#include "southbridge/via/vt8235/early_serial.c"
+#include "southbridge/via/vt8237r/early_serial.c"
#include <spd.h>
static inline int spd_read_byte(unsigned device, unsigned address)
@@ -84,7 +84,7 @@ void main(unsigned long bist)
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
- enable_vt8235_serial();
+ enable_vt8237r_serial();
console_init();
enable_smbus();
smbus_fixup(&ctrl);
diff --git a/src/southbridge/via/Kconfig b/src/southbridge/via/Kconfig
index 641c2a4..75a1395 100644
--- a/src/southbridge/via/Kconfig
+++ b/src/southbridge/via/Kconfig
@@ -1,3 +1,2 @@
source src/southbridge/via/k8t890/Kconfig
-source src/southbridge/via/vt8235/Kconfig
source src/southbridge/via/vt8237r/Kconfig
diff --git a/src/southbridge/via/Makefile.inc b/src/southbridge/via/Makefile.inc
index 1c239b1..db19438 100644
--- a/src/southbridge/via/Makefile.inc
+++ b/src/southbridge/via/Makefile.inc
@@ -1,3 +1,2 @@
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890
-subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8235) += vt8235
subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r
diff --git a/src/southbridge/via/vt8235/Kconfig b/src/southbridge/via/vt8235/Kconfig
deleted file mode 100644
index 1591274..0000000
--- a/src/southbridge/via/vt8235/Kconfig
+++ /dev/null
@@ -1,22 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2008-2009 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-config SOUTHBRIDGE_VIA_VT8235
- bool
-
diff --git a/src/southbridge/via/vt8235/Makefile.inc b/src/southbridge/via/vt8235/Makefile.inc
deleted file mode 100644
index 5c1068e..0000000
--- a/src/southbridge/via/vt8235/Makefile.inc
+++ /dev/null
@@ -1,24 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007, 2009 Rudolf Marek <r.marek(a)assembler.cz>
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-## GNU General Public License for more details.
-##
-## You should have received a copy of the GNU General Public License
-## along with this program; if not, write to the Free Software
-## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
-##
-
-ramstage-y += vt8235.c
-ramstage-y += ide.c
-ramstage-y += lpc.c
-ramstage-y += nic.c
-ramstage-y += usb.c
diff --git a/src/southbridge/via/vt8235/chip.h b/src/southbridge/via/vt8235/chip.h
deleted file mode 100644
index eb1e82b..0000000
--- a/src/southbridge/via/vt8235/chip.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _SOUTHBRIDGE_VIA_VT8235
-#define _SOUTHBRIDGE_VIA_VT8235
-
-struct southbridge_via_vt8235_config {
- /* PCI function enables */
- /* i.e. so that pci scan bus will find them. */
- /* I am putting in IDE as an example but obviously this needs
- * to be more complete!
- */
- int enable_ide;
- /* enables of functions of devices */
- int enable_usb;
- int enable_native_ide;
- int enable_com_ports;
- int enable_keyboard;
- int enable_nvram;
-};
-
-#endif /* _SOUTHBRIDGE_VIA_VT8235 */
diff --git a/src/southbridge/via/vt8235/early_serial.c b/src/southbridge/via/vt8235/early_serial.c
deleted file mode 100644
index b9bec5f..0000000
--- a/src/southbridge/via/vt8235/early_serial.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Enable the serial devices on the VIA
- */
-
-
-/* The base address is 0x15c, 0x2e, depending on config bytes */
-
-#define SIO_BASE 0x3f0
-#define SIO_DATA SIO_BASE+1
-
-static void vt8235_writepnpaddr(uint8_t val)
-{
- outb(val, 0x2e);
- outb(val, 0xeb);
-}
-
-static void vt8235_writepnpdata(uint8_t val)
-{
- outb(val, 0x2f);
- outb(val, 0xeb);
-}
-
-
-static void vt8235_writesiobyte(uint16_t reg, uint8_t val)
-{
- outb(val, reg);
-}
-
-static void vt8235_writesioword(uint16_t reg, uint16_t val)
-{
- outw(val, reg);
-}
-
-
-/* regs we use: 85, and the southbridge devfn is defined by the
- mainboard
- */
-
-static void enable_vt8235_serial(void)
-{
- // turn on pnp
- vt8235_writepnpaddr(0x87);
- vt8235_writepnpaddr(0x87);
- // now go ahead and set up com1.
- // set address
- vt8235_writepnpaddr(0x7);
- vt8235_writepnpdata(0x2);
- // enable serial out
- vt8235_writepnpaddr(0x30);
- vt8235_writepnpdata(0x1);
- // serial port 1 base address (FEh)
- vt8235_writepnpaddr(0x60);
- vt8235_writepnpdata(0xfe);
- // serial port 1 IRQ (04h)
- vt8235_writepnpaddr(0x70);
- vt8235_writepnpdata(0x4);
- // serial port 1 control
- vt8235_writepnpaddr(0xf0);
- vt8235_writepnpdata(0x2);
- // turn of pnp
- vt8235_writepnpaddr(0xaa);
-
- // set up reg to set baud rate.
- vt8235_writesiobyte(0x3fb, 0x80);
- // Set 115 kb
- vt8235_writesioword(0x3f8, 1);
- // Set 9.6 kb
- // WRITESIOWORD(0x3f8, 12)
- // now set no parity, one stop, 8 bits
- vt8235_writesiobyte(0x3fb, 3);
- // now turn on RTS, DRT
- vt8235_writesiobyte(0x3fc, 3);
- // Enable interrupts
- vt8235_writesiobyte(0x3f9, 0xf);
- // should be done. Dump a char for fun.
- vt8235_writesiobyte(0x3f8, 48);
-}
diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c
deleted file mode 100644
index c4bca9c..0000000
--- a/src/southbridge/via/vt8235/early_smbus.c
+++ /dev/null
@@ -1,247 +0,0 @@
-#define SMBUS_IO_BASE 0xf00
-
-#define SMBHSTSTAT 0x0
-#define SMBSLVSTAT 0x1
-#define SMBHSTCTL 0x2
-#define SMBHSTCMD 0x3
-#define SMBXMITADD 0x4
-#define SMBHSTDAT0 0x5
-#define SMBHSTDAT1 0x6
-#define SMBBLKDAT 0x7
-#define SMBSLVCTL 0x8
-#define SMBTRNSADD 0x9
-#define SMBSLVDATA 0xa
-#define SMLINK_PIN_CTL 0xe
-#define SMBUS_PIN_CTL 0xf
-
-/* Define register settings */
-#define HOST_RESET 0xff
-#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
-
-
-#define SMBUS_TIMEOUT (100*1000*10)
-
-#define I2C_TRANS_CMD 0x40
-#define CLOCK_SLAVE_ADDRESS 0x69
-
-static void enable_smbus(void)
-{
- device_t dev;
- unsigned char c;
- int i;
-
- /* Power management controller */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_8235), 0);
-
- if (dev == PCI_DEV_INVALID) {
- die("SMBUS controller not found\n");
- }
-
- // set IO base address to SMBUS_IO_BASE
- pci_write_config16(dev, 0xd0, SMBUS_IO_BASE | 1);
-
- // Enable SMBus
- pci_write_config8(dev, 0xd2, (0x4 << 1) | 1);
-
- /* make it work for I/O ...
- */
- pci_write_config16(dev, 4, 1);
-
- /* FIX for half baud rate problem */
- /* let clocks and the like settle */
- /* as yet arbitrary count - 1000 is too little 5000 works */
- for(i = 0 ; i < 5000 ; i++)
- outb(0x80,0x80);
-
- /*
- * The VT1211 serial port needs 48 mhz clock, on power up it is getting
- * only 24 mhz, there is some mysterious device on the smbus that can
- * fix this...this code below does it.
- * */
- outb(0xff, SMBUS_IO_BASE+SMBHSTSTAT);
- outb(0x7f, SMBUS_IO_BASE+SMBHSTDAT0);
- outb(0x83, SMBUS_IO_BASE+SMBHSTCMD);
- outb(CLOCK_SLAVE_ADDRESS<<1 , SMBUS_IO_BASE+SMBXMITADD);
- outb(8 | I2C_TRANS_CMD, SMBUS_IO_BASE+SMBHSTCTL);
-
- for (;;) {
- c = inb(SMBUS_IO_BASE+SMBHSTSTAT);
- if ((c & 1) == 0)
- break;
- }
-}
-
-
-static inline void smbus_delay(void)
-{
- outb(0x80, 0x80);
-}
-
-static int smbus_wait_until_ready(void)
-{
- unsigned char c;
- unsigned long loops;
- loops = SMBUS_TIMEOUT;
- do {
- smbus_delay();
- c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
- while((c & 1) == 1) {
- print_debug("c is ");
- print_debug_hex8(c);
- print_debug("\n");
- c = inb(SMBUS_IO_BASE + SMBHSTSTAT);
- /* nop */
- }
-
- } while(--loops);
- return loops?0:-1;
-}
-
-void smbus_reset(void)
-{
- outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
- outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
- outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
- outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT);
-
- smbus_wait_until_ready();
- print_debug("After reset status ");
- print_debug_hex8( inb(SMBUS_IO_BASE + SMBHSTSTAT));
- print_debug("\n");
-}
-
-
-
-static int smbus_wait_until_done(void)
-{
- unsigned long loops;
- unsigned char byte;
- loops = SMBUS_TIMEOUT;
- do {
- smbus_delay();
-
- byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
- if (byte & 1)
- break;
-
- } while(--loops);
- return loops?0:-1;
-}
-
-static void smbus_print_error(unsigned char host_status_register)
-{
-
- print_err("smbus_error: ");
- print_err_hex8(host_status_register);
- print_err("\n");
- if (host_status_register & (1 << 4)) {
- print_err("Interrupt/SMI# was Failed Bus Transaction\n");
- }
- if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
- }
- if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
- }
- if (host_status_register & (1 << 1)) {
- print_err("Interrupt/SMI# was Successful Completion\n");
- }
- if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
- }
-}
-
-
-/* SMBus routines borrowed from VIA's Trident Driver */
-/* this works, so I am not going to touch it for now -- rgm */
-static unsigned char smbus_read_byte(unsigned char devAdr,
- unsigned char bIndex)
-{
- unsigned short i;
- unsigned char bData;
- unsigned char sts = 0;
-
- /* clear host status */
- outb(0xff, SMBUS_IO_BASE);
-
- /* check SMBUS ready */
- for ( i = 0; i < 0xFFFF; i++ )
- if ( (inb(SMBUS_IO_BASE) & 0x01) == 0 )
- break;
-
- /* set host command */
- outb(bIndex, SMBUS_IO_BASE+3);
-
- /* set slave address */
- outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4);
-
- /* start */
- outb(0x48, SMBUS_IO_BASE+2);
-
- /* SMBUS Wait Ready */
- for ( i = 0; i < 0xFFFF; i++ )
- if ( ((sts = (inb(SMBUS_IO_BASE) & 0x1f)) & 0x01) == 0 )
- break;
-
- if ((sts & ~3) != 0) {
- smbus_print_error(sts);
- return 0;
- }
- bData=inb(SMBUS_IO_BASE+5);
-
- return bData;
-
-}
-
-/* for reference, here is the fancier version which we will use at some
- * point
- */
-# if 0
-int smbus_read_byte(unsigned device, unsigned address, unsigned char *result)
-{
- unsigned char host_status_register;
- unsigned char byte;
-
- reset();
-
- smbus_wait_until_ready();
-
- /* setup transaction */
- /* disable interrupts */
- outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
- /* set the device I'm talking too */
- outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBXMITADD);
- /* set the command/address... */
- outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
- /* set up for a byte data read */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2),
- SMBUS_IO_BASE + SMBHSTCTL);
-
- /* clear any lingering errors, so the transaction will run */
- outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
-
- /* clear the data byte...*/
- outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
-
- /* start the command */
- outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40),
- SMBUS_IO_BASE + SMBHSTCTL);
-
- /* poll for transaction completion */
- smbus_wait_until_done();
-
- host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
-
- /* Ignore the In Use Status... */
- host_status_register &= ~(1 << 6);
-
- /* read results of transaction */
- byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
- smbus_print_error(byte);
-
- *result = byte;
- return host_status_register != 0x02;
-}
-
-#endif
diff --git a/src/southbridge/via/vt8235/ide.c b/src/southbridge/via/vt8235/ide.c
deleted file mode 100644
index 176e70f..0000000
--- a/src/southbridge/via/vt8235/ide.c
+++ /dev/null
@@ -1,113 +0,0 @@
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <console/console.h>
-#include "chip.h"
-
-static void ide_init(struct device *dev)
-{
- struct southbridge_via_vt8235_config *conf = dev->chip_info;
- unsigned char enables;
-
- printk(BIOS_INFO, "Enabling VIA IDE.\n");
-
- /*if (!conf->enable_native_ide) { */
- /*
- * Run the IDE controller in 'compatibility mode - i.e. don't
- * use PCI interrupts. Using PCI ints confuses linux for some
- * reason.
- */
- printk(BIOS_INFO, "%s: enabling compatibility IDE addresses\n",
- __func__);
- enables = pci_read_config8(dev, 0x42);
- printk(BIOS_DEBUG, "enables in reg 0x42 0x%x\n", enables);
- enables &= ~0xc0; // compatibility mode
- pci_write_config8(dev, 0x42, enables);
- enables = pci_read_config8(dev, 0x42);
- printk(BIOS_DEBUG, "enables in reg 0x42 read back as 0x%x\n",
- enables);
- /* } */
-
- enables = pci_read_config8(dev, 0x40);
- printk(BIOS_DEBUG, "enables in reg 0x40 0x%x\n", enables);
- enables |= 3;
- pci_write_config8(dev, 0x40, enables);
- enables = pci_read_config8(dev, 0x40);
- printk(BIOS_DEBUG, "enables in reg 0x40 read back as 0x%x\n", enables);
-
- // Enable prefetch buffers
- enables = pci_read_config8(dev, 0x41);
- enables |= 0xf0;
- pci_write_config8(dev, 0x41, enables);
-
- // Lower thresholds (cause award does it)
- enables = pci_read_config8(dev, 0x43);
- enables &= ~0x0f;
- enables |= 0x05;
- pci_write_config8(dev, 0x43, enables);
-
- // PIO read prefetch counter (cause award does it)
- pci_write_config8(dev, 0x44, 0x18);
-
- // Use memory read multiple
- pci_write_config8(dev, 0x45, 0x1c);
-
- // address decoding.
- // we want "flexible", i.e. 1f0-1f7 etc. or native PCI
- // kevinh(a)ispiri.com - the standard linux drivers seem ass slow when
- // used in native mode - I've changed back to classic
- enables = pci_read_config8(dev, 0x9);
- printk(BIOS_DEBUG, "enables in reg 0x9 0x%x\n", enables);
- // by the book, set the low-order nibble to 0xa.
- if (conf->enable_native_ide) {
- enables &= ~0xf;
- // cf/cg silicon needs an 'f' here.
- enables |= 0xf;
- } else {
- enables &= ~0x5;
- }
-
- pci_write_config8(dev, 0x9, enables);
- enables = pci_read_config8(dev, 0x9);
- printk(BIOS_DEBUG, "enables in reg 0x9 read back as 0x%x\n", enables);
-
- // standard bios sets master bit.
- enables = pci_read_config8(dev, 0x4);
- printk(BIOS_DEBUG, "command in reg 0x4 0x%x\n", enables);
- enables |= 7;
-
- // No need for stepping - kevinh(a)ispiri.com
- enables &= ~0x80;
-
- pci_write_config8(dev, 0x4, enables);
- enables = pci_read_config8(dev, 0x4);
- printk(BIOS_DEBUG, "command in reg 0x4 reads back as 0x%x\n", enables);
-
- if (!conf->enable_native_ide) {
- // Use compatibility mode - per award bios
- pci_write_config32(dev, 0x10, 0x0);
- pci_write_config32(dev, 0x14, 0x0);
- pci_write_config32(dev, 0x18, 0x0);
- pci_write_config32(dev, 0x1c, 0x0);
-
- // Force interrupts to use compat mode - just like Award bios
- pci_write_config8(dev, 0x3d, 0x0);
- pci_write_config8(dev, 0x3c, 0xff);
- }
-}
-
-static struct device_operations ide_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = ide_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &ide_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_82C586_1,
-};
diff --git a/src/southbridge/via/vt8235/lpc.c b/src/southbridge/via/vt8235/lpc.c
deleted file mode 100644
index e6aac65..0000000
--- a/src/southbridge/via/vt8235/lpc.c
+++ /dev/null
@@ -1,261 +0,0 @@
-#include <arch/io.h>
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/ioapic.h>
-#include "chip.h"
-
-/* The epia-m is really short on interrupts available, so PCI interrupts A & D are ganged together and so are B & C.
- This is how the Award bios sets it up too.
- epia can be more generous as it does not need to reserve interrupts for cardbus devices, but if changed then
- make sure that ACPI dsdt is changed to suit.
-
- IRQ 0 = timer
- IRQ 1 = keyboard
- IRQ 2 = cascade
- IRQ 3 = COM 2
- IRQ 4 = COM 1
- IRQ 5 = available for PCI interrupts
- IRQ 6 = floppy or available for PCI if floppy controller disabled
- IRQ 7 = LPT or available if LPT port disabled
- IRQ 8 = rtc
- IRQ 9 = available for PCI interrupts
- IRQ 10 = cardbus slot or available for PCI if no cardbus (ie epia)
- IRQ 11 = cardbus slot or available for PCI if no cardbus (ie epia)
- IRQ 12 = PS2 mouse (hardwired to 12)
- IRQ 13 = legacy FPU interrupt
- IRQ 14 = IDE controller 1
- IRQ 15 = IDE controller 2
-
-*/
-static const unsigned char pciIrqs[4] = { 5 , 9 , 9, 5 };
-
-static const unsigned char usbPins[4] = { 'A','B','C','D'};
-static const unsigned char enetPins[4] = { 'A','B','C','D'};
-static const unsigned char slotPins[4] = { 'B','C','D','A'};
-static const unsigned char firewirePins[4] = { 'B','C','D','A'};
-static const unsigned char vt8235Pins[4] = { 'A','B','C','D'};
-static const unsigned char vgaPins[4] = { 'A','B','C','D'};
-static const unsigned char cbPins[4] = { 'A','B','C','D'};
-static const unsigned char riserPins[4] = { 'A','B','C','D'};
-
-
-static unsigned char *pin_to_irq(const unsigned char *pin)
-{
- static unsigned char Irqs[4];
- int i;
- for (i = 0 ; i < 4 ; i++)
- Irqs[i] = pciIrqs[ pin[i] - 'A' ];
-
- return Irqs;
-}
-
-static void pci_routing_fixup(struct device *dev)
-{
- printk(BIOS_INFO, "%s: dev is %p\n", __func__, dev);
-
- /* set up PCI IRQ routing */
- pci_write_config8(dev, 0x55, pciIrqs[0] << 4);
- pci_write_config8(dev, 0x56, pciIrqs[1] | (pciIrqs[2] << 4) );
- pci_write_config8(dev, 0x57, pciIrqs[3] << 4);
-
-
- // firewire built into southbridge
- printk(BIOS_INFO, "setting firewire\n");
- pci_assign_irqs(0, 0x0d, pin_to_irq(firewirePins));
-
- // Standard usb components
- printk(BIOS_INFO, "setting usb\n");
- pci_assign_irqs(0, 0x10, pin_to_irq(usbPins));
-
- // VT8235 + sound hardware
- printk(BIOS_INFO, "setting vt8235\n");
- pci_assign_irqs(0, 0x11, pin_to_irq(vt8235Pins));
-
- // Ethernet built into southbridge
- printk(BIOS_INFO, "setting ethernet\n");
- pci_assign_irqs(0, 0x12, pin_to_irq(enetPins));
-
- // VGA
- printk(BIOS_INFO, "setting vga\n");
- pci_assign_irqs(1, 0x00, pin_to_irq(vgaPins));
-
- // PCI slot
- printk(BIOS_INFO, "setting pci slot\n");
- pci_assign_irqs(0, 0x14, pin_to_irq(slotPins));
-
- // Cardbus slot
- printk(BIOS_INFO, "setting cardbus slot\n");
- pci_assign_irqs(0, 0x0a, pin_to_irq(cbPins));
-
- // Via 2 slot riser card 2nd slot
- printk(BIOS_INFO, "setting riser slot\n");
- pci_assign_irqs(0, 0x13, pin_to_irq(riserPins));
-
- printk(BIOS_SPEW, "%s: DONE\n", __func__);
-}
-
-/*
- * Set up the power management capabilities directly into ACPI mode. This
- * avoids having to handle any System Management Interrupts (SMI's) which I
- * can't figure out how to do !!!!
- */
-
-static void setup_pm(device_t dev)
-{
- // Set gen config 0
- pci_write_config8(dev, 0x80, 0x20);
-
- // Set ACPI base address to IO 0x400
- pci_write_config16(dev, 0x88, 0x0401);
-
- // set ACPI irq to 5
- pci_write_config8(dev, 0x82, 0x45);
-
- // primary interrupt channel
- pci_write_config16(dev, 0x84, 0x30f2);
-
- // throttle / stop clock control
- pci_write_config8(dev, 0x8d, 0x18);
-
- pci_write_config8(dev, 0x93, 0x88);
- pci_write_config8(dev, 0x94, 0xb0);
- pci_write_config8(dev, 0x95, 0xc0);
- pci_write_config8(dev, 0x98, 0);
- pci_write_config8(dev, 0x99, 0xea);
- pci_write_config8(dev, 0xe4, 0x14);
- pci_write_config8(dev, 0xe5, 0x08);
-
-
- // Enable ACPI access (and setup like award)
- pci_write_config8(dev, 0x81, 0x84);
-
- outw(0xffff, 0x400);
- outw(0xffff, 0x420);
- outw(0xffff, 0x428);
- outl(0xffffffff, 0x430);
-
- outw(0x0, 0x424);
- outw(0x0, 0x42a);
- outw(0x1, 0x42c);
- outl(0x0, 0x434);
- outl(0x01, 0x438);
- outb(0x0, 0x442);
- outl(0xffff7fff, 0x448);
- outw(0x001, 0x404);
-}
-
-static void vt8235_init(struct device *dev)
-{
- unsigned char enables;
-
- printk(BIOS_DEBUG, "vt8235 init\n");
-
- // enable the internal I/O decode
- enables = pci_read_config8(dev, 0x6C);
- enables |= 0x80;
- pci_write_config8(dev, 0x6C, enables);
-
- // Map 4MB of FLASH into the address space
- pci_write_config8(dev, 0x41, 0x7f);
-
- // Set bit 6 of 0x40, because Award does it (IO recovery time)
- // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI
- // interrupts can be properly marked as level triggered.
- enables = pci_read_config8(dev, 0x40);
- enables |= 0x45;
- pci_write_config8(dev, 0x40, enables);
-
- // Set 0x42 to 0xf0 to match Award bios
- enables = pci_read_config8(dev, 0x42);
- enables |= 0xf0;
- pci_write_config8(dev, 0x42, enables);
-
- /* Set 0x58 to 0x03 to match Award */
- pci_write_config8(dev, 0x58, 0x03);
-
- /* Set bit 3 of 0x4f to match award (use INIT# as cpu reset) */
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
-
- // Set bit 3 of 0x4a, to match award (dummy pci request)
- enables = pci_read_config8(dev, 0x4a);
- enables |= 0x08;
- pci_write_config8(dev, 0x4a, enables);
-
- // Set bit 3 of 0x4f to match award (use INIT# as cpu reset)
- enables = pci_read_config8(dev, 0x4f);
- enables |= 0x08;
- pci_write_config8(dev, 0x4f, enables);
-
- // Set 0x58 to 0x03 to match Award
- pci_write_config8(dev, 0x58, 0x03);
-
-
- /* enable serial irq */
- pci_write_config8(dev, 0x52, 0x9);
-
- /* dma */
- pci_write_config8(dev, 0x53, 0x00);
-
- // Power management setup
- setup_pm(dev);
-
- /* set up isa bus -- i/o recovery time, rom write enable, extend-ale */
- pci_write_config8(dev, 0x40, 0x54);
-
- // Start the rtc
- cmos_init(0);
-}
-
-/* total kludge to get lxb to call our children's set/enable functions - these are not called unless this
- device has a resource to set - so set a dummy one */
-static void vt8235_read_resources(device_t dev)
-{
- struct resource *res;
-
- pci_dev_read_resources(dev);
-
- res = new_resource(dev, 1);
- res->base = 0x0UL;
- res->size = 0x1000UL;
- res->limit = 0xffffUL;
- res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-
- res = new_resource(dev, 3); /* IOAPIC */
- res->base = IO_APIC_ADDR;
- res->size = 0x00001000;
- res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
-}
-
-static void vt8235_set_resources(device_t dev)
-{
- //struct resource *resource;
- //resource = find_resource(dev,1);
- //resource->flags |= IORESOURCE_STORED;
- pci_dev_set_resources(dev);
-}
-
-static void southbridge_init(struct device *dev)
-{
- vt8235_init(dev);
- pci_routing_fixup(dev);
-}
-
-static struct device_operations vt8235_lpc_ops = {
- .read_resources = vt8235_read_resources,
- .set_resources = vt8235_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = southbridge_init,
- .scan_bus = scan_static_bus,
-};
-
-static const struct pci_driver lpc_driver __pci_driver = {
- .ops = &vt8235_lpc_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_8235,
-};
diff --git a/src/southbridge/via/vt8235/nic.c b/src/southbridge/via/vt8235/nic.c
deleted file mode 100644
index 71f169c..0000000
--- a/src/southbridge/via/vt8235/nic.c
+++ /dev/null
@@ -1,36 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-
-/*
- * Enable the ethernet device and turn off stepping (because it is integrated
- * inside the southbridge)
- */
-static void nic_init(struct device *dev)
-{
- uint8_t byte;
-
- printk(BIOS_DEBUG, "Configuring VIA Rhine LAN\n");
-
- /* We don't need stepping - though the device supports it */
- byte = pci_read_config8(dev, PCI_COMMAND);
- byte &= ~PCI_COMMAND_WAIT;
- pci_write_config8(dev, PCI_COMMAND, byte);
-}
-
-static struct device_operations nic_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = nic_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &nic_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_8233_7,
-};
diff --git a/src/southbridge/via/vt8235/usb.c b/src/southbridge/via/vt8235/usb.c
deleted file mode 100644
index d684968..0000000
--- a/src/southbridge/via/vt8235/usb.c
+++ /dev/null
@@ -1,43 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-
-/* really nothing to do here, both usb 1.1 & 2.0 are normal PCI devices and so get resources allocated
- properly. They are part of the southbridge and are enabled in the chip enable function for the southbridge */
-
-static void usb_init(struct device *dev)
-{
- printk(BIOS_DEBUG, "Configuring VIA USB 1.1\n");
-
- /* pci_write_config8(dev, 0x04, 0x07); */
-
- /*
- * To disable; though do we need to do this?
- pci_write_config8(dev1, 0x3c, 0x00);
- pci_write_config8(dev1, 0x04, 0x00);
-
- Also, on the root dev, for enable:
- regval = pci_read_config8(dev0, 0x50);
- regval &= ~(0x36);
- pci_write_config8(dev0, 0x50, regval);
-
- (regval |= 0x36; for disable)
- */
-}
-
-static struct device_operations usb_ops = {
- .read_resources = pci_dev_read_resources,
- .set_resources = pci_dev_set_resources,
- .enable_resources = pci_dev_enable_resources,
- .init = usb_init,
- .enable = 0,
- .ops_pci = 0,
-};
-
-static const struct pci_driver northbridge_driver __pci_driver = {
- .ops = &usb_ops,
- .vendor = PCI_VENDOR_ID_VIA,
- .device = PCI_DEVICE_ID_VIA_82C586_2,
-};
diff --git a/src/southbridge/via/vt8235/vt8235.c b/src/southbridge/via/vt8235/vt8235.c
deleted file mode 100644
index 0f37be2..0000000
--- a/src/southbridge/via/vt8235/vt8235.c
+++ /dev/null
@@ -1,89 +0,0 @@
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ops.h>
-#include <device/pci_ids.h>
-#include <pc80/keyboard.h>
-#include <pc80/i8259.h>
-#include "chip.h"
-
-static void keyboard_on(struct device *dev)
-{
- u8 regval;
-
- regval = pci_read_config8(dev, 0x51);
- regval |= 0x05;
- regval &= 0xfd;
- pci_write_config8(dev, 0x51, regval);
-
- pc_keyboard_init();
-}
-
-#ifdef UNUSED_CODE
-void dump_south(device_t dev0)
-{
- int i,j;
-
- for(i = 0; i < 256; i += 16) {
- printk(BIOS_DEBUG, "0x%x: ", i);
- for(j = 0; j < 16; j++) {
- printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev0, i+j));
- }
- printk(BIOS_DEBUG, "\n");
- }
-}
-
-void set_led(void)
-{
- // set power led to steady now that coreboot has virtually done its job
- device_t dev;
- dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0);
- pci_write_config8(dev, 0x94, 0xb0);
-}
-#endif
-
-static void vt8235_enable(struct device *dev)
-{
- u8 regval;
- u16 vendor,model;
-
- vendor = pci_read_config16(dev,0);
- model = pci_read_config16(dev,0x2);
-
- printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model);
-
- /* If this is not the southbridge itself just return.
- * This is necessary because USB devices are slot 10, whereas this
- * device is slot 11 therefore usb devices get called first during
- * the bus scan. We don't want to wait until we could do dev->init
- * because that's too late.
- */
-
- if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235))
- return;
-
- printk(BIOS_DEBUG, "Initialising Devices\n");
-
- /* make sure interrupt controller is configured before keyboard init */
- setup_i8259();
-
- /* enable RTC and ethernet */
- regval = pci_read_config8(dev, 0x51);
- regval |= 0x18;
- pci_write_config8(dev, 0x51, regval);
-
- /* turn on keyboard */
- keyboard_on(dev);
-
- /* enable USB 1.1 & USB 2.0 - redundant really since we've
- * already been there - see note above
- */
- regval = pci_read_config8(dev, 0x50);
- regval &= ~(0x36);
- pci_write_config8(dev, 0x50, regval);
-}
-
-struct chip_operations southbridge_via_vt8235_ops = {
- CHIP_NAME("VIA VT8235 Southbridge")
- .enable_dev = vt8235_enable,
-};
diff --git a/src/southbridge/via/vt8237r/early_serial.c b/src/southbridge/via/vt8237r/early_serial.c
new file mode 100644
index 0000000..9143f46
--- /dev/null
+++ b/src/southbridge/via/vt8237r/early_serial.c
@@ -0,0 +1,77 @@
+/*
+ * Enable the serial devices on the VIA
+ */
+
+
+/* The base address is 0x15c, 0x2e, depending on config bytes */
+
+#define SIO_BASE 0x3f0
+#define SIO_DATA SIO_BASE+1
+
+static void vt8237r_writepnpaddr(uint8_t val)
+{
+ outb(val, 0x2e);
+ outb(val, 0xeb);
+}
+
+static void vt8237r_writepnpdata(uint8_t val)
+{
+ outb(val, 0x2f);
+ outb(val, 0xeb);
+}
+
+
+static void vt8237r_writesiobyte(uint16_t reg, uint8_t val)
+{
+ outb(val, reg);
+}
+
+static void vt8237r_writesioword(uint16_t reg, uint16_t val)
+{
+ outw(val, reg);
+}
+
+
+/* regs we use: 85, and the southbridge devfn is defined by the
+ mainboard
+ */
+
+static void enable_vt8237r_serial(void)
+{
+ // turn on pnp
+ vt8237r_writepnpaddr(0x87);
+ vt8237r_writepnpaddr(0x87);
+ // now go ahead and set up com1.
+ // set address
+ vt8237r_writepnpaddr(0x7);
+ vt8237r_writepnpdata(0x2);
+ // enable serial out
+ vt8237r_writepnpaddr(0x30);
+ vt8237r_writepnpdata(0x1);
+ // serial port 1 base address (FEh)
+ vt8237r_writepnpaddr(0x60);
+ vt8237r_writepnpdata(0xfe);
+ // serial port 1 IRQ (04h)
+ vt8237r_writepnpaddr(0x70);
+ vt8237r_writepnpdata(0x4);
+ // serial port 1 control
+ vt8237r_writepnpaddr(0xf0);
+ vt8237r_writepnpdata(0x2);
+ // turn of pnp
+ vt8237r_writepnpaddr(0xaa);
+
+ // set up reg to set baud rate.
+ vt8237r_writesiobyte(0x3fb, 0x80);
+ // Set 115 kb
+ vt8237r_writesioword(0x3f8, 1);
+ // Set 9.6 kb
+ // WRITESIOWORD(0x3f8, 12)
+ // now set no parity, one stop, 8 bits
+ vt8237r_writesiobyte(0x3fb, 3);
+ // now turn on RTS, DRT
+ vt8237r_writesiobyte(0x3fc, 3);
+ // Enable interrupts
+ vt8237r_writesiobyte(0x3f9, 0xf);
+ // should be done. Dump a char for fun.
+ vt8237r_writesiobyte(0x3f8, 48);
+}
1
0
Patch set updated for coreboot: 77f924f Move container_of() macro to stddef.h
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8109
-gerrit
commit 77f924f8239af067a40b43bdc7ab27abd0dbb904
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 11:09:11 2015 -0800
Move container_of() macro to stddef.h
It's not a SPI related macro, hence move it to stddef.h where
other similar macros live.
Change-Id: I1008894af7a272f1bc36d3ae6cee3881132b6ba9
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/include/spi_flash.h | 11 -----------
src/include/stddef.h | 11 +++++++++++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 7cf0229..8b8b0c5 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -28,17 +28,6 @@
#include <console/console.h>
#include <spi-generic.h>
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @ptr: the pointer to the member.
- * @type: the type of the container struct this is embedded in.
- * @member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
struct spi_flash {
struct spi_slave *spi;
diff --git a/src/include/stddef.h b/src/include/stddef.h
index 137de04..2c41c5e 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -32,6 +32,17 @@ typedef unsigned int wint_t;
offsetof(struct structure, member) == offset, \
"`struct " #structure "` offset for `" #member "` is not " #offset )
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
#ifdef __PRE_RAM__
#define ROMSTAGE_CONST const
#else
1
0
Patch set updated for coreboot: 9b4af1d Drop duplicate API from spi_flash.h
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8108
-gerrit
commit 9b4af1d02d734203b5464dd1d78f350604788b3d
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 11:06:29 2015 -0800
Drop duplicate API from spi_flash.h
This convenience API was never used.
Change-Id: If2a99967e7f8c02e9029f7766aeef1e1a1f3dd16
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/include/spi_flash.h | 18 ------------------
1 file changed, 18 deletions(-)
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 70ca784..7cf0229 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -58,22 +58,4 @@ struct spi_flash {
struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs);
-static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
- size_t len, void *buf)
-{
- return flash->read(flash, offset, len, buf);
-}
-
-static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
- size_t len, const void *buf)
-{
- return flash->write(flash, offset, len, buf);
-}
-
-static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
- size_t len)
-{
- return flash->erase(flash, offset, len);
-}
-
#endif /* _SPI_FLASH_H_ */
1
0
Patch set updated for coreboot: e015bcf northbridge: Drop print_ implementation from non-romcc boards
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7856
-gerrit
commit e015bcf5389b7a0dea97d0d31e100bdb22179764
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 12:59:54 2015 -0800
northbridge: Drop print_ implementation from non-romcc boards
Because we have no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/northbridge/amd/amdfam10/amdfam10.h | 7 +-
src/northbridge/amd/amdfam10/debug.c | 26 ++--
src/northbridge/amd/amdfam10/raminit_amdmct.c | 6 +-
src/northbridge/amd/amdfam10/setup_resource_map.c | 20 +--
src/northbridge/amd/amdk8/coherent_ht.c | 32 ++--
src/northbridge/amd/amdk8/debug.c | 22 +--
src/northbridge/amd/amdk8/f.h | 7 +-
src/northbridge/amd/amdk8/incoherent_ht.c | 10 +-
src/northbridge/amd/amdk8/raminit_test.c | 29 +---
src/northbridge/amd/amdmct/mct/mct_d.c | 2 +-
src/northbridge/amd/amdmct/mct/mctdqs_d.c | 14 +-
src/northbridge/amd/amdmct/mct/mctsrc.c | 20 +--
src/northbridge/amd/amdmct/mct/mcttmrl.c | 7 +-
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 14 +-
src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 7 +-
src/northbridge/amd/gx2/raminit.c | 2 +-
src/northbridge/amd/lx/raminit.c | 30 ++--
src/northbridge/dmp/vortex86ex/raminit.c | 12 +-
src/northbridge/intel/e7501/debug.c | 135 +++-------------
src/northbridge/intel/e7501/raminit.c | 18 +--
src/northbridge/intel/e7505/debug.c | 135 +++-------------
src/northbridge/intel/e7505/raminit.c | 18 +--
src/northbridge/intel/i3100/raminit.c | 27 ++--
src/northbridge/intel/i3100/raminit_ep80579.c | 180 ++++++----------------
src/northbridge/intel/i440bx/debug.c | 26 +---
src/northbridge/intel/i440bx/raminit.c | 8 +-
src/northbridge/intel/i440lx/raminit.c | 8 +-
src/northbridge/intel/i82810/debug.c | 47 ++----
src/northbridge/intel/i855/debug.c | 66 +++-----
src/northbridge/intel/i855/raminit.c | 24 +--
src/northbridge/intel/i945/debug.c | 4 +-
src/northbridge/via/cn700/raminit.c | 8 +-
src/northbridge/via/cn700/vga.c | 2 +-
src/northbridge/via/cx700/early_smbus.c | 38 ++---
src/northbridge/via/cx700/raminit.c | 36 ++---
src/northbridge/via/vx800/early_smbus.c | 50 +++---
src/northbridge/via/vx800/raminit.c | 8 +-
src/northbridge/via/vx900/chrome9hd.c | 6 +-
src/northbridge/via/vx900/early_smbus.c | 6 +-
src/northbridge/via/vx900/early_vx900.c | 6 +-
src/northbridge/via/vx900/lpc.c | 2 +-
src/northbridge/via/vx900/northbridge.c | 12 +-
src/northbridge/via/vx900/pcie.c | 4 +-
src/northbridge/via/vx900/raminit_ddr3.c | 2 +-
src/northbridge/via/vx900/sata.c | 47 +++---
45 files changed, 387 insertions(+), 803 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/amdfam10.h b/src/northbridge/amd/amdfam10/amdfam10.h
index d292306..ab4b42e 100644
--- a/src/northbridge/amd/amdfam10/amdfam10.h
+++ b/src/northbridge/amd/amdfam10/amdfam10.h
@@ -1147,11 +1147,7 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
-#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-#endif
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
@@ -1164,11 +1160,10 @@ static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
}
if(needs_reset) {
+ printk(BIOS_DEBUG, "mem trained failed\n");
#ifdef __PRE_RAM__
- print_debug("mem trained failed\n");
soft_reset();
#else
- printk(BIOS_DEBUG, "mem trained failed\n");
hard_reset();
#endif
}
diff --git a/src/northbridge/amd/amdfam10/debug.c b/src/northbridge/amd/amdfam10/debug.c
index 7d00af7..d1fdaf8 100644
--- a/src/northbridge/amd/amdfam10/debug.c
+++ b/src/northbridge/amd/amdfam10/debug.c
@@ -108,7 +108,7 @@ static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size)
val >>= 8;
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static void dump_pci_device(u32 dev)
@@ -122,7 +122,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
int i;
int end = start + size;
print_debug_pci_dev(dev);
- print_debug(" -- index_reg="); print_debug_hex32(index_reg);
+ printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg);
for(i = start; i < end; i++) {
u32 val;
@@ -135,7 +135,7 @@ static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start,
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg)
@@ -151,7 +151,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
int i;
print_debug_pci_dev(dev);
- print_debug(" index reg: "); print_debug_hex16(index_reg); print_debug(" type: "); print_debug_hex8(type);
+ printk(BIOS_DEBUG, " index reg: %04x type: %02x", index_reg, type);
type<<=28;
@@ -163,7 +163,7 @@ static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 l
val = pci_read_config32_index(dev, index_reg, i|type);
printk(BIOS_DEBUG, " %08x", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
@@ -221,7 +221,7 @@ static inline void dump_pci_devices_on_bus(u32 busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
u32 device;
device = ctrl->spd_addr[i];
@@ -241,7 +241,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->spd_addr[i+DIMM_SOCKETS];
if (device) {
@@ -260,14 +260,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static void dump_smbus_registers(void)
{
u32 device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -285,7 +285,7 @@ static void dump_smbus_registers(void)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
@@ -303,7 +303,7 @@ static inline void dump_io_resources(u32 port)
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -312,12 +312,12 @@ static inline void dump_io_resources(u32 port)
static inline void dump_mem(u32 start, u32 end)
{
u32 i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c
index e5c18a8..6b02209 100644
--- a/src/northbridge/amd/amdfam10/raminit_amdmct.c
+++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c
@@ -219,7 +219,7 @@ u32 mctGetLogicalCPUID(u32 Node)
break;
default:
/* FIXME: mabe we should die() here. */
- print_err("FIXME! CPU Version unknown or not supported! \n");
+ printk(BIOS_ERR, "FIXME! CPU Version unknown or not supported! \n");
ret = 0;
}
@@ -237,9 +237,9 @@ static void raminit_amdmct(struct sys_info *sysinfo)
struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat);
struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA;
- print_debug("raminit_amdmct begin:\n");
+ printk(BIOS_DEBUG, "raminit_amdmct begin:\n");
mctAutoInitMCT_D(pMCTstat, pDCTstatA);
- print_debug("raminit_amdmct end:\n");
+ printk(BIOS_DEBUG, "raminit_amdmct end:\n");
}
diff --git a/src/northbridge/amd/amdfam10/setup_resource_map.c b/src/northbridge/amd/amdfam10/setup_resource_map.c
index 2eeca44..ca7f964 100644
--- a/src/northbridge/amd/amdfam10/setup_resource_map.c
+++ b/src/northbridge/amd/amdfam10/setup_resource_map.c
@@ -23,7 +23,7 @@
static void setup_resource_map(const u32 *register_values, u32 max)
{
u32 i;
-// print_debug("setting up resource map....");
+// printk(BIOS_DEBUG, "setting up resource map....");
for(i = 0; i < max; i += 3) {
device_t dev;
@@ -37,14 +37,14 @@ static void setup_resource_map(const u32 *register_values, u32 max)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
-// print_debug("done.\n");
+// printk(BIOS_DEBUG, "done.\n");
}
void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_pci_dev, u32 offset_io_base)
{
u32 i;
-// print_debug("setting up resource map offset....");
+// printk(BIOS_DEBUG, "setting up resource map offset....");
for(i = 0; i < max; i += 3) {
device_t dev;
u32 where;
@@ -56,7 +56,7 @@ void setup_resource_map_offset(const u32 *register_values, u32 max, u32 offset_p
reg |= register_values[i+2] + offset_io_base;
pci_write_config32(dev, where, reg);
}
-// print_debug("done.\n");
+// printk(BIOS_DEBUG, "done.\n");
}
#define RES_PCI_IO 0x10
@@ -69,12 +69,12 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
u32 i;
#if RES_DEBUG
- print_debug("setting up resource map ex offset....");
+ printk(BIOS_DEBUG, "setting up resource map ex offset....");
#endif
#if RES_DEBUG
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
@@ -127,7 +127,7 @@ void setup_resource_map_x_offset(const u32 *register_values, u32 max, u32 offset
}
#if RES_DEBUG
- print_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
@@ -136,11 +136,11 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
u32 i;
#if RES_DEBUG
- print_debug("setting up resource map ex offset....");
+ printk(BIOS_DEBUG, "setting up resource map ex offset....");
#endif
#if RES_DEBUG
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
#endif
for(i = 0; i < max; i += 4) {
#if RES_DEBUG
@@ -189,7 +189,7 @@ void setup_resource_map_x(const u32 *register_values, u32 max)
}
#if RES_DEBUG
- print_debug("done.\n");
+ printk(BIOS_DEBUG, "done.\n");
#endif
}
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 8abb31f..a8d8700 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -145,7 +145,7 @@ static void disable_probes(void)
u32 val;
- print_spew("Disabling read/write/fill probes for UP... ");
+ printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... ");
val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
@@ -153,7 +153,7 @@ static void disable_probes(void)
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
pci_write_config32(NODE_HT(0), HT_TRANSACTION_CONTROL, val);
- print_spew("done.\n");
+ printk(BIOS_SPEW, "done.\n");
}
@@ -199,14 +199,13 @@ static void enable_routing(u8 node)
*/
/* Enable routing table */
- print_spew("Enabling routing table for node ");
- print_spew_hex8(node);
+ printk(BIOS_SPEW, "Enabling routing table for node %d", node);
val=pci_read_config32(NODE_HT(node), 0x6c);
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
- print_spew(" done.\n");
+ printk(BIOS_SPEW, " done.\n");
}
#if CONFIG_MAX_PHYSICAL_CPUS > 1
@@ -230,7 +229,7 @@ static u8 link_to_register(int ldt)
if (ldt&0x02) return 0x00;
/* we should never get here */
- print_spew("Unknown Link\n");
+ printk(BIOS_SPEW, "Unknown Link\n");
return 0;
}
@@ -248,15 +247,14 @@ static void rename_temp_node(u8 node)
{
uint32_t val;
- print_spew("Renaming current temporary node to ");
- print_spew_hex8(node);
+ printk(BIOS_SPEW, "Renaming current temporary node to %d", node);
val=pci_read_config32(NODE_HT(7), 0x60);
val &= (~7); /* clear low bits. */
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
- print_spew(" done.\n");
+ printk(BIOS_SPEW, " done.\n");
}
static int verify_connection(u8 dest)
@@ -514,7 +512,7 @@ static void setup_remote_node(u8 node)
};
int i;
- print_spew("setup_remote_node: ");
+ printk(BIOS_SPEW, "setup_remote_node: ");
/* copy the default resource map from node 0 */
for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
@@ -525,7 +523,7 @@ static void setup_remote_node(u8 node)
pci_write_config32(NODE_MP(7), reg, value);
}
- print_spew("done\n");
+ printk(BIOS_SPEW, "done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1*/
@@ -664,7 +662,7 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
static void setup_uniprocessor(void)
{
- print_spew("Enabling UP settings\n");
+ printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
if (tmp>0) return;
@@ -1491,7 +1489,7 @@ static unsigned setup_smp(void)
{
unsigned nodes;
- print_spew("Enabling SMP settings\n");
+ printk(BIOS_SPEW, "Enabling SMP settings\n");
nodes = setup_smp2();
#if CONFIG_MAX_PHYSICAL_CPUS > 2
@@ -1528,14 +1526,14 @@ static unsigned verify_mp_capabilities(unsigned nodes)
#if CONFIG_MAX_PHYSICAL_CPUS > 2
case 0x02: /* MPCap */
if(nodes > 2) {
- print_err("Going back to DP\n");
+ printk(BIOS_ERR, "Going back to DP\n");
return 2;
}
break;
#endif
case 0x00: /* Non SMP */
if(nodes >1 ) {
- print_err("Going back to UP\n");
+ printk(BIOS_ERR, "Going back to UP\n");
return 1;
}
break;
@@ -1613,7 +1611,7 @@ static void coherent_ht_finalize(unsigned nodes)
* registers on Hammer A0 revision.
*/
- print_spew("coherent_ht_finalize\n");
+ printk(BIOS_SPEW, "coherent_ht_finalize\n");
#if !CONFIG_K8_REV_F_SUPPORT
rev_a0 = is_cpu_rev_a0();
#endif
@@ -1654,7 +1652,7 @@ static void coherent_ht_finalize(unsigned nodes)
#endif
}
- print_spew("done\n");
+ printk(BIOS_SPEW, "done\n");
}
static int apply_cpu_errata_fixes(unsigned nodes)
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 4f9d8ca..c1021e5 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -54,7 +54,7 @@ static void dump_pci_device(unsigned dev)
val = pci_read_config8(dev, i);
printk(BIOS_DEBUG, " %02x", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#if CONFIG_K8_REV_F_SUPPORT
@@ -63,7 +63,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
{
int i;
print_debug_pci_dev(dev);
- print_debug(" -- index_reg="); print_debug_hex32(index_reg);
+ printk(BIOS_DEBUG, " -- index_reg=%08x", index_reg);
for(i = 0; i < 0x40; i++) {
uint32_t val;
@@ -76,7 +76,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
}
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
@@ -135,7 +135,7 @@ static inline void dump_pci_devices_on_bus(unsigned busn)
static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
@@ -155,7 +155,7 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
@@ -174,14 +174,14 @@ static void dump_spd_registers(const struct mem_controller *ctrl)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
@@ -199,7 +199,7 @@ static void dump_smbus_registers(void)
byte = status & 0xff;
printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
@@ -218,7 +218,7 @@ static inline void dump_io_resources(unsigned port)
val = inb(port);
printk(BIOS_DEBUG, " %02x",val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -227,13 +227,13 @@ static inline void dump_io_resources(unsigned port)
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index bfeee0e..4f958c5 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -564,11 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __PRE_RAM__
- print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n");
-#else
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
-#endif
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
case 1: //trained
@@ -581,11 +577,10 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
}
}
if(needs_reset) {
+ printk(BIOS_DEBUG, "mem trained failed\n");
#ifdef __PRE_RAM__
- print_debug("mem trained failed\n");
soft_reset();
#else
- printk(BIOS_DEBUG, "mem trained failed\n");
hard_reset();
#endif
}
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index cf8ad52..3c6cf33 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -342,7 +342,7 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
pci_write_config16(udev, upos + LINK_CTRL(uoffs), ctrl);
ctrl = pci_read_config16(udev, upos + LINK_CTRL(uoffs));
if (ctrl & ((1 << 4) | (1 << 8))) {
- print_err("Detected error on Hypertransport Link\n");
+ printk(BIOS_ERR, "Detected error on Hypertransport Link\n");
break;
}
}
@@ -362,10 +362,10 @@ static int ht_setup_chainx(device_t udev, uint8_t upos, uint8_t bus, unsigned of
pos = ht_lookup_slave_capability(dev);
if (!pos) {
- print_err("udev="); print_err_hex32(udev);
- print_err("\tupos="); print_err_hex32(upos);
- print_err("\tuoffs="); print_err_hex32(uoffs);
- print_err("\tHT link capability not found\n");
+ printk(BIOS_ERR, "udev=%08x", udev);
+ printk(BIOS_ERR, "\tupos=%08x", upos);
+ printk(BIOS_ERR, "\tuoffs=%08x", uoffs);
+ printk(BIOS_ERR, "\tHT link capability not found\n");
break;
}
diff --git a/src/northbridge/amd/amdk8/raminit_test.c b/src/northbridge/amd/amdk8/raminit_test.c
index fd2107c..be46f27 100644
--- a/src/northbridge/amd/amdk8/raminit_test.c
+++ b/src/northbridge/amd/amdk8/raminit_test.c
@@ -57,11 +57,7 @@ static uint32_t pci_read_config32(device_t dev, unsigned where)
(pci_register[addr + 3] << 24);
#if 0
- print_debug("pcir32(");
- print_debug_hex32(addr);
- print_debug("):");
- print_debug_hex32(value);
- print_debug("\n");
+ printk(BIOS_DEBUG, "pcir32(%08x): %08x\n", addr, value);
#endif
return value;
@@ -92,11 +88,7 @@ static void pci_write_config32(device_t dev, unsigned where, uint32_t value)
pci_register[addr + 3] = (value >> 24) & 0xff;
#if 0
- print_debug("pciw32(");
- print_debug_hex32(addr);
- print_debug(", ");
- print_debug_hex32(value);
- print_debug(")\n");
+ printk(BIOS_DEBUG, "pciw32(%08x, %08x)\n", addr, value);
#endif
}
@@ -285,13 +277,8 @@ static int spd_read_byte(unsigned device, unsigned address)
}
}
#if 0
- print_debug("spd_read_byte(");
- print_debug_hex32(device);
- print_debug(", ");
- print_debug_hex32(address);
- print_debug(") -> ");
- print_debug_hex32(result);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd_read_byte(%08x, %08x) -> %08x\n",
+ device, address, result);
#endif
if (spd_count >= spd_fail_count) {
result = -1;
@@ -392,9 +379,7 @@ static void test1(void)
raminit_main();
#if 0
- print_debug("spd_count: ");
- print_debug_hex32(spd_count);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd_count: %d\n", spd_count);
#endif
}
@@ -410,9 +395,7 @@ static void do_test2(int i)
reset_tests();
spd_fail_count = i;
- print_debug("\nSPD will fail after: ");
- print_debug_hex32(spd_fail_count);
- print_debug(" accesses.\n");
+ printk(BIOS_DEBUG, "\nSPD will fail after: %d accesses.\n", %d);
memcpy(&spd_data[0*256], spd_micron_512MB_DDR333, 256);
memcpy(&spd_data[1*256], spd_micron_512MB_DDR333, 256);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 924c5fb..7c7550d 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -262,7 +262,7 @@ restartinit:
node_sys_base += (pDCTstat->NodeSysLimit + 2) & ~0x0F;
}
if (NodesWmem == 0) {
- print_debug("No Nodes?!\n");
+ printk(BIOS_DEBUG, "No Nodes?!\n");
goto fatalexit;
}
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 17fb289..d7fd738 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -357,22 +357,20 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
for (Dir = 0; Dir < 2; Dir++) {
if (Dir == 0) {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
} else {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
}
for (Channel = 0; Channel < 2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) {
- print_debug("\t\tReceiver:"); print_debug_hex8(Receiver);
+ printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir];
- print_debug(": ");
for (i=0;i<8; i++) {
val = p[i];
- print_debug_hex8(val);
- print_debug(" ");
+ printk(BIOS_DEBUG, "%02x ", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index feb4170..9c1324d 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -459,12 +459,9 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
- print_debug("TrainRcvrEn: CH_MaxRdLat:\n");
+ printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel);
- print_debug(": ");
- print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
- print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
#endif
@@ -476,20 +473,17 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
u8 i;
u8 *p;
- print_debug("TrainRcvrEn: CH_D_B_RCVRDLY:\n");
+ printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n");
for(Channel = 0; Channel < 2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
for(Receiver = 0; Receiver<8; Receiver+=2) {
- print_debug("\t\tReceiver:");
- print_debug_hex8(Receiver);
+ printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
- print_debug(": ");
for (i=0;i<8; i++) {
val = p[i];
- print_debug_hex8(val);
- print_debug(" ");
+ printk(BIOS_DEBUG, "%02x ", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index 03ebf97..d31e744 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -198,12 +198,9 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
- print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n");
+ printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel);
- print_debug(": ");
- print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
- print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
#endif
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index d7084ad..6a9b921 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -371,22 +371,20 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
for (Dir = 0; Dir < 2; Dir++) {
if (Dir == 1) {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS WR:\n");
} else {
- print_debug("TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
+ printk(BIOS_DEBUG, "TrainDQSRdWrPos: CH_D_DIR_B_DQS RD:\n");
}
for (Channel = 0; Channel < 2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel); print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) {
- print_debug("\t\tReceiver:"); print_debug_hex8(Receiver);
+ printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir];
- print_debug(": ");
for (i=0;i<8; i++) {
val = p[i];
- print_debug_hex8(val);
- print_debug(" ");
+ printk(BIOS_DEBUG, "%02x ", val);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
index c7e1352..ec8df9a 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -192,12 +192,9 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
#if DQS_TRAIN_DEBUG > 0
{
u8 Channel;
- print_debug("maxRdLatencyTrain: CH_MaxRdLat:\n");
+ printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
for(Channel = 0; Channel<2; Channel++) {
- print_debug("Channel:"); print_debug_hex8(Channel);
- print_debug(": ");
- print_debug_hex8( pDCTstat->CH_MaxRdLat[Channel] );
- print_debug("\n");
+ printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
#endif
diff --git a/src/northbridge/amd/gx2/raminit.c b/src/northbridge/amd/gx2/raminit.c
index d9af161..fd872b3 100644
--- a/src/northbridge/amd/gx2/raminit.c
+++ b/src/northbridge/amd/gx2/raminit.c
@@ -606,6 +606,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
*ptr = (unsigned long)i;
}
- print_info("RAM DLL lock\n");
+ printk(BIOS_INFO, "RAM DLL lock\n");
}
diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c
index 7c95ab4..d8515c6 100644
--- a/src/northbridge/amd/lx/raminit.c
+++ b/src/northbridge/amd/lx/raminit.c
@@ -38,13 +38,13 @@ static void banner(const char *s)
static void __attribute__((noreturn)) hcf(void)
{
- print_emerg("DIE\n");
+ printk(BIOS_EMERG, "DIE\n");
/* this guarantees we flush the UART fifos (if any) and also
* ensures that things, in general, keep going so no debug output
* is lost
*/
while (1)
- print_emerg_char(0);
+ printk(BIOS_EMERG, "%c", 0);
}
static void auto_size_dimm(unsigned int dimm)
@@ -67,7 +67,7 @@ static void auto_size_dimm(unsigned int dimm)
/* EEPROM byte usage: (5) Number of DIMM Banks */
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
- print_emerg("Number of module banks not compatible\n");
+ printk(BIOS_EMERG, "Number of module banks not compatible\n");
post_code(ERROR_BANK_SET);
hcf();
}
@@ -78,7 +78,7 @@ static void auto_size_dimm(unsigned int dimm)
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
- print_emerg("Number of device banks not compatible\n");
+ printk(BIOS_EMERG, "Number of device banks not compatible\n");
post_code(ERROR_BANK_SET);
hcf();
}
@@ -94,7 +94,7 @@ static void auto_size_dimm(unsigned int dimm)
*/
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
- print_emerg("Assymetirc DIMM not compatible\n");
+ printk(BIOS_EMERG, "Assymetirc DIMM not compatible\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
@@ -111,7 +111,7 @@ static void auto_size_dimm(unsigned int dimm)
dimm_size = __builtin_ctz(dimm_size);
banner("TEST DIMM SIZE>8");
if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
- print_emerg("Only support up to 1 GB per DIMM\n");
+ printk(BIOS_EMERG, "Only support up to 1 GB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
hcf();
}
@@ -144,7 +144,7 @@ static void auto_size_dimm(unsigned int dimm)
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
banner("MAXCOLADDR");
if (spd_byte > MAX_COL_ADDR) {
- print_emerg("DIMM page size not compatible\n");
+ printk(BIOS_EMERG, "DIMM page size not compatible\n");
post_code(ERROR_SET_PAGE);
hcf();
}
@@ -186,7 +186,7 @@ static void checkDDRMax(void)
/* I don't think you need this check.
if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
- print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+ printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
post_code(POST_PLL_MEM_FAIL);
hcf();
} */
@@ -201,7 +201,7 @@ static void checkDDRMax(void)
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
- print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
+ printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
post_code(POST_PLL_MEM_FAIL);
hcf();
}
@@ -319,7 +319,7 @@ static void setCAS(void)
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz(casmap0)];
} else {
- print_emerg("DIMM CAS Latencies not compatible\n");
+ printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
post_code(ERROR_DIFF_DIMMS);
hcf();
}
@@ -513,7 +513,7 @@ static void EnableMTest(void)
msr.lo |= CFCLK_LOWER_TRISTATE_DIS_SET;
wrmsr(MC_CFCLK_DBUG, msr);
- print_info("Enabled MTest for TLA debug\n");
+ printk(BIOS_INFO, "Enabled MTest for TLA debug\n");
}
#endif
@@ -558,14 +558,14 @@ void sdram_set_spd_registers(const struct mem_controller *ctrl)
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM0 NOT COMPATIBLE\n");
+ printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
banner("Check DIMM 1");
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
- print_emerg("DIMM1 NOT COMPATIBLE\n");
+ printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
@@ -633,7 +633,7 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr = rdmsr(MC_CF07_DATA);
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
- print_emerg("No memory in the system\n");
+ printk(BIOS_EMERG, "No memory in the system\n");
post_code(ERROR_NO_DIMMS);
hcf();
}
@@ -775,6 +775,6 @@ void sdram_enable(int controllers, const struct mem_controller *ctrl)
msr.lo |= 1;
wrmsr(msrnum, msr);
}
- print_info("RAM DLL lock\n");
+ printk(BIOS_INFO, "RAM DLL lock\n");
}
diff --git a/src/northbridge/dmp/vortex86ex/raminit.c b/src/northbridge/dmp/vortex86ex/raminit.c
index 2382fe2..227b376 100644
--- a/src/northbridge/dmp/vortex86ex/raminit.c
+++ b/src/northbridge/dmp/vortex86ex/raminit.c
@@ -258,17 +258,17 @@ static u8 detect_ddr3_dram_size(void)
static void print_ddr3_memory_setup(void)
{
#if CONFIG_DEBUG_RAM_SETUP
- print_debug("DDR3 Timing Reg 0-3:\n");
- print_debug("NB 6e : ");
+ printk(BIOS_DEBUG, "DDR3 Timing Reg 0-3:\n");
+ printk(BIOS_DEBUG, "NB 6e : ");
print_debug_hex16(pci_read_config16(NB, 0x6e));
- print_debug("\nNB 74 : ");
+ printk(BIOS_DEBUG, "\nNB 74 : ");
print_debug_hex32(pci_read_config32(NB, 0x74));
- print_debug("\nNB 78 : ");
+ printk(BIOS_DEBUG, "\nNB 78 : ");
print_debug_hex32(pci_read_config32(NB, 0x78));
- print_debug("\nNB 7c : ");
+ printk(BIOS_DEBUG, "\nNB 7c : ");
print_debug_hex32(pci_read_config32(NB, 0x7c));
u16 mbr = pci_read_config16(NB, 0x6c);
- print_debug("\nNB 6c(MBR) : ");
+ printk(BIOS_DEBUG, "\nNB 6c(MBR) : ");
print_debug_hex16(mbr);
const char *s;
u8 col = get_ddr3_mem_reg_col(mbr);
diff --git a/src/northbridge/intel/e7501/debug.c b/src/northbridge/intel/e7501/debug.c
index 07f1596..32a1428 100644
--- a/src/northbridge/intel/e7501/debug.c
+++ b/src/northbridge/intel/e7501/debug.c
@@ -5,12 +5,8 @@
#if 1
static void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
static inline void print_pci_devices(void)
@@ -27,7 +23,7 @@ static inline void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -38,24 +34,12 @@ static void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
static inline void dump_pci_devices(void)
@@ -95,98 +79,55 @@ static inline void dump_pci_devices_on_bus(unsigned busn)
static inline void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = smbus_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
static inline void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( smbus_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -194,24 +135,12 @@ static inline void dump_smbus_registers(void)
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -219,31 +148,15 @@ static inline void dump_io_resources(unsigned port)
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -252,24 +165,12 @@ static inline void dump_io_resources(unsigned port)
static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
#endif
diff --git a/src/northbridge/intel/e7501/raminit.c b/src/northbridge/intel/e7501/raminit.c
index 2247a25..22d1bbc 100644
--- a/src/northbridge/intel/e7501/raminit.c
+++ b/src/northbridge/intel/e7501/raminit.c
@@ -27,9 +27,9 @@ Definitions:
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -784,7 +784,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -812,11 +812,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1523,13 +1523,13 @@ static void configure_e7501_dram_controller_mode(const struct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1961,7 +1961,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
diff --git a/src/northbridge/intel/e7505/debug.c b/src/northbridge/intel/e7505/debug.c
index 3d6ca2a..cdf6e7e 100644
--- a/src/northbridge/intel/e7505/debug.c
+++ b/src/northbridge/intel/e7505/debug.c
@@ -15,12 +15,8 @@
void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 16) & 0xff, (dev >> 11) & 0x1f, (dev >> 8) & 7);
}
void print_pci_devices(void)
@@ -37,7 +33,7 @@ void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -48,24 +44,12 @@ void dump_pci_device(unsigned dev)
for(i = 0; i < 256; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%02x:",i);
-#else
- print_debug("\n");
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = pci_read_config8(dev, i);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
void dump_pci_devices(void)
@@ -105,98 +89,55 @@ void dump_pci_devices_on_bus(unsigned busn)
void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
device = ctrl->channel1[i];
if (device) {
int j;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device);
-#else
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".1: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 128; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ", j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
status = spd_read_byte(device, j);
if (status < 0) {
break;
}
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
void dump_smbus_registers(void)
{
unsigned device;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(device = 1; device < 0x80; device++) {
int j;
if( spd_read_byte(device, 0) < 0 ) continue;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "smbus: %02x", device);
-#else
- print_debug("smbus: ");
- print_debug_hex8(device);
-#endif
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
@@ -204,24 +145,12 @@ void dump_smbus_registers(void)
if (status < 0) {
break;
}
- if ((j & 0xf) == 0) {
-#if !defined(__ROMCC__)
+ if ((j & 0xf) == 0)
printk(BIOS_DEBUG, "\n%02x: ",j);
-#else
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
-#endif
- }
byte = status & 0xff;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%02x ", byte);
-#else
- print_debug_hex8(byte);
- print_debug_char(' ');
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -229,31 +158,15 @@ void dump_io_resources(unsigned port)
{
int i;
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, "%04x:\n", port);
-#else
- print_debug_hex16(port);
- print_debug(":\n");
-#endif
for(i=0;i<256;i++) {
uint8_t val;
- if ((i & 0x0f) == 0) {
-#if !defined(__ROMCC__)
+ if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "%02x:", i);
-#else
- print_debug_hex8(i);
- print_debug_char(':');
-#endif
- }
val = inb(port);
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x",val);
-#else
- print_debug_char(' ');
- print_debug_hex8(val);
-#endif
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
port++;
}
@@ -262,23 +175,11 @@ void dump_io_resources(unsigned port)
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
-#if !defined(__ROMCC__)
+ if((i & 0xf)==0)
printk(BIOS_DEBUG, "\n%08x:", i);
-#else
- print_debug("\n");
- print_debug_hex32(i);
- print_debug(":");
-#endif
- }
-#if !defined(__ROMCC__)
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
-#else
- print_debug(" ");
- print_debug_hex8((unsigned char)*((unsigned char *)i));
-#endif
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c
index 909e740..b758c61 100644
--- a/src/northbridge/intel/e7505/raminit.c
+++ b/src/northbridge/intel/e7505/raminit.c
@@ -42,9 +42,9 @@ Definitions:
//#define VALIDATE_DIMM_COMPATIBILITY
#if CONFIG_DEBUG_RAM_SETUP
-#define RAM_DEBUG_MESSAGE(x) print_debug(x)
-#define RAM_DEBUG_HEX32(x) print_debug_hex32(x)
-#define RAM_DEBUG_HEX8(x) print_debug_hex8(x)
+#define RAM_DEBUG_MESSAGE(x) printk(BIOS_DEBUG, x)
+#define RAM_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
+#define RAM_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
#define DUMPNORTH() dump_pci_device(MCHDEV)
#else
#define RAM_DEBUG_MESSAGE(x)
@@ -605,7 +605,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES);
if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) {
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
continue;
}
#ifdef VALIDATE_DIMM_COMPATIBILITY
@@ -633,11 +633,11 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl)
// Made it through all the checks, this DIMM pair is usable
dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)));
} else
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
#else
switch (bDualChannel) {
case 0:
- print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n");
+ printk(BIOS_DEBUG, "Skipping un-matched DIMMs - only dual-channel operation supported\n");
break;
default:
@@ -1379,13 +1379,13 @@ static void configure_e7501_dram_controller_mode(const struct
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate E7501 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -1767,7 +1767,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
dimm_mask = spd_get_supported_dimms(ctrl);
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
enable_e7501_clocks(dimm_mask);
diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 4f5a989..ebe137b 100644
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -78,7 +78,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
reg |= register_values[i+2];
pci_write_config32(dev, where, reg);
}
- print_spew("done.\n");
+ printk(BIOS_SPEW, "done.\n");
}
struct dimm_size {
@@ -610,7 +610,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the spd and if ram is ddr or ddr2 */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\n");
+ printk(BIOS_ERR, "No memory for this cpu\n");
return;
}
return;
@@ -686,9 +686,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
die("Error - First dimm slot empty\n");
}
- print_debug("ODT Value = ");
- print_debug_hex32(data32);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
@@ -916,11 +914,8 @@ static void set_receive_enable(const struct mem_controller *ctrl)
}
}
- print_debug("Receive enable A = ");
- print_debug_hex32(recena);
- print_debug(", Receive enable B = ");
- print_debug_hex32(recenb);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Receive enable A = %08x, Receive enable B = %08x\n",
+ recena, recenb);
/* clear out the calibration area */
write32(MCBAR+DCALDATA+(16*4), 0x00000000);
@@ -972,7 +967,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
0xffffffff, 0xffffffff, 0x000000ff};
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\n");
+ printk(BIOS_DEBUG, "Starting SDRAM Enable\n");
/* 0x80 */
pci_write_config32(ctrl->f0, DRM,
@@ -1013,9 +1008,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
cas_latency = spd_set_drt_attributes(ctrl, mask, drc);
for(i=0;i<8;i+=2) { /* loop through each dimm to test */
- print_debug("DIMM ");
- print_debug_hex8(i);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DIMM %08x\n", i);
/* Apply NOP */
do_delay();
@@ -1158,7 +1151,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
write32(MCBAR+DCALCSR, 0x0008000f);
/* clear memory and init ECC */
- print_debug("Clearing memory\n");
+ printk(BIOS_DEBUG, "Clearing memory\n");
for(i=0;i<64;i+=4) {
write32(MCBAR+DCALDATA+i, 0x00000000);
}
@@ -1174,13 +1167,13 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
data32 |= (1 << 31);
pci_write_config32(ctrl->f0, 0x98, data32);
/* wait for completion */
- print_debug("Waiting for mem complete\n");
+ printk(BIOS_DEBUG, "Waiting for mem complete\n");
while(1) {
data32 = pci_read_config32(ctrl->f0, 0x98);
if( (data32 & (1<<31)) == 0)
break;
}
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* Set initialization complete */
/* 0x7c DRC */
diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index cff7879..b2858e4 100644
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -128,13 +128,7 @@ static struct dimm_size spd_get_dimm_size(u16 device)
sz.side1 = 0;
sz.side2 = 0;
out:
- print_debug("dimm ");
- print_debug_hex8(device);
- print_debug(" size = ");
- print_debug_hex8(sz.side1);
- print_debug(".");
- print_debug_hex8(sz.side2);
- print_debug("\n");
+ printk(BIOS_DEBUG, "dimm %02x size = %02x.%02x\n", device, sz.side1, sz.side2);
return sz;
}
@@ -165,25 +159,19 @@ static long spd_set_ram_size(const struct mem_controller *ctrl, u8 dimm_mask)
pci_write_config8(ctrl->f0, DRB+1 + (i*2), cum);
}
}
- print_debug("DRB = ");
- print_debug_hex32(pci_read_config32(ctrl->f0, DRB));
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRB = %08x\n", pci_read_config32(ctrl->f0, DRB));
cum >>= 1;
/* set TOM top of memory */
pci_write_config16(ctrl->f0, TOM, cum);
- print_debug("TOM = ");
- print_debug_hex16(cum);
- print_debug("\n");
+ printk(BIOS_DEBUG, "TOM = %04x\n", cum);
/* set TOLM top of low memory */
if (cum > 0x18) {
cum = 0x18;
}
cum <<= 11;
pci_write_config16(ctrl->f0, TOLM, cum);
- print_debug("TOLM = ");
- print_debug_hex16(cum);
- print_debug("\n");
+ printk(BIOS_DEBUG, "TOLM = %04x\n", cum);
return 0;
}
@@ -198,11 +186,7 @@ static u8 spd_detect_dimms(const struct mem_controller *ctrl)
device = ctrl->channel0[i];
if (device) {
byte = spd_read_byte(device, SPD_MEMORY_TYPE);
- print_debug("spd ");
- print_debug_hex8(device);
- print_debug(" = ");
- print_debug_hex8(byte);
- print_debug("\n");
+ printk(BIOS_DEBUG, "spd %02x = %02x\n", device, byte);
if (byte == 8) {
dimm_mask |= (1 << i);
}
@@ -245,11 +229,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
if ((value & 0xff) == 0) die("Invalid # of banks\n");
reg += log2(value & 0xff);
- print_debug("dimm ");
- print_debug_hex8(i);
- print_debug(" reg = ");
- print_debug_hex8(reg);
- print_debug("\n");
+ printk(BIOS_DEBUG, "dimm %02x reg = %02x\n", i, reg);
/* set device density */
dra |= ((31-reg));
@@ -266,11 +246,7 @@ static int spd_set_row_attributes(const struct mem_controller *ctrl,
value = spd_read_byte(ctrl->channel0[i], SPD_NUM_DIMM_BANKS);
dra |= ((value & 0x1) << 17);
- print_debug("DRA");
- print_debug_hex8(i);
- print_debug(" = ");
- print_debug_hex32(dra);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRA%02x = %08x\n", i, dra);
pci_write_config32(ctrl->f0, DRA + (i*4), dra);
}
@@ -321,9 +297,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
cl = 6;
else
die("CAS latency mismatch\n");
- print_debug("cl = ");
- print_debug_hex8(cl);
- print_debug("\n");
+ printk(BIOS_DEBUG, "cl = %02x\n", cl);
ci = cycle[index];
@@ -347,12 +321,8 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
if (trfc < val)
trfc = val;
}
- print_debug("trc = ");
- print_debug_hex8(trc);
- print_debug("\n");
- print_debug("trfc = ");
- print_debug_hex8(trfc);
- print_debug("\n");
+ printk(BIOS_DEBUG, "trc = %02x\n", trc);
+ printk(BIOS_DEBUG, "trfc = %02x\n", trfc);
/* Tras, Trtp, Twtr in cycles */
for (i = 0; i < DIMM_SOCKETS; i++) {
@@ -372,40 +342,26 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl,
if (twtr < val)
twtr = val;
}
- print_debug("tras = ");
- print_debug_hex8(tras);
- print_debug("\n");
- print_debug("trtp = ");
- print_debug_hex8(trtp);
- print_debug("\n");
- print_debug("twtr = ");
- print_debug_hex8(twtr);
- print_debug("\n");
+ printk(BIOS_DEBUG, "tras = %02x\n", tras);
+ printk(BIOS_DEBUG, "trtp = %02x\n", trtp);
+ printk(BIOS_DEBUG, "twtr = %02x\n", twtr);
val = (drt0[index] | ((trc - 11) << 12) | ((cl - 3) << 9)
| ((cl - 3) << 6) | ((cl - 3) << 3));
- print_debug("drt0 = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "drt0 = %08x\n", val);
pci_write_config32(ctrl->f0, DRT0, val);
val = (drt1[index] | ((tras - 8) << 28) | ((trtp - 2) << 25)
| (twtr << 15));
- print_debug("drt1 = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "drt1 = %08x\n", val);
pci_write_config32(ctrl->f0, DRT1, val);
val = (magic[index]);
- print_debug("magic = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "magic = %08x\n", val);
pci_write_config32(PCI_DEV(0, 0x08, 0), 0xcc, val);
val = (mrs[index] | (cl << 20));
- print_debug("mrs = ");
- print_debug_hex32(val);
- print_debug("\n");
+ printk(BIOS_DEBUG, "mrs = %08x\n", val);
return val;
}
@@ -432,9 +388,7 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
if (value > cycle)
cycle = value;
}
- print_debug("cycle = ");
- print_debug_hex8(cycle);
- print_debug("\n");
+ printk(BIOS_DEBUG, "cycle = %02x\n", cycle);
drc |= (1 << 20); /* enable ECC */
drc |= (3 << 30); /* enable CKE on each DIMM */
@@ -443,45 +397,40 @@ static int spd_set_dram_controller_mode(const struct mem_controller *ctrl,
/* TODO check: */
/* set front side bus speed */
msr = rdmsr(MSR_FSB_FREQ); /* returns 0 on Pentium M 90nm */
- print_debug("MSR FSB_FREQ(0xcd) = ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MSR FSB_FREQ(0xcd) = %08x%08x\n", msr.hi, msr.lo);
/* TODO check that this msr really indicates fsb speed! */
if (msr.lo & 0x07) {
- print_info("533 MHz FSB\n");
+ printk(BIOS_INFO, "533 MHz FSB\n");
if (cycle <= 0x25) {
drc |= 0x5;
- print_info("400 MHz DDR\n");
+ printk(BIOS_INFO, "400 MHz DDR\n");
} else if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\n");
+ printk(BIOS_INFO, "333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x4;
- print_info("266 MHz DDR\n");
+ printk(BIOS_INFO, "266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\n");
+ printk(BIOS_INFO, "200 MHz DDR\n");
}
}
else {
- print_info("400 MHz FSB\n");
+ printk(BIOS_INFO, "400 MHz FSB\n");
if (cycle <= 0x30) {
drc |= 0x7;
- print_info("333 MHz DDR\n");
+ printk(BIOS_INFO, "333 MHz DDR\n");
} else if (cycle <= 0x3d) {
drc |= 0x0;
- print_info("266 MHz DDR\n");
+ printk(BIOS_INFO, "266 MHz DDR\n");
} else {
drc |= 0x2;
- print_info("200 MHz DDR\n");
+ printk(BIOS_INFO, "200 MHz DDR\n");
}
}
- print_debug("DRC = ");
- print_debug_hex32(drc);
- print_debug("\n");
+ printk(BIOS_DEBUG, "DRC = %08x\n", drc);
return drc;
}
@@ -493,7 +442,7 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
/* Test if we can read the SPD */
dimm_mask = spd_detect_dimms(ctrl);
if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) {
- print_err("No memory for this cpu\n");
+ printk(BIOS_ERR, "No memory for this cpu\n");
return;
}
return;
@@ -520,16 +469,12 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
data32 = 0x00002010;
}
- print_debug("ODT Value = ");
- print_debug_hex32(data32);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT Value = %08x\n", data32);
pci_write_config32(ctrl->f0, DDR2ODTC, data32);
for (i = 0; i < 2; i++) {
- print_debug("ODT CS");
- print_debug_hex8(i);
- print_debug("\n");
+ printk(BIOS_DEBUG, "ODT CS%d\n", i);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
@@ -544,14 +489,11 @@ static void dump_dcal_regs(void)
int i;
for (i = 0x0; i < 0x2a0; i += 4) {
if ((i % 16) == 0) {
- print_debug("\n");
- print_debug_hex16(i);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%04x: ", i);
}
- print_debug_hex32(read32(BAR+i));
- print_debug(" ");
+ printk(BIOS_DEBUG, "%08x ", read32(BAR+i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
@@ -565,7 +507,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
u32 mode_reg;
mask = spd_detect_dimms(ctrl);
- print_debug("Starting SDRAM Enable\n");
+ printk(BIOS_DEBUG, "Starting SDRAM Enable\n");
/* Set DRAM type and Front Side Bus frequency */
drc = spd_set_dram_controller_mode(ctrl, mask);
@@ -593,9 +535,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
for (cs = 0; cs < 2; cs++) {
- print_debug("NOP CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NOP CS%d\n", cs);
udelay(16);
write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
@@ -606,9 +546,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Apply NOP */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("NOP CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "NOP CS%d\n", cs);
write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -617,9 +555,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Precharge all banks */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("Precharge CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Precharge CS%d\n", cs);
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -629,9 +565,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* EMRS: Enable DLLs, set OCD calibration mode to default */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("EMRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "EMRS CS%d\n", cs);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -640,9 +574,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* MRS: Reset DLLs */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("MRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MRS CS%d\n", cs);
write32(BAR+DCALADDR, mode_reg);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -652,9 +584,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Precharge all banks */
udelay(48);
for (cs = 0; cs < 2; cs++) {
- print_debug("Precharge CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Precharge CS%d\n", cs);
write32(BAR+DCALADDR, 0x04000000);
write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -665,9 +595,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (i = 0; i < 2; i++) {
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("Refresh CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "Refresh CS%d\n", cs);
write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -677,9 +605,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* MRS: Set DLLs to normal */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("MRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "MRS CS%d\n", cs);
write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -689,9 +615,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* EMRS: Enable DLLs */
udelay(16);
for (cs = 0; cs < 2; cs++) {
- print_debug("EMRS CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "EMRS CS%d\n", cs);
write32(BAR+DCALADDR, 0x0b840001);
write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
@@ -712,9 +636,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
/* Receive enable calibration */
udelay(16);
for (cs = 0; cs < 1; cs++) {
- print_debug("receive enable calibration CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "receive enable calibration CS%d\n", cs);
write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
do data32 = read32(BAR+DCALCSR);
while (data32 & 0x80000000);
@@ -738,18 +660,16 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
for (cs = 0; cs < 2; cs++) {
if (!(mask & (1<<cs)))
continue;
- print_debug("clear memory CS");
- print_debug_hex8(cs);
- print_debug("\n");
+ printk(BIOS_DEBUG, "clear memory CS%d\n", cs);
write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
do data32 = read32(BAR+MBCSR);
while (data32 & 0x80000000);
if (data32 & 0x40000000)
- print_debug("failed!\n");
+ printk(BIOS_DEBUG, "failed!\n");
}
/* Clear read/write FIFO pointers */
- print_debug("clear read/write fifo pointers\n");
+ printk(BIOS_DEBUG, "clear read/write fifo pointers\n");
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) | (1<<15));
udelay(16);
write32(BAR+DDRIOMC2, read32(BAR+DDRIOMC2) & ~(1<<15));
@@ -757,7 +677,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
dump_dcal_regs();
- print_debug("Done\n");
+ printk(BIOS_DEBUG, "Done\n");
/* Set initialization complete */
drc |= (1 << 29);
diff --git a/src/northbridge/intel/i440bx/debug.c b/src/northbridge/intel/i440bx/debug.c
index ef9d513..efd4326 100644
--- a/src/northbridge/intel/i440bx/debug.c
+++ b/src/northbridge/intel/i440bx/debug.c
@@ -35,34 +35,18 @@ void dump_spd_registers(void)
}
}
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
void dump_pci_device(unsigned dev)
{
int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x: %02x", i, val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index e3cfbdf..f191abe 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -752,7 +752,7 @@ static void set_dram_row_attributes(void)
PRINT_DEBUG("Found DIMM in slot %d\n", i);
if (edo && sd) {
- print_err("Mixing EDO/SDRAM unsupported!\n");
+ printk(BIOS_ERR, "Mixing EDO/SDRAM unsupported!\n");
die("HALT\n");
}
@@ -857,11 +857,11 @@ static void set_dram_row_attributes(void)
if (col == 4)
bpr |= 0xc0;
} else {
- print_err("# of banks of DIMM unsupported!\n");
+ printk(BIOS_ERR, "# of banks of DIMM unsupported!\n");
die("HALT\n");
}
if (dra == -1) {
- print_err("Page size not supported\n");
+ printk(BIOS_ERR, "Page size not supported\n");
die("HALT\n");
}
@@ -872,7 +872,7 @@ static void set_dram_row_attributes(void)
*/
struct dimm_size sz = spd_get_dimm_size(device);
if ((sz.side1 < 8)) {
- print_err("DIMMs smaller than 8MB per side\n"
+ printk(BIOS_ERR, "DIMMs smaller than 8MB per side\n"
"are not supported on this NB.\n");
die("HALT\n");
}
diff --git a/src/northbridge/intel/i440lx/raminit.c b/src/northbridge/intel/i440lx/raminit.c
index 7d283a1..ddabf25 100644
--- a/src/northbridge/intel/i440lx/raminit.c
+++ b/src/northbridge/intel/i440lx/raminit.c
@@ -32,10 +32,10 @@ Macros and definitions.
/* Debugging macros. */
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG(x)
diff --git a/src/northbridge/intel/i82810/debug.c b/src/northbridge/intel/i82810/debug.c
index c3e4fb9..b74bb36 100644
--- a/src/northbridge/intel/i82810/debug.c
+++ b/src/northbridge/intel/i82810/debug.c
@@ -1,73 +1,52 @@
#include <console/console.h>
#include <arch/io.h>
#include <spd.h>
-#include "i82810.h"
#include "raminit.h"
+#include <spd.h>
+#include <console/console.h>
#if CONFIG_DEBUG_RAM_SETUP
void dump_spd_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < DIMM_SOCKETS; i++) {
unsigned device;
device = DIMM0 + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "DIMM %d: %02x", i, device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
+ printk(BIOS_DEBUG, "\n%02x: ", j);
}
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 16) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 11) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 8) & 7);
-}
-
void dump_pci_device(unsigned dev)
{
int i;
- print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x\n", (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 7);
for (i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x: %02x", i, val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
#endif
diff --git a/src/northbridge/intel/i855/debug.c b/src/northbridge/intel/i855/debug.c
index 327f47d..ed26fad 100644
--- a/src/northbridge/intel/i855/debug.c
+++ b/src/northbridge/intel/i855/debug.c
@@ -22,12 +22,8 @@
static void print_debug_pci_dev(unsigned dev)
{
- print_debug("PCI: ");
- print_debug_hex8((dev >> 20) & 0xff);
- print_debug_char(':');
- print_debug_hex8((dev >> 15) & 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev >> 12) & 0x07);
+ printk(BIOS_DEBUG, "PCI: %02x:%02x.%x",
+ (dev >> 20) & 0xff, (dev >> 15) & 0x1f, (dev >> 12) & 0x07);
}
static inline void print_pci_devices(void)
@@ -44,7 +40,7 @@ static inline void print_pci_devices(void)
continue;
}
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -52,20 +48,16 @@ static void dump_pci_device(unsigned dev)
{
int i;
print_debug_pci_dev(dev);
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i <= 255; i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x:", i);
val = pci_read_config8(dev, i);
- print_debug_char(' ');
- print_debug_hex8(val);
- if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
- }
+ printk(BIOS_DEBUG, " %02x", val);
+ if ((i & 0x0f) == 0x0f)
+ printk(BIOS_DEBUG, "\n");
}
}
@@ -89,34 +81,27 @@ static inline void dump_pci_devices(void)
static inline void dump_spd_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 0; i < 2; i++) {
unsigned device;
device = DIMM0 + i;
if (device) {
int j;
- print_debug("dimm: ");
- print_debug_hex8(i);
- print_debug(".0: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "dimm: %02x.0: %02x", i, device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
@@ -124,30 +109,25 @@ static inline void dump_spd_registers(void)
static inline void dump_smbus_registers(void)
{
int i;
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
for(i = 1; i < 0x80; i++) {
unsigned device;
device = i;
int j;
- print_debug("smbus: ");
- print_debug_hex8(device);
+ printk(BIOS_DEBUG, "smbus: %02x", device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
- if ((j & 0xf) == 0) {
- print_debug("\n");
- print_debug_hex8(j);
- print_debug(": ");
- }
+ if ((j & 0xf) == 0)
+ printk(BIOS_DEBUG, "\n%02x: ", j);
status = smbus_read_byte(device, j);
if (status < 0) {
- print_debug("bad device\n");
+ printk(BIOS_DEBUG, "bad device\n");
break;
}
byte = status & 0xff;
- print_debug_hex8(byte);
- print_debug_char(' ');
+ printk(BIOS_DEBUG, "%02x ", byte);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
diff --git a/src/northbridge/intel/i855/raminit.c b/src/northbridge/intel/i855/raminit.c
index 0ab4d38..39e12d2 100644
--- a/src/northbridge/intel/i855/raminit.c
+++ b/src/northbridge/intel/i855/raminit.c
@@ -415,7 +415,7 @@ static void sdram_enable(void)
{
int i;
- print_debug("Ram enable 1\n");
+ printk(BIOS_DEBUG, "Ram enable 1\n");
delay();
delay();
@@ -433,16 +433,16 @@ static void sdram_enable(void)
delay();
delay();
- print_debug("Ram enable 4\n");
+ printk(BIOS_DEBUG, "Ram enable 4\n");
do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE);
delay();
delay();
delay();
- print_debug("Ram enable 5\n");
+ printk(BIOS_DEBUG, "Ram enable 5\n");
do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_DLL_RESET);
- print_debug("Ram enable 6\n");
+ printk(BIOS_DEBUG, "Ram enable 6\n");
do_ram_command(RAM_COMMAND_PRECHARGE, 0);
delay();
delay();
@@ -457,7 +457,7 @@ static void sdram_enable(void)
delay();
}
- print_debug("Ram enable 8\n");
+ printk(BIOS_DEBUG, "Ram enable 8\n");
do_ram_command(RAM_COMMAND_MRS, VG85X_MODE | SDRAM_MODE_NORMAL);
/* Set GME-M Mode Select bits back to NORMAL operation mode */
@@ -467,7 +467,7 @@ static void sdram_enable(void)
delay();
delay();
- print_debug("Ram enable 9\n");
+ printk(BIOS_DEBUG, "Ram enable 9\n");
set_initialize_complete();
delay();
@@ -476,11 +476,11 @@ static void sdram_enable(void)
delay();
delay();
- print_debug("After configuration:\n");
+ printk(BIOS_DEBUG, "After configuration:\n");
/* dump_pci_devices(); */
/*
- print_debug("\n\n***** RAM TEST *****\n");
+ printk(BIOS_DEBUG, "\n\n***** RAM TEST *****\n");
ram_check(0, 0xa0000);
ram_check(0x100000, 0x40000000);
*/
@@ -497,7 +497,7 @@ DIMM-independant configuration functions:
static void sdram_set_registers(void)
{
/*
- print_debug("Before configuration:\n");
+ printk(BIOS_DEBUG, "Before configuration:\n");
dump_pci_devices();
*/
}
@@ -572,13 +572,13 @@ static void spd_set_dram_controller_mode(uint8_t dimm_mask)
die_on_spd_error(value);
value &= 0x7f; // Mask off self-refresh bit
if (value > MAX_SPD_REFRESH_RATE) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// Get the appropriate i855 refresh mode for this DIMM
dimm_refresh_mode = refresh_rate_map[value];
if (dimm_refresh_mode > 7) {
- print_err("unsupported refresh rate\n");
+ printk(BIOS_ERR, "unsupported refresh rate\n");
continue;
}
// If this DIMM requires more frequent refresh than others,
@@ -965,7 +965,7 @@ static void sdram_set_spd_registers(void)
dimm_mask = spd_get_supported_dimms();
if (dimm_mask == 0) {
- print_debug("No usable memory for this controller\n");
+ printk(BIOS_DEBUG, "No usable memory for this controller\n");
} else {
PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask);
diff --git a/src/northbridge/intel/i945/debug.c b/src/northbridge/intel/i945/debug.c
index e47f762..397bd4b 100644
--- a/src/northbridge/intel/i945/debug.c
+++ b/src/northbridge/intel/i945/debug.c
@@ -109,12 +109,12 @@ void dump_spd_registers(void)
void dump_mem(unsigned start, unsigned end)
{
unsigned i;
- print_debug("dump_mem:");
+ printk(BIOS_DEBUG, "dump_mem:");
for(i=start;i<end;i++) {
if((i & 0xf)==0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c
index 0103c4f..747cbfd 100644
--- a/src/northbridge/via/cn700/raminit.c
+++ b/src/northbridge/via/cn700/raminit.c
@@ -25,10 +25,10 @@
#include "cn700.h"
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG_MEM(x) print_debug(x)
-#define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_MEM_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG_MEM(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_MEM_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_MEM_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_MEM_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG_MEM(x)
diff --git a/src/northbridge/via/cn700/vga.c b/src/northbridge/via/cn700/vga.c
index 4434e57..4826fcf 100644
--- a/src/northbridge/via/cn700/vga.c
+++ b/src/northbridge/via/cn700/vga.c
@@ -84,7 +84,7 @@ static void vga_init(device_t dev)
#undef OLD_BOCHS_METHOD
#ifdef OLD_BOCHS_METHOD
- print_debug("Copying BOCHS BIOS to 0xf000\n");
+ printk(BIOS_DEBUG, "Copying BOCHS BIOS to 0xf000\n");
/*
* Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
* This is for compatibility with the VGA ROM's BIOS callbacks.
diff --git a/src/northbridge/via/cx700/early_smbus.c b/src/northbridge/via/cx700/early_smbus.c
index 7c77bff..39e1753 100644
--- a/src/northbridge/via/cx700/early_smbus.c
+++ b/src/northbridge/via/cx700/early_smbus.c
@@ -46,15 +46,6 @@
#define SMBUS_DELAY() outb(0x80, 0x80)
-/* Debugging macros. */
-#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
-#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
-#endif
-
/* Internal functions */
#if CONFIG_DEBUG_SMBUS
static void smbus_print_error(unsigned char host_status_register, int loops)
@@ -63,28 +54,26 @@ static void smbus_print_error(unsigned char host_status_register, int loops)
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
- print_err("SMBus Error: ");
- print_err_hex8(host_status_register);
+ printk(BIOS_ERR, "SMBus Error: %02x\n", host_status_register);
- print_err("\n");
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\n");
+ printk(BIOS_ERR, "SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
+ printk(BIOS_ERR, "Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
+ printk(BIOS_ERR, "Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\n");
+ printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
+ printk(BIOS_ERR, "Host Busy\n");
}
}
#endif
@@ -239,9 +228,7 @@ static void dump_spd_data(const struct mem_controller *ctrl)
unsigned int val;
for (dimm = 0; dimm < DIMM_SOCKETS; dimm++) {
- print_debug("SPD Data for DIMM ");
- print_debug_hex8(dimm);
- print_debug("\n");
+ printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
val = get_spd_data(ctrl, dimm, 0);
if (val == 0xff) {
@@ -249,15 +236,12 @@ static void dump_spd_data(const struct mem_controller *ctrl)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\n");
+ printk(BIOS_DEBUG, "No DIMM present\n");
regs = 0;
}
for (offset = 0; offset < regs; offset++) {
- print_debug(" Offset ");
- print_debug_hex8(offset);
- print_debug(" = 0x");
- print_debug_hex8(get_spd_data(ctrl, dimm, offset));
- print_debug("\n");
+ printk(BIOS_DEBUG, " Offset %02x = 0x%02x\n",
+ offset, get_spd_data(ctrl, dimm, offset));
}
}
}
diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c
index a2e6dad..32be1ea 100644
--- a/src/northbridge/via/cx700/raminit.c
+++ b/src/northbridge/via/cx700/raminit.c
@@ -972,7 +972,7 @@ static void step_20_21(const struct mem_controller *ctrl)
read32(0x102020);
/* Step 21. Normal operation */
- print_spew("RAM Enable 5: Normal operation\n");
+ printk(BIOS_SPEW, "RAM Enable 5: Normal operation\n");
do_ram_command(ctrl, RAM_COMMAND_NORMAL);
udelay(3);
}
@@ -988,58 +988,58 @@ static void step_2_19(const struct mem_controller *ctrl)
pci_write_config8(MEMCTRL, 0x69, val);
/* Step 3 Apply NOP. */
- print_spew("RAM Enable 1: Apply NOP\n");
+ printk(BIOS_SPEW, "RAM Enable 1: Apply NOP\n");
do_ram_command(ctrl, RAM_COMMAND_NOP);
udelay(15);
// Step 4
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
// Step 5
udelay(400);
/* 6. Precharge all. Wait tRP. */
- print_spew("RAM Enable 2: Precharge all\n");
+ printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
// Step 7
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
/* Step 8. Mode register set. */
- print_spew("RAM Enable 4: Mode register set\n");
+ printk(BIOS_SPEW, "RAM Enable 4: Mode register set\n");
do_ram_command(ctrl, RAM_COMMAND_MRS); //enable dll
// Step 9
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
val = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_DRAM_NB_ODT);
if (val & DDR2_ODT_150ohm)
read32(0x102200); //DDR2_ODT_150ohm
else
read32(0x102020);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
// Step 10
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0x800);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
/* Step 11. Precharge all. Wait tRP. */
- print_spew("RAM Enable 2: Precharge all\n");
+ printk(BIOS_SPEW, "RAM Enable 2: Precharge all\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE);
// Step 12
- print_spew("SEND: ");
+ printk(BIOS_SPEW, "SEND: ");
read32(0x0);
- print_spew("OK\n");
+ printk(BIOS_SPEW, "OK\n");
/* Step 13. Perform 8 refresh cycles. Wait tRC each time. */
- print_spew("RAM Enable 3: CBR\n");
+ printk(BIOS_SPEW, "RAM Enable 3: CBR\n");
do_ram_command(ctrl, RAM_COMMAND_CBR);
/* JEDEC says only twice, do 8 times for posterity */
@@ -1047,14 +1047,14 @@ static void step_2_19(const struct mem_controller *ctrl)
for (i = 0; i < 8; i++) {
// Step 14
read32(0);
- print_spew(".");
+ printk(BIOS_SPEW, ".");
// Step 15
udelay(100);
}
/* Step 17. Mode register set. Wait 200us. */
- print_spew("\nRAM Enable 4: Mode register set\n");
+ printk(BIOS_SPEW, "\nRAM Enable 4: Mode register set\n");
//safe value for now, BL=8, WR=4, CAS=4
do_ram_command(ctrl, RAM_COMMAND_MRS);
diff --git a/src/northbridge/via/vx800/early_smbus.c b/src/northbridge/via/vx800/early_smbus.c
index f9b13eb..da2a559 100644
--- a/src/northbridge/via/vx800/early_smbus.c
+++ b/src/northbridge/via/vx800/early_smbus.c
@@ -50,42 +50,38 @@
#define SMBUS_DELAY() outb(0x80, 0x80)
#if CONFIG_DEBUG_SMBUS
-#define PRINT_DEBUG(x) print_debug(x)
-#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
+#define DEBUG(x...) printk(BIOS_DEBUG, x)
#else
-#define PRINT_DEBUG(x)
-#define PRINT_DEBUG_HEX16(x)
+#define DEBUG(x...) while (0) { }
#endif
/* Internal functions */
static void smbus_print_error(unsigned char host_status_register, int loops)
{
-// print_err("some i2c error\n");
+// printk(BIOS_ERR, "some i2c error\n");
/* Check if there actually was an error */
if (host_status_register == 0x00 || host_status_register == 0x40 ||
host_status_register == 0x42)
return;
- print_err("smbus_error: ");
- print_err_hex8(host_status_register);
- print_err("\n");
+ printk(BIOS_ERR, "smbus_error: %02x\n", host_status_register);
if (loops >= SMBUS_TIMEOUT) {
- print_err("SMBus Timout\n");
+ printk(BIOS_ERR, "SMBus Timout\n");
}
if (host_status_register & (1 << 4)) {
- print_err("Interrup/SMI# was Failed Bus Transaction\n");
+ printk(BIOS_ERR, "Interrup/SMI# was Failed Bus Transaction\n");
}
if (host_status_register & (1 << 3)) {
- print_err("Bus Error\n");
+ printk(BIOS_ERR, "Bus Error\n");
}
if (host_status_register & (1 << 2)) {
- print_err("Device Error\n");
+ printk(BIOS_ERR, "Device Error\n");
}
if (host_status_register & (1 << 1)) {
/* This isn't a real error... */
- print_debug("Interrupt/SMI# was Successful Completion\n");
+ printk(BIOS_DEBUG, "Interrupt/SMI# was Successful Completion\n");
}
if (host_status_register & (1 << 0)) {
- print_err("Host Busy\n");
+ printk(BIOS_ERR, "Host Busy\n");
}
}
@@ -185,11 +181,11 @@ void smbus_fixup(const struct mem_controller *mem_ctrl)
ram_slots = ARRAY_SIZE(mem_ctrl->channel0);
if (!ram_slots) {
- print_err("smbus_fixup() thinks there are no RAM slots!\n");
+ printk(BIOS_ERR, "smbus_fixup() thinks there are no RAM slots!\n");
return;
}
- PRINT_DEBUG("Waiting for SMBus to warm up");
+ DEBUG("Waiting for SMBus to warm up");
/*
* Bad SPD data should be either 0 or 0xff, but YMMV. So we look for
@@ -207,13 +203,13 @@ void smbus_fixup(const struct mem_controller *mem_ctrl)
result = get_spd_data(mem_ctrl->channel0[current_slot],
SPD_MEMORY_TYPE);
current_slot++;
- PRINT_DEBUG(".");
+ DEBUG(".");
}
if (i >= SMBUS_TIMEOUT)
- print_err("SMBus timed out while warming up\n");
+ printk(BIOS_ERR, "SMBus timed out while warming up\n");
else
- PRINT_DEBUG("Done\n");
+ DEBUG("Done\n");
}
/* Debugging Function */
@@ -224,9 +220,7 @@ static void dump_spd_data(void)
unsigned int val;
for (dimm = 0; dimm < 8; dimm++) {
- print_debug("SPD Data for DIMM ");
- print_debug_hex8(dimm);
- print_debug("\n");
+ printk(BIOS_DEBUG, "SPD Data for DIMM %02x\n", dimm);
val = get_spd_data(dimm, 0);
if (val == 0xff) {
@@ -234,16 +228,12 @@ static void dump_spd_data(void)
} else if (val == 0x80) {
regs = 128;
} else {
- print_debug("No DIMM present\n");
+ printk(BIOS_DEBUG, "No DIMM present\n");
regs = 0;
}
- for (offset = 0; offset < regs; offset++) {
- print_debug(" Offset ");
- print_debug_hex8(offset);
- print_debug(" = 0x");
- print_debug_hex8(get_spd_data(dimm, offset));
- print_debug("\n");
- }
+ for (offset = 0; offset < regs; offset++)
+ printk(BIOS_DEBUG, " Offset %02x = 0x%02x\n",
+ offset, get_spd_data(dimm, offset));
}
}
#else
diff --git a/src/northbridge/via/vx800/raminit.c b/src/northbridge/via/vx800/raminit.c
index 6d58f78..a7a5757 100644
--- a/src/northbridge/via/vx800/raminit.c
+++ b/src/northbridge/via/vx800/raminit.c
@@ -29,10 +29,10 @@
#endif
#if CONFIG_DEBUG_RAM_SETUP
-#define PRINT_DEBUG_MEM(x) print_debug(x)
-#define PRINT_DEBUG_MEM_HEX8(x) print_debug_hex8(x)
-#define PRINT_DEBUG_MEM_HEX16(x) print_debug_hex16(x)
-#define PRINT_DEBUG_MEM_HEX32(x) print_debug_hex32(x)
+#define PRINT_DEBUG_MEM(x) printk(BIOS_DEBUG, x)
+#define PRINT_DEBUG_MEM_HEX8(x) printk(BIOS_DEBUG, "%02x", x)
+#define PRINT_DEBUG_MEM_HEX16(x) printk(BIOS_DEBUG, "%04x", x)
+#define PRINT_DEBUG_MEM_HEX32(x) printk(BIOS_DEBUG, "%08x", x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG_MEM(x)
diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c
index b9fed6f..78a1a88 100644
--- a/src/northbridge/via/vx900/chrome9hd.c
+++ b/src/northbridge/via/vx900/chrome9hd.c
@@ -296,9 +296,9 @@ static void chrome9hd_biosguide_init_seq(device_t dev)
static void chrome9hd_init(device_t dev)
{
- print_debug("======================================================\n");
- print_debug("== Chrome9 HD INIT\n");
- print_debug("======================================================\n");
+ printk(BIOS_DEBUG, "======================================================\n");
+ printk(BIOS_DEBUG, "== Chrome9 HD INIT\n");
+ printk(BIOS_DEBUG, "======================================================\n");
chrome9hd_biosguide_init_seq(dev);
diff --git a/src/northbridge/via/vx900/early_smbus.c b/src/northbridge/via/vx900/early_smbus.c
index f006ce4..e796d8d 100644
--- a/src/northbridge/via/vx900/early_smbus.c
+++ b/src/northbridge/via/vx900/early_smbus.c
@@ -182,13 +182,13 @@ void dump_spd_data(spd_raw_data spd)
* I originally saw this way to present SPD data in code from VIA. I
* really liked the idea, so here it goes.
*/
- print_debug(" 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
- print_debug("---+------------------------------------------------");
+ printk(BIOS_DEBUG, " 00 01 02 03 04 05 06 07 07 09 0A 0B 0C 0D 0E 0F\n");
+ printk(BIOS_DEBUG, "---+------------------------------------------------");
for (i = 0; i < len; i++) {
reg = spd[i];
if ((i & 0x0f) == 0)
printk(BIOS_DEBUG, "\n%.2x |", i);
printk(BIOS_DEBUG, " %.2x", reg);
}
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c
index 2896680..425fe77 100644
--- a/src/northbridge/via/vx900/early_vx900.c
+++ b/src/northbridge/via/vx900/early_vx900.c
@@ -69,7 +69,7 @@ void vx900_print_strapping_info(void)
{
u8 strap = pci_read_config8(SNMIC, 0x56);
- print_debug("VX900 strapping pins indicate that:\n");
+ printk(BIOS_DEBUG, "VX900 strapping pins indicate that:\n");
printk(BIOS_DEBUG, " ROM is on %s bus\n",
(strap & (1 << 0)) ? "SPI" : "LPC");
printk(BIOS_DEBUG, " Auto reset is %s\n",
@@ -92,13 +92,13 @@ void vx900_print_strapping_info(void)
void vx900_disable_auto_reboot(void)
{
if (pci_read_config8(SNMIC, 0x56) & (1 << 1)) {
- print_debug("Auto-reboot is disabled in hardware\n");
+ printk(BIOS_DEBUG, "Auto-reboot is disabled in hardware\n");
return;
}
/* Disable the GP3 timer, which is the root of all evil */
pci_write_config8(LPC, 0x98, 0);
/* Yep, that's all it takes */
- print_debug("GP3 timer disabled."
+ printk(BIOS_DEBUG, "GP3 timer disabled."
" Auto-reboot should not give you any more trouble.\n");
}
diff --git a/src/northbridge/via/vx900/lpc.c b/src/northbridge/via/vx900/lpc.c
index ac5e4c8..bb2f1b2 100644
--- a/src/northbridge/via/vx900/lpc.c
+++ b/src/northbridge/via/vx900/lpc.c
@@ -146,7 +146,7 @@ static void vx900_lpc_ioapic_setup(device_t dev)
return;
}
- print_debug("VX900 LPC: Setting up the south module IOAPIC.\n");
+ printk(BIOS_DEBUG, "VX900 LPC: Setting up the south module IOAPIC.\n");
/* Enable IOAPIC
* So much work for one line of code. Talk about bloat :)
* The 8259 PIC should still work even if the IOAPIC is enabled, so
diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c
index f9c225d..e1f744c 100644
--- a/src/northbridge/via/vx900/northbridge.c
+++ b/src/northbridge/via/vx900/northbridge.c
@@ -80,7 +80,7 @@ static u64 vx900_get_top_of_ram(device_t mcu)
static void killme_debug_4g_remap_reg(u32 reg32)
{
if (reg32 & (1 << 0))
- print_debug("Mem remapping enabled\n");
+ printk(BIOS_DEBUG, "Mem remapping enabled\n");
u64 remapstart = (reg32 >> 2) & 0x3ff;
u64 remapend = (reg32 >> 14) & 0x3ff;
remapstart <<= 26;
@@ -122,7 +122,7 @@ static u64 vx900_remap_above_4g(device_t mcu, u32 tolm)
* becomes accessible at "to" to "until"
*/
if (tolm >= vx900_get_top_of_ram(mcu)) {
- print_debug("Nothing to remap\n");
+ printk(BIOS_DEBUG, "Nothing to remap\n");
}
/* This is how the Vendor BIOS. Keep it for comparison for now */
@@ -220,11 +220,11 @@ static void vx900_set_resources(device_t dev)
{
u32 pci_tolm, tomk, vx900_tolm, full_tolmk, fbufk, tolmk;
- print_debug("========================================"
+ printk(BIOS_DEBUG, "========================================"
"========================================\n");
- print_debug("============= VX900 memory sizing & Co. "
+ printk(BIOS_DEBUG, "============= VX900 memory sizing & Co. "
"========================================\n");
- print_debug("========================================"
+ printk(BIOS_DEBUG, "========================================"
"========================================\n");
int idx = 10;
@@ -282,7 +282,7 @@ static void vx900_set_resources(device_t dev)
set_top_of_ram(tolmk << 10);
- print_debug("======================================================\n");
+ printk(BIOS_DEBUG, "======================================================\n");
assign_resources(dev->link_list);
}
diff --git a/src/northbridge/via/vx900/pcie.c b/src/northbridge/via/vx900/pcie.c
index 109e5c9..b748c39 100644
--- a/src/northbridge/via/vx900/pcie.c
+++ b/src/northbridge/via/vx900/pcie.c
@@ -72,11 +72,11 @@ static void vx900_pcie_link_init(device_t dev)
pci_write_config8(dev, 0xa4, 0xff);
if (pci_read_config8(dev, 0x4a) & (1 << 3))
- print_debug("Unsupported request detected.\n");
+ printk(BIOS_DEBUG, "Unsupported request detected.\n");
pci_write_config8(dev, 0x15a, 0xff);
if (pci_read_config8(dev, 0x15a) & (1 << 1))
- print_debug("Negotiation pending.\n");
+ printk(BIOS_DEBUG, "Negotiation pending.\n");
/* Step 4: Read vendor ID */
/* FIXME: Do we want to run through the whole sequence and delay boot
diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c
index e6dace3..d1b2beb 100644
--- a/src/northbridge/via/vx900/raminit_ddr3.c
+++ b/src/northbridge/via/vx900/raminit_ddr3.c
@@ -1512,7 +1512,7 @@ static void vx900_dram_range(ramctr_timing * ctrl, rank_layout * ranks)
/* vvvvvvvvvv FIXME: Fix odd rank init vvvvvvvvvv */
if ((i & 1)) {
printk(BIOS_EMERG, "I cannot initialize rank %zu\n", i);
- print_emerg("I have to disable it\n");
+ printk(BIOS_EMERG, "I have to disable it\n");
continue;
}
/* ^^^^^^^^^^ FIXME: Fix odd rank init ^^^^^^^^^^ */
diff --git a/src/northbridge/via/vx900/sata.c b/src/northbridge/via/vx900/sata.c
index 63295e5..c5f36a8 100644
--- a/src/northbridge/via/vx900/sata.c
+++ b/src/northbridge/via/vx900/sata.c
@@ -44,47 +44,47 @@ static void vx900_print_sata_errors(u32 flags)
(flags & (1 << 27)) ? "detected" : "not detected");
/* Errors */
if (flags & (1 << 0))
- print_debug("\tRecovered data integrity ERROR\n");
+ printk(BIOS_DEBUG, "\tRecovered data integrity ERROR\n");
if (flags & (1 << 1))
- print_debug("\tRecovered data communication ERROR\n");
+ printk(BIOS_DEBUG, "\tRecovered data communication ERROR\n");
if (flags & (1 << 8))
- print_debug("\tNon-recovered Transient Data Integrity ERROR\n");
+ printk(BIOS_DEBUG, "\tNon-recovered Transient Data Integrity ERROR\n");
if (flags & (1 << 9))
- print_debug("\tNon-recovered Persistent Communication or"
+ printk(BIOS_DEBUG, "\tNon-recovered Persistent Communication or"
"\tData Integrity ERROR\n");
if (flags & (1 << 10))
- print_debug("\tProtocol ERROR\n");
+ printk(BIOS_DEBUG, "\tProtocol ERROR\n");
if (flags & (1 << 11))
- print_debug("\tInternal ERROR\n");
+ printk(BIOS_DEBUG, "\tInternal ERROR\n");
if (flags & (1 << 17))
- print_debug("\tPHY Internal ERROR\n");
+ printk(BIOS_DEBUG, "\tPHY Internal ERROR\n");
if (flags & (1 << 19))
- print_debug("\t10B to 8B Decode ERROR\n");
+ printk(BIOS_DEBUG, "\t10B to 8B Decode ERROR\n");
if (flags & (1 << 20))
- print_debug("\tDisparity ERROR\n");
+ printk(BIOS_DEBUG, "\tDisparity ERROR\n");
if (flags & (1 << 21))
- print_debug("\tCRC ERROR\n");
+ printk(BIOS_DEBUG, "\tCRC ERROR\n");
if (flags & (1 << 22))
- print_debug("\tHandshake ERROR\n");
+ printk(BIOS_DEBUG, "\tHandshake ERROR\n");
if (flags & (1 << 23))
- print_debug("\tLink Sequence ERROR\n");
+ printk(BIOS_DEBUG, "\tLink Sequence ERROR\n");
if (flags & (1 << 24))
- print_debug("\tTransport State Transition ERROR\n");
+ printk(BIOS_DEBUG, "\tTransport State Transition ERROR\n");
if (flags & (1 << 25))
- print_debug("\tUNRECOGNIZED FIS type\n");
+ printk(BIOS_DEBUG, "\tUNRECOGNIZED FIS type\n");
}
static void vx900_dbg_sata_errors(device_t dev)
{
/* Port 0 */
if (pci_read_config8(dev, 0xa0) & (1 << 0)) {
- print_debug("Device detected in SATA port 0.\n");
+ printk(BIOS_DEBUG, "Device detected in SATA port 0.\n");
u32 flags = pci_read_config32(dev, 0xa8);
vx900_print_sata_errors(flags);
};
/* Port 1 */
if (pci_read_config8(dev, 0xa1) & (1 << 0)) {
- print_debug("Device detected in SATA port 1.\n");
+ printk(BIOS_DEBUG, "Device detected in SATA port 1.\n");
u32 flags = pci_read_config32(dev, 0xac);
vx900_print_sata_errors(flags);
};
@@ -147,21 +147,18 @@ static void vx900_sata_write_phy_config(device_t dev, sata_phy_config cfg)
static void vx900_sata_dump_phy_config(sata_phy_config cfg)
{
- print_debug("SATA PHY config:\n");
+ printk(BIOS_DEBUG, "SATA PHY config:\n");
int i;
for (i = 0; i < sizeof(sata_phy_config); i++) {
unsigned char val;
- if ((i & 0x0f) == 0) {
- print_debug_hex8(i);
- print_debug_char(':');
- }
+ if ((i & 0x0f) == 0)
+ printk(BIOS_DEBUG, "%02x:", i);
val = cfg[i];
if ((i & 7) == 0)
- print_debug(" |");
- print_debug_char(' ');
- print_debug_hex8(val);
+ printk(BIOS_DEBUG, " |");
+ printk(BIOS_DEBUG, " %02x", val);
if ((i & 0x0f) == 0x0f) {
- print_debug("\n");
+ printk(BIOS_DEBUG, "\n");
}
}
}
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New patch to review for coreboot: a68bde2 Move container_of() macro to stddef.h
by Stefan Reinauer 05 Jan '15
by Stefan Reinauer 05 Jan '15
05 Jan '15
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8109
-gerrit
commit a68bde222cd70e1c61f497ff2931611402d1d5e4
Author: Stefan Reinauer <reinauer(a)chromium.org>
Date: Mon Jan 5 11:09:11 2015 -0800
Move container_of() macro to stddef.h
It's not a SPI related macro, hence move it to stddef.h where
other similar macros live.
Change-Id: I1008894af7a272f1bc36d3ae6cee3881132b6ba9
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/include/spi_flash.h | 11 -----------
src/include/stddef.h | 11 +++++++++++
2 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h
index 7cf0229..8b8b0c5 100644
--- a/src/include/spi_flash.h
+++ b/src/include/spi_flash.h
@@ -28,17 +28,6 @@
#include <console/console.h>
#include <spi-generic.h>
-/**
- * container_of - cast a member of a structure out to the containing structure
- * @ptr: the pointer to the member.
- * @type: the type of the container struct this is embedded in.
- * @member: the name of the member within the struct.
- *
- */
-#define container_of(ptr, type, member) ({ \
- const typeof( ((type *)0)->member ) *__mptr = (ptr); \
- (type *)( (char *)__mptr - offsetof(type,member) );})
-
struct spi_flash {
struct spi_slave *spi;
diff --git a/src/include/stddef.h b/src/include/stddef.h
index 137de04..2c41c5e 100644
--- a/src/include/stddef.h
+++ b/src/include/stddef.h
@@ -32,6 +32,17 @@ typedef unsigned int wint_t;
offsetof(struct structure, member) == offset, \
"`struct " #structure "` offset for `" #member "` is not " #offset )
+/**
+ * container_of - cast a member of a structure out to the containing structure
+ * @ptr: the pointer to the member.
+ * @type: the type of the container struct this is embedded in.
+ * @member: the name of the member within the struct.
+ *
+ */
+#define container_of(ptr, type, member) ({ \
+ const typeof( ((type *)0)->member ) *__mptr = (ptr); \
+ (type *)( (char *)__mptr - offsetof(type,member) );})
+
#ifdef __PRE_RAM__
#define ROMSTAGE_CONST const
#else
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