coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 61c5e46 samus: Updates for P2 board
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8131 -gerrit commit 61c5e461cfee4250f48afb50558383bbf3613c48 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 10 10:06:46 2014 -0700 samus: Updates for P2 board - RAM ID3 moved to GPIO65 to avoid Top Block Swap strap on GPIO66 - LTE_POWER_ON connection removed BUG=chrome-os-partner:29502 BRANCH=None TEST=none yet, preparing for new board Original-Change-Id: I521fe963cbed57ef5f56cfb0e89aec50bfc48b21 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203186 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 1eb65e058307a172f0af9c27d2d2d87d1b78c514) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibf16dcfd83242c487232f34a310c9f6b2cb69314 --- src/mainboard/google/samus/gpio.h | 6 +++--- src/mainboard/google/samus/spd/spd.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index f68ecdf..af3955f 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -90,12 +90,12 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ - PCH_GPIO_UNUSED, /* 65: UNUSED */ - PCH_GPIO_INPUT, /* 66: RAM_ID3 */ + PCH_GPIO_INPUT, /* 65: RAM_ID3 */ + PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */ - PCH_GPIO_OUT_HIGH, /* 70: LTE_POWER_ON */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ PCH_GPIO_UNUSED, /* 72: UNUSED */ PCH_GPIO_UNUSED, /* 73: UNUSED */ diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 77540af..82e4f8d 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -36,7 +36,7 @@ #define SPD_GPIO_BIT0 67 #define SPD_GPIO_BIT1 68 #define SPD_GPIO_BIT2 69 -#define SPD_GPIO_BIT3 66 +#define SPD_GPIO_BIT3 65 struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);

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New patch to review for coreboot: 0aea7f2 libpayload: Let GDB stub read/write memory with aligned MMIO words
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8130 -gerrit commit 0aea7f20adf19958d4c65948ac2e979a6a8e2a57 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jul 16 18:39:58 2014 -0700 libpayload: Let GDB stub read/write memory with aligned MMIO words Looks like we got our first SoC that actually insists on using word-sized accesses for its MMIO registers with the Rk3288. This patch changes the GDB command handler for reading and writing memory to always perform word-sized accesses. This isn't really perfect since the remote GDB interface is just not really meant to interact with MMIO (e.g. you shouldn't use this on something with read side effects), but for most of our purposes it should be good enough. BUG=chrome-os-partner:18390 TEST=Remote GDB works on Veyron even when writing MMIO registers. Original-Change-Id: I2ae52636593499f70701582811f1b692c1ea8fcc Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208554 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 028940934e6b45a02122b61bb859588bf8671938) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4185a6efe9a5211525781acd0a167b821e854211 --- payloads/libpayload/gdb/transport.c | 37 +++++++++++++++++++++++++++---------- 1 file changed, 27 insertions(+), 10 deletions(-) diff --git a/payloads/libpayload/gdb/transport.c b/payloads/libpayload/gdb/transport.c index 596ceb5..22983e1 100644 --- a/payloads/libpayload/gdb/transport.c +++ b/payloads/libpayload/gdb/transport.c @@ -16,9 +16,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <endian.h> #include <gdb.h> #include <libpayload.h> +/* MMIO word size is not standardized, but *usually* 32 (even on ARM64) */ +typedef u32 mmio_word_t; + static const int timeout_us = 100 * 1000; static const char output_overrun[] = "GDB output buffer overrun (try " "increasing reply.size)!\n"; @@ -55,7 +59,7 @@ void gdb_transport_teardown(void) /* Hex digit character <-> number conversion (illegal chars undefined!). */ -static s8 from_hex(unsigned char c) +static u8 from_hex(unsigned char c) { static const s8 values[] = { -1, 10, 11, 12, 13, 14, 15, -1, @@ -74,30 +78,43 @@ static char to_hex(u8 v) return digits[v & 0xf]; } -/* Message encode/decode functions */ +/* Message encode/decode functions (must access whole aligned words for MMIO) */ void gdb_message_encode_bytes(struct gdb_message *message, const void *data, int length) { - const u8 *bytes = data; die_if(message->used + length * 2 > message->size, output_overrun); + const mmio_word_t *aligned = + (mmio_word_t *)ALIGN_DOWN((uintptr_t)data, sizeof(*aligned)); + mmio_word_t word = be32toh(readl(aligned++)); while (length--) { - message->buf[message->used++] = to_hex(*bytes >> 4); - message->buf[message->used++] = to_hex(*bytes & 0xf); - bytes++; + u8 byte = (word >> ((((void *)aligned - data) - 1) * 8)); + message->buf[message->used++] = to_hex(byte >> 4); + message->buf[message->used++] = to_hex(byte & 0xf); + if (length && ++data == (void *)aligned) + word = be32toh(readl(aligned++)); } } void gdb_message_decode_bytes(const struct gdb_message *message, int offset, void *data, int length) { - u8 *bytes = data; die_if(offset + 2 * length > message->used, "Decode overrun in GDB " "message: %.*s", message->used, message->buf); + mmio_word_t *aligned = + (mmio_word_t *)ALIGN_DOWN((uintptr_t)data, sizeof(*aligned)); + int shift = ((void *)(aligned + 1) - data) * 8; + mmio_word_t word = be32toh(readl(aligned)) >> shift; while (length--) { - *bytes = from_hex(message->buf[offset++]) << 4; - *bytes += from_hex(message->buf[offset++]); - bytes++; + word <<= 8; + word |= from_hex(message->buf[offset++]) << 4; + word |= from_hex(message->buf[offset++]); + if (++data - (void *)aligned == sizeof(*aligned)) + writel(htobe32(word), aligned++); + } + if (data != (void *)aligned) { + shift = ((void *)(aligned + 1) - data) * 8; + clrsetbits_be32(aligned, ~((1 << shift) - 1), word << shift); } }

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New patch to review for coreboot: d931e02 libpayload: Expand setbits_le32() and fix readl() const-ness
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8129 -gerrit commit d931e027f1e34e8def418180ba4bc602ccad3c3b Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jul 17 10:43:15 2014 -0700 libpayload: Expand setbits_le32() and fix readl() const-ness setbits_le32() is not really arch-specific... the arch-specific part of accessing memory is wrapped by readl() and writel(), and the endianness can be accounted for with the right macros. Generalize the definitions, add a be32 version and move them to endian.h so that all platforms can use them. Also include endian.h from libpayload.h so we won't update any payload's old use of the macros (endianness is something useful enough to always have avalable anyway, and shouldn't clash with other things). This also fixes a bug where these macros would only be available if libpayload-config.h had been independently included before. Also fix a bug with readl() macros on all archs where they refused to work on const pointers (which they should). CQ-DEPEND=CL:208712 BUG=None TEST=Stuff still compiles. Built and booted on Storm. Original-Change-Id: I01a7fbadbb5d740675657d95c1e969027562ba8c Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/208713 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 951f8a6d77bc21bd793bf4f228a0965ade586f00) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I51c25f01b200b91abbe32c879905349bb05dc9c8 --- payloads/libpayload/include/arm/arch/io.h | 24 ++++++------------------ payloads/libpayload/include/arm64/arch/io.h | 12 ++++++------ payloads/libpayload/include/endian.h | 17 +++++++++++++++++ payloads/libpayload/include/libpayload.h | 1 + payloads/libpayload/include/x86/arch/io.h | 6 +++--- 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/payloads/libpayload/include/arm/arch/io.h b/payloads/libpayload/include/arm/arch/io.h index 5cb66dc..4b0a687 100644 --- a/payloads/libpayload/include/arm/arch/io.h +++ b/payloads/libpayload/include/arm/arch/io.h @@ -34,22 +34,22 @@ #include <stdint.h> #include <arch/cache.h> -static inline uint8_t readb(volatile void *_a) +static inline uint8_t readb(volatile const void *_a) { dmb(); - return *(volatile uint8_t *)_a; + return *(volatile const uint8_t *)_a; } -static inline uint16_t readw(volatile void *_a) +static inline uint16_t readw(volatile const void *_a) { dmb(); - return *(volatile uint16_t *)_a; + return *(volatile const uint16_t *)_a; } -static inline uint32_t readl(volatile void *_a) +static inline uint32_t readl(volatile const void *_a) { dmb(); - return *(volatile uint32_t *)_a; + return *(volatile const uint32_t *)_a; } static inline void writeb(uint8_t _v, volatile void *_a) @@ -73,17 +73,5 @@ static inline void writel(uint32_t _v, volatile void *_a) dmb(); } -/* - * Handy bit manipulation macros, BE version will have to be added when/if - * needed. - */ - -#ifdef CONFIG_LP_LITTLE_ENDIAN -#define clrsetbits_le32(addr, clear, set) writel((readl(addr) & ~(clear)) |\ - (set), (addr)) -#define setbits_le32(addr, set) writel(readl(addr) | (set), (addr)) -#define clrbits_le32(addr, clear) writel(readl(addr) & ~(clear), (addr)) -#endif - #endif diff --git a/payloads/libpayload/include/arm64/arch/io.h b/payloads/libpayload/include/arm64/arch/io.h index 8948e13..df3a0d5 100644 --- a/payloads/libpayload/include/arm64/arch/io.h +++ b/payloads/libpayload/include/arm64/arch/io.h @@ -34,22 +34,22 @@ #include <stdint.h> #include <arch/cache.h> -static inline uint8_t readb(volatile void *_a) +static inline uint8_t readb(volatile const void *_a) { dmb(); - return *(volatile uint8_t *)_a; + return *(volatile const uint8_t *)_a; } -static inline uint16_t readw(volatile void *_a) +static inline uint16_t readw(volatile const void *_a) { dmb(); - return *(volatile uint16_t *)_a; + return *(volatile const uint16_t *)_a; } -static inline uint32_t readl(volatile void *_a) +static inline uint32_t readl(volatile const void *_a) { dmb(); - return *(volatile uint32_t *)_a; + return *(volatile const uint32_t *)_a; } static inline void writeb(uint8_t _v, volatile void *_a) diff --git a/payloads/libpayload/include/endian.h b/payloads/libpayload/include/endian.h index dd4d9fa..3b79393 100644 --- a/payloads/libpayload/include/endian.h +++ b/payloads/libpayload/include/endian.h @@ -30,6 +30,7 @@ #ifndef _ENDIAN_H_ #define _ENDIAN_H_ +#include <arch/io.h> #include <arch/types.h> #include <libpayload-config.h> @@ -178,4 +179,20 @@ static inline void le32enc(void *pp, uint32_t u) #define letohl(in) le32toh(in) #define letohll(in) le64toh(in) +/* Handy bit manipulation macros */ + +#define clrsetbits_le32(addr, clear, set) writel(htole32((le32toh(readl(addr)) \ + & ~(clear)) | (set)), (addr)) +#define setbits_le32(addr, set) writel(htole32(le32toh(readl(addr)) \ + | (set)), (addr)) +#define clrbits_le32(addr, clear) writel(htole32(le32toh(readl(addr)) \ + & ~(clear)), (addr)) + +#define clrsetbits_be32(addr, clear, set) writel(htobe32((be32toh(readl(addr)) \ + & ~(clear)) | (set)), (addr)) +#define setbits_be32(addr, set) writel(htobe32(be32toh(readl(addr)) \ + | (set)), (addr)) +#define clrbits_be32(addr, clear) writel(htobe32(be32toh(readl(addr)) \ + & ~(clear)), (addr)) + #endif /* _ENDIAN_H_ */ diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 21b9da7..5bdd55d 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -46,6 +46,7 @@ #include <libpayload-config.h> #include <ctype.h> #include <die.h> +#include <endian.h> #include <ipchksum.h> #include <stddef.h> #include <stdio.h> diff --git a/payloads/libpayload/include/x86/arch/io.h b/payloads/libpayload/include/x86/arch/io.h index bcfd307..0cb610f 100644 --- a/payloads/libpayload/include/x86/arch/io.h +++ b/payloads/libpayload/include/x86/arch/io.h @@ -31,9 +31,9 @@ #ifndef _ARCH_IO_H #define _ARCH_IO_H -#define readb(_a) (*(volatile unsigned char *) (_a)) -#define readw(_a) (*(volatile unsigned short *) (_a)) -#define readl(_a) (*(volatile unsigned long *) (_a)) +#define readb(_a) (*(volatile const unsigned char *) (_a)) +#define readw(_a) (*(volatile const unsigned short *) (_a)) +#define readl(_a) (*(volatile const unsigned long *) (_a)) #define writeb(_v, _a) (*(volatile unsigned char *) (_a) = (_v)) #define writew(_v, _a) (*(volatile unsigned short *) (_a) = (_v))

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New patch to review for coreboot: 1fae97e libpayload: improve us timer accuracy
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8128 -gerrit commit 1fae97eec67c0b01eb3a0523ae5b8872d5213c07 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jul 10 12:49:46 2014 -0700 libpayload: improve us timer accuracy In cases where timer clock frequency is not an integer number of megahertz, the calculations in timer_us() lack accuracy. This patch modifies calculations to reduce the error. The maximum interval this calculation would support decreases, but it still is in excess of 1844674 seconds for a timer clocked by 10 MHz, which is more than enough. BUG=none TEST=manual . verified timer accuracy using a depthcharge CLI command Original-Change-Id: Iffb323db10e74b0ce3b4d59a56983bfee12e6805 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/207358 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit e1abf87d438de1a04714482d5b610671e8cc0663) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia892726187ab040dd235f493c92856c15951cc06 --- payloads/libpayload/libc/time.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 0d81634..8d07c4f 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -204,5 +204,5 @@ u64 timer_us(u64 base) } } - return timer_raw_value() / (hz / 1000000) - base; + return (1000000 * timer_raw_value()) / hz - base; }

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New patch to review for coreboot: 0f0e99a libpayload: Add Rock Chip drivers
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8127 -gerrit commit 0f0e99a8558ac858732c151371c09ecb7120b619 Author: huang lin <hl(a)rock-chips.com> Date: Fri Jun 20 11:34:46 2014 +0800 libpayload: Add Rock Chip drivers Add support: 1)Support driver rktimer 2)Support driver rkserial BUG=chrome-os-partner:29778 TEST=emerge-veyron libpayload Original-Change-Id: I2cccedf3b62883dd372842a7972e93f2ebbfb282 Original-Signed-off-by: huang lin <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/206184 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 387450d7c36b201bd177d46eb9f1d280fc043aab) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia6b7a8ee2439a6f2bf7577df822d3f4f3a1e441c --- payloads/libpayload/Config.in | 12 +++ payloads/libpayload/configs/config.arm64-generic | 1 + payloads/libpayload/configs/defconfig | 5 +- payloads/libpayload/configs/defconfig-arm | 4 +- payloads/libpayload/drivers/Makefile.inc | 3 +- payloads/libpayload/drivers/serial/rk_serial.c | 115 +++++++++++++++++++++++ payloads/libpayload/drivers/timer/rktimer.c | 44 +++++++++ 7 files changed, 180 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index a0889c8..6c95bfa 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -199,6 +199,11 @@ config TEGRA_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config RK_SERIAL_CONSOLE + bool "Rockchip SOC serial port driver" + depends on SERIAL_CONSOLE + default n + config IPQ806X_SERIAL_CONSOLE bool "IPQ806x SOC compatible serial port driver" depends on SERIAL_CONSOLE @@ -383,6 +388,8 @@ config TIMER_TEGRA_1US config TIMER_IPQ806X bool "Timer for ipq806x platforms" +config TIMER_RK + bool "Timer for Rockchip" endchoice config TIMER_MCT_HZ @@ -395,6 +402,11 @@ config TIMER_MCT_ADDRESS depends on TIMER_MCT default 0x101c0000 +config TIMER_RK_ADDRESS + hex "Rockchip timer base address" + depends on TIMER_RK + default 0xff810020 + config TIMER_TEGRA_1US_ADDRESS hex "Tegra u1s timer base address" depends on TIMER_TEGRA_1US diff --git a/payloads/libpayload/configs/config.arm64-generic b/payloads/libpayload/configs/config.arm64-generic index 97d865b..c2285fe 100644 --- a/payloads/libpayload/configs/config.arm64-generic +++ b/payloads/libpayload/configs/config.arm64-generic @@ -48,6 +48,7 @@ CONFIG_LP_TIMER_NONE=y # CONFIG_LP_TIMER_MCT is not set # CONFIG_LP_TIMER_TEGRA_1US is not set # CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_RK is not set CONFIG_LP_USB=y # CONFIG_LP_USB_OHCI is not set CONFIG_LP_USB_EHCI=y diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 1fbd961..a09a78c 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Wed Dec 31 11:36:31 2014 +# Mon Jan 5 15:27:43 2015 # # @@ -17,8 +17,8 @@ # Architecture Options # # CONFIG_LP_ARCH_ARM is not set -# CONFIG_LP_ARCH_ARM64 is not set CONFIG_LP_ARCH_X86=y +# CONFIG_LP_ARCH_ARM64 is not set # CONFIG_LP_MEMMAP_RAM_ONLY is not set # CONFIG_LP_MULTIBOOT is not set @@ -41,6 +41,7 @@ CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_8250_SERIAL_CONSOLE=y # CONFIG_LP_S5P_SERIAL_CONSOLE is not set # CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_RK_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_PL011_SERIAL_CONSOLE is not set CONFIG_LP_SERIAL_IOBASE=0x3f8 diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index 862443d..b765422 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Mon Jan 5 15:06:15 2015 +# Mon Jan 5 15:28:18 2015 # # @@ -40,6 +40,7 @@ CONFIG_LP_SERIAL_CONSOLE=y # CONFIG_LP_8250_SERIAL_CONSOLE is not set # CONFIG_LP_S5P_SERIAL_CONSOLE is not set # CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_RK_SERIAL_CONSOLE is not set # CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_SERIAL_SET_SPEED is not set # CONFIG_LP_SERIAL_ACS_FALLBACK is not set @@ -59,6 +60,7 @@ CONFIG_LP_TIMER_NONE=y # CONFIG_LP_TIMER_MCT is not set # CONFIG_LP_TIMER_TEGRA_1US is not set # CONFIG_LP_TIMER_IPQ806X is not set +# CONFIG_LP_TIMER_RK is not set CONFIG_LP_USB=y CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 538a8a6..0fc2faa 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -37,7 +37,7 @@ libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c - +libc-$(CONFIG_LP_RK_SERIAL_CONSOLE) += serial/rk_serial.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c libc-$(CONFIG_LP_CBMEM_CONSOLE) += cbmem_console.c @@ -50,6 +50,7 @@ libc-$(CONFIG_LP_TIMER_MCT) += timer/mct.c libc-$(CONFIG_LP_TIMER_RDTSC) += timer/rdtsc.c libc-$(CONFIG_LP_TIMER_TEGRA_1US) += timer/tegra_1us.c libc-$(CONFIG_LP_TIMER_IPQ806X) += timer/ipq806x.c +libc-$(CONFIG_LP_TIMER_RK) += timer/rktimer.c # Video console drivers libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c diff --git a/payloads/libpayload/drivers/serial/rk_serial.c b/payloads/libpayload/drivers/serial/rk_serial.c new file mode 100644 index 0000000..8c3f679 --- /dev/null +++ b/payloads/libpayload/drivers/serial/rk_serial.c @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Rockchip Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <libpayload-config.h> +#include <libpayload.h> +struct rk_uart { + union { + u32 uart_thr; /*Transmit holding register.*/ + u32 uart_rbr; /*Receive buffer register.*/ + u32 uart_dll; /* Divisor latch lsb.*/ + }; + union { + u32 uart_ier; /*Interrupt enable register.*/ + u32 uart_dlh; /* Divisor latch msb.*/ + }; + union { + uint32_t uart_iir; /*Interrupt identification register.*/ + uint32_t uart_fcr; /* FIFO control register.*/ + }; + u32 uart_lcr; + u32 uart_mcr; + u32 uart_lsr; + u32 uart_msr; + u32 uart_scr; + u32 reserved1[(0x30 - 0x20) / 4]; + u32 uart_srbr[(0x70 - 0x30) / 4]; + u32 uart_far; + u32 uart_tfr; + u32 uart_rfw; + u32 uart_usr; + u32 uart_tfl; + u32 uart_rfl; + u32 uart_srr; + u32 uart_srts; + u32 uart_sbcr; + u32 uart_sdmam; + u32 uart_sfe; + u32 uart_srt; + u32 uart_stet; + u32 uart_htx; + u32 uart_dmasa; + u32 reserver2[(0xf4 - 0xac) / 4]; + u32 uart_cpr; + u32 uart_ucv; + u32 uart_ctr; +}; +enum { + UART_LSR_DR = 0x1 << 0, /*Data ready.*/ + UART_LSR_OE = 0x1 << 1, /*Overrun.*/ + UART_LSR_PE = 0x1 << 2, /*Parity error.*/ + UART_LSR_FE = 0x1 << 3, /*Framing error.*/ + UART_LSR_BI = 0x1 << 4, /*Break.*/ + UART_LSR_THRE = 0x1 << 5, /*Xmit holding register empty.*/ + UART_LSR_TEMT = 0x1 << 6, /*Xmitter empty.*/ + UART_LSR_ERR = 0x1 << 7 /* Error.*/ +}; + +static struct rk_uart *uart_regs; +void serial_putchar(unsigned int c) +{ + while (!(readl(&uart_regs->uart_lsr) & UART_LSR_THRE)); + writel((c&0xff), &uart_regs->uart_thr); + if (c == '\n') + serial_putchar('\r'); +} + +int serial_havechar(void) +{ + uint8_t lsr = readl(&uart_regs->uart_lsr); + return (lsr & UART_LSR_DR) == UART_LSR_DR; +} + +int serial_getchar(void) +{ + while (!serial_havechar()); + return readl(&uart_regs->uart_rbr)&0xff; +} + +static struct console_input_driver consin = { + .havekey = &serial_havechar, + .getchar = &serial_getchar +}; + +static struct console_output_driver consout = {.putchar = &serial_putchar +}; + +void serial_init(void) +{ + if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) + return; + + uart_regs = (struct rk_uart *)lib_sysinfo.serial->baseaddr; +} + +void serial_console_init(void) +{ + serial_init(); + console_add_input_driver(&consin); + console_add_output_driver(&consout); +} diff --git a/payloads/libpayload/drivers/timer/rktimer.c b/payloads/libpayload/drivers/timer/rktimer.c new file mode 100644 index 0000000..1634b77 --- /dev/null +++ b/payloads/libpayload/drivers/timer/rktimer.c @@ -0,0 +1,44 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Rockchip Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <arch/io.h> +#include <libpayload.h> +#include <stdint.h> +struct rk_timer { + u32 timer_load_count0; + u32 timer_load_count1; + u32 timer_curr_value0; + u32 timer_curr_value1; + u32 timer_ctrl_reg; + u32 timer_int_status; +}; +uint64_t timer_hz(void) +{ + return 24000000; +} +uint64_t timer_raw_value(void) +{ + uint64_t upper; + uint64_t lower; + struct rk_timer *rk_timer; + rk_timer = (struct rk_timer *)CONFIG_LP_TIMER_RK_ADDRESS; + lower = (uint64_t) rk_timer->timer_curr_value0; + upper = (uint64_t) rk_timer->timer_curr_value1; + return (upper << 32) | lower; +}

1 0

New patch to review for coreboot: 3d2b4f9 libpayload: Reorder default memcpy, speed up memset and memcmp
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8126 -gerrit commit 3d2b4f917024a9924556e0f8c93a180ff028d609 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jun 12 10:28:57 2014 -0700 libpayload: Reorder default memcpy, speed up memset and memcmp The current default memcpy first copies single bytes to align the amount, then copies the rest as full words. In practice, the start of a buffer is much more likely to be word-aligned then the end, and aligned word access are usually more efficient. This patch reorders those accesses to first copy as many full words as possible and then finish the rest with byte accesses to optimize this common case. This fixes a data abort when using USB on ARM without CONFIG_GPL. Due to some limitations of how DMA memory is set up in coreboot on ARM, it currently does not support unaligned accesses. (This could be fixed with a more complicated patch, but it's usually not an issue... unless, of course, your memcpy happens to be braindead). Also add word-aligned accesses to memset and memcmp while I'm at it, and make memcmp's return value standard's compliant. BUG=chrome-os-partner:24957 TEST=Manual Original-Change-Id: I2a7bcb35626a05a9a43fcfd99eb958b485d7622a Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203547 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 05a64d2e107e1675cc3442e6dabe14a341e55673) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I0030ca8a203c97587b0da31a0a5e9e11b0be050f --- payloads/libpayload/libc/memory.c | 63 +++++++++++++++++++++++++-------------- 1 file changed, 40 insertions(+), 23 deletions(-) diff --git a/payloads/libpayload/libc/memory.c b/payloads/libpayload/libc/memory.c index 12d7e33..aec60e4 100644 --- a/payloads/libpayload/libc/memory.c +++ b/payloads/libpayload/libc/memory.c @@ -35,12 +35,22 @@ static void *default_memset(void *s, int c, size_t n) { - char *os = s; + size_t i; + void *ret = s; + unsigned long w = c & 0xff; - while (n--) - *(os++) = c; + for (i = 1; i < sizeof(unsigned long); i <<= 1) + w = (w << (i * 8)) | w; - return s; + for (i = 0; i < n / sizeof(unsigned long); i++) + ((unsigned long *)s)[i] = w; + + s += i * sizeof(unsigned long); + + for (i = 0; i < n % sizeof(unsigned long); i++) + ((u8 *)s)[i] = (u8)c; + + return ret; } void *memset(void *s, int c, size_t n) @@ -48,18 +58,17 @@ void *memset(void *s, int c, size_t n) static void *default_memcpy(void *dst, const void *src, size_t n) { - int i; + size_t i; void *ret = dst; - for(i = 0; i < n % sizeof(unsigned long); i++) - ((unsigned char *) dst)[i] = ((unsigned char *) src)[i]; + for(i = 0; i < n / sizeof(unsigned long); i++) + ((unsigned long *)dst)[i] = ((unsigned long *)src)[i]; - n -= i; - src += i; - dst += i; + src += i * sizeof(unsigned long); + dst += i * sizeof(unsigned long); - for(i = 0; i < n / sizeof(unsigned long); i++) - ((unsigned long *) dst)[i] = ((unsigned long *) src)[i]; + for(i = 0; i < n % sizeof(unsigned long); i++) + ((u8 *)dst)[i] = ((u8 *)src)[i]; return ret; } @@ -69,8 +78,7 @@ void *memcpy(void *dst, const void *src, size_t n) static void *default_memmove(void *dst, const void *src, size_t n) { - int i; - unsigned long offs; + size_t i, offs; if (src > dst) return memcpy(dst, src, n); @@ -78,8 +86,7 @@ static void *default_memmove(void *dst, const void *src, size_t n) offs = n - (n % sizeof(unsigned long)); for (i = (n % sizeof(unsigned long)) - 1; i >= 0; i--) - ((unsigned char *)dst)[i + offs] = - ((unsigned char *)src)[i + offs]; + ((u8 *)dst)[i + offs] = ((u8 *)src)[i + offs]; for (i = n / sizeof(unsigned long) - 1; i >= 0; i--) ((unsigned long *)dst)[i] = ((unsigned long *)src)[i]; @@ -95,17 +102,27 @@ void *memmove(void *dst, const void *src, size_t n) * * @param s1 Pointer to the first area to compare. * @param s2 Pointer to the second area to compare. - * @param len Size of the first area in bytes (both must have the same length). - * @return If len is 0, return zero. If the areas match, return zero. - * Otherwise return non-zero. + * @param n Size of the first area in bytes (both must have the same length). + * @return If n is 0, return zero. Otherwise, return a value less than, equal + * to, or greater than zero if s1 is found less than, equal to, or + * greater than s2 respectively. */ -static int default_memcmp(const void *s1, const void *s2, size_t len) +static int default_memcmp(const void *s1, const void *s2, size_t n) { - for (; len && *(char *)s1++ == *(char *)s2++; len--) ; - return len; + size_t i; + + for (i = 0; i < n / sizeof(unsigned long); i++) + if (((unsigned long *)s1)[i] != ((unsigned long *)s2)[i]) + break; /* fall through to find differing byte */ + + for (i *= sizeof(unsigned long); i < n; i++) + if (((u8 *)s1)[i] != ((u8 *)s2)[i]) + return ((u8 *)s1)[i] - ((u8 *)s2)[i]; + + return 0; } -int memcmp(const void *s1, const void *s2, size_t len) +int memcmp(const void *s1, const void *s2, size_t n) __attribute__((weak, alias("default_memcmp")));

1 0

New patch to review for coreboot: 7fb1ca8 libpayload arm64: Add gdb stub for arm64
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8125 -gerrit commit 7fb1ca843f3c00c3f50cdf43b319b0a8bbced21e Author: Furquan Shaikh <furquan(a)google.com> Date: Fri Jun 20 00:19:31 2014 -0700 libpayload arm64: Add gdb stub for arm64 Add stub implementation for gdb arm64 support. Currently all functions are kept empty to enable proper compilation of depthcharge and libpayload. As we get more clear about context management and stuff, we can add details for gdb as well. BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I0a8729671ab0764d424c0e3d50af86433d05b1e8 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204877 Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit d24e5c26b56a9882b3450b1e4988b56c3d73efd1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9b7d3d7060dd827ef4a46865e0f9a2b4e063d07d --- payloads/libpayload/arch/arm64/Makefile.inc | 2 + payloads/libpayload/arch/arm64/gdb.c | 69 +++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/payloads/libpayload/arch/arm64/Makefile.inc b/payloads/libpayload/arch/arm64/Makefile.inc index 7107d0c..bb09b8f 100644 --- a/payloads/libpayload/arch/arm64/Makefile.inc +++ b/payloads/libpayload/arch/arm64/Makefile.inc @@ -40,6 +40,8 @@ libc-y += cache.c cpu.S libc-y += selfboot.c libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c +libgdb-y += gdb.c + # Add other classes here when you put assembly files into them! head.o-S-ccopts += $(arm64_asm_flags) libc-S-ccopts += $(arm64_asm_flags) diff --git a/payloads/libpayload/arch/arm64/gdb.c b/payloads/libpayload/arch/arm64/gdb.c new file mode 100644 index 0000000..857272f --- /dev/null +++ b/payloads/libpayload/arch/arm64/gdb.c @@ -0,0 +1,69 @@ +/* + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but without any warranty; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <exception.h> +#include <gdb.h> +#include <libpayload.h> + +struct gdb_regs +{ + u64 x[32]; + struct fp_reg + { + u64 quad[2]; + } __attribute__((packed)) f[32]; + u32 fpcr; + u32 fpsr; + u32 spsr; +} __attribute__((packed)); + +static const u8 type_to_signal[] = { + [EXC_INV] = GDB_SIGILL, + [EXC_SYNC] = GDB_SIGTRAP, + [EXC_IRQ] = GDB_SIGSEGV, + [EXC_FIQ] = GDB_SIGSEGV, + [EXC_SERROR] = GDB_SIGSEGV +}; + +static int gdb_exception_hook(u32 type) +{ + return -1; +} + +void gdb_arch_init(void) +{ + exception_install_hook(&gdb_exception_hook); +} + +void gdb_arch_enter(void) +{ +} + +int gdb_arch_set_single_step(int on) +{ + /* GDB seems to only need this on x86, ARM works fine without it. */ + return -1; +} + +void gdb_arch_encode_regs(struct gdb_message *message) +{ +} + +void gdb_arch_decode_regs(int offset, struct gdb_message *message) +{ +}

1 0

New patch to review for coreboot: c25b65b libpayload arm64: Add selfboot.c required by depthcharge
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8124 -gerrit commit c25b65b544007a5531b7366ad0808cd36b399476 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 18 17:01:01 2014 -0700 libpayload arm64: Add selfboot.c required by depthcharge BUG=None BRANCH=None TEST=Compiles successfully Original-Change-Id: I2569cadf2d34f7211892f100ba715486d824b921 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204611 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit dd9e06e41da043a48b469a011c010a10a1a3b25a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I37fbc8cfea0870e7167ffa47dd63fc548e18c82e --- payloads/libpayload/arch/arm64/Makefile.inc | 1 + payloads/libpayload/arch/arm64/selfboot.c | 34 +++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/payloads/libpayload/arch/arm64/Makefile.inc b/payloads/libpayload/arch/arm64/Makefile.inc index 45582e0..7107d0c 100644 --- a/payloads/libpayload/arch/arm64/Makefile.inc +++ b/payloads/libpayload/arch/arm64/Makefile.inc @@ -37,6 +37,7 @@ libc-y += virtual.c libc-y += memcpy.S memset.S memmove.S libc-y += exception_asm.S exception.c libc-y += cache.c cpu.S +libc-y += selfboot.c libcbfs-$(CONFIG_LP_CBFS) += dummy_media.c # Add other classes here when you put assembly files into them! diff --git a/payloads/libpayload/arch/arm64/selfboot.c b/payloads/libpayload/arch/arm64/selfboot.c new file mode 100644 index 0000000..5c3e445 --- /dev/null +++ b/payloads/libpayload/arch/arm64/selfboot.c @@ -0,0 +1,34 @@ +/* + * Copyright 2014 Google Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <libpayload.h> + +void selfboot(void *entry) +{ + void (*entry_func)(void) = entry; + entry_func(); +}

1 0

New patch to review for coreboot: b6eb00b libpayload: Fix baseaddr access in serial/tegra.c
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8123 -gerrit commit b6eb00bc4fc6fe62906be2949e9e25158f66c50f Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 17 17:08:58 2014 -0700 libpayload: Fix baseaddr access in serial/tegra.c Fix baseaddr typecast to allow use in 32- and 64-bit systems BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: Ie5ded744d75a0ae4d1428d04ff2478bdfe54d146 Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204424 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit b56814fe5fc7d3a2fdfb324d4baafb27a9d3ffd6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icedc1c819e39b92a0dd92e98f848e15b3039dfbe --- payloads/libpayload/drivers/serial/tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/drivers/serial/tegra.c b/payloads/libpayload/drivers/serial/tegra.c index fa5ff16..a3dad2b 100644 --- a/payloads/libpayload/drivers/serial/tegra.c +++ b/payloads/libpayload/drivers/serial/tegra.c @@ -99,7 +99,7 @@ void serial_init(void) if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) return; - uart_regs = (struct tegra_uart *)lib_sysinfo.serial->baseaddr; + uart_regs = (struct tegra_uart *)(uintptr_t)lib_sysinfo.serial->baseaddr; } void serial_console_init(void)

1 0

New patch to review for coreboot: 89bb39d libpayload arm64: Correct function names for tlb invalidation
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8122 -gerrit commit 89bb39d28f49b1a5657060d6dd6baec6f9715359 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue Jun 17 17:07:27 2014 -0700 libpayload arm64: Correct function names for tlb invalidation Correct function names to make them consistent with depthcharge calling convention BUG=None BRANCH=None TEST=Compiles successfully for rush Original-Change-Id: I0fd8f7f929c3fe268710362d1fc19f9e15c4a23b Original-Signed-off-by: Furquan Shaikh <furquan(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/204423 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Furquan Shaikh <furquan(a)chromium.org> Original-Tested-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 36008e728b840d85bb98225c7bb1420b993181de) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4b446da8f2c273385ee885c4870966e18ba2a7a6 --- payloads/libpayload/arch/arm64/cache.c | 6 +++--- payloads/libpayload/include/arm64/arch/cache.h | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/arch/arm64/cache.c b/payloads/libpayload/arch/arm64/cache.c index f6faafa..05d6fb2 100644 --- a/payloads/libpayload/arch/arm64/cache.c +++ b/payloads/libpayload/arch/arm64/cache.c @@ -101,17 +101,17 @@ static void dcache_op_va(void const *addr, size_t len, enum dcache_op op) isb(); } -void dcache_clean_by_va(void const *addr, size_t len) +void dcache_clean_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCVAC); } -void dcache_clean_invalidate_by_va(void const *addr, size_t len) +void dcache_clean_invalidate_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCCIVAC); } -void dcache_invalidate_by_va(void const *addr, size_t len) +void dcache_invalidate_by_mva(void const *addr, size_t len) { dcache_op_va(addr, len, OP_DCIVAC); } diff --git a/payloads/libpayload/include/arm64/arch/cache.h b/payloads/libpayload/include/arm64/arch/cache.h index d1fc1aa..2d3175e 100644 --- a/payloads/libpayload/include/arm64/arch/cache.h +++ b/payloads/libpayload/include/arm64/arch/cache.h @@ -209,13 +209,13 @@ static inline void write_sctlr_el3(uint32_t val) void dcache_clean_invalidate_all(void); /* dcache clean by virtual address to PoC */ -void dcache_clean_by_va(void const *addr, size_t len); +void dcache_clean_by_mva(void const *addr, size_t len); /* dcache clean and invalidate by virtual address to PoC */ -void dcache_clean_invalidate_by_va(void const *addr, size_t len); +void dcache_clean_invalidate_by_mva(void const *addr, size_t len); /* dcache invalidate by virtual address to PoC */ -void dcache_invalidate_by_va(void const *addr, size_t len); +void dcache_invalidate_by_mva(void const *addr, size_t len); void dcache_clean_all(void);

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coreboot-gerrit January 2015