coreboot-gerrit January 2015

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Patch set updated for coreboot: cc7cca7 {north, south}bridge/*: Use system include path syntax over relative local
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8104 -gerrit commit cc7cca7621db36040e480285901a91cc86fa4d27 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 02:44:20 2015 +1100 {north,south}bridge/*: Use system include path syntax over relative local Change-Id: Ib7fe3a9d672a02c9a91e3b320fefdbd98fd16cff Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/gx2/northbridge.c | 2 +- src/northbridge/amd/lx/northbridge.c | 2 +- src/northbridge/amd/lx/raminit.c | 2 +- src/northbridge/intel/gm45/gm45.h | 2 +- src/northbridge/intel/gm45/gma.c | 2 +- src/northbridge/intel/haswell/report_platform.c | 2 +- src/northbridge/intel/i945/i945.h | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit_native.c | 8 ++++---- src/northbridge/intel/sandybridge/report_platform.c | 2 +- src/northbridge/intel/sandybridge/romstage_native.c | 4 ++-- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cs5535/chipsetinit.c | 4 ++-- src/southbridge/dmp/vortex86ex/southbridge.c | 4 ++-- src/southbridge/intel/bd82x6x/early_pch_native.c | 2 +- src/southbridge/intel/bd82x6x/early_rcba.c | 2 +- src/southbridge/intel/bd82x6x/early_thermal.c | 2 +- src/southbridge/intel/bd82x6x/early_usb_native.c | 2 +- src/southbridge/intel/bd82x6x/nvs.h | 3 ++- src/southbridge/intel/bd82x6x/smi.c | 3 +-- src/southbridge/intel/fsp_bd82x6x/nvs.h | 3 ++- src/southbridge/intel/fsp_bd82x6x/smi.c | 2 +- src/southbridge/intel/fsp_rangeley/romstage.c | 8 ++++---- src/southbridge/intel/ibexpeak/early_thermal.c | 2 +- src/southbridge/intel/ibexpeak/nvs.h | 3 ++- src/southbridge/intel/ibexpeak/smi.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- src/southbridge/intel/lynxpoint/nvs.h | 3 ++- 29 files changed, 42 insertions(+), 39 deletions(-) diff --git a/src/northbridge/amd/gx2/northbridge.c b/src/northbridge/amd/gx2/northbridge.c index a48226d..aa09e08 100644 --- a/src/northbridge/amd/gx2/northbridge.c +++ b/src/northbridge/amd/gx2/northbridge.c @@ -31,7 +31,7 @@ #include <cpu/x86/cache.h> #include <cpu/amd/vr.h> #include <cpu/cpu.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> void print_conf(void); diff --git a/src/northbridge/amd/lx/northbridge.c b/src/northbridge/amd/lx/northbridge.c index 4e84025..c4214ad 100644 --- a/src/northbridge/amd/lx/northbridge.c +++ b/src/northbridge/amd/lx/northbridge.c @@ -33,7 +33,7 @@ #include <cpu/amd/vr.h> #include <cpu/cpu.h> #include "northbridge.h" -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> /* here is programming for the various MSRs.*/ diff --git a/src/northbridge/amd/lx/raminit.c b/src/northbridge/amd/lx/raminit.c index 7c95ab4..656c6e5 100644 --- a/src/northbridge/amd/lx/raminit.c +++ b/src/northbridge/amd/lx/raminit.c @@ -22,7 +22,7 @@ #include <cpu/amd/lxdef.h> #include <arch/io.h> #include <spd.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "raminit.h" #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 0eaa629..4e50aba 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -21,7 +21,7 @@ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ #define __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#include "southbridge/intel/i82801ix/i82801ix.h" +#include <southbridge/intel/i82801ix/i82801ix.h> #include <stdint.h> #ifndef __ACPI__ diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 74e16ad..e366c3f 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -30,7 +30,7 @@ #include <cpu/x86/mtrr.h> #include <kconfig.h> -#include "drivers/intel/gma/i915_reg.h" +#include <drivers/intel/gma/i915_reg.h> #include "chip.h" #include "gm45.h" #include <drivers/intel/gma/intel_bios.h> diff --git a/src/northbridge/intel/haswell/report_platform.c b/src/northbridge/intel/haswell/report_platform.c index 8bb4a05..33da3b5 100644 --- a/src/northbridge/intel/haswell/report_platform.c +++ b/src/northbridge/intel/haswell/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/lynxpoint/pch.h" +#include <southbridge/intel/lynxpoint/pch.h> #include <arch/io.h> #include <cpu/x86/msr.h> #include "haswell.h" diff --git a/src/northbridge/intel/i945/i945.h b/src/northbridge/intel/i945/i945.h index fe59ebe..651b75a 100644 --- a/src/northbridge/intel/i945/i945.h +++ b/src/northbridge/intel/i945/i945.h @@ -27,7 +27,7 @@ #define DEFAULT_DMIBAR 0xfed18000 /* 4 KB */ #define DEFAULT_EPBAR 0xfed19000 /* 4 KB */ -#include "../../../southbridge/intel/i82801gx/i82801gx.h" +#include <southbridge/intel/i82801gx/i82801gx.h> /* Everything below this line is ignored in the DSDT */ #ifndef __ACPI__ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9ca98d5..7d37cb8 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -55,7 +55,7 @@ typedef u32 device_t; #include "nehalem.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <southbridge/intel/ibexpeak/me.h> #if REAL #include <delay.h> diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index f6c92db..0f13f01 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -34,7 +34,7 @@ #include "sandybridge.h" /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* * MRC scrambler seed offsets should be reserved in diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index de6dac7..77c4005 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -36,11 +36,11 @@ #include <lib.h> /* Management Engine is in the southbridge */ -#include "southbridge/intel/bd82x6x/me.h" +#include <southbridge/intel/bd82x6x/me.h> /* For SPD. */ -#include "southbridge/intel/bd82x6x/smbus.h" -#include "arch/cpu.h" -#include "cpu/x86/msr.h" +#include <southbridge/intel/bd82x6x/smbus.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ diff --git a/src/northbridge/intel/sandybridge/report_platform.c b/src/northbridge/intel/sandybridge/report_platform.c index 8230729..f189697 100644 --- a/src/northbridge/intel/sandybridge/report_platform.c +++ b/src/northbridge/intel/sandybridge/report_platform.c @@ -20,7 +20,7 @@ #include <console/console.h> #include <arch/cpu.h> #include <string.h> -#include "southbridge/intel/bd82x6x/pch.h" +#include <southbridge/intel/bd82x6x/pch.h> #include <arch/io.h> #include "sandybridge.h" diff --git a/src/northbridge/intel/sandybridge/romstage_native.c b/src/northbridge/intel/sandybridge/romstage_native.c index 737cd63..400a079 100644 --- a/src/northbridge/intel/sandybridge/romstage_native.c +++ b/src/northbridge/intel/sandybridge/romstage_native.c @@ -31,8 +31,8 @@ #include <cpu/intel/romstage.h> #include <halt.h> #include "raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> void main(unsigned long bist) { diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index 59d89b0..1a618b5 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -156,7 +156,7 @@ typedef union _PCI_ADDR { #define cimFusionMsgCMultiCoreDefault FALSE #define cimFusionMsgCStageDefault FALSE -#include "vendorcode/amd/cimx/sb800/AMDSBLIB.h" +#include <vendorcode/amd/cimx/sb800/AMDSBLIB.h> #if CONFIG_HAVE_ACPI_RESUME #include <spi-generic.h> diff --git a/src/southbridge/amd/cs5535/chipsetinit.c b/src/southbridge/amd/cs5535/chipsetinit.c index ab1b640..e6aec1d 100644 --- a/src/southbridge/amd/cs5535/chipsetinit.c +++ b/src/southbridge/amd/cs5535/chipsetinit.c @@ -7,11 +7,11 @@ #include <stdlib.h> #include <string.h> #include "chip.h" -#include "northbridge/amd/gx2/northbridge.h" +#include <northbridge/amd/gx2/northbridge.h> #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h> /* the structs in this file only set msr.lo. But ... that may not always be true */ diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 2fe1bc2..c8aeb56 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -26,10 +26,10 @@ #include <pc80/keyboard.h> #include <string.h> #include <delay.h> -#include "arch/io.h" +#include <arch/io.h> #include "chip.h" #include "southbridge.h" -#include "cpu/dmp/dmp_post_code.h" +#include <cpu/dmp/dmp_post_code.h> /* IRQ number to S/B PCI Interrupt routing table reg(0x58/0xb4) mapping table. */ static const unsigned char irq_to_int_routing[16] = { diff --git a/src/southbridge/intel/bd82x6x/early_pch_native.c b/src/southbridge/intel/bd82x6x/early_pch_native.c index 0863f34..a16da96 100644 --- a/src/southbridge/intel/bd82x6x/early_pch_native.c +++ b/src/southbridge/intel/bd82x6x/early_pch_native.c @@ -30,7 +30,7 @@ #include "pch.h" /* For DMI bar. */ -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0) diff --git a/src/southbridge/intel/bd82x6x/early_rcba.c b/src/southbridge/intel/bd82x6x/early_rcba.c index 114b174..d63b7b3 100644 --- a/src/southbridge/intel/bd82x6x/early_rcba.c +++ b/src/southbridge/intel/bd82x6x/early_rcba.c @@ -21,7 +21,7 @@ #include <stdint.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> void southbridge_configure_default_intmap(void) diff --git a/src/southbridge/intel/bd82x6x/early_thermal.c b/src/southbridge/intel/bd82x6x/early_thermal.c index 02ec9a7..2328be3 100644 --- a/src/southbridge/intel/bd82x6x/early_thermal.c +++ b/src/southbridge/intel/bd82x6x/early_thermal.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_206ax/model_206ax.h" +#include <cpu/intel/model_206ax/model_206ax.h> #include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b1f8447..f4ce625 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -22,7 +22,7 @@ #include <console/console.h> #include <device/pci_ids.h> #include <device/pci_def.h> -#include "northbridge/intel/sandybridge/sandybridge.h" /* For DEFAULT_RCBABASE. */ +#include <northbridge/intel/sandybridge/sandybridge.h> /* For DEFAULT_RCBABASE. */ #include "pch.h" void diff --git a/src/southbridge/intel/bd82x6x/nvs.h b/src/southbridge/intel/bd82x6x/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/bd82x6x/nvs.h +++ b/src/southbridge/intel/bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index a20232e..5bb153d 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ - #include <device/device.h> #include <device/pci.h> #include <console/console.h> @@ -29,7 +28,7 @@ #include <cpu/x86/smm.h> #include <string.h> #include "pch.h" -#include "northbridge/intel/sandybridge/sandybridge.h" +#include <northbridge/intel/sandybridge/sandybridge.h> extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/fsp_bd82x6x/nvs.h b/src/southbridge/intel/fsp_bd82x6x/nvs.h index 8557c02..dde07e2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/nvs.h +++ b/src/southbridge/intel/fsp_bd82x6x/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index 827b897..1847b22 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -31,7 +31,7 @@ #include "pch.h" #if CONFIG_NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE || CONFIG_NORTHBRIDGE_INTEL_FSP_IVYBRIDGE -#include "northbridge/intel/fsp_sandybridge/northbridge.h" +#include <northbridge/intel/fsp_sandybridge/northbridge.h> #endif extern unsigned char _binary_smm_start; diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..e0b903f 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -30,10 +30,10 @@ #include <cbmem.h> #include <console/console.h> #include <drivers/intel/fsp/fsp_util.h> -#include "northbridge/intel/fsp_rangeley/northbridge.h" -#include "southbridge/intel/fsp_rangeley/soc.h" -#include "southbridge/intel/fsp_rangeley/gpio.h" -#include "southbridge/intel/fsp_rangeley/romstage.h" +#include <northbridge/intel/fsp_rangeley/northbridge.h> +#include <southbridge/intel/fsp_rangeley/soc.h> +#include <southbridge/intel/fsp_rangeley/gpio.h> +#include <southbridge/intel/fsp_rangeley/romstage.h> #include <arch/cpu.h> #include <arch/stages.h> #include <cpu/x86/msr.h> diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c index d23749e..fee2269 100644 --- a/src/southbridge/intel/ibexpeak/early_thermal.c +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -20,7 +20,7 @@ #include <arch/io.h> #include "pch.h" -#include "cpu/intel/model_2065x/model_2065x.h" +#include <cpu/intel/model_2065x/model_2065x.h> #include <cpu/x86/msr.h> /* Early thermal init, must be done prior to giving ME its memory diff --git a/src/southbridge/intel/ibexpeak/nvs.h b/src/southbridge/intel/ibexpeak/nvs.h index 9cdfb13..037d665 100644 --- a/src/southbridge/intel/ibexpeak/nvs.h +++ b/src/southbridge/intel/ibexpeak/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 2ce9072..d83cd0a 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -31,7 +31,7 @@ #include <string.h> #include "pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> extern unsigned char _binary_smm_start; extern unsigned char _binary_smm_end; diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index e2032ad..39fc40c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -36,7 +36,7 @@ * 1. the chipset can do it * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind */ -#include "northbridge/intel/nehalem/nehalem.h" +#include <northbridge/intel/nehalem/nehalem.h> #include <arch/pci_mmio_cfg.h> /* While we read PMBASE dynamically in case it changed, let's diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 81b2321..790953f 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -18,7 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */

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Patch merged into coreboot/master: 089a510 northbridge/intel: Do not define include guard as 1
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit 089a51029221ddceb0cf61daecb275971d2b2f22 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 02:48:57 2015 +1100 northbridge/intel: Do not define include guard as 1 As `#ifndef` and not `#if` is used in the check for include guards, setting it to 1 is not needed. Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8103 Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8103 for details. -gerrit

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Patch merged into coreboot/master: ebe3a7a mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit ebe3a7aea368aad5fe4b2bb625db34d0a542cb64 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:27:54 2015 +1100 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion Use 'delay.h' header rather than directly including 'delay.c' source. N.B. Some amdfam10 and K8 boards are not included in this changeset since unrelated issues are woven in there. Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8086 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8086 for details. -gerrit

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Patch merged into coreboot/master: 77757c2 mainboard/*/romstage.c: Sanitize system header inclusions
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit 77757c22b9eede92234d07d65a23fdf4b970c8cf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 21:33:39 2015 +1100 mainboard/*/romstage.c: Sanitize system header inclusions Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8085 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/8085 for details. -gerrit

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Patch merged into coreboot/master: d76ac63 superio/smsc/lpc47n207: Hook into build system
by gerrit＠coreboot.org 05 Jan '15

05 Jan '15

the following patch was just integrated into master: commit d76ac6349df0147b9d8f7f09f8bb80343ecfb5e6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 17:21:52 2015 +1100 superio/smsc/lpc47n207: Hook into build system Provide proper Makefile and Kconfig components so that this superio is built as object code. Select superio component in mainboard Kconfig's to bring in the link-time symbols and thereby removing the need for .c inclusion. N.B. The LPC47N207 Super I/O does not physically exist on these boards. The Super I/O is found on external LPC debug card hardware and so should really be made selectable. However, this is beyond the scope of this specific fix, that rids us of .c inclusions in romstage.c Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8084 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8084 for details. -gerrit

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Patch set updated for coreboot: d833949 northbridge/intel: Do not define include guard as 1
by Edward O'Callaghan 05 Jan '15

05 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8103 -gerrit commit d833949a963ae2742dec0b1a731b360910c37386 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jan 6 02:48:57 2015 +1100 northbridge/intel: Do not define include guard as 1 As `#ifndef` and not `#if` is used in the check for include guards, setting it to 1 is not needed. Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/fsp_rangeley/northbridge.h | 2 +- src/northbridge/intel/fsp_sandybridge/northbridge.h | 4 ++-- src/northbridge/intel/gm45/delay.h | 4 ++-- src/northbridge/intel/gm45/gm45.h | 4 ++-- src/northbridge/intel/haswell/haswell.h | 4 ++-- src/northbridge/intel/nehalem/gma.h | 4 ++-- src/northbridge/intel/nehalem/nehalem.h | 4 ++-- src/northbridge/intel/sandybridge/sandybridge.h | 4 ++-- src/northbridge/intel/sch/sch.h | 4 ++-- 9 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.h b/src/northbridge/intel/fsp_rangeley/northbridge.h index abce07a..dab5a9c 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.h +++ b/src/northbridge/intel/fsp_rangeley/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_RANGELEY_NORTHBRIDGE_H__ #define DEFAULT_ECBASE CONFIG_MMCONF_BASE_ADDRESS diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.h b/src/northbridge/intel/fsp_sandybridge/northbridge.h index 9a0cf42..d67d696 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.h +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ /* Chipset types */ #define SANDYBRIDGE_MOBILE 0 @@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/gm45/delay.h b/src/northbridge/intel/gm45/delay.h index dda6cf4..a28a3f1 100644 --- a/src/northbridge/intel/gm45/delay.h +++ b/src/northbridge/intel/gm45/delay.h @@ -18,11 +18,11 @@ */ #ifndef __NORTHBRIDGE_INTEL_GM45_DELAY_H__ -#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ 1 +#define __NORTHBRIDGE_INTEL_GM45_DELAY_H__ #include <delay.h> void ns100delay(u32); void udelay_from_reset(u32); -#endif +#endif /* __NORTHBRIDGE_INTEL_GM45_DELAY_H__ */ diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h index 673160b..5bdf9e4 100644 --- a/src/northbridge/intel/gm45/gm45.h +++ b/src/northbridge/intel/gm45/gm45.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_GM45_GM45_H__ -#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ 1 +#define __NORTHBRIDGE_INTEL_GM45_GM45_H__ #include "southbridge/intel/i82801ix/i82801ix.h" @@ -434,4 +434,4 @@ struct acpi_rsdp; unsigned long northbridge_write_acpi_tables(unsigned long start, struct acpi_rsdp *rsdp); #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_GM45_GM45_H__ */ diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 55f6f28..d8221a9 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ -#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ 1 +#define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ /* Chipset types */ #define HASWELL_MOBILE 0 @@ -233,4 +233,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */ diff --git a/src/northbridge/intel/nehalem/gma.h b/src/northbridge/intel/nehalem/gma.h index f0e1c53..baf12f2 100644 --- a/src/northbridge/intel/nehalem/gma.h +++ b/src/northbridge/intel/nehalem/gma.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ 1 +#define __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ /* mailbox 0: header */ typedef struct { @@ -118,4 +118,4 @@ typedef struct { opregion_vbt_t vbt; } __attribute__((packed)) igd_opregion_t; -#endif +#endif /* __NORTHBRIDGE_INTEL_NEHALEM_GMA_H__ */ diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index 60cafdf..73137b2 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -20,7 +20,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ -#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ 1 +#define __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ #ifndef __ASSEMBLER__ @@ -623,4 +623,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_NEHALEM_NEHALEM_H__ */ diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index d38bf0b..0790ae8 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -19,7 +19,7 @@ */ #ifndef __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ -#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ 1 +#define __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ /* Chipset types */ #define SANDYBRIDGE_MOBILE 0 @@ -240,4 +240,4 @@ int init_igd_opregion(igd_opregion_t *igd_opregion); #endif #endif -#endif +#endif /* __NORTHBRIDGE_INTEL_SANDYBRIDGE_SANDYBRIDGE_H__ */ diff --git a/src/northbridge/intel/sch/sch.h b/src/northbridge/intel/sch/sch.h index 5700842..3eb0825 100644 --- a/src/northbridge/intel/sch/sch.h +++ b/src/northbridge/intel/sch/sch.h @@ -20,7 +20,7 @@ */ #ifndef __SCH_PULSBO_H__ -#define __SCH_PULSBO_H__ 1 +#define __SCH_PULSBO_H__ int sch_port_access_read(int port, int reg, int bytes); void sch_port_access_write(int port, int reg, int bytes, long data); @@ -51,4 +51,4 @@ void sch_port_access_write_ram_cmd(int cmd, int port, int reg, int data); /* FIXME: should probably be in southbridge, but is setup in romstage, too */ #define CMC_SHADOW 0x3faf0000 -#endif +#endif /* __SCH_PULSBO_H__ */

1 0

New patch to review for coreboot: bdc7e43 samus: Updates from P2 build
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8135 -gerrit commit bdc7e430ccd002014f7d09959f162eccce842a8f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Jun 18 14:03:08 2014 +0800 samus: Updates from P2 build - SPD GPIO table was changed from earlier builds and GPIO67 needs to be swapped with GPIO69 - Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD - Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround - In order to support both P2A and P2B with one firmware image we need to read the EC board version and use the right SPD GPIO for bit3 - Touchpad I2C address changed to 0x4a/0x26 BUG=chrome-os-partner:29502 BRANCH=None TEST=boot on P2A and P2B boards Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/204818 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d --- src/mainboard/google/samus/acpi/mainboard.asl | 4 ++-- src/mainboard/google/samus/ec.h | 4 ++++ src/mainboard/google/samus/gpio.h | 2 +- src/mainboard/google/samus/romstage.c | 1 - src/mainboard/google/samus/spd/Makefile.inc | 2 +- src/mainboard/google/samus/spd/hynix_8Gb.spd.hex | 8 +++---- src/mainboard/google/samus/spd/spd.c | 30 +++++++++++++++++------- src/mainboard/google/samus/spd/spd.h | 5 ++-- 8 files changed, 37 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 5a052b9..eb66818 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -65,7 +65,7 @@ Scope (\_SB.PCI0.I2C0) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x25, // SlaveAddress + 0x26, // SlaveAddress ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode @@ -97,7 +97,7 @@ Scope (\_SB.PCI0.I2C0) Name (_CRS, ResourceTemplate() { I2cSerialBus ( - 0x4b, // SlaveAddress + 0x4a, // SlaveAddress ControllerInitiated, // SlaveMode 400000, // ConnectionSpeed AddressingMode7Bit, // AddressingMode diff --git a/src/mainboard/google/samus/ec.h b/src/mainboard/google/samus/ec.h index 9f95898..7bcfcae 100644 --- a/src/mainboard/google/samus/ec.h +++ b/src/mainboard/google/samus/ec.h @@ -22,6 +22,10 @@ #include <ec/google/chromeec/ec_commands.h> +#define SAMUS_EC_BOARD_PROTO1_9 0 +#define SAMUS_EC_BOARD_PROTO2_A 1 +#define SAMUS_EC_BOARD_PROTO2_B 2 + #define EC_SCI_GPI 36 /* GPIO36 is EC_SCI# */ #define EC_SMI_GPI 34 /* GPIO34 is EC_SMI# */ diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index af3955f..c2f5fde 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -91,7 +91,7 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ PCH_GPIO_INPUT, /* 65: RAM_ID3 */ - PCH_GPIO_UNUSED, /* 66: UNUSED (STRAP) */ + PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */ diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 9594287..cfa5fc3 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -22,7 +22,6 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> -#include <broadwell/cpu.h> //#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc index ccce912..774ea57 100644 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -21,7 +21,7 @@ romstage-y += spd.c SPD_BIN = $(obj)/spd.bin -# { GPIO66, GPIO69, GPIO68, GPIO67 } +# { GPIO65, GPIO67, GPIO68, GPIO69 } SPD_SOURCES = empty # 0b0000 SPD_SOURCES += empty # 0b0001 SPD_SOURCES += empty # 0b0010 diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex index 14002c1..b065b91 100644 --- a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex +++ b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex @@ -1,6 +1,6 @@ -# Hynix H9CCNNN8JTMLAR-NTM LPDDR3-S8B 16Gb(x32, 2CS) -# banks 8, ranks 2, rows 15, columns 10, density 8192 Mb, x32 -92 11 F1 03 05 19 02 0B 03 11 01 08 0A 00 FE 00 +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 +# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16 +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 @@ -8,7 +8,7 @@ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 -48 39 43 43 4E 4E 4E 38 4A 54 4D 4C 41 52 2D 4E +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E 54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 0409302..00e694e 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -24,6 +24,8 @@ #include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/romstage.h> +#include <ec/google/chromeec/ec.h> +#include <mainboard/google/samus/ec.h> #include <mainboard/google/samus/gpio.h> #include <mainboard/google/samus/spd/spd.h> @@ -80,25 +82,33 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { + int spd_bits[4] = { + SPD_GPIO_BIT0, + SPD_GPIO_BIT1, + SPD_GPIO_BIT2, + SPD_GPIO_BIT3 + }; int spd_gpio[4]; int spd_index; int spd_file_len; struct cbfs_file *spd_file; - spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); - spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); - spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); - spd_gpio[3] = get_gpio(SPD_GPIO_BIT3); + /* Proto2B boards use a different GPIO for SPD index bit 3 */ + if (google_chromeec_get_board_version() <= SAMUS_EC_BOARD_PROTO2_A) + spd_bits[3] = SPD_GPIO_BIT3_OLD; + + spd_gpio[0] = get_gpio(spd_bits[0]); + spd_gpio[1] = get_gpio(spd_bits[1]); + spd_gpio[2] = get_gpio(spd_bits[2]); + spd_gpio[3] = get_gpio(spd_bits[3]); spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | (spd_gpio[1] << 1) | spd_gpio[0]; printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " "GPIO%d=%d GPIO%d=%d)\n", spd_index, - SPD_GPIO_BIT3, spd_gpio[3], - SPD_GPIO_BIT2, spd_gpio[2], - SPD_GPIO_BIT1, spd_gpio[1], - SPD_GPIO_BIT0, spd_gpio[0]); + spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], + spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); if (!spd_file) @@ -120,5 +130,9 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) memcpy(pei_data->spd_data[1][0], ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + /* Make sure a valid SPD was found */ + if (pei_data->spd_data[0][0][0] == 0) + die("Invalid SPD data."); + mainboard_print_spd_info(pei_data->spd_data[0][0]); } diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 82e4f8d..4b2f3aa 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -33,10 +33,11 @@ #define SPD_PART_LEN 18 /* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 67 +#define SPD_GPIO_BIT0 69 #define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 69 +#define SPD_GPIO_BIT2 67 #define SPD_GPIO_BIT3 65 +#define SPD_GPIO_BIT3_OLD 66 struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);

1 0

New patch to review for coreboot: c39de9e x86: Initialize drivers in SMM context if needed
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8134 -gerrit commit c39de9efe0fa9c9876ccec69e965be2de69d1b48 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Jun 19 15:39:29 2014 -0700 x86: Initialize drivers in SMM context if needed This adds a block in the SMI handler to call init functions for drivers which may be used in SMM. A static variable is used to ensure the init functions are only called once. BUG=chrome-os-partner:29580 BRANCH=mccloud TEST=Built and booted on mccloud, system no longer hangs when pressing power button at the dev mode screen. Also tested on parrot. Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee Original-Reviewed-on: https://chromium-review.googlesource.com/204764 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861 --- src/cpu/x86/smm/smihandler.c | 14 ++++++++++++++ src/cpu/x86/smm/smm_module_handler.c | 14 ++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/src/cpu/x86/smm/smihandler.c b/src/cpu/x86/smm/smihandler.c index c864df2..bd03030 100644 --- a/src/cpu/x86/smm/smihandler.c +++ b/src/cpu/x86/smm/smihandler.c @@ -24,6 +24,12 @@ #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> +#if CONFIG_SPI_FLASH_SMM +#include <spi-generic.h> +#endif + +static int do_driver_init = 1; + #if !CONFIG_SMM_TSEG /* TSEG handler locks in assembly */ typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; @@ -184,6 +190,14 @@ void smi_handler(u32 smm_revision) return; } + /* Allow drivers to initialize variables in SMM context. */ + if (do_driver_init) { +#if CONFIG_SPI_FLASH_SMM + spi_init(); +#endif + do_driver_init = 0; + } + /* Call chipset specific SMI handlers. */ if (cpu_smi_handler) cpu_smi_handler(node, &state_save); diff --git a/src/cpu/x86/smm/smm_module_handler.c b/src/cpu/x86/smm/smm_module_handler.c index 79863d8..8c0e804 100644 --- a/src/cpu/x86/smm/smm_module_handler.c +++ b/src/cpu/x86/smm/smm_module_handler.c @@ -22,6 +22,12 @@ #include <cpu/x86/smm.h> #include <rmodule.h> +#if CONFIG_SPI_FLASH_SMM +#include <spi-generic.h> +#endif + +static int do_driver_init = 1; + typedef enum { SMI_LOCKED, SMI_UNLOCKED } smi_semaphore; /* SMI multiprocessing semaphore */ @@ -154,6 +160,14 @@ void asmlinkage smm_handler_start(void *arg) printk(BIOS_SPEW, "\nSMI# #%d\n", cpu); + /* Allow drivers to initialize variables in SMM context. */ + if (do_driver_init) { +#if CONFIG_SPI_FLASH_SMM + spi_init(); +#endif + do_driver_init = 0; + } + cpu_smi_handler(); northbridge_smi_handler(); southbridge_smi_handler();

1 0

New patch to review for coreboot: f05d7d2 samus: Enable EC ALS device
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8133 -gerrit commit f05d7d238e21358d09bd25ec1a6945f4237d1b71 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jun 13 10:36:34 2014 -0700 samus: Enable EC ALS device Enable the ACPI Device for the EC ALS. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203744 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d --- src/mainboard/google/samus/acpi/ec.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/samus/acpi/ec.asl b/src/mainboard/google/samus/acpi/ec.asl index 995c941..746498a 100644 --- a/src/mainboard/google/samus/acpi/ec.asl +++ b/src/mainboard/google/samus/acpi/ec.asl @@ -20,5 +20,8 @@ /* mainboard configuration */ #include <mainboard/google/samus/ec.h> +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + /* ACPI code for EC functions */ #include <ec/google/chromeec/acpi/ec.asl>

1 0

New patch to review for coreboot: cb3ce72 chrome ec: Add ACPI Device for ALS if enabled
by Marc Jones 05 Jan '15

05 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8132 -gerrit commit cb3ce72753a1dca7ab2246ec827d039ba2f5b7f1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Jun 13 10:35:22 2014 -0700 chrome ec: Add ACPI Device for ALS if enabled The EC can export ALS information if the sensor is attached to it directly rather than to the host. This adds a basic ACPI ALS device and implements the required information. The kernel does not use the _ALR tuple set but it is required by the ACPI spec so this just adds the sample two point response curve defined in ACPI 5.0 section 9.2.5. The EC does not currently send events for lux value changes so a polling interval of 1 second is defined. BUG=chrome-os-partner:24208 BRANCH=None TEST=build and boot on samus, add acpi-als driver to the kernel and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203743 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f --- src/ec/google/chromeec/acpi/als.asl | 70 +++++++++++++++++++++++++++++++++++++ src/ec/google/chromeec/acpi/ec.asl | 4 +++ 2 files changed, 74 insertions(+) diff --git a/src/ec/google/chromeec/acpi/als.asl b/src/ec/google/chromeec/acpi/als.asl new file mode 100644 index 0000000..8bc68bf --- /dev/null +++ b/src/ec/google/chromeec/acpi/als.asl @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Device (ALS) +{ + Name (_HID, "ACPI0008") + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) + { + Return (0xF) + } + + /* + * Returns the current ambient light illuminance reading in lux + * + * 0: Reading is below the range of sensitivity of the sensor + * -1: Reading is above the range or sensitivity of the sensor + */ + Method (_ALI, 0, NotSerialized) + { + Return (^^ALS0) + } + + /* + * Returns a recommended polling frequency in tenths of seconds + * + * 0: No need to poll, async notifications will indicate changes + */ + Name (_ALP, 10) + + /* + * Returns a package of packages where each tuple consists of a pair + * of integers mapping ambient light illuminance to display brightness. + * + * {<display luminance adjustment>, <ambient light illuminance>} + * + * Ambient light illuminance values are specified in lux. + * + * Display luminance adjustment values are relative percentages where + * 100 is no (0%) display brightness adjustment. Values <100 indicate + * negative adjustment (dimming) and values >100 indicate positive + * adjustment (brightening). + * + * This is currently unused by the Linux kernel ACPI ALS driver but + * is required by the ACPI specification so just define a basic two + * point response curve. + */ + Name (_ALR, Package () + { + Package () { 70, 30 }, // Min { -30% adjust at 30 lux } + Package () { 150, 1000 } // Max { +50% adjust at 1000 lux } + }) +} diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 650efd2..2760f19 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -431,4 +431,8 @@ Device (EC0) #include "ac.asl" #include "battery.asl" + +#ifdef EC_ENABLE_ALS_DEVICE + #include "als.asl" +#endif }

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coreboot-gerrit January 2015