coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

1 participants
1236 discussions

Patch set updated for coreboot: 7279679 AMD Mainboards - PlatformGnbPcie.c: Fix Doxygen errors
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8073 -gerrit commit 7279679551c76d1173803c32298928e2101cc0d2 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:24:07 2014 -0700 AMD Mainboards - PlatformGnbPcie.c: Fix Doxygen errors Remove PeiServices param for OemInitEarly - it doesn't exist in the function. Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 1 - src/mainboard/amd/olivehill/PlatformGnbPcie.c | 1 - src/mainboard/amd/olivehillplus/PlatformGnbPcie.c | 1 - src/mainboard/amd/parmer/PlatformGnbPcie.c | 1 - src/mainboard/amd/persimmon/PlatformGnbPcie.c | 1 - src/mainboard/amd/south_station/PlatformGnbPcie.c | 1 - src/mainboard/amd/thatcher/PlatformGnbPcie.c | 1 - src/mainboard/amd/torpedo/PlatformGnbPcie.c | 1 - src/mainboard/amd/union_station/PlatformGnbPcie.c | 1 - src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 1 - src/mainboard/asrock/imb-a180/PlatformGnbPcie.c | 1 - src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 1 - src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c | 1 - src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c | 1 - src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c | 1 - src/mainboard/lenovo/g505s/PlatformGnbPcie.c | 1 - src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c | 1 - src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 1 - 19 files changed, 19 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index c3f9d9a..0ca6cbd 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -34,7 +34,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 1f5b750..f677597 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -116,7 +116,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c index 4e5382a..2ca1a8c 100644 --- a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c @@ -110,7 +110,6 @@ const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 7ab91cd..cf57ffb 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -153,7 +153,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index c13a383..f2fe96b 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -33,7 +33,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index ca33c6b..8c24408 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -34,7 +34,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 5df2691..c642c78 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -159,7 +159,6 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index 893b48b..2c5990a 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -101,7 +101,6 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 68ac8b6..ca34816 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index b591642..76e5ade 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c index da1910e..c807a6a 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c @@ -116,7 +116,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index f837925..762fe9f 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -135,7 +135,6 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c index 3e86817..05d2844 100644 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c @@ -37,7 +37,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c index d48475c..66f7119 100644 --- a/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c @@ -110,7 +110,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c index 450bbd3..42e1985 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c @@ -152,7 +152,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 66152a6..c82532f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -34,7 +34,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * **/ diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c index 450bbd3..42e1985 100644 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c +++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c @@ -152,7 +152,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index ae79dc8..ceb7c38 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index 16d1b4a..ace22e7 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID

1 0

Patch set updated for coreboot: 48f0e20 AMD Mainboards - platform_cfg.h: Fixes for doxygen
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8071 -gerrit commit 48f0e203e8b8e13f7ae8f9c6872ae176c50a73f3 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:08:15 2014 -0700 AMD Mainboards - platform_cfg.h: Fixes for doxygen - Move @def BIOS_SIZE description to the next line - SB_GEN2 changed to SB_GPP_GEN2 - Move the SIO_HWM_BASE_ADDRESS description to the next line Change-Id: Ia3496b0108484f557627304553461932a100dfa5 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 8 +++++--- src/mainboard/amd/inagua/platform_cfg.h | 5 +++-- src/mainboard/amd/persimmon/platform_cfg.h | 5 +++-- src/mainboard/amd/south_station/platform_cfg.h | 5 +++-- src/mainboard/amd/torpedo/platform_cfg.h | 3 ++- src/mainboard/amd/union_station/platform_cfg.h | 5 +++-- src/mainboard/asrock/e350m1/platform_cfg.h | 8 +++++--- src/mainboard/asus/m5a88-v/platform_cfg.h | 8 +++++--- src/mainboard/avalue/eax-785e/platform_cfg.h | 8 +++++--- src/mainboard/gizmosphere/gizmo/platform_cfg.h | 5 +++-- src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 5 +++-- src/mainboard/lippert/frontrunner-af/platform_cfg.h | 5 +++-- src/mainboard/lippert/toucan-af/platform_cfg.h | 5 +++-- 13 files changed, 46 insertions(+), 29 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 6944ab2..29f92d2 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 4bd6a0e..9ca6d95 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 5357370..f1b0fdc 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 4bd6a0e..9ca6d95 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index de4e89d..311214c 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -25,7 +25,8 @@ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In Hudson-2, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 4bd6a0e..9ca6d95 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 6944ab2..29f92d2 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index 6944ab2..25574b7 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index 6944ab2..25574b7 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 401d981..8163af3 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -26,7 +26,8 @@ #define LEGACY_FREE 1 /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -195,7 +196,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index bbd1d14..2d946f8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -23,7 +23,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -192,7 +193,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 03146d0..0c3308d 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -190,7 +191,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 25b0485..29f3916 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -190,7 +191,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */

1 0

Patch merged into coreboot/master: 182e551 smihandler.c: Fix doxygen errors in southbridge_smi_handler
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 182e551f2d3556ca679237d914ba33bda2de1cbe Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:29:08 2014 -0700 smihandler.c: Fix doxygen errors in southbridge_smi_handler Correct the param to match the functions. Change-Id: Id002c549a6ba6a7be4fa5eee396769eaa2510698 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8074 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/8074 for details. -gerrit

1 0

Patch merged into coreboot/master: 24e2e95 atomic.h: Fix doxygen errors
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 24e2e951b91dd2e177f2ff133362e0cc0cf6b505 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:36:06 2014 -0700 atomic.h: Fix doxygen errors - @v & @i need to be @param v & @param i - add the @file command Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8075 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8075 for details. -gerrit

1 0

Patch merged into coreboot/master: 6e22225 remove vx900_int16 doxygen module/group
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 6e22225d605b6cfddf3407dfc83f524650851f0e Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 14:44:38 2014 -0700 remove vx900_int16 doxygen module/group This doxygen directive was creating a top level modules section, which had the vx900_int15 code as its only member. I do think that breaking the code into documented sections is a good plan, but in an effort to clean up the output, I'm removing this for now. Change-Id: I3f7e2f704136ebbd1961c5946bac4c2edbd6a371 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8070 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8070 for details. -gerrit

1 0

Patch merged into coreboot/master: ba9d51e documentation: Add small coreboot logo in PNG format
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit ba9d51ee3888c6b95c86383cb17afb64dd0e04c9 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 14:47:43 2014 -0700 documentation: Add small coreboot logo in PNG format The doxygen output looks better with the coreboot logo, so I'm adding the 2k png from the wiki to the documentation directory to use in the doxygen build. Change-Id: I95ca67fb311e0b39a12ad9c5a1a53a99f7fec2d9 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/8067 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8067 for details. -gerrit

1 0

Patch set updated for coreboot: 79da95e atomic.h: Fix doxygen errors
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8075 -gerrit commit 79da95e4c82bfe2b9085b39999ecffa1010487d9 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:36:06 2014 -0700 atomic.h: Fix doxygen errors - @v & @i need to be @param v & @param i - add the @file command Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/arch/x86/include/arch/smp/atomic.h | 21 +++++++++++---------- src/include/smp/atomic.h | 22 +++++++++++++--------- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h index 18bbae2..d7964e5 100644 --- a/src/arch/x86/include/arch/smp/atomic.h +++ b/src/arch/x86/include/arch/smp/atomic.h @@ -10,35 +10,36 @@ typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } -/* +/** @file x86/include/arch/smp/atomic.h + * * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. */ /** * atomic_read - read atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed + * Atomically reads the value of v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value + * @param v: pointer of type atomic_t + * @param i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed + * Atomically sets the value of v to i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed + * Atomically increments v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) @@ -51,9 +52,9 @@ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) /** * atomic_dec - decrement atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed + * Atomically decrements v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ static __inline__ __attribute__((always_inline)) void atomic_dec(atomic_t *v) diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 44be4c5..bc50534 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -9,20 +9,24 @@ typedef struct { int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } /** + * @file include/smp/atomic.h + */ + +/** * atomic_read - read atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed + * Atomically reads the value of v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value + * @param v: pointer of type atomic_t + * @param i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed + * Atomically sets the value of v to i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_set(v,i) (((v)->counter) = (i)) @@ -30,9 +34,9 @@ typedef struct { int counter; } atomic_t; /** * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed + * Atomically increments v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_inc(v) (((v)->counter)++) @@ -40,9 +44,9 @@ typedef struct { int counter; } atomic_t; /** * atomic_dec - decrement atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed + * Atomically decrements v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_dec(v) (((v)->counter)--)

1 0

Patch set updated for coreboot: 6e54b7b documentation: Add small coreboot logo in PNG format
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8067 -gerrit commit 6e54b7b1a983672433047903e23925239dc8a712 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 14:47:43 2014 -0700 documentation: Add small coreboot logo in PNG format The doxygen output looks better with the coreboot logo, so I'm adding the 2k png from the wiki to the documentation directory to use in the doxygen build. Change-Id: I95ca67fb311e0b39a12ad9c5a1a53a99f7fec2d9 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- documentation/coreboot_logo.png | Bin 0 -> 2236 bytes 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/documentation/coreboot_logo.png b/documentation/coreboot_logo.png new file mode 100644 index 0000000..dde1aa6 Binary files /dev/null and b/documentation/coreboot_logo.png differ

1 0

New patch to review for coreboot: 86f6582 southbridge/hudson: only enable XHCI when USE_BLOBS is set
by Felix Held 04 Jan '15

04 Jan '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8090 -gerrit commit 86f65823b0fd84e59d6d9fc0ea617aaf263b7f43 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun Jan 4 17:33:41 2015 +0100 southbridge/hudson: only enable XHCI when USE_BLOBS is set only enable XHCI when the firmware is present Change-Id: I1de706d753da76a9e7c4fec2c5a5cae9e639c3da Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/southbridge/amd/agesa/hudson/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index f957c48..510db70 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -45,7 +45,7 @@ config EHCI_BAR config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" - default y + default y if USE_BLOBS help The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured

1 0

New patch to review for coreboot: 4d4516f hudson: reintroduce HUDSON_DISABLE_IMC option
by Felix Held 04 Jan '15

04 Jan '15

Felix Held (felix-coreboot(a)felixheld.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8089 -gerrit commit 4d4516f5bc541edd7445ba0070b9d84743203677 Author: Felix Held <felix-coreboot(a)felixheld.de> Date: Sun Jan 4 17:19:59 2015 +0100 hudson: reintroduce HUDSON_DISABLE_IMC option HUDSON_DISABLE_IMC was introduced in 1a59039c24cfe5c74a805064d3a360709ad16526 option gets used in 99799d668255bbf0d502be4914d0646385350153 for asus/f2a85-m option gets killed in 1b1b795f97d2aaa2c6104f164ed2b4e792895019, but is still used in source agesa based boards (asus/f2a85-m and asus/f2a85-m_le) Change-Id: I448a0dc7c9fef504f89cfd192ca74172425fb3e0 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- src/southbridge/amd/agesa/hudson/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index acc2d72..f957c48 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -59,8 +59,13 @@ config HUDSON_XHCI_FWM help Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 +config HUDSON_DISABLE_IMC + bool + default n + config HUDSON_IMC_FWM bool "Add imc firmware" + depends on !HUDSON_DISABLE_IMC default y if USE_BLOBS help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2015