coreboot-gerrit January 2015

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New patch to review for coreboot: 00281ac mainboard/*/romstage.c: Use 'delay.h' header over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8088 -gerrit commit 00281ac12d95d817cba8ee396a9dce6cb4af6874 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 01:40:07 2015 +1100 mainboard/*/romstage.c: Use 'delay.h' header over .c inclusion Change-Id: I1fe9e91b9abd9a7f10685796c0e466f71ba51a90 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 2 +- src/mainboard/a-trend/atc-6240/romstage.c | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 2 +- src/mainboard/asus/mew-am/romstage.c | 2 +- src/mainboard/asus/mew-vm/romstage.c | 2 +- src/mainboard/asus/p2b-d/romstage.c | 2 +- src/mainboard/asus/p2b-ds/romstage.c | 2 +- src/mainboard/asus/p2b-f/romstage.c | 2 +- src/mainboard/asus/p2b-ls/romstage.c | 2 +- src/mainboard/asus/p2b/romstage.c | 2 +- src/mainboard/asus/p3b-f/romstage.c | 2 +- src/mainboard/azza/pt-6ibd/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/biostar/m6tba/romstage.c | 2 +- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 2 +- src/mainboard/digitallogic/adl855pc/romstage.c | 2 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxc/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 2 +- src/mainboard/hp/e_vectra_p2706t/romstage.c | 2 +- src/mainboard/intel/d810e2cb/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/lanner/em8510/romstage.c | 2 +- src/mainboard/mitac/6513wu/romstage.c | 2 +- src/mainboard/msi/ms6119/romstage.c | 2 +- src/mainboard/msi/ms6147/romstage.c | 2 +- src/mainboard/msi/ms6156/romstage.c | 2 +- src/mainboard/msi/ms6178/romstage.c | 2 +- src/mainboard/nec/powermate2000/romstage.c | 2 +- src/mainboard/nokia/ip530/romstage.c | 2 +- src/mainboard/rca/rm4100/romstage.c | 2 +- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 2 +- src/mainboard/thomson/ip1000/romstage.c | 2 +- src/mainboard/tyan/s1846/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/romstage.c | 2 +- 41 files changed, 41 insertions(+), 41 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index bfe210e..65cd10a 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 20846fd..96a8334 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 73fef6e..567a436 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 213d480..8f02fdf 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index f6032ef..034a819 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 7aa3688..22cd13a 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 0d41d14..9d685c3 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index a93b743..5270435 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index 6a5ad02..2534845 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index bfe210e..65cd10a 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index a3aeb9a..bb18441 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index 9c40af7..0729367 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 667360a..75abe35 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <lib.h> #include <spd.h> diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 7151d40..7a48d42 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index 654c8c1..34da50c 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index 73fef71..d69ecb1 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -4,7 +4,7 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <lib.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801dx/i82801dx.h> diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index db69906..10b45c8 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index ac437ac..5cede89 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index d1a0b09..da18884 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82801ix/i82801ix.h> #include <cpu/x86/bist.h> #include <timestamp.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index e61c653..d63f78e 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 3ac2dfa..12a1781 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index dcdd552..4b9340d 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -30,7 +30,7 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <lib.h> /* TODO: It's a PC87364 actually! */ diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index e7b78f8..4c1f452 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82801bx/i82801bx.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "gpio.c" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 5145a50..8393479 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -25,7 +25,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <console/console.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index 8a17113..cba05f3 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index 0216001..1f02786 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -27,7 +27,7 @@ #include <stdlib.h> #include <lib.h> #include <spd.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <southbridge/intel/i82801dx/i82801dx.h> diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index ea2c009..7c997d5 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index 403f8ef..7127635 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index b4432e0..d292665 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 9b9cb14..997a3f2 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 5059074..776627f 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index f13f746..3d32e3f 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/intel/i82810/raminit.h> #include <cpu/x86/bist.h> #include <southbridge/intel/i82801ax/i82801ax.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 8a08c76..34c8fb7 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 9da69b5..4a0ce0a 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index c1cbb1d..a41913a 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index 5627296..88cc5bc 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -23,7 +23,7 @@ #include <device/pci_def.h> #include <arch/io.h> #include <device/pnp_def.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index c338642..69b5a37 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -26,7 +26,7 @@ #include <console/console.h> #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 4bf2615..97c0242 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -28,7 +28,7 @@ #include <lib.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8235/early_serial.c" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index a10f755..4078011 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -34,7 +34,7 @@ #include <lib.h> #include <northbridge/via/vx800/vx800.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include <string.h> /* This file contains the board-special SI value for raminit.c. */ diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 615ad2c..c66f6bd 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -28,7 +28,7 @@ #include <lib.h> #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 5a74255..ed2d9dd 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -28,7 +28,7 @@ #include <lib.h> #include <northbridge/via/cx700/raminit.h> #include <cpu/x86/bist.h> -#include "drivers/pc80/udelay_io.c" +#include <delay.h> #include <delay.h> #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c"

1 0

Patch set updated for coreboot: e00527b mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8086 -gerrit commit e00527b2a1a56255c3ae9f861553f19519ea8ce8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:27:54 2015 +1100 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion Use 'delay.h' header rather than directly including 'delay.c' source. N.B. Some amdfam10 and K8 boards are not included in this changeset since unrelated issues are woven in there. Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 2 +- src/mainboard/a-trend/atc-6240/romstage.c | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 2 +- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/mahogany/romstage.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/p2b-d/romstage.c | 2 +- src/mainboard/asus/p2b-ds/romstage.c | 2 +- src/mainboard/asus/p2b-f/romstage.c | 2 +- src/mainboard/asus/p2b-ls/romstage.c | 2 +- src/mainboard/asus/p2b/romstage.c | 2 +- src/mainboard/asus/p3b-f/romstage.c | 2 +- src/mainboard/azza/pt-6ibd/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/biostar/m6tba/romstage.c | 2 +- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxc/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/ibm/e325/romstage.c | 2 +- src/mainboard/ibm/e326/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 2 +- src/mainboard/iwill/dk8s2/romstage.c | 2 +- src/mainboard/iwill/dk8x/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/mainboard/mitac/6513wu/romstage.c | 2 +- src/mainboard/msi/ms6119/romstage.c | 2 +- src/mainboard/msi/ms6147/romstage.c | 2 +- src/mainboard/msi/ms6156/romstage.c | 2 +- src/mainboard/msi/ms7135/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/mainboard/newisys/khepri/romstage.c | 2 +- src/mainboard/nokia/ip530/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 2 +- src/mainboard/sunw/ultra40/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/mainboard/tyan/s1846/romstage.c | 2 +- src/mainboard/tyan/s2850/romstage.c | 2 +- src/mainboard/tyan/s2875/romstage.c | 2 +- src/mainboard/tyan/s2880/romstage.c | 2 +- src/mainboard/tyan/s2881/romstage.c | 2 +- src/mainboard/tyan/s2882/romstage.c | 2 +- src/mainboard/tyan/s2885/romstage.c | 2 +- src/mainboard/tyan/s2891/romstage.c | 2 +- src/mainboard/tyan/s2892/romstage.c | 2 +- src/mainboard/tyan/s2895/romstage.c | 2 +- src/mainboard/tyan/s4880/romstage.c | 2 +- src/mainboard/tyan/s4882/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/romstage.c | 2 +- src/mainboard/winent/mb6047/romstage.c | 2 +- 69 files changed, 69 insertions(+), 69 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 155a86d..bfe210e 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index baf8972..20846fd 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 9f918bb..73fef6e 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 5b9b6ca..279c15f 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 6e3de07..1a7c203 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -28,7 +28,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 906ff85..9b6006d 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <spd.h> diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index f49aa61..1c5debe 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -12,7 +12,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index c360245..daa4ad4 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -9,7 +9,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87360/pc87360.h> diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 16cc02b..67a1f7a 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 34f4514..c5d3f07 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index f96d4be..e642cbd 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 0b95475..ebdb095 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 2f8dc4f..5127618 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 87d0d71..0b1555c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -36,7 +36,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index f5c5654..4040c60 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -36,7 +36,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 28e4e60..7aa3688 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index af226d5..0d41d14 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index e46ce61..a93b743 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index dbc359a..6a5ad02 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 155a86d..bfe210e 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 2636d4e..a3aeb9a 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index bac2097..9c40af7 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 5035f57..667360a 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <lib.h> #include <spd.h> #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 4630820..7151d40 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 72c2dd0..03f00c4 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index ea33555..654c8c1 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include <superio/nsc/pc97317/pc97317.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index b9a5630..ac437ac 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -27,7 +27,7 @@ #include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "memory.c" diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 9a2af16..d1a0b09 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "../qemu-i440fx/memory.c" diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 3897551..e61c653 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 995a657..3ac2dfa 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 44fa4ca..1638863 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -35,7 +35,7 @@ #include <southbridge/sis/sis966/sis966.h> #include "southbridge/sis/sis966/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 008b353..cb83c08 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -37,7 +37,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 984b262..0785c54 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -43,7 +43,7 @@ #include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 54a543d..bb24b33 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 794fd15..4ccc7fe 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 0e579ef..47d8fda 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 9a45217..40c7137 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 0525aa9..208c0b3 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index ca7edad..8a17113 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71805f/f71805f.h> diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index e4ef459..fa5e914 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index c157c99..ea2c009 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index d3a51e4..403f8ef 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 95780bf..b4432e0 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 9073be1..9b9cb14 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 290423b..88992a5 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -38,7 +38,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 142a496..dd816e6 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -35,7 +35,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <reset.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 0f7d943..3f53a7f 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -17,7 +17,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 2fc5cbe..8a08c76 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 5599a24..5ce8090 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index ca02936..c1cbb1d 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 8c4724f..bb754b8 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 6cecf18..9d1034b 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 201e686..c338642 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index c6d3734..7f291ae 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index ea2f4eb..fa3bcf5 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 0e1ac98..49ff6bc 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index acfcec3..78cccc2 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 0e1ac98..49ff6bc 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index d321a45..138d1c0 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 4856d46..93189f1 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 4e11a1f..881972d 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index b2fe6fd..086df63 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/lpc47b397/lpc47b397.h> diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 53432af..71646c2 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index c0a3918..a3ae994 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 373756f..4bf2615 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8235/early_serial.c" #include <spd.h> diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 8f64949..a10f755 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -35,7 +35,7 @@ #include <northbridge/via/vx800/vx800.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <string.h> /* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 7261e20..615ad2c 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 8204ae3..5a74255 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cx700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c" #include "northbridge/via/cx700/early_serial.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 7be35f9..905248e 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c"

1 0

Patch set updated for coreboot: 46f1bdd northbridge/via/vx800/examples: Remove rotting source
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8087 -gerrit commit 46f1bdd60d978f952dab02ba741707d72b8ba42e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:29:36 2015 +1100 northbridge/via/vx800/examples: Remove rotting source This is just bit-rotting and its likely this will continue to rot by the time someone notices it exits it will be too late (i.e., today). Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/vx800/examples/chipset_init.c | 1241 -------------------- .../via/vx800/examples/driving_clk_phase_data.c | 242 ---- src/northbridge/via/vx800/examples/romstage.c | 541 --------- 3 files changed, 2024 deletions(-) diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c deleted file mode 100644 index 3f9c70f..0000000 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ /dev/null @@ -1,1241 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if CONFIG_HAVE_ACPI_RESUME -#include <arch/acpi.h> -#endif -#include "../vx800.h" - -#include <arch/io.h> -#include "pci_rawops.h" - -static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = { - // Combine Stage1 registers - {0x00, 0xFF, SB_LPC_REG(0x41), 0x40, 0x40}, - - // Acpi init registers in sb stage1 - {0x00, 0xFF, SB_LPC_REG(0x40), 0x04, 0x04}, // Enable 4D0/4D1 support - {0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08}, // Enable RTC port 74/75 - {0x00, 0xFF, SB_LPC_REG(0x51), 0x0D, 0x0D}, // and KBC - {0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09}, // Enable Serial IRQ - {0x00, 0xFF, SB_LPC_REG(0x67), 0x00, 0x04}, // Set FERR voltage to 1.5v - {0x00, 0xFF, SB_LPC_REG(0x98), 0xFF, 0x00}, // Disable GP3 Timer - - {0x00, 0xFF, SB_IDEC_REG(0xb9), 0x01, 0x01}, - - {0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39}, // Enable SMM A-Seg, MSI and Io APIC - ///// SPI-BAR. - //// SPI_BASE_ADDRESS = 0xFED1 0000 - {0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00}, - {0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1}, - {0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE}, - ///// End of 2008-04-17 - - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mNbStage2InitTable[] = { - // D0F0: AGP Feature. For 3353, No AGP Feature - - // D0F2~D0F3 is configured by MemoryInit Peim - - // D0F4: NB PMU - { 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB }, - { 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05 }, - { 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8 }, - { 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF }, - { 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC }, - { 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19 }, - { 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00 }, - { 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF }, - { 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF }, - { 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC }, - { 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0 }, - { 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6 }, - { 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20 }, - - // D0F5: NB APIC, PXPTRF and MSGC - //Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex. - //Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase. - //Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase. - { 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18 }, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1. - { 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00 }, //Set RVC1RPSW, RVC1RQ1T to 1. - { 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0 }, - { 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01 }, // RWAKEEN - //{ 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00 }, //RTDNP2B32EN - { 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00 }, //RP2P1ABORT - - -// fine-tune -// If no settings, C7 will hang or reboot in XP, but CN will not. - { 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03 }, - { 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01 }, - { 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10 }, - { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08 }, - { 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04 }, // ACPI Base addr - { 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01 }, // APIC MSI - { 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00 }, // APIC MSI - //GTL - { 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66 }, - { 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20 }, - { 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00 }, - - - // End of Table - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = { - // D17F0: LPC - { 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44 }, // Enable I/O Recovery Time, 4D0/4D1 Support - { 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0 }, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD - { 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B }, // RENDTX, ENWBTO, ENRBTO - //{ 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10 }, // It is related to INTH# - //{ 0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C }, //RMRPW, RIRPW // Reserved in 409 by Eric - - // Internal RTC, Mouse, Keyboard // set in PEI by Eric - //{ 0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D }, // Enable Internal RTC, Internal PS2 Mouse/Keyboard - - // RTC - { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01 }, //RTC Rx32 Map to Centrury Byte - - //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02 }, // RDMEGAS - //{ 0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08 }, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric - - // Serial IRQ // set in PEI by Eric - //{ 0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09 }, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock. - - // Enable 4D0h/4D1h Port - //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04 }, // EISAXT // set in PEI by Eric - - // Config ROM Interface - // Enable SPI/Set SPI Memory Base Address - // It is initialized in PEI Phase - - // Subsystem ID/Vendor ID Back Door - { 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06 }, - { 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11 }, - { 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09 }, - { 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34 }, - - { 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40 }, - { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51 }, // Orgin value 0x53, modify for 409 by Eric - { 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01 }, - - - { 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00 }, // Setting PCI device enable - { 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00 }, // Setting PCI device enable - { 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00 }, // Setting HDAC enable - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = { - //PCI1 Programming Sequence - //(1)Configure D17F7 - { 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03 }, - { 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 }, // Reserved in 409 by Eric - { 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 }, //RENPPB, RP2CFLSH - { 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 }, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion - // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. - // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) - //(2)Configure D19F0 - { 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 }, - - //(3)Performance Recommended Setting - - //Save Power - { 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01 }, - { 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00 }, - //Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance - { 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82 }, - { 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0 }, - { 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE }, - - //Cycle Control - { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01 }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C }, - //Arbitration control - { 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F }, - { 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0 }, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = { - { 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08 }, //RVWREQ, ROABKDOOR - - //CCA's Register Programming sequence - { 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08 }, //Config Azalia's upstream cycle high priority and other low priority - { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80 }, //Disable bypass asynchronous circuit - { 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11 }, // Set SM Internal Device and HDAC Occupy Timer - { 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11 }, // Set SM Internal Device and HDAC Promote Timer - { 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02 }, //Use SB internal devices's original REQ - { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00 }, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C }, //RLCKXP2C, RFSBVK. - { 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00 }, //RBLKAPIC, RAZC3 - { 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02 }, //RNMIFSB, RFSBVK - { 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90 }, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme - { 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00 }, //Let CCA use dynamic clock. - //The CCA is also relate to D17F0 - //{ 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00 }, //Disable CCA Test Mode - { 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00 }, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = { - //{0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05}, //set to native mode - {0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07}, - //{0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F}, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = { - { 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40 }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04 }, - //{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void AcpiInit(void) -{ - device_t_raw rawdevice = 0; - u8 sbchiprev; - rawdevice = PCI_RAWDEV(0, 0x11, 0); - // Set the PMIO base io address - pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE, - 0xff80); - // Enable PMIO - pci_rawmodify_config16(rawdevice, 0x80, 0x8000, 0x8000); - // Enable Soft Resume - outw(inw(VX800_ACPI_IO_BASE + 0x04) | 0x8000, - VX800_ACPI_IO_BASE + 0x04); - - // Get SB Revision - sbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev); - - // Fill Register Table - via_pci_inittable(sbchiprev, mSbStage1InitTbl); - - // Close all SMI/Io Traps - outb(0x00, VX800_ACPI_IO_BASE + 0x42); -} - -void Stage2NbInit(void) -{ - device_t_raw rawdevice = 0; - u8 nbchiprev; - u32 subid = 0; - rawdevice = PCI_RAWDEV(0, 0, 4); - nbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "NB chip revision =%x\n", nbchiprev); - - via_pci_inittable(nbchiprev, mNbStage2InitTable); - - rawdevice = PCI_RAWDEV(0, 0, 0); - - subid = PCI_DEVICE_ID_VIA_VX855_D0F0 << 16 + PCI_VENDOR_ID_VIA; - pci_rawwrite_config32(rawdevice, 0x2C, subid); - - //vx855 NB no pcie bus - //vx855 NB no apic -} - -void IDECSupportOption(u8 sbchiprev) -{ - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0, 0x08); - - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x00, 0x80); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x0A, 0x01, 0xFF); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00); - - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE -// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE - - via_pci_inittable(sbchiprev, IDEC_INIT); -} - -void InitIDEC(u8 sbchiprev) -{ - IDECSupportOption(sbchiprev); -} - -void InitUHCI(u8 Number, u8 bEnable) -{ - u8 Mask, Value; - u16 D16; - u8 BaseAddress; - u8 BitShift; - // USB Device 16 - // Function : Number - // 0 : 0 - // 1 : 1 - // 2 : 2 - // The BitShift is got from Datasheet. - - switch (Number) { - case 0: - BaseAddress = 0; - BitShift = 4; - break; - case 1: - BaseAddress = 1; - BitShift = 5; - break; - case 2: - default: - BaseAddress = 2; - BitShift = 2; - break; - } - - if (bEnable) { - Mask = 0x1 << BitShift; - Value = 0x0; - } else { - Mask = 0x0; - Value = 0x1 << BitShift; - } - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask); - - - if (bEnable) { - D16 = 0; - pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x20, D16); - - // Config some Control Register - Mask = 0x00; - Value = 0x12; - - pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x41, Value, Mask); - Mask = 0x00; - Value = 0xEB; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x4B, Value, Mask); - } - return; -} - -static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = { - //EHCI - { 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0 }, - { 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80 }, - { 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E }, - { 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94 }, - { 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A }, - { 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A }, - { 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11 }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void InitEHCI(u8 Number, u8 bEnable) -{ - u8 Mask, Value; - u8 EHCIRevision; - - if (bEnable) { - Mask = 0x1 << 1; - Value = 0x0; - } else { - Mask = 0x0; - Value = 0x1 << 1; - } - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask); - - - if (bEnable) { - // Get Chipset Revision - EHCIRevision = - pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6); - printk(BIOS_DEBUG, "EHCI Revision =%x\n", EHCIRevision); - via_pci_inittable(EHCIRevision, mEHCIInitTable); - } -} - -#define TRUE 1 -void InitUSBC(u8 sbchiprev) -{ - InitUHCI(0, TRUE); - InitUHCI(1, TRUE); - InitUHCI(2, TRUE); - InitEHCI(0, TRUE); -} - -void WriteSbApicIndexedReg(u8 Idx, u32 Data) -{ - u32 Data32; - u32 ApicIdxAdr = VX800SB_APIC_BASE; - u32 ApicDataAdr = VX800SB_APIC_BASE + VX800SB_APIC_DATA_OFFSET; - *((u8 *) ApicIdxAdr) = Idx; - Data32 = (*((u32 *) ApicDataAdr)); //this read is needed when write APIC ID ,dont know why. - Data32 = Data; - *((u32 *) ApicDataAdr) = Data32; -} - -void SbApicMmioRegInit(void) -{ - u32 Offset; - WriteSbApicIndexedReg(3, 1); - WriteSbApicIndexedReg(0, 4); - for (Offset = 0x10; Offset < VX800SB_APIC_ENTRY_NUMBER; - Offset += 2) { - WriteSbApicIndexedReg(Offset + 1, 0); - WriteSbApicIndexedReg(Offset, 0x10000); - } -} - -void SbApicInit(u8 sbchiprev) -{ - via_pci_inittable(sbchiprev, mSbApicInitTable); - SbApicMmioRegInit(); -} - -void SbAcpiInit(void) -{ - u8 Mask, Value; - // Enable ACPI - Mask = 0x01; - Value = 0x01; - io_rawmodify_config8(VX800_ACPI_IO_BASE + 0x04, Value, Mask); -} - -#define HPET_ENABLE_BIT 0x80 -#define R_SB_HPET_CONTROL 0x68 -#define HPET_BASE_ADDRESS 0xFED0 // 0xFED00000 -#define R_SB_HPET_ADDRESS 0x69 - -void HpetInit(void) -{ - u8 HpetEnable = HPET_ENABLE_BIT; - u16 HpetBase = HPET_BASE_ADDRESS; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL, - HpetEnable); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), - R_SB_HPET_ADDRESS + 1, HpetBase); -} - -static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = { - // Power Management - { 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20 }, - { 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18 }, - - //Miscellaneous Configuration 1 - { 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28 }, - { 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1 }, - { 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10 }, - { 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2 }, - - //Voltage Change Function Enable - { 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21 }, - //Internal PCIe and NM PLL Control - { 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA }, - - { 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80 }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void InitPMU(u8 sbchiprev) -{ - u8 Mask, Value; - // Set PMU Registers - via_pci_inittable(sbchiprev, mPMUInitTable); - - - // Set SCI IRQ and its level trigger - Mask = 0x0F; - Value = 0x09; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x82, Value, Mask); - - Mask = 0x02; - Value = 0x02; - io_rawmodify_config8(0x4d1, Value, Mask); -} - -#define R_SB_MULTI_FUNCTION_SELECT_1 0xE4 -#define R_SB_CX_STATE_BREAK_EVENT_ENABLE_1 0xE6 -#define PMIO_PROCESSOR_CONTROL 0x26 -#define R_SB_PCI_ARBITRATION_2 0x76 -#define R_SB_AUTO_SWITCH_P_STATE 0x8A - -void InitCPUCStatueSupport() -{ - u8 Mask, Value; - - // Config Cx State - // Now it is C2 & C4 Up Down Mode - Mask = 0xFF; - Value = 0x30; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask); //SB_LPC_REG - - Mask = 0xFF; - Value = 0x1F; - io_rawmodify_config8(VX800_ACPI_IO_BASE + PMIO_PROCESSOR_CONTROL, - Value, Mask); - - Mask = 0x00; - Value = 0x80; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask); //SB_VLINK_REG - - Mask = 0xFF; - Value = 0x00; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask); //SB_VLINK_REG - - Mask = 0xFF; - Value = 0x1F; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask); //SB_VLINK_REG -} - -void InitSBPM(u8 sbchiprev) -{ - InitPMU(sbchiprev); - SbAcpiInit(); - InitCPUCStatueSupport(); -} - -void Stage2SbInit(void) -{ - device_t_raw rawdevice = 0; - u8 sbchiprev; - - rawdevice = PCI_RAWDEV(0, 11, 0); - sbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev); - - //SBBasicInit - via_pci_inittable(sbchiprev, mBusControllerInitTable); - via_pci_inittable(sbchiprev, mPCI1InitTable); - via_pci_inittable(sbchiprev, mCCAInitTable); - - - InitIDEC(sbchiprev); - - InitUSBC(sbchiprev); - - InitSBPM(sbchiprev); - - SbApicInit(sbchiprev); - - HpetInit(); - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG - -} - -void init_VIA_chipset(void) -{ - printk(BIOS_DEBUG, "In: init_VIA_chipset\n"); - //1.nbstage1 is done in raminit. - //2.sbstage1 - AcpiInit(); - //3.nbstage2 - Stage2NbInit(); - - //4.sbstage2 - Stage2SbInit(); - - //5.open hdac - pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04); - printk(BIOS_DEBUG, "End: init_VIA_chipset\n"); -} - -/** - * @brief Main function of the DRAM part of coreboot. - * - * Coreboot is divided into Pre-DRAM part and DRAM part. - * - * - * Device Enumeration: - * In the dev_enumerate() phase, - */ - -void main(void) -{ - struct lb_memory *lb_mem; -#if CONFIG_HAVE_ACPI_RESUME - void *wake_vec; -#endif - - u16 tmp; - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - acpi_sleep_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - - u8 y, x; - init_VIA_chipset(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - -#if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, - pci_rawread_config8(PCI_RAWDEV(0, 3, 0), - 0x88)); -#endif - - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40); //close CE-ATA (Consumer Electronics-ATA) and NFC - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40); //close USB Device Mode - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5 - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci - - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb - - printk(BIOS_INFO, "=================SB 50h=%02x \n", - pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50)); - - /* FIXME: Is there a better way to handle this? */ - init_timer(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - - /* Find the devices we don't have hard coded knowledge about. */ - dev_enumerate(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV - (0, 0x10, 4), - x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - post_code(0x66); - /* Now compute and assign the bus resources. */ - dev_configure(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - post_code(0x88); - /* Now actually enable devices on the bus */ - dev_enable(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - /* And of course initialize devices on the bus */ -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - dev_initialize(); - post_code(0x89); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - -// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571); - -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - -#if 0 - y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d); - y &= 0x0f; - y |= 0x40; - pci_rawwrite_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d, y); -#endif - -#if 0 - static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD }; - static const d0f2pcitable[16 * 7 + 1] = { - 0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09, - 0x00, 0x00, 0x10, 0xA2, 0x88, 0xCE, - 0xFF, 0x0F, 0x00, 0xAA, 0x0A, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xCC, 0x66, 0xAA, 0x55, 0x30, 0x38, 0x0C, 0x00, 0x00, 0x00, - 0x00, 0x22, 0x00, 0xAA, 0x00, 0x00, - 0x44, 0x44, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0B, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0A, 0x01, 0x41, 0x06, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x88, 0x56, 0x70, 0x77, 0x77, 0x07, 0x77, 0x77, 0x04, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x33, 0x33, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x44, 0x44, 0x14, 0x00, - 0x75 - }; - - static const d0f4pcitable[16 * 6 + 3] = { - 0x30, 0x00, 0x00, - 0xFF, 0xFF, 0xCC, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0xE0, 0xD6, 0x80, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x02, 0x03, 0x04, 0x04, 0x00, 0x00, 0x04, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x12, 0x12, 0x00, 0x00, 0x08, 0xF4, - 0x01, 0x01, 0x79, 0x79, 0x0A, 0x00, - }; - static const d0f5pcitable[16 * 10] = { - 0x13, 0x0E, 0x00, 0x00, 0xD2, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x18, 0x9A, 0x00, 0x81, 0x28, 0xC0, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x26, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - - static const d0f7pcitable[16 * 9] = { - 0x00, 0x2A, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x29, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - static const d1f0pcitable[3] = { - 0x01, 0x80, 0x40 - }; - - static const dcf0pcitable[96] = { - 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0xC2, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x40, 0x01, 0x03, 0x01, 0x7E, 0x01, - 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF9, - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - - static const d10f4pcitable[48] = { - 0x00, 0x20, 0x43, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x9E, 0x68, - 0x00, 0x09, 0x13, 0x94, 0x03, 0x10, - 0x80, 0x60, 0x11, 0xBF, 0x00, 0xFF, 0x0F, 0x00, 0x04, 0x0B, - 0xCC, 0xCC, 0x00, 0xCC, 0x00, 0x00, - 0x20, 0x20, 0x01, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x00, 0xC0, - }; - - static const d11f0pcitable[16 * 12] = { - 0x44, 0x40, 0xF0, 0x0B, 0x00, 0x00, 0x00, 0x03, 0x00, 0x20, - 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, - 0xC1, 0x4D, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, - 0x00, 0x51, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x80, 0x00, - 0xD0, 0xFE, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x11, 0x09, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, - 0x20, 0x84, 0x49, 0x00, 0x88, 0x00, 0x00, 0x00, 0x01, 0x08, - 0x1F, 0x00, 0x07, 0x1A, 0x00, 0x00, - 0x00, 0x6E, 0xBC, 0x88, 0x28, 0xC1, 0x10, 0x80, 0x00, 0x80, - 0x20, 0x88, 0x00, 0x00, 0x00, 0xAD, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, - 0x00, 0x00, 0x10, 0xD0, 0xFE, 0x90, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xE7, 0x03, 0xA0, 0x60, 0x20, 0xC0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - }; - - static const d11f7pcitable[192] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x43, - 0x08, 0x80, 0x11, 0x11, 0x02, 0x0F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x20, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x82, 0xC8, 0xEE, 0x01, 0x0C, 0x0F, 0xD0, 0x48, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x07, 0x00, 0x21, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x93, 0x08, 0x00, 0x5E, 0x00, 0x80, 0x29, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, - }; - -#define OPTION_1 1 -#define NOOPTION_1 1 -#ifdef OPTION_1 - static const OPTION_1_d11f0pcitable[16 * 12] = { - 0x44, 0x80, 0xf0, 0x0b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x20, - 0x00, 0x00, 0x04, 0x01, 0x08, 0x00, - 0xc0, 0x4d, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, - 0x00, 0x53, 0x00, 0xfe, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x80, 0x00, - 0xd0, 0xfe, 0x00, 0x00, 0xdf, 0x00, - 0x06, 0x11, 0x53, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x84, 0x4a, 0x00, 0xda, 0x40, 0x00, 0x00, 0x01, 0x40, - 0x1f, 0x00, 0x07, 0x18, 0x00, 0x00, - 0x00, 0x2e, 0xbc, 0x00, 0x28, 0xc1, 0x10, 0x80, 0x00, 0x80, - 0x08, 0x88, 0x00, 0x00, 0x00, 0xad, - 0x06, 0x11, 0x53, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x40, 0x80, 0x40, - 0x00, 0x00, 0x00, 0xd3, 0xfe, 0x53, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x41, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xeb, 0x03, 0xa0, 0x60, 0x20, 0x80, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - }; -#endif - - u8 i; -/* error form ---- but add the chance to resume - for(i=0;i<5;i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); - } -*/ - -/* RO reg - for(i=0;i<5;i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); - } -*/ - -//boot ok, resume still err in linux -#if 1 - for (i = 0; i < 9; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } - //9 is warm reset reg, // boot err in coreboot - for (i = 10; i < 64; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } - //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash. - for (i = 65; i < 113; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } -#endif -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x66, 0x09); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x70, 0xdd); - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x90, 0x09); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x92, 0x40); - -#endif - - - -#if 1 - - -//d0f3 -/* */ - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 - //set bit4 cause the ide not be found -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b); - //set bit1 cause the ide not be found - -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12); - - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00); -#endif - -//boot ok, resume err in coreboot -#if 1 - for (i = 0; i < 99; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d, - d0f4pcitable[i]); - } -#endif - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xe9, 0x90); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xec, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xed, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xee, 0x0); -#endif - - -#if 1 -//boot ok, resume still err in linux - for (i = 0; i < 160; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60, - d0f5pcitable[i]); - } - for (i = 0; i < 144; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60, - d0f7pcitable[i]); - } - for (i = 0; i < 3; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0, - d1f0pcitable[i]); - } - for (i = 0; i < 96; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40, - dcf0pcitable[i]); - } -#endif - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x61, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x63, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x76, 0xd0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x88, 0x81); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x89, 0x01); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x8A, 0x60); -#endif - -//d15f0 - -#if 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2); - -//boot ok, resume still err in linux, and if disable USB, then all ok -// for(i=0;i<48;i++){ - for (i = 0; i < 44; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40, - d10f4pcitable[i]); - } -#endif - -//#ifdef NOOPTION_1 -#if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6b, 0x01); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6d, 0x00); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6e, 0x08); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80); -#endif - -#if 1 -//before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok -// for(i=0;i<192;i++){ - for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail - - //7-18 is my familar part - for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# - for (i = 24; i < 27; i++) { //sleep ok , resume sleep err 1 resume 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //5b port 80h - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08); - // i++; - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]); - - for (i = 28; i < 72; i++) { //sleep ok , resume sleep err 1 , resume 1ci - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //7273ACPI BASE - - for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - //B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]); - i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); - //multiplex with VCP - // i = i | 0x30; - i = i & 0xf7; - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i); - - - - for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - - for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } -#endif -#ifdef NOOPTION_1 -// for(i=0;i<192;i++){ - for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail - - //7-18 is my familar part - for (i = 7; i < 18; i++) { // sleep err 2 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 18; i < 21; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# - for (i = 24; i < 27; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //5b port 80h - i++; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - - for (i = 28; i < 72; i++) { //sleep ok , resume??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - //7273ACPI BASE - - for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - //B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]); - i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); - //multiplex with VCP - // i = i | 0x30; - i = i & 0xf7; - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i); - - - - for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } -#endif - -#if 1 - pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); //5324 - pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0, - PCI_VENDOR_ID_VIA); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); //8353 - i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79); - i &= ~0x40; - i |= 0x40; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); - -//boot ok, resume still err in linux - for (i = 0; i < 192; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, - d11f7pcitable[i]); - } -#endif -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x61, 0x2a); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x63, 0xa0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x64, 0xaa); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x84, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f); -#endif - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31); - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00); -#endif -#endif - - u8 i911; - //disable CHB L.L - //set VGA memory selection - i911 = pci_rawread_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0); - i911 &= 0xF8; - //ByteVal |= 0x03; - i911 |= 0x01; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911); - -#if 1 - struct device *dev; - printk(BIOS_INFO, "========= dump all devices...\n"); - for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type == DEVICE_PATH_PCI) { - printk(BIOS_DEBUG, "%s dump\n", dev_path(dev)); - x = y = 0; - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_read_config8(dev, x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } - } - printk(BIOS_INFO, "\n"); - } -#endif - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);// - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// -} diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c deleted file mode 100644 index c62de6e..0000000 --- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - #include "northbridge/via/vx800/driving_clk_phase_data.h" - -// DQS Driving -//Reg0xE0, 0xE1 -// According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE}; -static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE}; - -// DQ Driving -//Reg0xE2, 0xE3 -// For DDR2: According to bank to set DRAM DQ Driving -static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; -static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; - - -// CS Driving -//Reg0xE4, 0xE5 -// According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44}; -static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44}; -static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44}; -// MAA Driving -//Reg0xE8, Reg0xE9 -static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = - { - //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~ - }; - -static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = - { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - { 6, 0x86 }, // total MAB chips = 00 ~ 06 - { 18, 0x86 }, // total MAB chips = 06 ~ 18 - {255, 0xDB } // total MAB chips = 18 ~ - }; - -// DCLK Driving -//Reg0xE6, 0xE7 -// For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M - -static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; -static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; - -/* -Duty cycle -Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB -D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF -According to DRAM frequency to control Duty Cycle -*/ -static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank - {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 }, - {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30} - }; - -static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank - {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 } - }; - - -/* -DRAM Clock Phase Control for FeedBack Mode -Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 -Processing: - 1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode - 2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b - 3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO - ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b - */ -static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } - }; - -static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank - {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 }, - {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 } - }; - -/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank - {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, - {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 } - };*/ - -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } - }; - -/* -DRAM Write Data phase control -Modify NB Reg: Rx74/Rx75/Rx76 -*/ -/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank - {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, - {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 } - };*/ - -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank - {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 }, - {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 }, - {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } - }; - -/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank - {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, - {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 } - }; -*/ -/* -DQ/DQS Output Delay Control -Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 -*/ -static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = - { - // RxF0 RxF1 RxF2 RxF3 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 - }; -static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = - { - // RxF4 RxF5 RxF6 RxF7 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 - }; - -/* -DQ/DQS input Capture Control -modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B -*/ - -/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } - };*/ - - -static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 } - }; - -static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank - {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 }, - {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 } - }; - -static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = -{ -// Rx70 Rx71 - { 0x00, 0x05 }, // DDR800 - { 0x00, 0x06 }, // DDR667 - { 0x00, 0x04 }, // DDR533 - { 0x00, 0x05 } // DDR400 -}; -static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = -{ -// Rx70 Rx71 - {0x00 , 0x04}, // DDR800 - {0x00 , 0x04}, // DDR667 - {0x00 , 0x03}, // DDR533 - {0x00 , 0x04} // DDR400 -}; diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c deleted file mode 100644 index c96511e..0000000 --- a/src/northbridge/via/vx800/examples/romstage.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include "console/console.c" -#include "lib/ramtest.c" -#include "northbridge/via/vx800/vx800.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" -#include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "lib/memcpy.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "driving_clk_phase_data.c" -#include "northbridge/via/vx800/raminit.h" -#include "northbridge/via/vx800/raminit.c" - -static int acpi_is_wakeup_early_via_vx800(void) -{ - device_t dev; - u16 tmp, result; - - print_debug("In acpi_is_wakeup_early_via_vx800\n"); - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_LPC), 0); - - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); - - /* Enable ACPI access RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - print_debug(" boot_mode="); - print_debug_hex16(result); - print_debug("\n"); - return result; -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - device_t dev; - uint16_t values; - - print_debug("In enable_mainboard_devices \n"); - - /* Enable P2P bridge Header for external PCI bus. */ - dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); - pci_write_config8(dev, 0x4f, 0x41); -} - -static void enable_shadow_ram(void) -{ - uint8_t shadowreg; - - pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); - /* 0xf0000-0xfffff - ACPI tables */ - shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); - /* 0xe0000-0xeffff - elfload? */ - - pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); -} - -/* -this table contains the value needed to be set before begin to init dram. -Note: REV_Bx should be cared when porting a new board!!!!! */ -static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { - //VT3409 no pcie - 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range - 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control - // Set ROMSIP value by software - - /*0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit - 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 - 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 - 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB - 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD - 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) - 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) - 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */ - - - // CPU Host Bus Control - 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy - 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer - 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 - 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 - - - // Set APIC and SMRAM - 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control - 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg - 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table -}; - -#define USE_VCP 1 //0 means use DVP -#define USE_COM1 1 -#define USE_COM2 0 - -#define gCom1Base 0x3f8 -#define gCom2Base 0x2f8 - -void EmbedComInit(void) -{ - u8 ByteVal; - u16 ComBase; - - //enable NB multiple function control - ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f); - ByteVal = ByteVal | 0x01; - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal); - - //VGA Enable - ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1); - ByteVal = ByteVal | 0x80; - pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal); - - ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7); - ByteVal = ByteVal | 0x08; - pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal); - - //Enable p2p IO/mem - ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4); - ByteVal = ByteVal | 0x07; - pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal); - - //Turn on Graphic chip IO port port access - ByteVal = inb(0x3C3); - ByteVal = ByteVal | 0x01; - outb(ByteVal, 0x3C3); - - //Turn off Graphic chip Register protection - outb(0x10, 0x3C4); - ByteVal = inb(0x3C5); - ByteVal = ByteVal | 0x01; - outb(ByteVal, 0x3C5); - - //south module pad share enable 0x3C5.78[7] - outb(0x78, 0x3C4); - ByteVal = inb(0x3C5); - ByteVal = ByteVal | 0x80; - outb(ByteVal, 0x3C5); - - //enable UART Function multiplex with DVP or VCP pad D17F0Rx46[7,6] - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46); - //multiplex with VCP - if (USE_VCP == 1) - ByteVal = (ByteVal & 0x3F) | 0x40; - //multiplex with DVP - else - ByteVal = (ByteVal & 0x3F) | 0xC0; - pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); - - //enable embeded com1 and com2 D17F0RxB0[5,4] - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); - ByteVal = ByteVal & 0xcf; - //multiplex with VCP - if (USE_COM1 == 1) - ByteVal = ByteVal | 0x10; - if (USE_COM2 == 1) - ByteVal = ByteVal | 0x20; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal); - - if (USE_COM1 == 1) - ComBase = gCom1Base; - else - ComBase = gCom2Base; - -//noharddrive - - //set embeded com1 IO base = 0x3E8 - //D17F0RB4 - //ByteVal = 0xFD; - if (USE_COM1 == 1) { - ByteVal = (u8) ((gCom1Base >> 3) | 0x80); - pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); - ByteVal = (ByteVal & 0xf0) | 0x04; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); - } - //set embeded com2 IO base = 0x2E8 - //D17F0RB5 - //ByteVal = 0xDD; - if (USE_COM2 == 1) { - ByteVal = (u8) ((gCom2Base >> 3) | 0x80); - pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); - ByteVal = (ByteVal & 0x0f) | 0x30; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); - } - //no port 80 biger then 0x10 - - //disable interrupt - ByteVal = inb(ComBase + 3); - outb(ByteVal & 0x7F, ComBase + 3); - outb(0x00, ComBase + 1); - - //set baudrate - ByteVal = inb(ComBase + 3); - outb(ByteVal | 0x80, ComBase + 3); - outb(0x01, ComBase); - outb(0x00, ComBase + 1); - - //set frame fromat - ByteVal = inb(ComBase + 3); - outb(ByteVal & 0x3F, ComBase + 3); - outb(0x03, ComBase + 3); - outb(0x00, ComBase + 2); - outb(0x00, ComBase + 4); - - //SOutput("Embeded com output\n"); - //while(1); -} - -void main(unsigned long bist) -{ - unsigned cpu_reset = 0; - u16 boot_mode; - u8 rambits; - - //device_t dev; - /* Enable multifunction for northbridge. */ - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); - EmbedComInit(); - //enable_vx800_serial(); - //uart_init(); - -/* 1. D15F0 - -a) RxBAh = 71h - -b) RxBBh = 05h - -c) RxBEh = 71h - -d) RxBFh = 05h - -2. D17F0 - -a) RxA0h = 06h - -b) RxA1h = 11h - -c) RxA2h = 27h - -d) RxA3h = 32h - -e) Rx79h = 40h - -f) Rx72h = 27h - -g) Rx73h = 32h -*/ - - u8 Data8; - - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2, - PCI_DEVICE_ID_VIA_VX855_LPC); - Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79); - Data8 &= ~0x40; - Data8 |= 0x40; - pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); - - console_init(); //there are to function defination of console_init(), while the src/archi386/lib is the right one - - /* decide if this is a s3 wakeup or a normal boot */ - boot_mode = acpi_is_wakeup_early_via_vx800(); - /*add this, to transfer "cpu restart" to "cold boot" - When this boot is not a S3 resume, and PCI registers had been written, - then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */ - if ((boot_mode != 3) - && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { - outb(6, 0xcf9); - } - - /*x86 cold boot I/O cmd */ - enable_smbus(); - //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this - - if (bist == 0) { - // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); - //print_debug("doing early_mtrr\n"); - //early_mtrr_init(); - } - - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - print_debug("Enabling mainboard devices\n"); - enable_mainboard_devices(); - - u8 Data; - device_t device; - /* Get NB Chip revision from D0F4RxF6, revision will be used in via_pci_inittable */ - device = PCI_DEV(0, 0, 4); - Data = pci_read_config8(device, 0xf6); - print_debug("NB chip revision ="); - print_debug_hex8(Data); - print_debug("\n"); - /* make NB ready before draminit */ - via_pci_inittable(Data, mNbStage1InitTbl); - - /*add this. - When resume from s3, draminit is skiped, so need to recovery any PCI register related to draminit. - and d0f3 didnt lost its Power during whole s3 time, so any register not belongs to d0f3 need to be recoveried . */ -#if 1 - if (boot_mode == 3) { - u8 i; - u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - DRAM_SYS_ATTR DramAttr; - - print_debug("This is a S3 wakeup\n"); - - memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); - /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */ - DRAMDetect(&DramAttr); - - /*begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot */ - device = PCI_DEV(0, 0, 3); - for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - rambits = pci_read_config8(device, ramregs[i]); - if (rambits != 0) - break; - } - - DRAMDRDYSetting(&DramAttr); - - Data = 0x80; // this value is same with dev_init.c - pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); - pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2); - Data = pci_read_config8(MEMCTRL, 0x88); - pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data); - - DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here! - SetUMARam(); // I just copy this function from draminit to here! - print_debug("Resume from S3, RAM init was ignored\n"); - } else { - ddr2_ram_setup(); - ram_check(0, 640 * 1024); - } -#endif - //ddr2_ram_setup(); - /*this line is the same with cx700 port . */ - enable_shadow_ram(); - - /* - For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, - so before this happen, I need to backup the content of mem to top-mem. - I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c - */ -#if PAYLOAD_IS_SEABIOS==1 // - if (boot_mode == 3) { - /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html - I want move the 1M data, I have to set some MTRRs myself. */ - /* setting mtrr before back memory save s3 resume time about 0.14 seconds */ - /*because CAR stack use cache, and here to use cache , must be careful, - 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) - 2 before stack switch, no use variable that have value set before this - 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. - */ - u32 memtop = *(u32 *) WAKE_MEM_INFO; - u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000; - u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000; - u32 memtop3 = - *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000; - u32 memtop4 = - *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + - 0xe0000; - /* __asm__ volatile ( - "movl $0x204, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl %0,%%eax\n\t" - "orl $(0 | 6), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x205, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" - "orl $(0 | 0x800), %%eax\n\t" - "wrmsr\n\t" - ::"g"(memtop2) - ); - __asm__ volatile ( - "movl $0x206, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl %0,%%eax\n\t" - "orl $(0 | 6), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x207, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" - "orl $(0 | 0x800), %%eax\n\t" - "wrmsr\n\t" - ::"g"(memtop1) - ); - __asm__ volatile ( - "movl $0x208, %ecx\n\t" - "xorl %edx, %edx\n\t" - "movl $0,%eax\n\t" - "orl $(0 | 6), %eax\n\t" - "wrmsr\n\t" - - "movl $0x209, %ecx\n\t" - "xorl %edx, %edx\n\t" - "movl $0x100000,%eax\n\t" - "decl %eax\n\t" - "notl %eax\n\t" - "orl $(0 | 0x800), %eax\n\t" - "wrmsr\n\t" - ); - */ - // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c - // these two memcpy not not be enabled if set the MTRR around this two lines. - /*__asm__ volatile ( - "movl $0, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0xa0000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) - ); - __asm__ volatile ( - "movl $0xe0000, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0x20000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) - );*/ - print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this - memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - - 64 * 1024 - 0x100000), - (unsigned char *) 0, 0xa0000); - memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - - 64 * 1024 - 0x100000 + 0xe0000), - (unsigned char *) 0xe0000, 0x20000); - - /* restore the MTRR previously modified. */ -/* __asm__ volatile ( - "wbinvd\n\t" - "xorl %edx, %edx\n\t" - "xorl %eax, %eax\n\t" - "movl $0x204, %ecx\n\t" - "wrmsr\n\t" - "movl $0x205, %ecx\n\t" - "wrmsr\n\t" - "movl $0x206, %ecx\n\t" - "wrmsr\n\t" - "movl $0x207, %ecx\n\t" - "wrmsr\n\t" - "movl $0x208, %ecx\n\t" - "wrmsr\n\t" - "movl $0x209, %ecx\n\t" - "wrmsr\n\t" - );*/ - } -#endif -}

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Patch set updated for coreboot: 9442977 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8086 -gerrit commit 94429779962e4295c74e75d28910789dcc692323 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:27:54 2015 +1100 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion Use 'delay.h' header rather than directly including 'delay.c' source. N.B. Some amdfam10 and K8 boards are not included in this changeset since unrelated issues are woven in there. Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 2 +- src/mainboard/a-trend/atc-6240/romstage.c | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 2 +- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/mahogany/romstage.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/p2b-d/romstage.c | 2 +- src/mainboard/asus/p2b-ds/romstage.c | 2 +- src/mainboard/asus/p2b-f/romstage.c | 2 +- src/mainboard/asus/p2b-ls/romstage.c | 2 +- src/mainboard/asus/p2b/romstage.c | 2 +- src/mainboard/asus/p3b-f/romstage.c | 2 +- src/mainboard/azza/pt-6ibd/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/biostar/m6tba/romstage.c | 2 +- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxc/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/ibm/e325/romstage.c | 2 +- src/mainboard/ibm/e326/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 2 +- src/mainboard/iwill/dk8s2/romstage.c | 2 +- src/mainboard/iwill/dk8x/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/mainboard/mitac/6513wu/romstage.c | 2 +- src/mainboard/msi/ms6119/romstage.c | 2 +- src/mainboard/msi/ms6147/romstage.c | 2 +- src/mainboard/msi/ms6156/romstage.c | 2 +- src/mainboard/msi/ms7135/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/mainboard/newisys/khepri/romstage.c | 2 +- src/mainboard/nokia/ip530/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 2 +- src/mainboard/sunw/ultra40/romstage.c | 2 +- src/mainboard/supermicro/h8dmr/romstage.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/mainboard/tyan/s1846/romstage.c | 2 +- src/mainboard/tyan/s2850/romstage.c | 2 +- src/mainboard/tyan/s2875/romstage.c | 2 +- src/mainboard/tyan/s2880/romstage.c | 2 +- src/mainboard/tyan/s2881/romstage.c | 2 +- src/mainboard/tyan/s2882/romstage.c | 2 +- src/mainboard/tyan/s2885/romstage.c | 2 +- src/mainboard/tyan/s2891/romstage.c | 2 +- src/mainboard/tyan/s2892/romstage.c | 2 +- src/mainboard/tyan/s2895/romstage.c | 2 +- src/mainboard/tyan/s4880/romstage.c | 2 +- src/mainboard/tyan/s4882/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/romstage.c | 2 +- src/mainboard/winent/mb6047/romstage.c | 2 +- 71 files changed, 71 insertions(+), 71 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 155a86d..bfe210e 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index baf8972..20846fd 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 9f918bb..73fef6e 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 5b9b6ca..279c15f 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 6e3de07..1a7c203 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -28,7 +28,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 906ff85..9b6006d 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <spd.h> diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index f49aa61..1c5debe 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -12,7 +12,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index c360245..daa4ad4 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -9,7 +9,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87360/pc87360.h> diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 16cc02b..67a1f7a 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 34f4514..c5d3f07 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index f96d4be..e642cbd 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 0b95475..ebdb095 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 2f8dc4f..5127618 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 87d0d71..0b1555c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -36,7 +36,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index f5c5654..4040c60 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -36,7 +36,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 28e4e60..7aa3688 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index af226d5..0d41d14 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index e46ce61..a93b743 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index dbc359a..6a5ad02 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 155a86d..bfe210e 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 2636d4e..a3aeb9a 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index bac2097..9c40af7 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 5035f57..667360a 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <lib.h> #include <spd.h> #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 4630820..7151d40 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 72c2dd0..03f00c4 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index ea33555..654c8c1 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include <superio/nsc/pc97317/pc97317.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index b9a5630..ac437ac 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -27,7 +27,7 @@ #include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "memory.c" diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 9a2af16..d1a0b09 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "../qemu-i440fx/memory.c" diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 3897551..e61c653 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 995a657..3ac2dfa 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 44fa4ca..1638863 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -35,7 +35,7 @@ #include <southbridge/sis/sis966/sis966.h> #include "southbridge/sis/sis966/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 008b353..cb83c08 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -37,7 +37,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 984b262..0785c54 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -43,7 +43,7 @@ #include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 54a543d..bb24b33 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 794fd15..4ccc7fe 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 0e579ef..47d8fda 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 9a45217..40c7137 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 0525aa9..208c0b3 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index ca7edad..8a17113 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71805f/f71805f.h> diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index e4ef459..fa5e914 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index c157c99..ea2c009 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index d3a51e4..403f8ef 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 95780bf..b4432e0 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 9073be1..9b9cb14 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 290423b..88992a5 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -38,7 +38,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 142a496..dd816e6 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -35,7 +35,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <reset.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 0f7d943..3f53a7f 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -17,7 +17,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 2fc5cbe..8a08c76 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 5599a24..5ce8090 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index ca02936..c1cbb1d 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 8c4724f..bb754b8 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 84198d2..bd4d7a1 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -33,7 +33,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 25ccd6e..6133006 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 6cecf18..9d1034b 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 201e686..c338642 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index c6d3734..7f291ae 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index ea2f4eb..fa3bcf5 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 0e1ac98..49ff6bc 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index acfcec3..78cccc2 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 0e1ac98..49ff6bc 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index d321a45..138d1c0 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 4856d46..93189f1 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 4e11a1f..881972d 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index b2fe6fd..086df63 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/lpc47b397/lpc47b397.h> diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 53432af..71646c2 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index c0a3918..a3ae994 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 373756f..4bf2615 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8235/early_serial.c" #include <spd.h> diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 8f64949..a10f755 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -35,7 +35,7 @@ #include <northbridge/via/vx800/vx800.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <string.h> /* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 7261e20..615ad2c 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 8204ae3..5a74255 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cx700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c" #include "northbridge/via/cx700/early_serial.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 7be35f9..905248e 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c"

1 0

Patch set updated for coreboot: c8e1d7b northbridge/via/vx800/examples: Remove rotting source
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8087 -gerrit commit c8e1d7b8d0d3abe2a19c221c84040e9b0951cf4c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:29:36 2015 +1100 northbridge/via/vx800/examples: Remove rotting source This is just bit-rotting and its likely this will continue to rot by the time someone notices it exits it will be too late (i.e., today). Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/vx800/examples/chipset_init.c | 1241 -------------------- .../via/vx800/examples/driving_clk_phase_data.c | 242 ---- src/northbridge/via/vx800/examples/romstage.c | 541 --------- 3 files changed, 2024 deletions(-) diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c deleted file mode 100644 index 3f9c70f..0000000 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ /dev/null @@ -1,1241 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if CONFIG_HAVE_ACPI_RESUME -#include <arch/acpi.h> -#endif -#include "../vx800.h" - -#include <arch/io.h> -#include "pci_rawops.h" - -static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = { - // Combine Stage1 registers - {0x00, 0xFF, SB_LPC_REG(0x41), 0x40, 0x40}, - - // Acpi init registers in sb stage1 - {0x00, 0xFF, SB_LPC_REG(0x40), 0x04, 0x04}, // Enable 4D0/4D1 support - {0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08}, // Enable RTC port 74/75 - {0x00, 0xFF, SB_LPC_REG(0x51), 0x0D, 0x0D}, // and KBC - {0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09}, // Enable Serial IRQ - {0x00, 0xFF, SB_LPC_REG(0x67), 0x00, 0x04}, // Set FERR voltage to 1.5v - {0x00, 0xFF, SB_LPC_REG(0x98), 0xFF, 0x00}, // Disable GP3 Timer - - {0x00, 0xFF, SB_IDEC_REG(0xb9), 0x01, 0x01}, - - {0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39}, // Enable SMM A-Seg, MSI and Io APIC - ///// SPI-BAR. - //// SPI_BASE_ADDRESS = 0xFED1 0000 - {0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00}, - {0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1}, - {0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE}, - ///// End of 2008-04-17 - - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mNbStage2InitTable[] = { - // D0F0: AGP Feature. For 3353, No AGP Feature - - // D0F2~D0F3 is configured by MemoryInit Peim - - // D0F4: NB PMU - { 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB }, - { 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05 }, - { 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8 }, - { 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF }, - { 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC }, - { 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19 }, - { 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00 }, - { 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF }, - { 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF }, - { 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC }, - { 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0 }, - { 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6 }, - { 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20 }, - - // D0F5: NB APIC, PXPTRF and MSGC - //Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex. - //Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase. - //Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase. - { 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18 }, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1. - { 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00 }, //Set RVC1RPSW, RVC1RQ1T to 1. - { 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0 }, - { 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01 }, // RWAKEEN - //{ 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00 }, //RTDNP2B32EN - { 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00 }, //RP2P1ABORT - - -// fine-tune -// If no settings, C7 will hang or reboot in XP, but CN will not. - { 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03 }, - { 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01 }, - { 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10 }, - { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08 }, - { 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04 }, // ACPI Base addr - { 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01 }, // APIC MSI - { 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00 }, // APIC MSI - //GTL - { 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66 }, - { 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20 }, - { 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00 }, - - - // End of Table - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = { - // D17F0: LPC - { 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44 }, // Enable I/O Recovery Time, 4D0/4D1 Support - { 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0 }, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD - { 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B }, // RENDTX, ENWBTO, ENRBTO - //{ 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10 }, // It is related to INTH# - //{ 0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C }, //RMRPW, RIRPW // Reserved in 409 by Eric - - // Internal RTC, Mouse, Keyboard // set in PEI by Eric - //{ 0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D }, // Enable Internal RTC, Internal PS2 Mouse/Keyboard - - // RTC - { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01 }, //RTC Rx32 Map to Centrury Byte - - //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02 }, // RDMEGAS - //{ 0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08 }, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric - - // Serial IRQ // set in PEI by Eric - //{ 0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09 }, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock. - - // Enable 4D0h/4D1h Port - //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04 }, // EISAXT // set in PEI by Eric - - // Config ROM Interface - // Enable SPI/Set SPI Memory Base Address - // It is initialized in PEI Phase - - // Subsystem ID/Vendor ID Back Door - { 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06 }, - { 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11 }, - { 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09 }, - { 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34 }, - - { 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40 }, - { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51 }, // Orgin value 0x53, modify for 409 by Eric - { 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01 }, - - - { 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00 }, // Setting PCI device enable - { 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00 }, // Setting PCI device enable - { 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00 }, // Setting HDAC enable - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = { - //PCI1 Programming Sequence - //(1)Configure D17F7 - { 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03 }, - { 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 }, // Reserved in 409 by Eric - { 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 }, //RENPPB, RP2CFLSH - { 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 }, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion - // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. - // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) - //(2)Configure D19F0 - { 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 }, - - //(3)Performance Recommended Setting - - //Save Power - { 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01 }, - { 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00 }, - //Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance - { 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82 }, - { 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0 }, - { 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE }, - - //Cycle Control - { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01 }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C }, - //Arbitration control - { 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F }, - { 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0 }, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = { - { 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08 }, //RVWREQ, ROABKDOOR - - //CCA's Register Programming sequence - { 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08 }, //Config Azalia's upstream cycle high priority and other low priority - { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80 }, //Disable bypass asynchronous circuit - { 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11 }, // Set SM Internal Device and HDAC Occupy Timer - { 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11 }, // Set SM Internal Device and HDAC Promote Timer - { 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02 }, //Use SB internal devices's original REQ - { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00 }, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C }, //RLCKXP2C, RFSBVK. - { 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00 }, //RBLKAPIC, RAZC3 - { 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02 }, //RNMIFSB, RFSBVK - { 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90 }, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme - { 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00 }, //Let CCA use dynamic clock. - //The CCA is also relate to D17F0 - //{ 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00 }, //Disable CCA Test Mode - { 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00 }, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = { - //{0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05}, //set to native mode - {0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07}, - //{0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F}, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = { - { 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40 }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04 }, - //{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void AcpiInit(void) -{ - device_t_raw rawdevice = 0; - u8 sbchiprev; - rawdevice = PCI_RAWDEV(0, 0x11, 0); - // Set the PMIO base io address - pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE, - 0xff80); - // Enable PMIO - pci_rawmodify_config16(rawdevice, 0x80, 0x8000, 0x8000); - // Enable Soft Resume - outw(inw(VX800_ACPI_IO_BASE + 0x04) | 0x8000, - VX800_ACPI_IO_BASE + 0x04); - - // Get SB Revision - sbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev); - - // Fill Register Table - via_pci_inittable(sbchiprev, mSbStage1InitTbl); - - // Close all SMI/Io Traps - outb(0x00, VX800_ACPI_IO_BASE + 0x42); -} - -void Stage2NbInit(void) -{ - device_t_raw rawdevice = 0; - u8 nbchiprev; - u32 subid = 0; - rawdevice = PCI_RAWDEV(0, 0, 4); - nbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "NB chip revision =%x\n", nbchiprev); - - via_pci_inittable(nbchiprev, mNbStage2InitTable); - - rawdevice = PCI_RAWDEV(0, 0, 0); - - subid = PCI_DEVICE_ID_VIA_VX855_D0F0 << 16 + PCI_VENDOR_ID_VIA; - pci_rawwrite_config32(rawdevice, 0x2C, subid); - - //vx855 NB no pcie bus - //vx855 NB no apic -} - -void IDECSupportOption(u8 sbchiprev) -{ - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0, 0x08); - - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x00, 0x80); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x0A, 0x01, 0xFF); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00); - - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE -// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE - - via_pci_inittable(sbchiprev, IDEC_INIT); -} - -void InitIDEC(u8 sbchiprev) -{ - IDECSupportOption(sbchiprev); -} - -void InitUHCI(u8 Number, u8 bEnable) -{ - u8 Mask, Value; - u16 D16; - u8 BaseAddress; - u8 BitShift; - // USB Device 16 - // Function : Number - // 0 : 0 - // 1 : 1 - // 2 : 2 - // The BitShift is got from Datasheet. - - switch (Number) { - case 0: - BaseAddress = 0; - BitShift = 4; - break; - case 1: - BaseAddress = 1; - BitShift = 5; - break; - case 2: - default: - BaseAddress = 2; - BitShift = 2; - break; - } - - if (bEnable) { - Mask = 0x1 << BitShift; - Value = 0x0; - } else { - Mask = 0x0; - Value = 0x1 << BitShift; - } - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask); - - - if (bEnable) { - D16 = 0; - pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x20, D16); - - // Config some Control Register - Mask = 0x00; - Value = 0x12; - - pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x41, Value, Mask); - Mask = 0x00; - Value = 0xEB; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x4B, Value, Mask); - } - return; -} - -static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = { - //EHCI - { 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0 }, - { 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80 }, - { 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E }, - { 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94 }, - { 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A }, - { 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A }, - { 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11 }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void InitEHCI(u8 Number, u8 bEnable) -{ - u8 Mask, Value; - u8 EHCIRevision; - - if (bEnable) { - Mask = 0x1 << 1; - Value = 0x0; - } else { - Mask = 0x0; - Value = 0x1 << 1; - } - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask); - - - if (bEnable) { - // Get Chipset Revision - EHCIRevision = - pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6); - printk(BIOS_DEBUG, "EHCI Revision =%x\n", EHCIRevision); - via_pci_inittable(EHCIRevision, mEHCIInitTable); - } -} - -#define TRUE 1 -void InitUSBC(u8 sbchiprev) -{ - InitUHCI(0, TRUE); - InitUHCI(1, TRUE); - InitUHCI(2, TRUE); - InitEHCI(0, TRUE); -} - -void WriteSbApicIndexedReg(u8 Idx, u32 Data) -{ - u32 Data32; - u32 ApicIdxAdr = VX800SB_APIC_BASE; - u32 ApicDataAdr = VX800SB_APIC_BASE + VX800SB_APIC_DATA_OFFSET; - *((u8 *) ApicIdxAdr) = Idx; - Data32 = (*((u32 *) ApicDataAdr)); //this read is needed when write APIC ID ,dont know why. - Data32 = Data; - *((u32 *) ApicDataAdr) = Data32; -} - -void SbApicMmioRegInit(void) -{ - u32 Offset; - WriteSbApicIndexedReg(3, 1); - WriteSbApicIndexedReg(0, 4); - for (Offset = 0x10; Offset < VX800SB_APIC_ENTRY_NUMBER; - Offset += 2) { - WriteSbApicIndexedReg(Offset + 1, 0); - WriteSbApicIndexedReg(Offset, 0x10000); - } -} - -void SbApicInit(u8 sbchiprev) -{ - via_pci_inittable(sbchiprev, mSbApicInitTable); - SbApicMmioRegInit(); -} - -void SbAcpiInit(void) -{ - u8 Mask, Value; - // Enable ACPI - Mask = 0x01; - Value = 0x01; - io_rawmodify_config8(VX800_ACPI_IO_BASE + 0x04, Value, Mask); -} - -#define HPET_ENABLE_BIT 0x80 -#define R_SB_HPET_CONTROL 0x68 -#define HPET_BASE_ADDRESS 0xFED0 // 0xFED00000 -#define R_SB_HPET_ADDRESS 0x69 - -void HpetInit(void) -{ - u8 HpetEnable = HPET_ENABLE_BIT; - u16 HpetBase = HPET_BASE_ADDRESS; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL, - HpetEnable); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), - R_SB_HPET_ADDRESS + 1, HpetBase); -} - -static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = { - // Power Management - { 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20 }, - { 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18 }, - - //Miscellaneous Configuration 1 - { 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28 }, - { 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1 }, - { 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10 }, - { 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2 }, - - //Voltage Change Function Enable - { 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21 }, - //Internal PCIe and NM PLL Control - { 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA }, - - { 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80 }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void InitPMU(u8 sbchiprev) -{ - u8 Mask, Value; - // Set PMU Registers - via_pci_inittable(sbchiprev, mPMUInitTable); - - - // Set SCI IRQ and its level trigger - Mask = 0x0F; - Value = 0x09; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x82, Value, Mask); - - Mask = 0x02; - Value = 0x02; - io_rawmodify_config8(0x4d1, Value, Mask); -} - -#define R_SB_MULTI_FUNCTION_SELECT_1 0xE4 -#define R_SB_CX_STATE_BREAK_EVENT_ENABLE_1 0xE6 -#define PMIO_PROCESSOR_CONTROL 0x26 -#define R_SB_PCI_ARBITRATION_2 0x76 -#define R_SB_AUTO_SWITCH_P_STATE 0x8A - -void InitCPUCStatueSupport() -{ - u8 Mask, Value; - - // Config Cx State - // Now it is C2 & C4 Up Down Mode - Mask = 0xFF; - Value = 0x30; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask); //SB_LPC_REG - - Mask = 0xFF; - Value = 0x1F; - io_rawmodify_config8(VX800_ACPI_IO_BASE + PMIO_PROCESSOR_CONTROL, - Value, Mask); - - Mask = 0x00; - Value = 0x80; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask); //SB_VLINK_REG - - Mask = 0xFF; - Value = 0x00; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask); //SB_VLINK_REG - - Mask = 0xFF; - Value = 0x1F; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask); //SB_VLINK_REG -} - -void InitSBPM(u8 sbchiprev) -{ - InitPMU(sbchiprev); - SbAcpiInit(); - InitCPUCStatueSupport(); -} - -void Stage2SbInit(void) -{ - device_t_raw rawdevice = 0; - u8 sbchiprev; - - rawdevice = PCI_RAWDEV(0, 11, 0); - sbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev); - - //SBBasicInit - via_pci_inittable(sbchiprev, mBusControllerInitTable); - via_pci_inittable(sbchiprev, mPCI1InitTable); - via_pci_inittable(sbchiprev, mCCAInitTable); - - - InitIDEC(sbchiprev); - - InitUSBC(sbchiprev); - - InitSBPM(sbchiprev); - - SbApicInit(sbchiprev); - - HpetInit(); - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG - -} - -void init_VIA_chipset(void) -{ - printk(BIOS_DEBUG, "In: init_VIA_chipset\n"); - //1.nbstage1 is done in raminit. - //2.sbstage1 - AcpiInit(); - //3.nbstage2 - Stage2NbInit(); - - //4.sbstage2 - Stage2SbInit(); - - //5.open hdac - pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04); - printk(BIOS_DEBUG, "End: init_VIA_chipset\n"); -} - -/** - * @brief Main function of the DRAM part of coreboot. - * - * Coreboot is divided into Pre-DRAM part and DRAM part. - * - * - * Device Enumeration: - * In the dev_enumerate() phase, - */ - -void main(void) -{ - struct lb_memory *lb_mem; -#if CONFIG_HAVE_ACPI_RESUME - void *wake_vec; -#endif - - u16 tmp; - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - acpi_sleep_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - - u8 y, x; - init_VIA_chipset(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - -#if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, - pci_rawread_config8(PCI_RAWDEV(0, 3, 0), - 0x88)); -#endif - - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40); //close CE-ATA (Consumer Electronics-ATA) and NFC - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40); //close USB Device Mode - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5 - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci - - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb - - printk(BIOS_INFO, "=================SB 50h=%02x \n", - pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50)); - - /* FIXME: Is there a better way to handle this? */ - init_timer(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - - /* Find the devices we don't have hard coded knowledge about. */ - dev_enumerate(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV - (0, 0x10, 4), - x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - post_code(0x66); - /* Now compute and assign the bus resources. */ - dev_configure(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - post_code(0x88); - /* Now actually enable devices on the bus */ - dev_enable(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - /* And of course initialize devices on the bus */ -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - dev_initialize(); - post_code(0x89); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - -// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571); - -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - -#if 0 - y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d); - y &= 0x0f; - y |= 0x40; - pci_rawwrite_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d, y); -#endif - -#if 0 - static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD }; - static const d0f2pcitable[16 * 7 + 1] = { - 0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09, - 0x00, 0x00, 0x10, 0xA2, 0x88, 0xCE, - 0xFF, 0x0F, 0x00, 0xAA, 0x0A, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xCC, 0x66, 0xAA, 0x55, 0x30, 0x38, 0x0C, 0x00, 0x00, 0x00, - 0x00, 0x22, 0x00, 0xAA, 0x00, 0x00, - 0x44, 0x44, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0B, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0A, 0x01, 0x41, 0x06, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x88, 0x56, 0x70, 0x77, 0x77, 0x07, 0x77, 0x77, 0x04, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x33, 0x33, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x44, 0x44, 0x14, 0x00, - 0x75 - }; - - static const d0f4pcitable[16 * 6 + 3] = { - 0x30, 0x00, 0x00, - 0xFF, 0xFF, 0xCC, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0xE0, 0xD6, 0x80, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x02, 0x03, 0x04, 0x04, 0x00, 0x00, 0x04, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x12, 0x12, 0x00, 0x00, 0x08, 0xF4, - 0x01, 0x01, 0x79, 0x79, 0x0A, 0x00, - }; - static const d0f5pcitable[16 * 10] = { - 0x13, 0x0E, 0x00, 0x00, 0xD2, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x18, 0x9A, 0x00, 0x81, 0x28, 0xC0, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x26, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - - static const d0f7pcitable[16 * 9] = { - 0x00, 0x2A, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x29, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - static const d1f0pcitable[3] = { - 0x01, 0x80, 0x40 - }; - - static const dcf0pcitable[96] = { - 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0xC2, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x40, 0x01, 0x03, 0x01, 0x7E, 0x01, - 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF9, - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - - static const d10f4pcitable[48] = { - 0x00, 0x20, 0x43, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x9E, 0x68, - 0x00, 0x09, 0x13, 0x94, 0x03, 0x10, - 0x80, 0x60, 0x11, 0xBF, 0x00, 0xFF, 0x0F, 0x00, 0x04, 0x0B, - 0xCC, 0xCC, 0x00, 0xCC, 0x00, 0x00, - 0x20, 0x20, 0x01, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x00, 0xC0, - }; - - static const d11f0pcitable[16 * 12] = { - 0x44, 0x40, 0xF0, 0x0B, 0x00, 0x00, 0x00, 0x03, 0x00, 0x20, - 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, - 0xC1, 0x4D, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, - 0x00, 0x51, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x80, 0x00, - 0xD0, 0xFE, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x11, 0x09, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, - 0x20, 0x84, 0x49, 0x00, 0x88, 0x00, 0x00, 0x00, 0x01, 0x08, - 0x1F, 0x00, 0x07, 0x1A, 0x00, 0x00, - 0x00, 0x6E, 0xBC, 0x88, 0x28, 0xC1, 0x10, 0x80, 0x00, 0x80, - 0x20, 0x88, 0x00, 0x00, 0x00, 0xAD, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, - 0x00, 0x00, 0x10, 0xD0, 0xFE, 0x90, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xE7, 0x03, 0xA0, 0x60, 0x20, 0xC0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - }; - - static const d11f7pcitable[192] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x43, - 0x08, 0x80, 0x11, 0x11, 0x02, 0x0F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x20, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x82, 0xC8, 0xEE, 0x01, 0x0C, 0x0F, 0xD0, 0x48, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x07, 0x00, 0x21, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x93, 0x08, 0x00, 0x5E, 0x00, 0x80, 0x29, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, - }; - -#define OPTION_1 1 -#define NOOPTION_1 1 -#ifdef OPTION_1 - static const OPTION_1_d11f0pcitable[16 * 12] = { - 0x44, 0x80, 0xf0, 0x0b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x20, - 0x00, 0x00, 0x04, 0x01, 0x08, 0x00, - 0xc0, 0x4d, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, - 0x00, 0x53, 0x00, 0xfe, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x80, 0x00, - 0xd0, 0xfe, 0x00, 0x00, 0xdf, 0x00, - 0x06, 0x11, 0x53, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x84, 0x4a, 0x00, 0xda, 0x40, 0x00, 0x00, 0x01, 0x40, - 0x1f, 0x00, 0x07, 0x18, 0x00, 0x00, - 0x00, 0x2e, 0xbc, 0x00, 0x28, 0xc1, 0x10, 0x80, 0x00, 0x80, - 0x08, 0x88, 0x00, 0x00, 0x00, 0xad, - 0x06, 0x11, 0x53, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x40, 0x80, 0x40, - 0x00, 0x00, 0x00, 0xd3, 0xfe, 0x53, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x41, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xeb, 0x03, 0xa0, 0x60, 0x20, 0x80, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - }; -#endif - - u8 i; -/* error form ---- but add the chance to resume - for(i=0;i<5;i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); - } -*/ - -/* RO reg - for(i=0;i<5;i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); - } -*/ - -//boot ok, resume still err in linux -#if 1 - for (i = 0; i < 9; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } - //9 is warm reset reg, // boot err in coreboot - for (i = 10; i < 64; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } - //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash. - for (i = 65; i < 113; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } -#endif -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x66, 0x09); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x70, 0xdd); - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x90, 0x09); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x92, 0x40); - -#endif - - - -#if 1 - - -//d0f3 -/* */ - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 - //set bit4 cause the ide not be found -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b); - //set bit1 cause the ide not be found - -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12); - - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00); -#endif - -//boot ok, resume err in coreboot -#if 1 - for (i = 0; i < 99; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d, - d0f4pcitable[i]); - } -#endif - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xe9, 0x90); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xec, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xed, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xee, 0x0); -#endif - - -#if 1 -//boot ok, resume still err in linux - for (i = 0; i < 160; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60, - d0f5pcitable[i]); - } - for (i = 0; i < 144; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60, - d0f7pcitable[i]); - } - for (i = 0; i < 3; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0, - d1f0pcitable[i]); - } - for (i = 0; i < 96; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40, - dcf0pcitable[i]); - } -#endif - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x61, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x63, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x76, 0xd0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x88, 0x81); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x89, 0x01); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x8A, 0x60); -#endif - -//d15f0 - -#if 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2); - -//boot ok, resume still err in linux, and if disable USB, then all ok -// for(i=0;i<48;i++){ - for (i = 0; i < 44; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40, - d10f4pcitable[i]); - } -#endif - -//#ifdef NOOPTION_1 -#if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6b, 0x01); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6d, 0x00); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6e, 0x08); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80); -#endif - -#if 1 -//before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok -// for(i=0;i<192;i++){ - for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail - - //7-18 is my familar part - for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# - for (i = 24; i < 27; i++) { //sleep ok , resume sleep err 1 resume 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //5b port 80h - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08); - // i++; - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]); - - for (i = 28; i < 72; i++) { //sleep ok , resume sleep err 1 , resume 1ci - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //7273ACPI BASE - - for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - //B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]); - i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); - //multiplex with VCP - // i = i | 0x30; - i = i & 0xf7; - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i); - - - - for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - - for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } -#endif -#ifdef NOOPTION_1 -// for(i=0;i<192;i++){ - for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail - - //7-18 is my familar part - for (i = 7; i < 18; i++) { // sleep err 2 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 18; i < 21; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# - for (i = 24; i < 27; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //5b port 80h - i++; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - - for (i = 28; i < 72; i++) { //sleep ok , resume??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - //7273ACPI BASE - - for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - //B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]); - i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); - //multiplex with VCP - // i = i | 0x30; - i = i & 0xf7; - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i); - - - - for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } -#endif - -#if 1 - pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); //5324 - pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0, - PCI_VENDOR_ID_VIA); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); //8353 - i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79); - i &= ~0x40; - i |= 0x40; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); - -//boot ok, resume still err in linux - for (i = 0; i < 192; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, - d11f7pcitable[i]); - } -#endif -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x61, 0x2a); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x63, 0xa0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x64, 0xaa); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x84, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f); -#endif - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31); - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00); -#endif -#endif - - u8 i911; - //disable CHB L.L - //set VGA memory selection - i911 = pci_rawread_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0); - i911 &= 0xF8; - //ByteVal |= 0x03; - i911 |= 0x01; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911); - -#if 1 - struct device *dev; - printk(BIOS_INFO, "========= dump all devices...\n"); - for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type == DEVICE_PATH_PCI) { - printk(BIOS_DEBUG, "%s dump\n", dev_path(dev)); - x = y = 0; - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_read_config8(dev, x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } - } - printk(BIOS_INFO, "\n"); - } -#endif - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);// - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// -} diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c deleted file mode 100644 index c62de6e..0000000 --- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - #include "northbridge/via/vx800/driving_clk_phase_data.h" - -// DQS Driving -//Reg0xE0, 0xE1 -// According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE}; -static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE}; - -// DQ Driving -//Reg0xE2, 0xE3 -// For DDR2: According to bank to set DRAM DQ Driving -static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; -static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; - - -// CS Driving -//Reg0xE4, 0xE5 -// According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44}; -static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44}; -static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44}; -// MAA Driving -//Reg0xE8, Reg0xE9 -static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = - { - //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~ - }; - -static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = - { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - { 6, 0x86 }, // total MAB chips = 00 ~ 06 - { 18, 0x86 }, // total MAB chips = 06 ~ 18 - {255, 0xDB } // total MAB chips = 18 ~ - }; - -// DCLK Driving -//Reg0xE6, 0xE7 -// For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M - -static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; -static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; - -/* -Duty cycle -Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB -D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF -According to DRAM frequency to control Duty Cycle -*/ -static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank - {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 }, - {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30} - }; - -static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank - {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 } - }; - - -/* -DRAM Clock Phase Control for FeedBack Mode -Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 -Processing: - 1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode - 2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b - 3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO - ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b - */ -static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } - }; - -static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank - {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 }, - {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 } - }; - -/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank - {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, - {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 } - };*/ - -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } - }; - -/* -DRAM Write Data phase control -Modify NB Reg: Rx74/Rx75/Rx76 -*/ -/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank - {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, - {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 } - };*/ - -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank - {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 }, - {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 }, - {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } - }; - -/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank - {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, - {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 } - }; -*/ -/* -DQ/DQS Output Delay Control -Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 -*/ -static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = - { - // RxF0 RxF1 RxF2 RxF3 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 - }; -static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = - { - // RxF4 RxF5 RxF6 RxF7 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 - }; - -/* -DQ/DQS input Capture Control -modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B -*/ - -/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } - };*/ - - -static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 } - }; - -static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank - {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 }, - {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 } - }; - -static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = -{ -// Rx70 Rx71 - { 0x00, 0x05 }, // DDR800 - { 0x00, 0x06 }, // DDR667 - { 0x00, 0x04 }, // DDR533 - { 0x00, 0x05 } // DDR400 -}; -static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = -{ -// Rx70 Rx71 - {0x00 , 0x04}, // DDR800 - {0x00 , 0x04}, // DDR667 - {0x00 , 0x03}, // DDR533 - {0x00 , 0x04} // DDR400 -}; diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c deleted file mode 100644 index c96511e..0000000 --- a/src/northbridge/via/vx800/examples/romstage.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include "console/console.c" -#include "lib/ramtest.c" -#include "northbridge/via/vx800/vx800.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" -#include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "lib/memcpy.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "driving_clk_phase_data.c" -#include "northbridge/via/vx800/raminit.h" -#include "northbridge/via/vx800/raminit.c" - -static int acpi_is_wakeup_early_via_vx800(void) -{ - device_t dev; - u16 tmp, result; - - print_debug("In acpi_is_wakeup_early_via_vx800\n"); - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_LPC), 0); - - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); - - /* Enable ACPI access RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - print_debug(" boot_mode="); - print_debug_hex16(result); - print_debug("\n"); - return result; -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - device_t dev; - uint16_t values; - - print_debug("In enable_mainboard_devices \n"); - - /* Enable P2P bridge Header for external PCI bus. */ - dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); - pci_write_config8(dev, 0x4f, 0x41); -} - -static void enable_shadow_ram(void) -{ - uint8_t shadowreg; - - pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); - /* 0xf0000-0xfffff - ACPI tables */ - shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); - /* 0xe0000-0xeffff - elfload? */ - - pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); -} - -/* -this table contains the value needed to be set before begin to init dram. -Note: REV_Bx should be cared when porting a new board!!!!! */ -static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { - //VT3409 no pcie - 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range - 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control - // Set ROMSIP value by software - - /*0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit - 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 - 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 - 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB - 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD - 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) - 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) - 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */ - - - // CPU Host Bus Control - 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy - 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer - 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 - 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 - - - // Set APIC and SMRAM - 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control - 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg - 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table -}; - -#define USE_VCP 1 //0 means use DVP -#define USE_COM1 1 -#define USE_COM2 0 - -#define gCom1Base 0x3f8 -#define gCom2Base 0x2f8 - -void EmbedComInit(void) -{ - u8 ByteVal; - u16 ComBase; - - //enable NB multiple function control - ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f); - ByteVal = ByteVal | 0x01; - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal); - - //VGA Enable - ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1); - ByteVal = ByteVal | 0x80; - pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal); - - ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7); - ByteVal = ByteVal | 0x08; - pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal); - - //Enable p2p IO/mem - ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4); - ByteVal = ByteVal | 0x07; - pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal); - - //Turn on Graphic chip IO port port access - ByteVal = inb(0x3C3); - ByteVal = ByteVal | 0x01; - outb(ByteVal, 0x3C3); - - //Turn off Graphic chip Register protection - outb(0x10, 0x3C4); - ByteVal = inb(0x3C5); - ByteVal = ByteVal | 0x01; - outb(ByteVal, 0x3C5); - - //south module pad share enable 0x3C5.78[7] - outb(0x78, 0x3C4); - ByteVal = inb(0x3C5); - ByteVal = ByteVal | 0x80; - outb(ByteVal, 0x3C5); - - //enable UART Function multiplex with DVP or VCP pad D17F0Rx46[7,6] - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46); - //multiplex with VCP - if (USE_VCP == 1) - ByteVal = (ByteVal & 0x3F) | 0x40; - //multiplex with DVP - else - ByteVal = (ByteVal & 0x3F) | 0xC0; - pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); - - //enable embeded com1 and com2 D17F0RxB0[5,4] - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); - ByteVal = ByteVal & 0xcf; - //multiplex with VCP - if (USE_COM1 == 1) - ByteVal = ByteVal | 0x10; - if (USE_COM2 == 1) - ByteVal = ByteVal | 0x20; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal); - - if (USE_COM1 == 1) - ComBase = gCom1Base; - else - ComBase = gCom2Base; - -//noharddrive - - //set embeded com1 IO base = 0x3E8 - //D17F0RB4 - //ByteVal = 0xFD; - if (USE_COM1 == 1) { - ByteVal = (u8) ((gCom1Base >> 3) | 0x80); - pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); - ByteVal = (ByteVal & 0xf0) | 0x04; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); - } - //set embeded com2 IO base = 0x2E8 - //D17F0RB5 - //ByteVal = 0xDD; - if (USE_COM2 == 1) { - ByteVal = (u8) ((gCom2Base >> 3) | 0x80); - pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); - ByteVal = (ByteVal & 0x0f) | 0x30; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); - } - //no port 80 biger then 0x10 - - //disable interrupt - ByteVal = inb(ComBase + 3); - outb(ByteVal & 0x7F, ComBase + 3); - outb(0x00, ComBase + 1); - - //set baudrate - ByteVal = inb(ComBase + 3); - outb(ByteVal | 0x80, ComBase + 3); - outb(0x01, ComBase); - outb(0x00, ComBase + 1); - - //set frame fromat - ByteVal = inb(ComBase + 3); - outb(ByteVal & 0x3F, ComBase + 3); - outb(0x03, ComBase + 3); - outb(0x00, ComBase + 2); - outb(0x00, ComBase + 4); - - //SOutput("Embeded com output\n"); - //while(1); -} - -void main(unsigned long bist) -{ - unsigned cpu_reset = 0; - u16 boot_mode; - u8 rambits; - - //device_t dev; - /* Enable multifunction for northbridge. */ - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); - EmbedComInit(); - //enable_vx800_serial(); - //uart_init(); - -/* 1. D15F0 - -a) RxBAh = 71h - -b) RxBBh = 05h - -c) RxBEh = 71h - -d) RxBFh = 05h - -2. D17F0 - -a) RxA0h = 06h - -b) RxA1h = 11h - -c) RxA2h = 27h - -d) RxA3h = 32h - -e) Rx79h = 40h - -f) Rx72h = 27h - -g) Rx73h = 32h -*/ - - u8 Data8; - - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2, - PCI_DEVICE_ID_VIA_VX855_LPC); - Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79); - Data8 &= ~0x40; - Data8 |= 0x40; - pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); - - console_init(); //there are to function defination of console_init(), while the src/archi386/lib is the right one - - /* decide if this is a s3 wakeup or a normal boot */ - boot_mode = acpi_is_wakeup_early_via_vx800(); - /*add this, to transfer "cpu restart" to "cold boot" - When this boot is not a S3 resume, and PCI registers had been written, - then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */ - if ((boot_mode != 3) - && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { - outb(6, 0xcf9); - } - - /*x86 cold boot I/O cmd */ - enable_smbus(); - //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this - - if (bist == 0) { - // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); - //print_debug("doing early_mtrr\n"); - //early_mtrr_init(); - } - - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - print_debug("Enabling mainboard devices\n"); - enable_mainboard_devices(); - - u8 Data; - device_t device; - /* Get NB Chip revision from D0F4RxF6, revision will be used in via_pci_inittable */ - device = PCI_DEV(0, 0, 4); - Data = pci_read_config8(device, 0xf6); - print_debug("NB chip revision ="); - print_debug_hex8(Data); - print_debug("\n"); - /* make NB ready before draminit */ - via_pci_inittable(Data, mNbStage1InitTbl); - - /*add this. - When resume from s3, draminit is skiped, so need to recovery any PCI register related to draminit. - and d0f3 didnt lost its Power during whole s3 time, so any register not belongs to d0f3 need to be recoveried . */ -#if 1 - if (boot_mode == 3) { - u8 i; - u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - DRAM_SYS_ATTR DramAttr; - - print_debug("This is a S3 wakeup\n"); - - memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); - /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */ - DRAMDetect(&DramAttr); - - /*begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot */ - device = PCI_DEV(0, 0, 3); - for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - rambits = pci_read_config8(device, ramregs[i]); - if (rambits != 0) - break; - } - - DRAMDRDYSetting(&DramAttr); - - Data = 0x80; // this value is same with dev_init.c - pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); - pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2); - Data = pci_read_config8(MEMCTRL, 0x88); - pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data); - - DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here! - SetUMARam(); // I just copy this function from draminit to here! - print_debug("Resume from S3, RAM init was ignored\n"); - } else { - ddr2_ram_setup(); - ram_check(0, 640 * 1024); - } -#endif - //ddr2_ram_setup(); - /*this line is the same with cx700 port . */ - enable_shadow_ram(); - - /* - For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, - so before this happen, I need to backup the content of mem to top-mem. - I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c - */ -#if PAYLOAD_IS_SEABIOS==1 // - if (boot_mode == 3) { - /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html - I want move the 1M data, I have to set some MTRRs myself. */ - /* setting mtrr before back memory save s3 resume time about 0.14 seconds */ - /*because CAR stack use cache, and here to use cache , must be careful, - 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) - 2 before stack switch, no use variable that have value set before this - 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. - */ - u32 memtop = *(u32 *) WAKE_MEM_INFO; - u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000; - u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000; - u32 memtop3 = - *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000; - u32 memtop4 = - *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + - 0xe0000; - /* __asm__ volatile ( - "movl $0x204, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl %0,%%eax\n\t" - "orl $(0 | 6), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x205, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" - "orl $(0 | 0x800), %%eax\n\t" - "wrmsr\n\t" - ::"g"(memtop2) - ); - __asm__ volatile ( - "movl $0x206, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl %0,%%eax\n\t" - "orl $(0 | 6), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x207, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" - "orl $(0 | 0x800), %%eax\n\t" - "wrmsr\n\t" - ::"g"(memtop1) - ); - __asm__ volatile ( - "movl $0x208, %ecx\n\t" - "xorl %edx, %edx\n\t" - "movl $0,%eax\n\t" - "orl $(0 | 6), %eax\n\t" - "wrmsr\n\t" - - "movl $0x209, %ecx\n\t" - "xorl %edx, %edx\n\t" - "movl $0x100000,%eax\n\t" - "decl %eax\n\t" - "notl %eax\n\t" - "orl $(0 | 0x800), %eax\n\t" - "wrmsr\n\t" - ); - */ - // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c - // these two memcpy not not be enabled if set the MTRR around this two lines. - /*__asm__ volatile ( - "movl $0, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0xa0000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) - ); - __asm__ volatile ( - "movl $0xe0000, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0x20000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) - );*/ - print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this - memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - - 64 * 1024 - 0x100000), - (unsigned char *) 0, 0xa0000); - memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - - 64 * 1024 - 0x100000 + 0xe0000), - (unsigned char *) 0xe0000, 0x20000); - - /* restore the MTRR previously modified. */ -/* __asm__ volatile ( - "wbinvd\n\t" - "xorl %edx, %edx\n\t" - "xorl %eax, %eax\n\t" - "movl $0x204, %ecx\n\t" - "wrmsr\n\t" - "movl $0x205, %ecx\n\t" - "wrmsr\n\t" - "movl $0x206, %ecx\n\t" - "wrmsr\n\t" - "movl $0x207, %ecx\n\t" - "wrmsr\n\t" - "movl $0x208, %ecx\n\t" - "wrmsr\n\t" - "movl $0x209, %ecx\n\t" - "wrmsr\n\t" - );*/ - } -#endif -}

1 0

New patch to review for coreboot: a83e16c northbridge/via/vx800/examples: Remove rotting source
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8087 -gerrit commit a83e16c6c93a2907e525e82050236ba2a62ac8bb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:29:36 2015 +1100 northbridge/via/vx800/examples: Remove rotting source This is just bit-rotting and its likely this will continue to rot by the time someone notices it exits it will be too late (i.e., today). Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/via/vx800/examples/chipset_init.c | 1241 -------------------- .../via/vx800/examples/driving_clk_phase_data.c | 242 ---- src/northbridge/via/vx800/examples/romstage.c | 541 --------- 3 files changed, 2024 deletions(-) diff --git a/src/northbridge/via/vx800/examples/chipset_init.c b/src/northbridge/via/vx800/examples/chipset_init.c deleted file mode 100644 index 3f9c70f..0000000 --- a/src/northbridge/via/vx800/examples/chipset_init.c +++ /dev/null @@ -1,1241 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#if CONFIG_HAVE_ACPI_RESUME -#include <arch/acpi.h> -#endif -#include "../vx800.h" - -#include <arch/io.h> -#include "pci_rawops.h" - -static const struct VIA_PCI_REG_INIT_TABLE mSbStage1InitTbl[] = { - // Combine Stage1 registers - {0x00, 0xFF, SB_LPC_REG(0x41), 0x40, 0x40}, - - // Acpi init registers in sb stage1 - {0x00, 0xFF, SB_LPC_REG(0x40), 0x04, 0x04}, // Enable 4D0/4D1 support - {0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08}, // Enable RTC port 74/75 - {0x00, 0xFF, SB_LPC_REG(0x51), 0x0D, 0x0D}, // and KBC - {0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09}, // Enable Serial IRQ - {0x00, 0xFF, SB_LPC_REG(0x67), 0x00, 0x04}, // Set FERR voltage to 1.5v - {0x00, 0xFF, SB_LPC_REG(0x98), 0xFF, 0x00}, // Disable GP3 Timer - - {0x00, 0xFF, SB_IDEC_REG(0xb9), 0x01, 0x01}, - - {0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39}, // Enable SMM A-Seg, MSI and Io APIC - ///// SPI-BAR. - //// SPI_BASE_ADDRESS = 0xFED1 0000 - {0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00}, - {0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1}, - {0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1}, -// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE}, - ///// End of 2008-04-17 - - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mNbStage2InitTable[] = { - // D0F0: AGP Feature. For 3353, No AGP Feature - - // D0F2~D0F3 is configured by MemoryInit Peim - - // D0F4: NB PMU - { 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB }, - { 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05 }, - { 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8 }, - { 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF }, - { 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC }, - { 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19 }, - { 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00 }, - { 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF }, - { 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF }, - { 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC }, - { 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0 }, - { 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6 }, - { 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20 }, - - // D0F5: NB APIC, PXPTRF and MSGC - //Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex. - //Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase. - //Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase. - { 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18 }, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1. - { 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00 }, //Set RVC1RPSW, RVC1RQ1T to 1. - { 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0 }, - { 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01 }, // RWAKEEN - //{ 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00 }, //RTDNP2B32EN - { 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20 }, - { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00 }, //RP2P1ABORT - - -// fine-tune -// If no settings, C7 will hang or reboot in XP, but CN will not. - { 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03 }, - { 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00 }, - { 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01 }, - { 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10 }, - { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08 }, - { 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04 }, // ACPI Base addr - { 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01 }, // APIC MSI - { 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00 }, // APIC MSI - //GTL - { 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66 }, - { 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33 }, - { 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20 }, - { 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00 }, - - - // End of Table - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = { - // D17F0: LPC - { 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44 }, // Enable I/O Recovery Time, 4D0/4D1 Support - { 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0 }, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD - { 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B }, // RENDTX, ENWBTO, ENRBTO - //{ 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10 }, // It is related to INTH# - //{ 0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C }, //RMRPW, RIRPW // Reserved in 409 by Eric - - // Internal RTC, Mouse, Keyboard // set in PEI by Eric - //{ 0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D }, // Enable Internal RTC, Internal PS2 Mouse/Keyboard - - // RTC - { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01 }, //RTC Rx32 Map to Centrury Byte - - //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02 }, // RDMEGAS - //{ 0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08 }, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric - - // Serial IRQ // set in PEI by Eric - //{ 0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09 }, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock. - - // Enable 4D0h/4D1h Port - //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04 }, // EISAXT // set in PEI by Eric - - // Config ROM Interface - // Enable SPI/Set SPI Memory Base Address - // It is initialized in PEI Phase - - // Subsystem ID/Vendor ID Back Door - { 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06 }, - { 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11 }, - { 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09 }, - { 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34 }, - - { 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40 }, - { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51 }, // Orgin value 0x53, modify for 409 by Eric - { 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01 }, - - - { 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00 }, // Setting PCI device enable - { 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00 }, // Setting PCI device enable - { 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00 }, // Setting HDAC enable - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = { - //PCI1 Programming Sequence - //(1)Configure D17F7 - { 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03 }, - { 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 }, // Reserved in 409 by Eric - { 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 }, //RENPPB, RP2CFLSH - { 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 }, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion - // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. - // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) - //(2)Configure D19F0 - { 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 }, - - //(3)Performance Recommended Setting - - //Save Power - { 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01 }, - { 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00 }, - //Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance - { 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82 }, - { 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0 }, - { 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE }, - - //Cycle Control - { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01 }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C }, - //Arbitration control - { 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F }, - { 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0 }, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = { - { 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08 }, //RVWREQ, ROABKDOOR - - //CCA's Register Programming sequence - { 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08 }, //Config Azalia's upstream cycle high priority and other low priority - { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80 }, //Disable bypass asynchronous circuit - { 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11 }, // Set SM Internal Device and HDAC Occupy Timer - { 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11 }, // Set SM Internal Device and HDAC Promote Timer - { 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02 }, //Use SB internal devices's original REQ - { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00 }, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C }, //RLCKXP2C, RFSBVK. - { 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00 }, //RBLKAPIC, RAZC3 - { 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02 }, //RNMIFSB, RFSBVK - { 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90 }, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme - { 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00 }, //Let CCA use dynamic clock. - //The CCA is also relate to D17F0 - //{ 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00 }, //Disable CCA Test Mode - { 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00 }, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = { - //{0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05}, //set to native mode - {0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07}, - //{0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F}, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table -}; - -static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = { - { 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40 }, - { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04 }, - //{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void AcpiInit(void) -{ - device_t_raw rawdevice = 0; - u8 sbchiprev; - rawdevice = PCI_RAWDEV(0, 0x11, 0); - // Set the PMIO base io address - pci_rawmodify_config16(rawdevice, 0x88, VX800_ACPI_IO_BASE, - 0xff80); - // Enable PMIO - pci_rawmodify_config16(rawdevice, 0x80, 0x8000, 0x8000); - // Enable Soft Resume - outw(inw(VX800_ACPI_IO_BASE + 0x04) | 0x8000, - VX800_ACPI_IO_BASE + 0x04); - - // Get SB Revision - sbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev); - - // Fill Register Table - via_pci_inittable(sbchiprev, mSbStage1InitTbl); - - // Close all SMI/Io Traps - outb(0x00, VX800_ACPI_IO_BASE + 0x42); -} - -void Stage2NbInit(void) -{ - device_t_raw rawdevice = 0; - u8 nbchiprev; - u32 subid = 0; - rawdevice = PCI_RAWDEV(0, 0, 4); - nbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "NB chip revision =%x\n", nbchiprev); - - via_pci_inittable(nbchiprev, mNbStage2InitTable); - - rawdevice = PCI_RAWDEV(0, 0, 0); - - subid = PCI_DEVICE_ID_VIA_VX855_D0F0 << 16 + PCI_VENDOR_ID_VIA; - pci_rawwrite_config32(rawdevice, 0x2C, subid); - - //vx855 NB no pcie bus - //vx855 NB no apic -} - -void IDECSupportOption(u8 sbchiprev) -{ - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0, 0x08); - - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x00, 0x80); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x0A, 0x01, 0xFF); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x45, 0x80, 0x00); - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x40, 0x02, 0x00); - - pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x00, 0x05); //COMPATIBLE MODE -// pci_rawmodify_config8(PCI_RAWDEV(0, 0xf, 0), 0x09, 0x05, 0x05);//native MODE - - via_pci_inittable(sbchiprev, IDEC_INIT); -} - -void InitIDEC(u8 sbchiprev) -{ - IDECSupportOption(sbchiprev); -} - -void InitUHCI(u8 Number, u8 bEnable) -{ - u8 Mask, Value; - u16 D16; - u8 BaseAddress; - u8 BitShift; - // USB Device 16 - // Function : Number - // 0 : 0 - // 1 : 1 - // 2 : 2 - // The BitShift is got from Datasheet. - - switch (Number) { - case 0: - BaseAddress = 0; - BitShift = 4; - break; - case 1: - BaseAddress = 1; - BitShift = 5; - break; - case 2: - default: - BaseAddress = 2; - BitShift = 2; - break; - } - - if (bEnable) { - Mask = 0x1 << BitShift; - Value = 0x0; - } else { - Mask = 0x0; - Value = 0x1 << BitShift; - } - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask); - - - if (bEnable) { - D16 = 0; - pci_rawwrite_config16(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x20, D16); - - // Config some Control Register - Mask = 0x00; - Value = 0x12; - - pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x41, Value, Mask); - Mask = 0x00; - Value = 0xEB; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, BaseAddress), - 0x4B, Value, Mask); - } - return; -} - -static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = { - //EHCI - { 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0 }, - { 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80 }, - { 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E }, - { 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94 }, - { 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A }, - { 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03 }, - { 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A }, - { 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01 }, - { 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11 }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void InitEHCI(u8 Number, u8 bEnable) -{ - u8 Mask, Value; - u8 EHCIRevision; - - if (bEnable) { - Mask = 0x1 << 1; - Value = 0x0; - } else { - Mask = 0x0; - Value = 0x1 << 1; - } - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, Value, Mask); - - - if (bEnable) { - // Get Chipset Revision - EHCIRevision = - pci_rawread_config8(PCI_RAWDEV(0, 0x10, 4), 0xF6); - printk(BIOS_DEBUG, "EHCI Revision =%x\n", EHCIRevision); - via_pci_inittable(EHCIRevision, mEHCIInitTable); - } -} - -#define TRUE 1 -void InitUSBC(u8 sbchiprev) -{ - InitUHCI(0, TRUE); - InitUHCI(1, TRUE); - InitUHCI(2, TRUE); - InitEHCI(0, TRUE); -} - -void WriteSbApicIndexedReg(u8 Idx, u32 Data) -{ - u32 Data32; - u32 ApicIdxAdr = VX800SB_APIC_BASE; - u32 ApicDataAdr = VX800SB_APIC_BASE + VX800SB_APIC_DATA_OFFSET; - *((u8 *) ApicIdxAdr) = Idx; - Data32 = (*((u32 *) ApicDataAdr)); //this read is needed when write APIC ID ,dont know why. - Data32 = Data; - *((u32 *) ApicDataAdr) = Data32; -} - -void SbApicMmioRegInit(void) -{ - u32 Offset; - WriteSbApicIndexedReg(3, 1); - WriteSbApicIndexedReg(0, 4); - for (Offset = 0x10; Offset < VX800SB_APIC_ENTRY_NUMBER; - Offset += 2) { - WriteSbApicIndexedReg(Offset + 1, 0); - WriteSbApicIndexedReg(Offset, 0x10000); - } -} - -void SbApicInit(u8 sbchiprev) -{ - via_pci_inittable(sbchiprev, mSbApicInitTable); - SbApicMmioRegInit(); -} - -void SbAcpiInit(void) -{ - u8 Mask, Value; - // Enable ACPI - Mask = 0x01; - Value = 0x01; - io_rawmodify_config8(VX800_ACPI_IO_BASE + 0x04, Value, Mask); -} - -#define HPET_ENABLE_BIT 0x80 -#define R_SB_HPET_CONTROL 0x68 -#define HPET_BASE_ADDRESS 0xFED0 // 0xFED00000 -#define R_SB_HPET_ADDRESS 0x69 - -void HpetInit(void) -{ - u8 HpetEnable = HPET_ENABLE_BIT; - u16 HpetBase = HPET_BASE_ADDRESS; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_HPET_CONTROL, - HpetEnable); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), - R_SB_HPET_ADDRESS + 1, HpetBase); -} - -static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = { - // Power Management - { 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20 }, - { 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00 }, - { 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18 }, - - //Miscellaneous Configuration 1 - { 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28 }, - { 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1 }, - { 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10 }, - { 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2 }, - - //Voltage Change Function Enable - { 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21 }, - //Internal PCIe and NM PLL Control - { 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA }, - - { 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80 }, - { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table -}; - -void InitPMU(u8 sbchiprev) -{ - u8 Mask, Value; - // Set PMU Registers - via_pci_inittable(sbchiprev, mPMUInitTable); - - - // Set SCI IRQ and its level trigger - Mask = 0x0F; - Value = 0x09; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x82, Value, Mask); - - Mask = 0x02; - Value = 0x02; - io_rawmodify_config8(0x4d1, Value, Mask); -} - -#define R_SB_MULTI_FUNCTION_SELECT_1 0xE4 -#define R_SB_CX_STATE_BREAK_EVENT_ENABLE_1 0xE6 -#define PMIO_PROCESSOR_CONTROL 0x26 -#define R_SB_PCI_ARBITRATION_2 0x76 -#define R_SB_AUTO_SWITCH_P_STATE 0x8A - -void InitCPUCStatueSupport() -{ - u8 Mask, Value; - - // Config Cx State - // Now it is C2 & C4 Up Down Mode - Mask = 0xFF; - Value = 0x30; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_CX_STATE_BREAK_EVENT_ENABLE_1, Value, Mask); //SB_LPC_REG - - Mask = 0xFF; - Value = 0x1F; - io_rawmodify_config8(VX800_ACPI_IO_BASE + PMIO_PROCESSOR_CONTROL, - Value, Mask); - - Mask = 0x00; - Value = 0x80; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 7), R_SB_PCI_ARBITRATION_2, Value, Mask); //SB_VLINK_REG - - Mask = 0xFF; - Value = 0x00; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_MULTI_FUNCTION_SELECT_1, Value, Mask); //SB_VLINK_REG - - Mask = 0xFF; - Value = 0x1F; - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), R_SB_AUTO_SWITCH_P_STATE, Value, Mask); //SB_VLINK_REG -} - -void InitSBPM(u8 sbchiprev) -{ - InitPMU(sbchiprev); - SbAcpiInit(); - InitCPUCStatueSupport(); -} - -void Stage2SbInit(void) -{ - device_t_raw rawdevice = 0; - u8 sbchiprev; - - rawdevice = PCI_RAWDEV(0, 11, 0); - sbchiprev = pci_rawread_config8(rawdevice, 0xf6); - printk(BIOS_DEBUG, "SB chip revision =%x\n", sbchiprev); - - //SBBasicInit - via_pci_inittable(sbchiprev, mBusControllerInitTable); - via_pci_inittable(sbchiprev, mPCI1InitTable); - via_pci_inittable(sbchiprev, mCCAInitTable); - - - InitIDEC(sbchiprev); - - InitUSBC(sbchiprev); - - InitSBPM(sbchiprev); - - SbApicInit(sbchiprev); - - HpetInit(); - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0);//SB_VLINK_REG - -} - -void init_VIA_chipset(void) -{ - printk(BIOS_DEBUG, "In: init_VIA_chipset\n"); - //1.nbstage1 is done in raminit. - //2.sbstage1 - AcpiInit(); - //3.nbstage2 - Stage2NbInit(); - - //4.sbstage2 - Stage2SbInit(); - - //5.open hdac - pci_rawmodify_config32(PCI_RAWDEV(0, 0x11, 7), 0xd1, 0, 0x04); - printk(BIOS_DEBUG, "End: init_VIA_chipset\n"); -} - -/** - * @brief Main function of the DRAM part of coreboot. - * - * Coreboot is divided into Pre-DRAM part and DRAM part. - * - * - * Device Enumeration: - * In the dev_enumerate() phase, - */ - -void main(void) -{ - struct lb_memory *lb_mem; -#if CONFIG_HAVE_ACPI_RESUME - void *wake_vec; -#endif - - u16 tmp; - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - acpi_sleep_type = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - - u8 y, x; - init_VIA_chipset(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - -#if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, - pci_rawread_config8(PCI_RAWDEV(0, 3, 0), - 0x88)); -#endif - - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x51, 0x40, 0x40); //close CE-ATA (Consumer Electronics-ATA) and NFC - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x0, 0x40);//open USB Device Mode Enable - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x40, 0x40); //close USB Device Mode - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x04, 0x04);//close USB 1.1 UHCI Port 4-5 - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x02, 0x02);//close USB 2.0 ehci - - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x00, 0x76);//open all usb and usb mode - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x50, 0x76, 0x76);//close all usb - - printk(BIOS_INFO, "=================SB 50h=%02x \n", - pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50)); - - /* FIXME: Is there a better way to handle this? */ - init_timer(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - - /* Find the devices we don't have hard coded knowledge about. */ - dev_enumerate(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV - (0, 0x10, 4), - x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - post_code(0x66); - /* Now compute and assign the bus resources. */ - dev_configure(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - post_code(0x88); - /* Now actually enable devices on the bus */ - dev_enable(); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - /* And of course initialize devices on the bus */ -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - - dev_initialize(); - post_code(0x89); - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - -// pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571); - -#if 0 - x = y = 0; - printk(BIOS_INFO, "dump ehci3 \n"); - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } -#endif - -#if 0 - y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d); - y &= 0x0f; - y |= 0x40; - pci_rawwrite_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d, y); -#endif - -#if 0 - static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD }; - static const d0f2pcitable[16 * 7 + 1] = { - 0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09, - 0x00, 0x00, 0x10, 0xA2, 0x88, 0xCE, - 0xFF, 0x0F, 0x00, 0xAA, 0x0A, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xCC, 0x66, 0xAA, 0x55, 0x30, 0x38, 0x0C, 0x00, 0x00, 0x00, - 0x00, 0x22, 0x00, 0xAA, 0x00, 0x00, - 0x44, 0x44, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0B, 0x00, 0x08, 0x00, 0x00, 0x00, 0x0A, 0x01, 0x41, 0x06, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x88, 0x56, 0x70, 0x77, 0x77, 0x07, 0x77, 0x77, 0x04, - 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x33, 0x33, 0x77, 0x77, 0x77, 0x77, 0x77, 0x77, - 0x77, 0x77, 0x44, 0x44, 0x14, 0x00, - 0x75 - }; - - static const d0f4pcitable[16 * 6 + 3] = { - 0x30, 0x00, 0x00, - 0xFF, 0xFF, 0xCC, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0xE0, 0xD6, 0x80, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x01, 0x02, 0x03, 0x04, 0x04, 0x00, 0x00, 0x04, 0x04, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x12, 0x12, 0x00, 0x00, 0x08, 0xF4, - 0x01, 0x01, 0x79, 0x79, 0x0A, 0x00, - }; - static const d0f5pcitable[16 * 10] = { - 0x13, 0x0E, 0x00, 0x00, 0xD2, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x18, 0x9A, 0x00, 0x81, 0x28, 0xC0, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x26, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - - static const d0f7pcitable[16 * 9] = { - 0x00, 0x2A, 0x00, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x29, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - static const d1f0pcitable[3] = { - 0x01, 0x80, 0x40 - }; - - static const dcf0pcitable[96] = { - 0x10, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x00, 0xC2, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, - 0x40, 0x01, 0x03, 0x01, 0x7E, 0x01, - 0x08, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF9, - 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - - static const d10f4pcitable[48] = { - 0x00, 0x20, 0x43, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x9E, 0x68, - 0x00, 0x09, 0x13, 0x94, 0x03, 0x10, - 0x80, 0x60, 0x11, 0xBF, 0x00, 0xFF, 0x0F, 0x00, 0x04, 0x0B, - 0xCC, 0xCC, 0x00, 0xCC, 0x00, 0x00, - 0x20, 0x20, 0x01, 0x00, 0x05, 0x00, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x20, 0x00, 0xC0, - }; - - static const d11f0pcitable[16 * 12] = { - 0x44, 0x40, 0xF0, 0x0B, 0x00, 0x00, 0x00, 0x03, 0x00, 0x20, - 0x00, 0x00, 0x04, 0x00, 0x08, 0x00, - 0xC1, 0x4D, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, - 0x00, 0x51, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x80, 0x00, - 0xD0, 0xFE, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x11, 0x09, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, - 0x20, 0x84, 0x49, 0x00, 0x88, 0x00, 0x00, 0x00, 0x01, 0x08, - 0x1F, 0x00, 0x07, 0x1A, 0x00, 0x00, - 0x00, 0x6E, 0xBC, 0x88, 0x28, 0xC1, 0x10, 0x80, 0x00, 0x80, - 0x20, 0x88, 0x00, 0x00, 0x00, 0xAD, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, - 0x00, 0x00, 0x10, 0xD0, 0xFE, 0x90, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x04, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xE7, 0x03, 0xA0, 0x60, 0x20, 0xC0, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - }; - - static const d11f7pcitable[192] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x80, 0x43, - 0x08, 0x80, 0x11, 0x11, 0x02, 0x0F, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x00, 0x00, 0x20, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, - 0x82, 0xC8, 0xEE, 0x01, 0x0C, 0x0F, 0xD0, 0x48, 0x00, 0x00, - 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, - 0x07, 0x00, 0x21, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x93, 0x08, 0x00, 0x5E, 0x00, 0x80, 0x29, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, - }; - -#define OPTION_1 1 -#define NOOPTION_1 1 -#ifdef OPTION_1 - static const OPTION_1_d11f0pcitable[16 * 12] = { - 0x44, 0x80, 0xf0, 0x0b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x20, - 0x00, 0x00, 0x04, 0x01, 0x08, 0x00, - 0xc0, 0x4d, 0x19, 0x80, 0x00, 0x00, 0x00, 0x00, 0x60, 0x00, - 0x00, 0x53, 0x00, 0xfe, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x04, 0x80, 0x00, - 0xd0, 0xfe, 0x00, 0x00, 0xdf, 0x00, - 0x06, 0x11, 0x53, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x20, 0x84, 0x4a, 0x00, 0xda, 0x40, 0x00, 0x00, 0x01, 0x40, - 0x1f, 0x00, 0x07, 0x18, 0x00, 0x00, - 0x00, 0x2e, 0xbc, 0x00, 0x28, 0xc1, 0x10, 0x80, 0x00, 0x80, - 0x08, 0x88, 0x00, 0x00, 0x00, 0xad, - 0x06, 0x11, 0x53, 0x83, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x00, 0x40, 0x80, 0x40, - 0x00, 0x00, 0x00, 0xd3, 0xfe, 0x53, - 0x01, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x01, 0x41, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0xeb, 0x03, 0xa0, 0x60, 0x20, 0x80, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, - }; -#endif - - u8 i; -/* error form ---- but add the chance to resume - for(i=0;i<5;i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); - } -*/ - -/* RO reg - for(i=0;i<5;i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); - } -*/ - -//boot ok, resume still err in linux -#if 1 - for (i = 0; i < 9; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } - //9 is warm reset reg, // boot err in coreboot - for (i = 10; i < 64; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } - //0x90 look d0f2 appendixA1 , if set this to 09 or 0b, then some ddr2 will crash. - for (i = 65; i < 113; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), i + 0x50, - d0f2pcitable[i]); - } -#endif -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x66, 0x09); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x70, 0xdd); - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x90, 0x09); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 2), 0x92, 0x40); - -#endif - - - -#if 1 - - -//d0f3 -/* */ - // pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x3b); setting, my lspci is 0x29 - //set bit4 cause the ide not be found -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x2b); - //set bit1 cause the ide not be found - -// pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x86, 0x29); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x95, 0x05); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0x99, 0x12); - - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xde, 0x00); -#endif - -//boot ok, resume err in coreboot -#if 1 - for (i = 0; i < 99; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), i + 0x8d, - d0f4pcitable[i]); - } -#endif - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xe9, 0x90); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xec, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xed, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xee, 0x0); -#endif - - -#if 1 -//boot ok, resume still err in linux - for (i = 0; i < 160; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 5), i + 0x60, - d0f5pcitable[i]); - } - for (i = 0; i < 144; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), i + 0x60, - d0f7pcitable[i]); - } - for (i = 0; i < 3; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 1, 0), i + 0xb0, - d1f0pcitable[i]); - } - for (i = 0; i < 96; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), i + 0x40, - dcf0pcitable[i]); - } -#endif - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x61, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x63, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 7), 0x76, 0xd0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x88, 0x81); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x89, 0x01); - pci_rawwrite_config8(PCI_RAWDEV(0, 0xc, 0), 0x8A, 0x60); -#endif - -//d15f0 - -#if 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2); - -//boot ok, resume still err in linux, and if disable USB, then all ok -// for(i=0;i<48;i++){ - for (i = 0; i < 44; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), i + 0x40, - d10f4pcitable[i]); - } -#endif - -//#ifdef NOOPTION_1 -#if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6b, 0x01); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6d, 0x00); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6e, 0x08); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80); -#endif - -#if 1 -//before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok -// for(i=0;i<192;i++){ - for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail - - //7-18 is my familar part - for (i = 7; i < 18; i++) { //sleep ok ,resume sleep err 2 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# - for (i = 24; i < 27; i++) { //sleep ok , resume sleep err 1 resume 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //5b port 80h - pci_rawmodify_config8(PCI_RAWDEV(0, 0x11, 0), 0x5b, 0x0, 0x08); - // i++; - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i+0x40, d11f0pcitable[i]); - - for (i = 28; i < 72; i++) { //sleep ok , resume sleep err 1 , resume 1ci - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //7273ACPI BASE - - for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - //B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, d11f0pcitable[112]); - i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); - //multiplex with VCP - // i = i | 0x30; - i = i & 0xf7; - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i); - - - - for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - - - for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } -#endif -#ifdef NOOPTION_1 -// for(i=0;i<192;i++){ - for (i = 0; i < 6; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - //6 is uart and dvp vcp, will have // HAVE no com1 ,and no gui show,textmode ok ,s3 sleep ok, resume fail - - //7-18 is my familar part - for (i = 7; i < 18; i++) { // sleep err 2 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 18; i < 21; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //0x55 56 57 irq intA#B#C# linkA#linkB#linkC# - for (i = 24; i < 27; i++) { //sleep ok , resume ??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - d11f0pcitable[i]); - } - //5b port 80h - i++; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - - for (i = 28; i < 72; i++) { //sleep ok , resume??? - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - //7273ACPI BASE - - for (i = 74; i < 112; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - //B0B4B5 dvp vcp, if copy this ,then no uart, no gui(of unbuntu) - // pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0xb0, OPTION_1_d11f0pcitable[112]); - i = pci_rawread_config8(PCI_RAWDEV(0, 17, 0), 0xB0); - //multiplex with VCP - // i = i | 0x30; - i = i & 0xf7; - pci_rawwrite_config8(PCI_RAWDEV(0, 17, 0), 0xB0, i); - - - - for (i = 113; i < 114; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 115; i < 116; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } - - for (i = 118; i < 192; i++) { //boot ok, resume still err in linux - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, - OPTION_1_d11f0pcitable[i]); - } -#endif - -#if 1 - pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, PCI_DEVICE_ID_VIA_VX855_IDE); //5324 - pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA0, - PCI_VENDOR_ID_VIA); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0xA2, PCI_DEVICE_ID_VIA_VX855_LPC); //8353 - i = pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x79); - i &= ~0x40; - i |= 0x40; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), 0x79, i); - pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); - -//boot ok, resume still err in linux - for (i = 0; i < 192; i++) { - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, - d11f7pcitable[i]); - } -#endif -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x61, 0x2a); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x63, 0xa0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x64, 0xaa); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x84, 0x0); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f); -#endif - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20); - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31); - -#ifdef OPTION_1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00); -#endif -#endif - - u8 i911; - //disable CHB L.L - //set VGA memory selection - i911 = pci_rawread_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0); - i911 &= 0xF8; - //ByteVal |= 0x03; - i911 |= 0x01; - pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911); - -#if 1 - struct device *dev; - printk(BIOS_INFO, "========= dump all devices...\n"); - for (dev = all_devices; dev; dev = dev->next) { - if (dev->path.type == DEVICE_PATH_PCI) { - printk(BIOS_DEBUG, "%s dump\n", dev_path(dev)); - x = y = 0; - for (; x < 16; x++) { - y = 0; - for (; y < 16; y++) { - printk(BIOS_INFO, "%02x ", - pci_read_config8(dev, x * 16 + y)); - } - printk(BIOS_INFO, "\n"); - } - } - printk(BIOS_INFO, "\n"); - } -#endif - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);// - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// -} diff --git a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c b/src/northbridge/via/vx800/examples/driving_clk_phase_data.c deleted file mode 100644 index c62de6e..0000000 --- a/src/northbridge/via/vx800/examples/driving_clk_phase_data.c +++ /dev/null @@ -1,242 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - #include "northbridge/via/vx800/driving_clk_phase_data.h" - -// DQS Driving -//Reg0xE0, 0xE1 -// According to #Bank to set DRAM DQS Driving -// #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_DQSA_Driving_Table[4] = { 0xEE, 0xEE, 0xEE, 0xEE}; -static const u8 DDR2_DQSB_Driving_Table[2] = { 0xEE, 0xEE}; - -// DQ Driving -//Reg0xE2, 0xE3 -// For DDR2: According to bank to set DRAM DQ Driving -static const u8 DDR2_DQA_Driving_Table[4] = { 0xAC, 0xAC, 0xAC, 0xAC }; -static const u8 DDR2_DQB_Driving_Table[2] = { 0xCA, 0xCA }; - - -// CS Driving -//Reg0xE4, 0xE5 -// According to #Bank to set DRAM CS Driving -// DDR1 #Bank 1 2 3 4 5 6 7 8 -static const u8 DDR2_CSA_Driving_Table_x8[4] = { 0x44, 0x44, 0x44, 0x44 }; -static const u8 DDR2_CSB_Driving_Table_x8[2] = { 0x44, 0x44}; -static const u8 DDR2_CSA_Driving_Table_x16[4]= { 0x44, 0x44, 0x44, 0x44}; -static const u8 DDR2_CSB_Driving_Table_x16[2]= { 0x44, 0x44}; -// MAA Driving -//Reg0xE8, Reg0xE9 -static const u8 DDR2_MAA_Driving_Table[MA_Table][5] = - { - //Chip number, 400, 533, 667 800 ;(SRAS, SCAS, SWE)RxE8 - { 6, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 00 ~ 06 - { 18, 0x86, 0x86, 0x86, 0x86}, // total MAA chips = 06 ~ 18 - {255, 0xDB, 0xDB, 0xDB, 0xDB} // total MAA chips = 18 ~ - }; - -static const u8 DDR2_MAB_Driving_Table[MA_Table][2] = - { - // Chip number, Value ;(SRAS, SCAS, SWE)RxE9 - { 6, 0x86 }, // total MAB chips = 00 ~ 06 - { 18, 0x86 }, // total MAB chips = 06 ~ 18 - {255, 0xDB } // total MAB chips = 18 ~ - }; - -// DCLK Driving -//Reg0xE6, 0xE7 -// For DDR2: According to #Freq to set DRAM DCLK Driving -// freq 400M, 533M, 667M, 800M - -static const u8 DDR2_DCLKA_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; -static const u8 DDR2_DCLKB_Driving_Table[4] = { 0xFF, 0xFF, 0xFF, 0xFF }; - -/* -Duty cycle -Duty cycle Control for DQ/DQS/DDRCKG in ChA & ChB -D0F3RxEC/D0F3RxED/D0F3RxEE/D0F3RxEF -According to DRAM frequency to control Duty Cycle -*/ -static const u8 ChA_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xEC, 0x00, 0x30, 0x30, 0x30, 0x30 }, // 1Rank - {0xEE, 0x0F, 0x40, 0x40, 0x00, 0x00 }, - {0xEF, 0xCF, 0x00, 0x30, 0x30, 0x30} - }; - -static const u8 ChB_Duty_Control_DDR2[DUTY_CYCLE_REG_NUM][DUTY_CYCLE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0xED, 0x00, 0x88, 0x88, 0x84, 0x88 }, // 1Rank - {0xEE, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0xEF, 0xFC, 0x00, 0x00, 0x00, 0x00 } - }; - - -/* -DRAM Clock Phase Control for FeedBack Mode -Modify NB Reg: Rx90[7]/Rx91/Rx92/Rx93/Rx94 -Processing: - 1.Program VIA_NB3DRAM_REG90[7]=0b for FeedBack mode - 2.Program clock phase value with ChA/B DCLK enable, VIA_NB3DRAM_REG91[7:3]=00b - 3.Check ChB rank #, if 0, VIA_NB3DRAM_REG91[7]=1b, to disable ChB DCLKO - ChA DCLKO can not be disable, so always program VIA_NB3DRAM_REG91[3]=0b - */ -static const u8 DDR2_ChA_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07 }, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } - }; - -static const u8 DDR2_ChB_Clk_Phase_Table_1R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0x0F, 0x20, 0x10, 0x00, 0x70 }, // 1Rank - {0x92, 0x0F, 0x40, 0x30, 0x30, 0x20 }, - {0x93, 0x0F, 0x60, 0x50, 0x40, 0x30 } - }; - -/*static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x04, 0x03, 0x04, 0x01 }, // 1Rank - {0x92, 0xF8, 0x03, 0x06, 0x05, 0x04 }, - {0x93, 0xF8, 0x03, 0x07, 0x06, 0x05 } - };*/ - -static const u8 DDR2_ChA_Clk_Phase_Table_2R[3][Clk_Phase_Table_DDR2_Width] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x91, 0xF8, 0x02, 0x01, 0x00, 0x07}, // 1Rank - {0x92, 0xF8, 0x04, 0x03, 0x03, 0x02 }, - {0x93, 0xF8, 0x06, 0x05, 0x04, 0x03 } - }; - -/* -DRAM Write Data phase control -Modify NB Reg: Rx74/Rx75/Rx76 -*/ -/*static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x03, 0x04, 0x05, 0x02 }, // 1Rank - {0x75, 0xF8, 0x03, 0x04, 0x05, 0x02 }, - {0x76, 0x00, 0x10, 0x80, 0x00, 0x07 } - };*/ - -static const u8 DDR2_ChA_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0xF8, 0x01, 0x00, 0x00, 0x07 }, // 1Rank - {0x75, 0xF8, 0x01, 0x00, 0x00, 0x07 }, - {0x76, 0x10, 0x80, 0x87, 0x07, 0x06 }, - {0x8C, 0xFC, 0x03, 0x03, 0x03, 0x03 } - }; - -/*static const u8 DDR2_ChB_WrtData_Phase_Table[WrtData_REG_NUM ][WrtData_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x74, 0x8F, 0x30, 0x40, 0x30, 0x20 }, // 1Rank - {0x75, 0x8F, 0x30, 0x40, 0x30, 0x20 }, - {0x8A, 0x00, 0x10, 0x80, 0x07, 0x07 } - }; -*/ -/* -DQ/DQS Output Delay Control -Modify NB D0F3: RxF0/RxF1/RxF2/RxF3 -*/ -static const u8 DDR2_CHA_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = - { - // RxF0 RxF1 RxF2 RxF3 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 - }; -static const u8 DDR2_CHB_DQ_DQS_Delay_Table[4][DQ_DQS_Delay_Table_Width] = - { - // RxF4 RxF5 RxF6 RxF7 - { 0x00, 0x00, 0x00, 0x00 },// DDR400 - { 0x00, 0x00, 0x00, 0x00 },// DDR533 - { 0x00, 0x00, 0x00, 0x00 },// DDR667 - { 0x00, 0x00, 0x00, 0x00 }// DDR800 - }; - -/* -DQ/DQS input Capture Control -modify NB D0F3_Reg:Rx78/Rx79/Rx7A/Rx7B -*/ - -/*static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0x00, 0x83, 0x8D, 0x87, 0x83 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x10, 0x30, 0x20, 0x10 } - };*/ - - -static const u8 DDR2_ChA_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x78, 0xC0, 0x0D, 0x07, 0x03, 0x01 }, // 1Rank - {0x7A, 0xF0, 0x00, 0x00, 0x00, 0x00 }, - {0x7B, 0x00, 0x34, 0x34, 0x20, 0x10 } - }; - -static const u8 DDR2_ChB_DQS_Input_Capture_Tbl[DQS_INPUT_CAPTURE_REG_NUM ][DQS_INPUT_CAPTURE_FREQ_NUM] = - { - // (And NOT) DDR800 DDR667 DDR533 DDR400 - //Reg Mask Value Value Value Value - {0x79, 0x00, 0x89, 0x89, 0x87, 0x83 }, // 1Rank - {0x7A, 0x0F, 0x00, 0x00, 0x00, 0x00 }, - {0x8B, 0x00, 0x34, 0x34, 0x20, 0x10 } - }; - -static const u8 Fixed_DQSA_1_2_Rank_Table[4][2] = -{ -// Rx70 Rx71 - { 0x00, 0x05 }, // DDR800 - { 0x00, 0x06 }, // DDR667 - { 0x00, 0x04 }, // DDR533 - { 0x00, 0x05 } // DDR400 -}; -static const u8 Fixed_DQSA_3_4_Rank_Table[4][2] = -{ -// Rx70 Rx71 - {0x00 , 0x04}, // DDR800 - {0x00 , 0x04}, // DDR667 - {0x00 , 0x03}, // DDR533 - {0x00 , 0x04} // DDR400 -}; diff --git a/src/northbridge/via/vx800/examples/romstage.c b/src/northbridge/via/vx800/examples/romstage.c deleted file mode 100644 index c96511e..0000000 --- a/src/northbridge/via/vx800/examples/romstage.c +++ /dev/null @@ -1,541 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 One Laptop per Child, Association, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - - -#include <stdint.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include "console/console.c" -#include "lib/ramtest.c" -#include "northbridge/via/vx800/vx800.h" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" -#include "pc80/udelay_io.c" -#include "lib/delay.c" -#include "lib/memcpy.c" -#include "cpu/x86/lapic/boot_cpu.c" -#include "driving_clk_phase_data.c" -#include "northbridge/via/vx800/raminit.h" -#include "northbridge/via/vx800/raminit.c" - -static int acpi_is_wakeup_early_via_vx800(void) -{ - device_t dev; - u16 tmp, result; - - print_debug("In acpi_is_wakeup_early_via_vx800\n"); - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VX855_LPC), 0); - - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - - /* Set ACPI base address to I/O VX800_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VX800_ACPI_IO_BASE | 0x1); - - /* Enable ACPI access RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); - - tmp = inw(VX800_ACPI_IO_BASE + 0x04); - result = ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0; - print_debug(" boot_mode="); - print_debug_hex16(result); - print_debug("\n"); - return result; -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -static void enable_mainboard_devices(void) -{ - device_t dev; - uint16_t values; - - print_debug("In enable_mainboard_devices \n"); - - /* Enable P2P bridge Header for external PCI bus. */ - dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); - pci_write_config8(dev, 0x4f, 0x41); -} - -static void enable_shadow_ram(void) -{ - uint8_t shadowreg; - - pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); - /* 0xf0000-0xfffff - ACPI tables */ - shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83); - shadowreg |= 0x30; - pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); - /* 0xe0000-0xeffff - elfload? */ - - pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff); -} - -/* -this table contains the value needed to be set before begin to init dram. -Note: REV_Bx should be cared when porting a new board!!!!! */ -static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { - //VT3409 no pcie - 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range - 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - //0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control - // Set ROMSIP value by software - - /*0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit - 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 - 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 - 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB - 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD - 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) - 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) - 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) */ - - - // CPU Host Bus Control - 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - //0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - //0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - //0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - //0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - //0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy - 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer - 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - //0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 - 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 - - - // Set APIC and SMRAM - 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control - 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg - 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table -}; - -#define USE_VCP 1 //0 means use DVP -#define USE_COM1 1 -#define USE_COM2 0 - -#define gCom1Base 0x3f8 -#define gCom2Base 0x2f8 - -void EmbedComInit(void) -{ - u8 ByteVal; - u16 ComBase; - - //enable NB multiple function control - ByteVal = pci_read_config8(PCI_DEV(0, 0, 0), 0x4f); - ByteVal = ByteVal | 0x01; - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, ByteVal); - - //VGA Enable - ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA1); - ByteVal = ByteVal | 0x80; - pci_write_config8(PCI_DEV(0, 0, 3), 0xA1, ByteVal); - - ByteVal = pci_read_config8(PCI_DEV(0, 0, 3), 0xA7); - ByteVal = ByteVal | 0x08; - pci_write_config8(PCI_DEV(0, 0, 3), 0xA7, ByteVal); - - //Enable p2p IO/mem - ByteVal = pci_read_config8(PCI_DEV(0, 1, 0), 0x4); - ByteVal = ByteVal | 0x07; - pci_write_config8(PCI_DEV(0, 1, 0), 0x4, ByteVal); - - //Turn on Graphic chip IO port port access - ByteVal = inb(0x3C3); - ByteVal = ByteVal | 0x01; - outb(ByteVal, 0x3C3); - - //Turn off Graphic chip Register protection - outb(0x10, 0x3C4); - ByteVal = inb(0x3C5); - ByteVal = ByteVal | 0x01; - outb(ByteVal, 0x3C5); - - //south module pad share enable 0x3C5.78[7] - outb(0x78, 0x3C4); - ByteVal = inb(0x3C5); - ByteVal = ByteVal | 0x80; - outb(ByteVal, 0x3C5); - - //enable UART Function multiplex with DVP or VCP pad D17F0Rx46[7,6] - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0x46); - //multiplex with VCP - if (USE_VCP == 1) - ByteVal = (ByteVal & 0x3F) | 0x40; - //multiplex with DVP - else - ByteVal = (ByteVal & 0x3F) | 0xC0; - pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal); - - //enable embeded com1 and com2 D17F0RxB0[5,4] - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0); - ByteVal = ByteVal & 0xcf; - //multiplex with VCP - if (USE_COM1 == 1) - ByteVal = ByteVal | 0x10; - if (USE_COM2 == 1) - ByteVal = ByteVal | 0x20; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB0, ByteVal); - - if (USE_COM1 == 1) - ComBase = gCom1Base; - else - ComBase = gCom2Base; - -//noharddrive - - //set embeded com1 IO base = 0x3E8 - //D17F0RB4 - //ByteVal = 0xFD; - if (USE_COM1 == 1) { - ByteVal = (u8) ((gCom1Base >> 3) | 0x80); - pci_write_config8(PCI_DEV(0, 17, 0), 0xB4, ByteVal); - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); - ByteVal = (ByteVal & 0xf0) | 0x04; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); - } - //set embeded com2 IO base = 0x2E8 - //D17F0RB5 - //ByteVal = 0xDD; - if (USE_COM2 == 1) { - ByteVal = (u8) ((gCom2Base >> 3) | 0x80); - pci_write_config8(PCI_DEV(0, 17, 0), 0xB5, ByteVal); - ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xb2); - ByteVal = (ByteVal & 0x0f) | 0x30; - pci_write_config8(PCI_DEV(0, 17, 0), 0xB2, ByteVal); - } - //no port 80 biger then 0x10 - - //disable interrupt - ByteVal = inb(ComBase + 3); - outb(ByteVal & 0x7F, ComBase + 3); - outb(0x00, ComBase + 1); - - //set baudrate - ByteVal = inb(ComBase + 3); - outb(ByteVal | 0x80, ComBase + 3); - outb(0x01, ComBase); - outb(0x00, ComBase + 1); - - //set frame fromat - ByteVal = inb(ComBase + 3); - outb(ByteVal & 0x3F, ComBase + 3); - outb(0x03, ComBase + 3); - outb(0x00, ComBase + 2); - outb(0x00, ComBase + 4); - - //SOutput("Embeded com output\n"); - //while(1); -} - -void main(unsigned long bist) -{ - unsigned cpu_reset = 0; - u16 boot_mode; - u8 rambits; - - //device_t dev; - /* Enable multifunction for northbridge. */ - pci_write_config8(PCI_DEV(0, 0, 0), 0x4f, 0x01); - EmbedComInit(); - //enable_vx800_serial(); - //uart_init(); - -/* 1. D15F0 - -a) RxBAh = 71h - -b) RxBBh = 05h - -c) RxBEh = 71h - -d) RxBFh = 05h - -2. D17F0 - -a) RxA0h = 06h - -b) RxA1h = 11h - -c) RxA2h = 27h - -d) RxA3h = 32h - -e) Rx79h = 40h - -f) Rx72h = 27h - -g) Rx73h = 32h -*/ - - u8 Data8; - - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBA, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_write_config16(PCI_DEV(0, 0xf, 0), 0xBE, - PCI_DEVICE_ID_VIA_VX855_IDE); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA0, PCI_VENDOR_ID_VIA); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0xA2, - PCI_DEVICE_ID_VIA_VX855_LPC); - Data8 = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x79); - Data8 &= ~0x40; - Data8 |= 0x40; - pci_write_config8(PCI_DEV(0, 0x11, 0), 0x79, Data8); - pci_write_config16(PCI_DEV(0, 0x11, 0), 0x72, - PCI_DEVICE_ID_VIA_VX855_LPC); - - console_init(); //there are to function defination of console_init(), while the src/archi386/lib is the right one - - /* decide if this is a s3 wakeup or a normal boot */ - boot_mode = acpi_is_wakeup_early_via_vx800(); - /*add this, to transfer "cpu restart" to "cold boot" - When this boot is not a S3 resume, and PCI registers had been written, - then this must be a cpu restart(result of os reboot cmd). so we need a real "cold boot". */ - if ((boot_mode != 3) - && (pci_read_config8(PCI_DEV(0, 0, 3), 0x80) != 0)) { - outb(6, 0xcf9); - } - - /*x86 cold boot I/O cmd */ - enable_smbus(); - //smbus_fixup(&ctrl);// this fix does help vx800!, but vx855 no need this - - if (bist == 0) { - // CAR need mtrr untill mem is ok, so i disable this early_mtrr_init(); - //print_debug("doing early_mtrr\n"); - //early_mtrr_init(); - } - - /* Halt if there was a built-in self test failure. */ - report_bist_failure(bist); - - print_debug("Enabling mainboard devices\n"); - enable_mainboard_devices(); - - u8 Data; - device_t device; - /* Get NB Chip revision from D0F4RxF6, revision will be used in via_pci_inittable */ - device = PCI_DEV(0, 0, 4); - Data = pci_read_config8(device, 0xf6); - print_debug("NB chip revision ="); - print_debug_hex8(Data); - print_debug("\n"); - /* make NB ready before draminit */ - via_pci_inittable(Data, mNbStage1InitTbl); - - /*add this. - When resume from s3, draminit is skiped, so need to recovery any PCI register related to draminit. - and d0f3 didnt lost its Power during whole s3 time, so any register not belongs to d0f3 need to be recoveried . */ -#if 1 - if (boot_mode == 3) { - u8 i; - u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; - DRAM_SYS_ATTR DramAttr; - - print_debug("This is a S3 wakeup\n"); - - memset(&DramAttr, 0, sizeof(DRAM_SYS_ATTR)); - /*Step1 DRAM Detection; DDR1 or DDR2; Get SPD Data; Rank Presence;64 or 128bit; Unbuffered or registered; 1T or 2T */ - DRAMDetect(&DramAttr); - - /*begin to get ram size, 43,42 41 40 contains the end address of last rank in ddr2-slot */ - device = PCI_DEV(0, 0, 3); - for (rambits = 0, i = 0; i < ARRAY_SIZE(ramregs); i++) { - rambits = pci_read_config8(device, ramregs[i]); - if (rambits != 0) - break; - } - - DRAMDRDYSetting(&DramAttr); - - Data = 0x80; // this value is same with dev_init.c - pci_write_config8(PCI_DEV(0, 0, 4), 0xa3, Data); - pci_write_config8(PCI_DEV(0, 17, 7), 0x60, rambits << 2); - Data = pci_read_config8(MEMCTRL, 0x88); - pci_write_config8(PCI_DEV(0, 17, 7), 0xE5, Data); - - DRAMRegFinalValue(&DramAttr); // I just copy this function from draminit to here! - SetUMARam(); // I just copy this function from draminit to here! - print_debug("Resume from S3, RAM init was ignored\n"); - } else { - ddr2_ram_setup(); - ram_check(0, 640 * 1024); - } -#endif - //ddr2_ram_setup(); - /*this line is the same with cx700 port . */ - enable_shadow_ram(); - - /* - For coreboot most time of S3 resume is the same as normal boot, so some memory area under 1M become dirty, - so before this happen, I need to backup the content of mem to top-mem. - I will reserve the 1M top-men in LBIO table in coreboot_table.c and recovery the content of 1M-mem in wakeup.c - */ -#if PAYLOAD_IS_SEABIOS==1 // - if (boot_mode == 3) { - /* some idea of Libo.Feng at amd.com in http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html - I want move the 1M data, I have to set some MTRRs myself. */ - /* setting mtrr before back memory save s3 resume time about 0.14 seconds */ - /*because CAR stack use cache, and here to use cache , must be careful, - 1 during these mtrr code, must no function call, (after this mtrr, I think it should be ok to use function) - 2 before stack switch, no use variable that have value set before this - 3 due to 2, take care of "cpu_reset", I directlly set it to ZERO. - */ - u32 memtop = *(u32 *) WAKE_MEM_INFO; - u32 memtop1 = *(u32 *) WAKE_MEM_INFO - 0x100000; - u32 memtop2 = *(u32 *) WAKE_MEM_INFO - 0x200000; - u32 memtop3 = - *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000; - u32 memtop4 = - *(u32 *) WAKE_MEM_INFO - 64 * 1024 - 0x100000 + - 0xe0000; - /* __asm__ volatile ( - "movl $0x204, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl %0,%%eax\n\t" - "orl $(0 | 6), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x205, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" - "orl $(0 | 0x800), %%eax\n\t" - "wrmsr\n\t" - ::"g"(memtop2) - ); - __asm__ volatile ( - "movl $0x206, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl %0,%%eax\n\t" - "orl $(0 | 6), %%eax\n\t" - "wrmsr\n\t" - - "movl $0x207, %%ecx\n\t" - "xorl %%edx, %%edx\n\t" - "movl $0x100000,%%eax\n\t" - "decl %%eax\n\t" - "notl %%eax\n\t" - "orl $(0 | 0x800), %%eax\n\t" - "wrmsr\n\t" - ::"g"(memtop1) - ); - __asm__ volatile ( - "movl $0x208, %ecx\n\t" - "xorl %edx, %edx\n\t" - "movl $0,%eax\n\t" - "orl $(0 | 6), %eax\n\t" - "wrmsr\n\t" - - "movl $0x209, %ecx\n\t" - "xorl %edx, %edx\n\t" - "movl $0x100000,%eax\n\t" - "decl %eax\n\t" - "notl %eax\n\t" - "orl $(0 | 0x800), %eax\n\t" - "wrmsr\n\t" - ); - */ - // WAKE_MEM_INFO is inited in get_set_top_available_mem in tables.c - // these two memcpy not not be enabled if set the MTRR around this two lines. - /*__asm__ volatile ( - "movl $0, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0xa0000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop3) - ); - __asm__ volatile ( - "movl $0xe0000, %%esi\n\t" - "movl %0, %%edi\n\t" - "movl $0x20000, %%ecx\n\t" - "shrl $2, %%ecx\n\t" - "rep movsd\n\t" - ::"g"(memtop4) - );*/ - print_debug("copy memory to high memory to protect s3 wakeup vector code \n"); //this can have function call, because no variable used before this - memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - - 64 * 1024 - 0x100000), - (unsigned char *) 0, 0xa0000); - memcpy((unsigned char *) ((*(u32 *) WAKE_MEM_INFO) - - 64 * 1024 - 0x100000 + 0xe0000), - (unsigned char *) 0xe0000, 0x20000); - - /* restore the MTRR previously modified. */ -/* __asm__ volatile ( - "wbinvd\n\t" - "xorl %edx, %edx\n\t" - "xorl %eax, %eax\n\t" - "movl $0x204, %ecx\n\t" - "wrmsr\n\t" - "movl $0x205, %ecx\n\t" - "wrmsr\n\t" - "movl $0x206, %ecx\n\t" - "wrmsr\n\t" - "movl $0x207, %ecx\n\t" - "wrmsr\n\t" - "movl $0x208, %ecx\n\t" - "wrmsr\n\t" - "movl $0x209, %ecx\n\t" - "wrmsr\n\t" - );*/ - } -#endif -}

1 0

New patch to review for coreboot: d74b4d8 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8086 -gerrit commit d74b4d86683c902b250029361931003edf7de356 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jan 5 00:27:54 2015 +1100 mainboard/*/romstage.c: Fix 'lib/delay.c' inclusion Use 'delay.h' header rather than directly including 'delay.c' source. Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 2 +- src/mainboard/a-trend/atc-6240/romstage.c | 2 +- src/mainboard/abit/be6-ii_v2_0/romstage.c | 2 +- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/mahogany/romstage.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 2 +- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/asrock/939a785gmh/romstage.c | 2 +- src/mainboard/asus/a8n_e/romstage.c | 2 +- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2n-e/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/p2b-d/romstage.c | 2 +- src/mainboard/asus/p2b-ds/romstage.c | 2 +- src/mainboard/asus/p2b-f/romstage.c | 2 +- src/mainboard/asus/p2b-ls/romstage.c | 2 +- src/mainboard/asus/p2b/romstage.c | 2 +- src/mainboard/asus/p3b-f/romstage.c | 2 +- src/mainboard/azza/pt-6ibd/romstage.c | 2 +- src/mainboard/bcom/winnetp680/romstage.c | 2 +- src/mainboard/biostar/m6tba/romstage.c | 2 +- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 2 +- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxc/romstage.c | 2 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +- src/mainboard/gigabyte/m57sli/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/ibm/e325/romstage.c | 2 +- src/mainboard/ibm/e326/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 2 +- src/mainboard/iwill/dk8s2/romstage.c | 2 +- src/mainboard/iwill/dk8x/romstage.c | 2 +- src/mainboard/jetway/j7f2/romstage.c | 2 +- src/mainboard/kontron/kt690/romstage.c | 2 +- src/mainboard/mitac/6513wu/romstage.c | 2 +- src/mainboard/msi/ms6119/romstage.c | 2 +- src/mainboard/msi/ms6147/romstage.c | 2 +- src/mainboard/msi/ms6156/romstage.c | 2 +- src/mainboard/msi/ms7135/romstage.c | 2 +- src/mainboard/msi/ms7260/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/mainboard/msi/ms9282/romstage.c | 2 +- src/mainboard/msi/ms9652_fam10/romstage.c | 2 +- src/mainboard/newisys/khepri/romstage.c | 2 +- src/mainboard/nokia/ip530/romstage.c | 2 +- src/mainboard/nvidia/l1_2pvv/romstage.c | 2 +- src/mainboard/siemens/sitemp_g1p1/romstage.c | 2 +- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 2 +- src/mainboard/sunw/ultra40/romstage.c | 2 +- src/mainboard/supermicro/h8dme/romstage.c | 2 +- src/mainboard/supermicro/h8dmr/romstage.c | 2 +- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 2 +- src/mainboard/supermicro/h8qme_fam10/romstage.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- src/mainboard/tyan/s1846/romstage.c | 2 +- src/mainboard/tyan/s2850/romstage.c | 2 +- src/mainboard/tyan/s2875/romstage.c | 2 +- src/mainboard/tyan/s2880/romstage.c | 2 +- src/mainboard/tyan/s2881/romstage.c | 2 +- src/mainboard/tyan/s2882/romstage.c | 2 +- src/mainboard/tyan/s2885/romstage.c | 2 +- src/mainboard/tyan/s2891/romstage.c | 2 +- src/mainboard/tyan/s2892/romstage.c | 2 +- src/mainboard/tyan/s2895/romstage.c | 2 +- src/mainboard/tyan/s2912/romstage.c | 2 +- src/mainboard/tyan/s2912_fam10/romstage.c | 2 +- src/mainboard/tyan/s4880/romstage.c | 2 +- src/mainboard/tyan/s4882/romstage.c | 2 +- src/mainboard/via/epia-cn/romstage.c | 2 +- src/mainboard/via/epia-m700/romstage.c | 2 +- src/mainboard/via/pc2500e/romstage.c | 2 +- src/mainboard/via/vt8454c/romstage.c | 2 +- src/mainboard/winent/mb6047/romstage.c | 2 +- 82 files changed, 82 insertions(+), 82 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 155a86d..bfe210e 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index baf8972..20846fd 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 9f918bb..73fef6e 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 5b9b6ca..279c15f 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 6e3de07..1a7c203 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -28,7 +28,7 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 906ff85..9b6006d 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <spd.h> diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index f49aa61..1c5debe 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -12,7 +12,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index c360245..daa4ad4 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -9,7 +9,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87360/pc87360.h> diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 16cc02b..67a1f7a 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 34f4514..c5d3f07 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index f96d4be..e642cbd 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 0b95475..ebdb095 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 2f8dc4f..5127618 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -35,7 +35,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 4cf64cc..c558a5e 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -32,7 +32,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <lib.h> #include <spd.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 87d0d71..0b1555c 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -36,7 +36,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index f5c5654..4040c60 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -36,7 +36,7 @@ unsigned int get_sbdn(unsigned bus); #include <cpu/amd/model_fxx_rev.h> #include <halt.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 28e4e60..7aa3688 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index af226d5..0d41d14 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index e46ce61..a93b743 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index dbc359a..6a5ad02 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 155a86d..bfe210e 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 2636d4e..a3aeb9a 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index bac2097..9c40af7 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 5035f57..667360a 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <lib.h> #include <spd.h> #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index 4630820..7151d40 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 72c2dd0..03f00c4 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index ea33555..654c8c1 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include <superio/nsc/pc97317/pc97317.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index b9a5630..ac437ac 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -27,7 +27,7 @@ #include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "memory.c" diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 9a2af16..d1a0b09 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/bist.h> #include <timestamp.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "../qemu-i440fx/memory.c" diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 3897551..e61c653 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 995a657..3ac2dfa 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 44fa4ca..1638863 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -35,7 +35,7 @@ #include <southbridge/sis/sis966/sis966.h> #include "southbridge/sis/sis966/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index da12a97..a613649 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -32,7 +32,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 008b353..cb83c08 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -37,7 +37,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 984b262..0785c54 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -43,7 +43,7 @@ #include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 54a543d..bb24b33 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 794fd15..4ccc7fe 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 0e579ef..47d8fda 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 9a45217..40c7137 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 0525aa9..208c0b3 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -11,7 +11,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index ca7edad..8a17113 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -28,7 +28,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71805f/f71805f.h> diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index e4ef459..fa5e914 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index c157c99..ea2c009 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82801ax/i82801ax.h> #include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index d3a51e4..403f8ef 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 95780bf..b4432e0 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index 9073be1..9b9cb14 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 290423b..88992a5 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -38,7 +38,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 96381e7..9fbb665 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -32,7 +32,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <lib.h> #include <spd.h> #include <cpu/x86/lapic.h> diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 142a496..dd816e6 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -35,7 +35,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <reset.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index d607a7d..80b7e0c 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -33,7 +33,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 4c4af88..2ab529d 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -36,7 +36,7 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 0f7d943..3f53a7f 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -17,7 +17,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 2fc5cbe..8a08c76 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 982b775..9090a24 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -33,7 +33,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 5599a24..5ce8090 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -31,7 +31,7 @@ #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index ca02936..c1cbb1d 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 8c4724f..bb754b8 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 2135563..6d75b28 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -30,7 +30,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 84198d2..bd4d7a1 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -33,7 +33,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 0fec554..3e1b11d 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -36,7 +36,7 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index b34259f..105c98d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -36,7 +36,7 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 25ccd6e..6133006 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 6cecf18..9d1034b 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 201e686..c338642 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -27,7 +27,7 @@ #include <southbridge/intel/i82371eb/i82371eb.h> #include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index c6d3734..7f291ae 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index ea2f4eb..fa3bcf5 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 0e1ac98..49ff6bc 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index acfcec3..78cccc2 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 0e1ac98..49ff6bc 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index d321a45..138d1c0 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index 4856d46..93189f1 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 4e11a1f..881972d 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index b2fe6fd..086df63 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/lpc47b397/lpc47b397.h> diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index f62e516..45fbac4 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -33,7 +33,7 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index bef0783..dfa56c4 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -36,7 +36,7 @@ #include "southbridge/nvidia/mcp55/early_smbus.c" #include <northbridge/amd/amdfam10/raminit.h> #include <northbridge/amd/amdfam10/amdfam10.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 53432af..71646c2 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -11,7 +11,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index c0a3918..a3ae994 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -10,7 +10,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 373756f..4bf2615 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "southbridge/via/vt8235/early_serial.c" #include <spd.h> diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index 8f64949..a10f755 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -35,7 +35,7 @@ #include <northbridge/via/vx800/vx800.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include <string.h> /* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 7261e20..615ad2c 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cn700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "southbridge/via/vt8237r/early_smbus.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index 8204ae3..5a74255 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -29,7 +29,7 @@ #include <northbridge/via/cx700/raminit.h> #include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" -#include "lib/delay.c" +#include <delay.h> #include "northbridge/via/cx700/early_smbus.c" #include "lib/debug.c" #include "northbridge/via/cx700/early_serial.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 7be35f9..905248e 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> -#include "lib/delay.c" +#include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c"

1 0

New patch to review for coreboot: 5b0384d mainboard/*/romstage.c: Sanitize system header inclusions
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8085 -gerrit commit 5b0384d2a20d57bc55e3a60b0bfb30d4e7c40d38 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 21:33:39 2015 +1100 mainboard/*/romstage.c: Sanitize system header inclusions Fix system include paths to be consistent. Chipset support is part of the Coreboot 'system' and hence 'non-local' (i.e., in the same directory or context). One possible product of this, is to perhaps allow future work to do pre-compiled headers (PCH) on the buildbot for faster build times. However, this currently just makes mainboard's consistent. Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/a-trend/atc-6220/romstage.c | 6 +++--- src/mainboard/a-trend/atc-6240/romstage.c | 6 +++--- src/mainboard/aaeon/pfm-540i_revb/romstage.c | 8 ++++---- src/mainboard/abit/be6-ii_v2_0/romstage.c | 6 +++--- src/mainboard/advansus/a785e-i/romstage.c | 10 +++++----- src/mainboard/amd/bimini_fam10/romstage.c | 12 ++++++------ src/mainboard/amd/db800/romstage.c | 8 ++++---- src/mainboard/amd/dbm690t/romstage.c | 8 ++++---- src/mainboard/amd/dinar/romstage.c | 4 ++-- src/mainboard/amd/inagua/romstage.c | 4 ++-- src/mainboard/amd/mahogany/romstage.c | 12 ++++++------ src/mainboard/amd/mahogany_fam10/romstage.c | 16 ++++++++-------- src/mainboard/amd/norwich/romstage.c | 8 ++++---- src/mainboard/amd/olivehill/romstage.c | 8 ++++---- src/mainboard/amd/olivehillplus/romstage.c | 8 ++++---- src/mainboard/amd/parmer/romstage.c | 8 ++++---- src/mainboard/amd/persimmon/romstage.c | 8 ++++---- src/mainboard/amd/pistachio/romstage.c | 8 ++++---- src/mainboard/amd/rumba/romstage.c | 6 +++--- src/mainboard/amd/serengeti_cheetah/romstage.c | 6 +++--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 12 ++++++------ src/mainboard/amd/south_station/romstage.c | 4 ++-- src/mainboard/amd/thatcher/romstage.c | 8 ++++---- src/mainboard/amd/tilapia_fam10/romstage.c | 16 ++++++++-------- src/mainboard/amd/torpedo/romstage.c | 4 ++-- src/mainboard/amd/union_station/romstage.c | 4 ++-- src/mainboard/aopen/dxplplusu/romstage.c | 4 ++-- src/mainboard/apple/macbook21/romstage.c | 6 +++--- src/mainboard/arima/hdama/romstage.c | 4 ++-- src/mainboard/artecgroup/dbe61/romstage.c | 8 ++++---- src/mainboard/asrock/939a785gmh/romstage.c | 12 ++++++------ src/mainboard/asrock/e350m1/romstage.c | 4 ++-- src/mainboard/asrock/imb-a180/romstage.c | 8 ++++---- src/mainboard/asus/a8n_e/romstage.c | 10 +++++----- src/mainboard/asus/a8v-e_deluxe/romstage.c | 8 ++++---- src/mainboard/asus/a8v-e_se/romstage.c | 8 ++++---- src/mainboard/asus/dsbf/romstage.c | 4 ++-- src/mainboard/asus/k8v-x/romstage.c | 8 ++++---- src/mainboard/asus/m2n-e/romstage.c | 10 +++++----- src/mainboard/asus/m2v-mx_se/romstage.c | 6 +++--- src/mainboard/asus/m2v/romstage.c | 6 +++--- src/mainboard/asus/m4a78-em/romstage.c | 16 ++++++++-------- src/mainboard/asus/m4a785-m/romstage.c | 16 ++++++++-------- src/mainboard/asus/m5a88-v/romstage.c | 10 +++++----- src/mainboard/asus/mew-am/romstage.c | 6 +++--- src/mainboard/asus/mew-vm/romstage.c | 6 +++--- src/mainboard/asus/p2b-d/romstage.c | 6 +++--- src/mainboard/asus/p2b-ds/romstage.c | 6 +++--- src/mainboard/asus/p2b-f/romstage.c | 6 +++--- src/mainboard/asus/p2b-ls/romstage.c | 6 +++--- src/mainboard/asus/p2b/romstage.c | 6 +++--- src/mainboard/asus/p3b-f/romstage.c | 6 +++--- src/mainboard/avalue/eax-785e/romstage.c | 10 +++++----- src/mainboard/azza/pt-6ibd/romstage.c | 6 +++--- src/mainboard/bachmann/ot200/romstage.c | 8 ++++---- src/mainboard/bcom/winnetp680/romstage.c | 4 ++-- src/mainboard/biostar/m6tba/romstage.c | 6 +++--- src/mainboard/broadcom/blast/romstage.c | 6 +++--- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 6 +++--- src/mainboard/digitallogic/adl855pc/romstage.c | 6 +++--- src/mainboard/digitallogic/msm800sev/romstage.c | 8 ++++---- src/mainboard/dmp/vortex86ex/romstage.c | 6 +++--- src/mainboard/ecs/p6iwp-fe/romstage.c | 6 +++--- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/getac/p470/romstage.c | 6 +++--- src/mainboard/gigabyte/ga-6bxc/romstage.c | 6 +++--- src/mainboard/gigabyte/ga-6bxe/romstage.c | 6 +++--- src/mainboard/gigabyte/ga-b75m-d3h/romstage.c | 8 ++++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 12 ++++++------ src/mainboard/gigabyte/m57sli/romstage.c | 10 +++++----- src/mainboard/gigabyte/ma785gm/romstage.c | 16 ++++++++-------- src/mainboard/gigabyte/ma785gmt/romstage.c | 16 ++++++++-------- src/mainboard/gigabyte/ma78gm/romstage.c | 16 ++++++++-------- src/mainboard/gizmosphere/gizmo/romstage.c | 6 +++--- src/mainboard/gizmosphere/gizmo2/romstage.c | 8 ++++---- src/mainboard/google/butterfly/romstage.c | 8 ++++---- src/mainboard/google/link/romstage.c | 8 ++++---- src/mainboard/google/parrot/romstage.c | 8 ++++---- src/mainboard/google/peppy/romstage.c | 10 +++++----- src/mainboard/google/slippy/romstage.c | 10 +++++----- src/mainboard/google/stout/romstage.c | 8 ++++---- src/mainboard/hp/dl145_g1/romstage.c | 6 +++--- src/mainboard/hp/dl145_g3/romstage.c | 8 ++++---- src/mainboard/hp/dl165_g6_fam10/romstage.c | 12 ++++++------ src/mainboard/hp/e_vectra_p2706t/romstage.c | 6 +++--- src/mainboard/ibm/e325/romstage.c | 4 ++-- src/mainboard/ibm/e326/romstage.c | 4 ++-- src/mainboard/iei/kino-780am2-fam10/romstage.c | 16 ++++++++-------- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 8 ++++---- src/mainboard/intel/baskingridge/romstage.c | 8 ++++---- src/mainboard/intel/cougar_canyon2/romstage.c | 10 +++++----- src/mainboard/intel/d810e2cb/romstage.c | 6 +++--- src/mainboard/intel/d945gclf/romstage.c | 6 +++--- src/mainboard/intel/eagleheights/romstage.c | 6 +++--- src/mainboard/intel/emeraldlake2/romstage.c | 8 ++++---- src/mainboard/intel/mtarvon/romstage.c | 4 ++-- src/mainboard/intel/truxton/romstage.c | 4 ++-- src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/romstage.c | 6 +++--- src/mainboard/iwill/dk8s2/romstage.c | 6 +++--- src/mainboard/iwill/dk8x/romstage.c | 6 +++--- src/mainboard/jetway/j7f2/romstage.c | 4 ++-- src/mainboard/jetway/pa78vm5/romstage.c | 16 ++++++++-------- src/mainboard/kontron/986lcd-m/romstage.c | 6 +++--- src/mainboard/kontron/kt690/romstage.c | 8 ++++---- src/mainboard/kontron/ktqm77/romstage.c | 8 ++++---- src/mainboard/lanner/em8510/romstage.c | 6 +++--- src/mainboard/lenovo/t530/romstage.c | 4 ++-- src/mainboard/lenovo/t60/romstage.c | 6 +++--- src/mainboard/lenovo/x201/romstage.c | 8 ++++---- src/mainboard/lenovo/x220/romstage.c | 8 ++++---- src/mainboard/lenovo/x230/romstage.c | 8 ++++---- src/mainboard/lenovo/x60/romstage.c | 6 +++--- src/mainboard/lippert/frontrunner-af/romstage.c | 8 ++++---- src/mainboard/lippert/frontrunner/romstage.c | 8 ++++---- src/mainboard/lippert/hurricane-lx/romstage.c | 8 ++++---- src/mainboard/lippert/literunner-lx/romstage.c | 8 ++++---- src/mainboard/lippert/roadrunner-lx/romstage.c | 8 ++++---- src/mainboard/lippert/spacerunner-lx/romstage.c | 8 ++++---- src/mainboard/lippert/toucan-af/romstage.c | 8 ++++---- src/mainboard/mitac/6513wu/romstage.c | 6 +++--- src/mainboard/msi/ms6119/romstage.c | 6 +++--- src/mainboard/msi/ms6147/romstage.c | 4 ++-- src/mainboard/msi/ms6156/romstage.c | 6 +++--- src/mainboard/msi/ms6178/romstage.c | 6 +++--- src/mainboard/msi/ms7135/romstage.c | 10 +++++----- src/mainboard/msi/ms7260/romstage.c | 10 +++++----- src/mainboard/msi/ms9185/romstage.c | 8 ++++---- src/mainboard/msi/ms9282/romstage.c | 10 +++++----- src/mainboard/msi/ms9652_fam10/romstage.c | 14 +++++++------- src/mainboard/nec/powermate2000/romstage.c | 6 +++--- src/mainboard/newisys/khepri/romstage.c | 4 ++-- src/mainboard/nokia/ip530/romstage.c | 6 +++--- src/mainboard/nvidia/l1_2pvv/romstage.c | 10 +++++----- src/mainboard/packardbell/ms2290/romstage.c | 8 ++++---- src/mainboard/pcengines/alix1c/romstage.c | 8 ++++---- src/mainboard/pcengines/alix2d/romstage.c | 8 ++++---- src/mainboard/rca/rm4100/romstage.c | 6 +++--- src/mainboard/roda/rk886ex/romstage.c | 6 +++--- src/mainboard/samsung/lumpy/romstage.c | 8 ++++---- src/mainboard/samsung/stumpy/romstage.c | 8 ++++---- src/mainboard/siemens/sitemp_g1p1/romstage.c | 8 ++++---- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 6 +++--- src/mainboard/sunw/ultra40/romstage.c | 10 +++++----- src/mainboard/supermicro/h8dme/romstage.c | 10 +++++----- src/mainboard/supermicro/h8dmr/romstage.c | 10 +++++----- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 14 +++++++------- src/mainboard/supermicro/h8qgi/romstage.c | 6 +++--- src/mainboard/supermicro/h8qme_fam10/romstage.c | 14 +++++++------- src/mainboard/supermicro/h8scm/romstage.c | 6 +++--- src/mainboard/supermicro/h8scm_fam10/romstage.c | 18 +++++++++--------- src/mainboard/supermicro/x7db8/romstage.c | 4 ++-- src/mainboard/technexion/tim5690/romstage.c | 8 ++++---- src/mainboard/technexion/tim8690/romstage.c | 8 ++++---- src/mainboard/thomson/ip1000/romstage.c | 6 +++--- src/mainboard/traverse/geos/romstage.c | 8 ++++---- src/mainboard/tyan/s1846/romstage.c | 6 +++--- src/mainboard/tyan/s2735/romstage.c | 4 ++-- src/mainboard/tyan/s2850/romstage.c | 4 ++-- src/mainboard/tyan/s2875/romstage.c | 4 ++-- src/mainboard/tyan/s2880/romstage.c | 4 ++-- src/mainboard/tyan/s2881/romstage.c | 4 ++-- src/mainboard/tyan/s2882/romstage.c | 4 ++-- src/mainboard/tyan/s2885/romstage.c | 4 ++-- src/mainboard/tyan/s2891/romstage.c | 10 +++++----- src/mainboard/tyan/s2892/romstage.c | 10 +++++----- src/mainboard/tyan/s2895/romstage.c | 10 +++++----- src/mainboard/tyan/s2912/romstage.c | 10 +++++----- src/mainboard/tyan/s2912_fam10/romstage.c | 14 +++++++------- src/mainboard/tyan/s4880/romstage.c | 4 ++-- src/mainboard/tyan/s4882/romstage.c | 4 ++-- src/mainboard/tyan/s8226/romstage.c | 6 +++--- src/mainboard/via/epia-cn/romstage.c | 4 ++-- src/mainboard/via/epia-m700/romstage.c | 6 +++--- src/mainboard/via/epia-m850/romstage.c | 4 ++-- src/mainboard/via/pc2500e/romstage.c | 4 ++-- src/mainboard/via/vt8454c/romstage.c | 4 ++-- src/mainboard/winent/mb6047/romstage.c | 10 +++++----- src/mainboard/winent/pl6064/romstage.c | 8 ++++---- src/mainboard/wyse/s50/romstage.c | 6 +++--- 181 files changed, 682 insertions(+), 682 deletions(-) diff --git a/src/mainboard/a-trend/atc-6220/romstage.c b/src/mainboard/a-trend/atc-6220/romstage.c index 16c9286..155a86d 100644 --- a/src/mainboard/a-trend/atc-6220/romstage.c +++ b/src/mainboard/a-trend/atc-6220/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/a-trend/atc-6240/romstage.c b/src/mainboard/a-trend/atc-6240/romstage.c index 8485285..baf8972 100644 --- a/src/mainboard/a-trend/atc-6240/romstage.c +++ b/src/mainboard/a-trend/atc-6240/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <lib.h> diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c index a664e9e..7c44614 100644 --- a/src/mainboard/aaeon/pfm-540i_revb/romstage.c +++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c @@ -27,15 +27,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/abit/be6-ii_v2_0/romstage.c b/src/mainboard/abit/be6-ii_v2_0/romstage.c index 63dfec6..9f918bb 100644 --- a/src/mainboard/abit/be6-ii_v2_0/romstage.c +++ b/src/mainboard/abit/be6-ii_v2_0/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 20cb703..fa8671f 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -35,12 +35,12 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/x86/lapic.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> @@ -66,7 +66,7 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index e6646f5..a9d7ea0 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -34,13 +34,13 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -57,12 +57,12 @@ static int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 63e9275..e7532cf 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -24,16 +24,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index c9a04f5..5b9b6ca 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -26,14 +26,14 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <spd.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -49,7 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index ad6bce3..64efdd6 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -30,10 +30,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "nb_cimx.h" #include <sb_cimx.h> diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 1a80e5c..1f63979 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -32,9 +32,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 00223ae..6e3de07 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -27,17 +27,17 @@ #include <console/console.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -50,7 +50,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 13470e2..7b9dad5 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #include <spd.h> @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 2c82937..9daa1d6 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -24,14 +24,14 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 82dcd60..2262782 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index f603d73..6fa3af6 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -32,10 +32,10 @@ #include <cpu/amd/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/pi/avalon/hudson.h" -#include "cpu/amd/pi/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/pi/avalon/hudson.h> +#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index e38d715..1fb709a 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 581c2c2..2fdab41 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -32,16 +32,16 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index af4253d..906ff85 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -26,12 +26,12 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <spd.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -45,7 +45,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index 248baa0..fb21b2f 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -5,8 +5,8 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -22,7 +22,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index ec0682a..f49aa61 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -9,9 +9,9 @@ #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" #include <reset.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> @@ -50,7 +50,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 6388b42..54e48e7 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -35,14 +35,14 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> @@ -79,12 +79,12 @@ static int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index ccf84b6..5f902c3 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,10 +32,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 319cd3a..30808a4 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,11 +31,11 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> #include "src/superio/smsc/lpc47n217/early_serial.c" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index f5ac2e0..16974a1 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -59,12 +59,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index e3f41a0..6c2f2c5 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -29,9 +29,9 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/kbc1100/kbc1100.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index c75cf7a..714eb3c 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,8 +32,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 8bb179a..b42ff2e 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -25,8 +25,8 @@ #include <console/console.h> #include <cpu/x86/bist.h> -#include "southbridge/intel/i82801dx/i82801dx.h" -#include "northbridge/intel/e7505/raminit.h" +#include <southbridge/intel/i82801dx/i82801dx.h> +#include <northbridge/intel/e7505/raminit.h> #include <device/pnp_def.h> #include <superio/smsc/lpc47m10x/lpc47m10x.h> diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index 443fdc5..dfa6847 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -36,9 +36,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> void setup_ich7_gpios(void) { diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 137d3eb..c360245 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -8,12 +8,12 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87360/pc87360.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 63f89f1..7d753b3 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -24,15 +24,15 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "spd_table.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 417f9a7..16cc02b 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -27,18 +27,18 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -52,7 +52,7 @@ static inline int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 604c923..aabdd74 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,10 +31,10 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <sb_cimx.h> #include "SBPLATFORM.h" diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 1ba1104..efeed35 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627uhg/w83627uhg.h> diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index c0fa6a5..34f4514 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -32,18 +32,18 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" @@ -59,7 +59,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 0d55e53..f96d4be 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -34,16 +34,16 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -76,7 +76,7 @@ void soft_reset(void) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 3ed2491..0b95475 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -34,16 +34,16 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -76,7 +76,7 @@ void soft_reset(void) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/dsbf/romstage.c b/src/mainboard/asus/dsbf/romstage.c index fbd0848..d7bcb89 100644 --- a/src/mainboard/asus/dsbf/romstage.c +++ b/src/mainboard/asus/dsbf/romstage.c @@ -32,8 +32,8 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> -#include "northbridge/intel/i3100/i3100.h" -#include "southbridge/intel/i3100/i3100.h" +#include <northbridge/intel/i3100/i3100.h> +#include <southbridge/intel/i3100/i3100.h> #include <southbridge/intel/i3100/early_smbus.c> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index dab3193..2f8dc4f 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -34,16 +34,16 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -74,7 +74,7 @@ void soft_reset(void) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index d12b77c..4cf64cc 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -31,15 +31,15 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <lib.h> #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -55,14 +55,14 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 42b03c8..87d0d71 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -35,14 +35,14 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -58,7 +58,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index f776351..f5c5654 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -35,14 +35,14 @@ unsigned int get_sbdn(unsigned bus); #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <halt.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -61,7 +61,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "southbridge/via/k8t890/early_car.c" -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 0a03d59..4dda4a2 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 84d2b97..5230e2f 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 4753bb0..be922d0 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -35,12 +35,12 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/x86/lapic.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> @@ -64,7 +64,7 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" diff --git a/src/mainboard/asus/mew-am/romstage.c b/src/mainboard/asus/mew-am/romstage.c index 15d7791..213d480 100644 --- a/src/mainboard/asus/mew-am/romstage.c +++ b/src/mainboard/asus/mew-am/romstage.c @@ -24,10 +24,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801ax/i82801ax.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index 3c67af3..f6032ef 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -25,9 +25,9 @@ #include <stdlib.h> #include <console/console.h> #include <superio/smsc/lpc47b272/lpc47b272.h> -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/asus/p2b-d/romstage.c b/src/mainboard/asus/p2b-d/romstage.c index 8307311..28e4e60 100644 --- a/src/mainboard/asus/p2b-d/romstage.c +++ b/src/mainboard/asus/p2b-d/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/asus/p2b-ds/romstage.c b/src/mainboard/asus/p2b-ds/romstage.c index 56992c5..af226d5 100644 --- a/src/mainboard/asus/p2b-ds/romstage.c +++ b/src/mainboard/asus/p2b-ds/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/asus/p2b-f/romstage.c b/src/mainboard/asus/p2b-f/romstage.c index 7cf0099..e46ce61 100644 --- a/src/mainboard/asus/p2b-f/romstage.c +++ b/src/mainboard/asus/p2b-f/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b-ls/romstage.c b/src/mainboard/asus/p2b-ls/romstage.c index fb90a68..dbc359a 100644 --- a/src/mainboard/asus/p2b-ls/romstage.c +++ b/src/mainboard/asus/p2b-ls/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P2B-LS has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p2b/romstage.c b/src/mainboard/asus/p2b/romstage.c index 16c9286..155a86d 100644 --- a/src/mainboard/asus/p2b/romstage.c +++ b/src/mainboard/asus/p2b/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/asus/p3b-f/romstage.c b/src/mainboard/asus/p3b-f/romstage.c index 2655fc7..2636d4e 100644 --- a/src/mainboard/asus/p3b-f/romstage.c +++ b/src/mainboard/asus/p3b-f/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: The ASUS P3B-F has a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 65f499b..528488e 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -35,12 +35,12 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" -#include "cpu/x86/lapic.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/amd/mtrr.h> @@ -67,7 +67,7 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include "spd.h" diff --git a/src/mainboard/azza/pt-6ibd/romstage.c b/src/mainboard/azza/pt-6ibd/romstage.c index 804e34c..bac2097 100644 --- a/src/mainboard/azza/pt-6ibd/romstage.c +++ b/src/mainboard/azza/pt-6ibd/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> /* FIXME: It's a Winbond W83977EF, actually. */ #include <superio/winbond/w83977tf/w83977tf.h> diff --git a/src/mainboard/bachmann/ot200/romstage.c b/src/mainboard/bachmann/ot200/romstage.c index 7951a57..4f65cbf 100644 --- a/src/mainboard/bachmann/ot200/romstage.c +++ b/src/mainboard/bachmann/ot200/romstage.c @@ -26,13 +26,13 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/bcom/winnetp680/romstage.c b/src/mainboard/bcom/winnetp680/romstage.c index 170a909..5035f57 100644 --- a/src/mainboard/bcom/winnetp680/romstage.c +++ b/src/mainboard/bcom/winnetp680/romstage.c @@ -25,8 +25,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <lib.h> diff --git a/src/mainboard/biostar/m6tba/romstage.c b/src/mainboard/biostar/m6tba/romstage.c index a91318d..4630820 100644 --- a/src/mainboard/biostar/m6tba/romstage.c +++ b/src/mainboard/biostar/m6tba/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index a97c3b8..72c2dd0 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -9,13 +9,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index cfda5db..ea33555 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ #include <superio/nsc/pc97317/pc97317.h> #include <lib.h> diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c index ce8ef13..73fef71 100644 --- a/src/mainboard/digitallogic/adl855pc/romstage.c +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -7,12 +7,12 @@ #include "drivers/pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "southbridge/intel/i82801dx/i82801dx.h" -#include "northbridge/intel/i855/raminit.h" +#include <southbridge/intel/i82801dx/i82801dx.h> +#include <northbridge/intel/i855/raminit.h> #include "northbridge/intel/i855/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index 4df217f..8260cde 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -4,17 +4,17 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/dmp/vortex86ex/romstage.c b/src/mainboard/dmp/vortex86ex/romstage.c index d43df8d..5deebc5 100644 --- a/src/mainboard/dmp/vortex86ex/romstage.c +++ b/src/mainboard/dmp/vortex86ex/romstage.c @@ -25,10 +25,10 @@ #include <cpu/x86/cache.h> #include <halt.h> #include "drivers/pc80/i8254.c" -#include "northbridge/dmp/vortex86ex/northbridge.h" -#include "southbridge/dmp/vortex86ex/southbridge.h" +#include <northbridge/dmp/vortex86ex/northbridge.h> +#include <southbridge/dmp/vortex86ex/southbridge.h> #include "northbridge/dmp/vortex86ex/raminit.c" -#include "cpu/dmp/dmp_post_code.h" +#include <cpu/dmp/dmp_post_code.h> #define DMP_CPUID_SX 0x31504d44 #define DMP_CPUID_DX 0x32504d44 diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 0ffcfa5..db69906 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -25,10 +25,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801ax/i82801ax.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <lib.h> diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index c617a0a..b9a5630 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -28,7 +28,7 @@ #include <timestamp.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "memory.c" diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 658051c..9a2af16 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -29,7 +29,7 @@ #include <timestamp.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "../qemu-i440fx/memory.c" diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index b57e6b7..c4b053f 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -32,9 +32,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 9e465dd..3897551 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 369a23f..995a657 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index 6fea437..a1515ee 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -30,10 +30,10 @@ #include <console/console.h> #include <superio/ite/it8728f/it8728f.h> #include <superio/ite/common/ite.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 10bbb6f..44fa4ca 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -32,15 +32,15 @@ #include <console/console.h> #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "southbridge/sis/sis966/sis966.h" +#include <southbridge/sis/sis966/sis966.h> #include "southbridge/sis/sis966/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" @@ -56,7 +56,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -78,7 +78,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/sis/sis966/early_setup_ss.h" +#include <southbridge/sis/sis966/early_setup_ss.h> #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index b2e1d70..da12a97 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -31,13 +31,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -61,9 +61,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index a0f9e76..ecc1e31 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -30,20 +30,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -56,12 +56,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index a0f9e76..ecc1e31 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -30,20 +30,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -56,12 +56,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index b9d27f7..3c57f19 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -60,12 +60,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index a0c3d28..f420bf2 100644 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,13 +33,13 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define MSR_MTRR_VARIABLE_BASE6 0x020C #define MSR_MTRR_VARIABLE_MASK6 0x020D diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index 82dcd60..2262782 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -31,10 +31,10 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> #include "cbmem.h" diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 6cf86ad..70a6f44 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -31,10 +31,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index f58ab13..873de91 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -32,10 +32,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include "ec/google/chromeec/ec.h" #include <arch/cpu.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 69711d9..7d67abd 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -31,10 +31,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index 38c224b..9a1fb76 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -24,12 +24,12 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" +#include <cpu/intel/haswell/haswell.h> #include "ec/google/chromeec/ec.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "onboard.h" diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fd190ed..6feebac 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -24,11 +24,11 @@ #include <string.h> #include <cbfs.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" const struct rcba_config_instruction rcba_config[] = { diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index e8f2927..f856c59 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -31,10 +31,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 2b42e73..db3c306 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -12,14 +12,14 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include <delay.h> -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "southbridge/amd/amd8111/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 474f273..008b353 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -36,13 +36,13 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" @@ -66,7 +66,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 9e10360..984b262 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -39,16 +39,16 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> #include <spd.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "southbridge/broadcom/bcm5785/early_setup.c" @@ -71,11 +71,11 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index f54e0e8..dcdd552 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -27,9 +27,9 @@ /* TODO: It's a PC87364 actually! */ #include <superio/nsc/pc87360/pc87360.h> /* TODO: It's i810E actually! */ -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index 4e1e925..54a543d 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -9,12 +9,12 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index 2ac90ab..794fd15 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -9,12 +9,12 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87366/pc87366.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" #include <spd.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index e1230e5..1d1595e 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -34,20 +34,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71859/f71859.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) @@ -59,12 +59,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c index b11f5cb..401d362 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -24,16 +24,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index e02ae7a..7aea6b6 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -21,10 +21,10 @@ #include <stdint.h> #include <stddef.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" +#include <cpu/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> #include "gpio.h" const struct rcba_config_instruction rcba_config[] = { diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 7194851..6344e1b 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -35,11 +35,11 @@ #include <reset.h> #include <superio/smsc/sio1007/chip.h> #include <fsp_util.h> -#include "northbridge/intel/fsp_sandybridge/northbridge.h" -#include "northbridge/intel/fsp_sandybridge/raminit.h" -#include "southbridge/intel/fsp_bd82x6x/pch.h" -#include "southbridge/intel/fsp_bd82x6x/gpio.h" -#include "southbridge/intel/fsp_bd82x6x/me.h" +#include <northbridge/intel/fsp_sandybridge/northbridge.h> +#include <northbridge/intel/fsp_sandybridge/raminit.h> +#include <southbridge/intel/fsp_bd82x6x/pch.h> +#include <southbridge/intel/fsp_bd82x6x/gpio.h> +#include <southbridge/intel/fsp_bd82x6x/me.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include "gpio.h" diff --git a/src/mainboard/intel/d810e2cb/romstage.c b/src/mainboard/intel/d810e2cb/romstage.c index a6958ee..e7b78f8 100644 --- a/src/mainboard/intel/d810e2cb/romstage.c +++ b/src/mainboard/intel/d810e2cb/romstage.c @@ -24,10 +24,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801bx/i82801bx.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801bx/i82801bx.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "gpio.c" #include <lib.h> diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 4194a80..c8b53ed 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -32,9 +32,9 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index b41e0c5..b0efb7d 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -35,8 +35,8 @@ #include "southbridge/intel/i3100/reset.c" #include <superio/intel/i3100/i3100.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i3100/i3100.h" -#include "southbridge/intel/i3100/i3100.h" +#include <northbridge/intel/i3100/i3100.h> +#include <southbridge/intel/i3100/i3100.h> #include "lib/debug.c" // XXX #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) @@ -67,7 +67,7 @@ static inline int spd_read_byte(u16 device, u8 address) return smbus_read_byte(device, address); } -#include "northbridge/intel/i3100/raminit.h" +#include <northbridge/intel/i3100/raminit.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index ffb44a0..adcf175 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -31,10 +31,10 @@ #include <cbmem.h> #include <console/console.h> #include <superio/smsc/sio1007/chip.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 959beab..61f9a2c 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -28,10 +28,10 @@ #include <console/console.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" -#include "northbridge/intel/i3100/raminit.h" +#include <northbridge/intel/i3100/raminit.h> #include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 4c15f67..5145a50 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -29,11 +29,11 @@ #include <console/console.h> #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" -#include "northbridge/intel/i3100/raminit_ep80579.h" +#include <northbridge/intel/i3100/raminit_ep80579.h> #include <superio/intel/i3100/i3100.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "lib/debug.c" // XXX -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 00d4a38..6d9824f 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -273,7 +273,7 @@ int selectcard(void) #endif #include "northbridge/intel/sch/early_init.c" -#include "northbridge/intel/sch/raminit.h" +#include <northbridge/intel/sch/raminit.h> #include "northbridge/intel/sch/raminit.c" static void sch_enable_lpc(void) diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index a429568..0e579ef 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -8,9 +8,9 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index d2371b5..9a45217 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -8,9 +8,9 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index 50869f7..0525aa9 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -8,9 +8,9 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" diff --git a/src/mainboard/jetway/j7f2/romstage.c b/src/mainboard/jetway/j7f2/romstage.c index a66467b..ca7edad 100644 --- a/src/mainboard/jetway/j7f2/romstage.c +++ b/src/mainboard/jetway/j7f2/romstage.c @@ -25,8 +25,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 5121605..6e8e43a 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -35,20 +35,20 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71863fg/f71863fg.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdfam10/debug.c" #if CONFIG_TTYS0_BASE == 0x2f8 @@ -64,12 +64,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 652d8cb..e72c3dc 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -34,9 +34,9 @@ #include <cpu/x86/bist.h> #include <halt.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 24cae41..e4ef459 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -27,16 +27,16 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/amd/mtrr.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -49,7 +49,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 6926952..31f1b22 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -30,10 +30,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lanner/em8510/romstage.c b/src/mainboard/lanner/em8510/romstage.c index c1a02f4..0216001 100644 --- a/src/mainboard/lanner/em8510/romstage.c +++ b/src/mainboard/lanner/em8510/romstage.c @@ -30,12 +30,12 @@ #include "drivers/pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "southbridge/intel/i82801dx/i82801dx.h" -#include "northbridge/intel/i855/raminit.h" +#include <southbridge/intel/i82801dx/i82801dx.h> +#include <northbridge/intel/i855/raminit.h> #include "northbridge/intel/i855/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 0a49ed0..fbf47ac 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -24,8 +24,8 @@ #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 571a21c..094e1dc 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -36,9 +36,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index e58f5f6..64636c4 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -42,11 +42,11 @@ #include "gpio.h" #include "dock.h" #include "arch/early_variables.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <southbridge/intel/ibexpeak/pch.h> +#include <northbridge/intel/nehalem/nehalem.h> -#include "northbridge/intel/nehalem/raminit.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index d9c8aa0..d0fb8e6 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -30,10 +30,10 @@ #include <cpu/x86/lapic.h> #include <arch/acpi.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 0bb137e..4ea272d 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -32,10 +32,10 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit_native.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> #include <cbfs.h> diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index af9b1be..b997637 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -36,9 +36,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "dock.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index d21a565..0f718f2 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -32,15 +32,15 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 3be4eb3..f86d558 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -6,10 +6,10 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> -#include "southbridge/amd/cs5535/cs5535.h" +#include <southbridge/amd/cs5535/cs5535.h> #include "southbridge/amd/cs5535/early_smbus.c" #include "southbridge/amd/cs5535/early_setup.c" @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF; } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c" diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 416a8fb..8e802f3 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -27,16 +27,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 8b48640..9199772 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -28,15 +28,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 4d8a6fd..dc503ed 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -27,16 +27,16 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 3c25c08..2a22140 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -28,15 +28,15 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index e655f9a..415cdbe 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -32,16 +32,16 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" #include "cbmem.h" -#include "cpu/amd/mtrr.h" -#include "cpu/amd/agesa/s3_resume.h" +#include <cpu/amd/mtrr.h> +#include <cpu/amd/agesa/s3_resume.h> #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) diff --git a/src/mainboard/mitac/6513wu/romstage.c b/src/mainboard/mitac/6513wu/romstage.c index 2710082..c157c99 100644 --- a/src/mainboard/mitac/6513wu/romstage.c +++ b/src/mainboard/mitac/6513wu/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82801ax/i82801ax.h" -#include "northbridge/intel/i82810/raminit.h" +#include <southbridge/intel/i82801ax/i82801ax.h> +#include <northbridge/intel/i82810/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6119/romstage.c b/src/mainboard/msi/ms6119/romstage.c index fb30e49..d3a51e4 100644 --- a/src/mainboard/msi/ms6119/romstage.c +++ b/src/mainboard/msi/ms6119/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6147/romstage.c b/src/mainboard/msi/ms6147/romstage.c index 916f0e9..95780bf 100644 --- a/src/mainboard/msi/ms6147/romstage.c +++ b/src/mainboard/msi/ms6147/romstage.c @@ -24,8 +24,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <cpu/x86/bist.h> diff --git a/src/mainboard/msi/ms6156/romstage.c b/src/mainboard/msi/ms6156/romstage.c index e8dbb02..9073be1 100644 --- a/src/mainboard/msi/ms6156/romstage.c +++ b/src/mainboard/msi/ms6156/romstage.c @@ -24,11 +24,11 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83977tf/w83977tf.h> #include <lib.h> diff --git a/src/mainboard/msi/ms6178/romstage.c b/src/mainboard/msi/ms6178/romstage.c index 66a9c9b..5059074 100644 --- a/src/mainboard/msi/ms6178/romstage.c +++ b/src/mainboard/msi/ms6178/romstage.c @@ -26,9 +26,9 @@ #include <console/console.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 15c02f5..290423b 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -29,18 +29,18 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" @@ -62,7 +62,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index fd8fbfb..96381e7 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -31,15 +31,15 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <lib.h> #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -54,7 +54,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -70,7 +70,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index bd82436..142a496 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -34,14 +34,14 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <reset.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/nsc/pc87417/pc87417.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" @@ -64,7 +64,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 9a6e21f..d607a7d 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -32,14 +32,14 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <spd.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> @@ -63,14 +63,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> //set GPIO to input mode #define MCP55_MB_SETUP \ diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..4c4af88 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -55,7 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" @@ -69,9 +69,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/nec/powermate2000/romstage.c b/src/mainboard/nec/powermate2000/romstage.c index 6bbfc1a..f13f746 100644 --- a/src/mainboard/nec/powermate2000/romstage.c +++ b/src/mainboard/nec/powermate2000/romstage.c @@ -25,9 +25,9 @@ #include <stdlib.h> #include <console/console.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i82810/raminit.h" -#include "cpu/x86/bist.h" -#include "southbridge/intel/i82801ax/i82801ax.h" +#include <northbridge/intel/i82810/raminit.h> +#include <cpu/x86/bist.h> +#include <southbridge/intel/i82801ax/i82801ax.h> #include "drivers/pc80/udelay_io.c" #include <lib.h> diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index b34882e..0f7d943 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -16,13 +16,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/nokia/ip530/romstage.c b/src/mainboard/nokia/ip530/romstage.c index 3c5511b..2fc5cbe 100644 --- a/src/mainboard/nokia/ip530/romstage.c +++ b/src/mainboard/nokia/ip530/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include <lib.h> diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index df78a0c..982b775 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -32,13 +32,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -53,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index ca96c87..1c5745f 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -41,11 +41,11 @@ #include <cpu/intel/romstage.h> #include "arch/early_variables.h" -#include "southbridge/intel/ibexpeak/pch.h" -#include "northbridge/intel/nehalem/nehalem.h" +#include <southbridge/intel/ibexpeak/pch.h> +#include <northbridge/intel/nehalem/nehalem.h> -#include "northbridge/intel/nehalem/raminit.h" -#include "southbridge/intel/ibexpeak/me.h" +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> static void pch_enable_lpc(void) { diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index f4bbc31..38541e7 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -25,12 +25,12 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" -#include "northbridge/amd/lx/raminit.h" +#include <southbridge/amd/cs5536/cs5536.h> +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 1316d5e..6f62311 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -25,12 +25,12 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> #include <cpu/amd/car.h> -#include "southbridge/amd/cs5536/cs5536.h" -#include "northbridge/amd/lx/raminit.h" +#include <southbridge/amd/cs5536/cs5536.h> +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/rca/rm4100/romstage.c b/src/mainboard/rca/rm4100/romstage.c index 500416a..9da69b5 100644 --- a/src/mainboard/rca/rm4100/romstage.c +++ b/src/mainboard/rca/rm4100/romstage.c @@ -27,11 +27,11 @@ #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i82830/raminit.h" +#include <northbridge/intel/i82830/raminit.h> #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801dx/i82801dx.h" +#include <southbridge/intel/i82801dx/i82801dx.h> #include "southbridge/intel/i82801dx/reset.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "spd_table.h" #include "gpio.c" #include "southbridge/intel/i82801dx/tco_timer.c" diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e8ada36..a7fd007 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -34,9 +34,9 @@ #include <console/console.h> #include <cpu/x86/bist.h> #include <halt.h> -#include "northbridge/intel/i945/i945.h" -#include "northbridge/intel/i945/raminit.h" -#include "southbridge/intel/i82801gx/i82801gx.h" +#include <northbridge/intel/i945/i945.h> +#include <northbridge/intel/i945/raminit.h> +#include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h" void setup_ich7_gpios(void) diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index b356fa8..93cc068 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -33,10 +33,10 @@ #include <cbmem.h> #include <console/console.h> #include <bootmode.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 1462132..abaf48e 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -34,10 +34,10 @@ #include <bootmode.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include "northbridge/intel/sandybridge/sandybridge.h" -#include "northbridge/intel/sandybridge/raminit.h" -#include "southbridge/intel/bd82x6x/pch.h" -#include "southbridge/intel/bd82x6x/gpio.h" +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> #include <arch/cpu.h> #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 4beb8c9..5599a24 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -30,15 +30,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -65,7 +65,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 531e223..ca02936 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/ite/it8671f/it8671f.h> #include <lib.h> diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 99d0dfb..8c4724f 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -10,14 +10,14 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/smsc/lpc47b397/lpc47b397.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "superio/smsc/lpc47b397/early_gpio.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index e3e7386..2135563 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -29,13 +29,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -62,14 +62,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 7d1f834..84198d2 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -32,13 +32,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -54,14 +54,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index b393c34..0fec554 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -56,14 +56,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index c231e31..07c3c33 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -24,11 +24,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "northbridge/amd/agesa/family10/reset_test.h" +#include <northbridge/amd/agesa/family10/reset_test.h> #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..b34259f 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" // for enable the FAN -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -62,14 +62,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 0bbd8bc..ed82a38 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -24,11 +24,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "northbridge/amd/agesa/family10/reset_test.h" +#include <northbridge/amd/agesa/family10/reset_test.h> #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/nuvoton/wpcm450/wpcm450.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 917e9e3..5d6274c 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -34,18 +34,18 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include <lib.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/sb700/sb700.h" -#include "southbridge/amd/sb700/smbus.h" -#include "southbridge/amd/sr5650/sr5650.h" +#include <southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/smbus.h> +#include <southbridge/amd/sr5650/sr5650.h> #include <superio/nuvoton/wpcm450/wpcm450.h> #include "northbridge/amd/amdfam10/debug.c" @@ -58,12 +58,12 @@ static int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" #include <spd.h> diff --git a/src/mainboard/supermicro/x7db8/romstage.c b/src/mainboard/supermicro/x7db8/romstage.c index 83e34b5..b4364a3 100644 --- a/src/mainboard/supermicro/x7db8/romstage.c +++ b/src/mainboard/supermicro/x7db8/romstage.c @@ -32,8 +32,8 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <northbridge/intel/i5000/raminit.h> -#include "northbridge/intel/i3100/i3100.h" -#include "southbridge/intel/i3100/i3100.h" +#include <northbridge/intel/i3100/i3100.h> +#include <southbridge/intel/i3100/i3100.h> #include <southbridge/intel/i3100/early_smbus.c> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 68373b9..25ccd6e 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -26,15 +26,15 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -50,7 +50,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 0ba0fce..6cecf18 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -26,15 +26,15 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include <spd.h> -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" @@ -50,7 +50,7 @@ static inline int spd_read_byte(u32 device, u32 address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8.h" +#include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" diff --git a/src/mainboard/thomson/ip1000/romstage.c b/src/mainboard/thomson/ip1000/romstage.c index ede49f7..5627296 100644 --- a/src/mainboard/thomson/ip1000/romstage.c +++ b/src/mainboard/thomson/ip1000/romstage.c @@ -27,11 +27,11 @@ #include <console/console.h> #include <lib.h> #include <superio/smsc/smscsuperio/smscsuperio.h> -#include "northbridge/intel/i82830/raminit.h" +#include <northbridge/intel/i82830/raminit.h> #include "northbridge/intel/i82830/memory_initialized.c" -#include "southbridge/intel/i82801dx/i82801dx.h" +#include <southbridge/intel/i82801dx/i82801dx.h> #include "southbridge/intel/i82801dx/reset.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "spd_table.h" #include "gpio.c" #include "southbridge/intel/i82801dx/tco_timer.c" diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c index 76e4a5c..1226518 100644 --- a/src/mainboard/traverse/geos/romstage.c +++ b/src/mainboard/traverse/geos/romstage.c @@ -25,14 +25,14 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> int spd_read_byte(unsigned int device, unsigned int address) { diff --git a/src/mainboard/tyan/s1846/romstage.c b/src/mainboard/tyan/s1846/romstage.c index 10af34d..201e686 100644 --- a/src/mainboard/tyan/s1846/romstage.c +++ b/src/mainboard/tyan/s1846/romstage.c @@ -24,11 +24,11 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "southbridge/intel/i82371eb/i82371eb.h" -#include "northbridge/intel/i440bx/raminit.h" +#include <southbridge/intel/i82371eb/i82371eb.h> +#include <northbridge/intel/i440bx/raminit.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include <superio/nsc/pc87309/pc87309.h> #include <lib.h> diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c index 5d4fd0e..514aa61 100644 --- a/src/mainboard/tyan/s2735/romstage.c +++ b/src/mainboard/tyan/s2735/romstage.c @@ -9,11 +9,11 @@ #include <lib.h> #include <spd.h> #include "southbridge/intel/i82801ex/early_smbus.c" -#include "northbridge/intel/e7501/raminit.h" +#include <northbridge/intel/e7501/raminit.h> #include "northbridge/intel/e7501/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 952b19d..c6d3734 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 8f87257..ea2f4eb 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 873652b..0e1ac98 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index c020f3e..acfcec3 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -10,13 +10,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 873652b..0e1ac98 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -11,13 +11,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index df602ea..d321a45 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -10,13 +10,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index e97b026..4856d46 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -10,15 +10,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -37,7 +37,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "northbridge/amd/amdk8/early_ht.c" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 57da072..4e11a1f 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -10,15 +10,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -36,7 +36,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 0e42f76..b2fe6fd 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -10,14 +10,14 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/lpc47b397/lpc47b397.h> #include "superio/smsc/lpc47b397/early_gpio.c" -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -51,7 +51,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> //set GPIO to input mode #define CK804_MB_SETUP \ diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 55cb95e..f62e516 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -32,13 +32,13 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -53,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/f.h" +#include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" @@ -69,7 +69,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 6dae693..bef0783 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -34,14 +34,14 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/nvidia/mcp55/early_smbus.c" -#include "northbridge/amd/amdfam10/raminit.h" -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" @@ -55,7 +55,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include "northbridge/amd/amdfam10/amdfam10.h" +#include <northbridge/amd/amdfam10/amdfam10.h> #include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" #include "northbridge/amd/amdfam10/pci.c" #include "resourcemap.c" @@ -69,9 +69,9 @@ static inline int spd_read_byte(unsigned device, unsigned address) RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+59, 0x00, 0x60,/* GPIP60 FANCTL0 */ \ RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */ -#include "southbridge/nvidia/mcp55/early_setup_ss.h" +#include <southbridge/nvidia/mcp55/early_setup_ss.h> #include "southbridge/nvidia/mcp55/early_setup_car.c" -#include "cpu/amd/microcode.h" +#include <cpu/amd/microcode.h> #include "cpu/amd/model_10xxx/init_cpus.c" #include "northbridge/amd/amdfam10/early_ht.c" diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index c106b1c..53432af 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -10,13 +10,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 17379b5..c0a3918 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -9,13 +9,13 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/early_smbus.c" -#include "northbridge/amd/amdk8/raminit.h" +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index ac28874..e14292e 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -24,11 +24,11 @@ #include <arch/cpu.h> #include <console/console.h> #include <arch/stages.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "northbridge/amd/agesa/family10/reset_test.h" +#include <northbridge/amd/agesa/family10/reset_test.h> #include <nb_cimx.h> #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-cn/romstage.c b/src/mainboard/via/epia-cn/romstage.c index 8a0d384..373756f 100644 --- a/src/mainboard/via/epia-cn/romstage.c +++ b/src/mainboard/via/epia-cn/romstage.c @@ -26,8 +26,8 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index c9b1e8b..8f64949 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -32,14 +32,14 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/vx800/vx800.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/vx800/vx800.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include <string.h> /* This file contains the board-special SI value for raminit.c. */ #include "driving_clk_phase_data.c" -#include "northbridge/via/vx800/raminit.h" +#include <northbridge/via/vx800/raminit.h> #include "northbridge/via/vx800/raminit.c" #include "wakeup.h" #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 899c5a6..09f8f62 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -33,8 +33,8 @@ #include <timestamp.h> #include <console/cbmem_console.h> -#include "northbridge/via/vx900/early_vx900.h" -#include "northbridge/via/vx900/raminit.h" +#include <northbridge/via/vx900/early_vx900.h> +#include <northbridge/via/vx900/raminit.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 57e5cd0..7261e20 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -26,8 +26,8 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/cn700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cn700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" diff --git a/src/mainboard/via/vt8454c/romstage.c b/src/mainboard/via/vt8454c/romstage.c index bb2d878..8204ae3 100644 --- a/src/mainboard/via/vt8454c/romstage.c +++ b/src/mainboard/via/vt8454c/romstage.c @@ -26,8 +26,8 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "northbridge/via/cx700/raminit.h" -#include "cpu/x86/bist.h" +#include <northbridge/via/cx700/raminit.h> +#include <cpu/x86/bist.h> #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "northbridge/via/cx700/early_smbus.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index a725beb..7be35f9 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -10,15 +10,15 @@ #include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "southbridge/nvidia/ck804/early_smbus.h" -#include "northbridge/amd/amdk8/raminit.h" +#include <southbridge/nvidia/ck804/early_smbus.h> +#include <northbridge/amd/amdk8/raminit.h> #include "lib/delay.c" -#include "cpu/x86/lapic.h" +#include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> -#include "cpu/x86/bist.h" +#include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) @@ -36,7 +36,7 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/nvidia/ck804/early_setup_ss.h" +#include <southbridge/nvidia/ck804/early_setup_ss.h> #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" #if CONFIG_SET_FIDVID diff --git a/src/mainboard/winent/pl6064/romstage.c b/src/mainboard/winent/pl6064/romstage.c index 56b1329..ff68a8c 100644 --- a/src/mainboard/winent/pl6064/romstage.c +++ b/src/mainboard/winent/pl6064/romstage.c @@ -26,16 +26,16 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/lxdef.h> -#include "southbridge/amd/cs5536/cs5536.h" +#include <southbridge/amd/cs5536/cs5536.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> -#include "northbridge/amd/lx/raminit.h" +#include <northbridge/amd/lx/raminit.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) diff --git a/src/mainboard/wyse/s50/romstage.c b/src/mainboard/wyse/s50/romstage.c index 6283c9c..fea26cf 100644 --- a/src/mainboard/wyse/s50/romstage.c +++ b/src/mainboard/wyse/s50/romstage.c @@ -25,8 +25,8 @@ #include <device/pnp_def.h> #include <console/console.h> #include <lib.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> #include <cpu/amd/gx2def.h> #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -40,7 +40,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) return smbus_read_byte(device, address); } -#include "northbridge/amd/gx2/raminit.h" +#include <northbridge/amd/gx2/raminit.h> #include "northbridge/amd/gx2/pll_reset.c" #include "northbridge/amd/gx2/raminit.c" #include "lib/generic_sdram.c"

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Patch merged into coreboot/master: 9e687a6 superio/smsc/lpc47b272/superio.c: Remove dead code
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 9e687a62b1ed6322ed13ebe21602fa80027cdd34 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:35:43 2015 +1100 superio/smsc/lpc47b272/superio.c: Remove dead code Remove dead debug code, we have superiotool for this reason. Restructure file to be consistent with other superio's thereby avoiding forward declarations of functions. Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8083 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8083 for details. -gerrit

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Patch merged into coreboot/master: 520a328 src/superio/smsc/lpc47m10x/superio.c: Remove dead code
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 520a328e5a6c0185b6735ff68c0e166ba9a4d36d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:28:37 2015 +1100 src/superio/smsc/lpc47m10x/superio.c: Remove dead code Remove dead debug code, we have superiotool for this reason. Restructure file to be consistent with other superio's thereby avoiding forward declarations of functions. Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/8082 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8082 for details. -gerrit

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coreboot-gerrit January 2015