coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

1 participants
1236 discussions

Patch set updated for coreboot: a60d0b8 superio/smsc/lpc47b397: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8079 -gerrit commit a60d0b8322020948088c1bb87ef4a5b9dd175b7a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:41:27 2015 +1100 superio/smsc/lpc47b397: Use link-time symbols over .c inclusion Change-Id: I344f2a8d2ae5f6f3fa04d79773ee1c59de69e425 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/sunw/ultra40/Kconfig | 1 + src/mainboard/sunw/ultra40/romstage.c | 2 +- src/mainboard/tyan/s2895/romstage.c | 2 +- src/superio/smsc/lpc47b397/Makefile.inc | 1 + src/superio/smsc/lpc47b397/early_serial.c | 4 +++- src/superio/smsc/lpc47b397/lpc47b397.h | 11 ++++++++--- 6 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 3fb5591..8f3ff2a 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 7c112da..99d0dfb 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -16,7 +16,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/smsc/lpc47b397/early_serial.c" +#include <superio/smsc/lpc47b397/lpc47b397.h> #include "cpu/x86/bist.h" #include "superio/smsc/lpc47b397/early_gpio.c" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 4f0e552..0e42f76 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -15,7 +15,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/smsc/lpc47b397/early_serial.c" +#include <superio/smsc/lpc47b397/lpc47b397.h> #include "superio/smsc/lpc47b397/early_gpio.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc index 30101cf..d25febc 100644 --- a/src/superio/smsc/lpc47b397/Makefile.inc +++ b/src/superio/smsc/lpc47b397/Makefile.inc @@ -20,4 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 953cd4b..047145e 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -21,6 +21,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "lpc47b397.h" static void pnp_enter_conf_state(pnp_devfn_t dev) @@ -35,7 +37,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) outb(0xaa, port); } -static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b397/lpc47b397.h b/src/superio/smsc/lpc47b397/lpc47b397.h index 310084a..996b7cd 100644 --- a/src/superio/smsc/lpc47b397/lpc47b397.h +++ b/src/superio/smsc/lpc47b397/lpc47b397.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47B397_LPC47B397_H -#define SUPERIO_SMSC_LPC47B397_LPC47B397_H +#ifndef SUPERIO_SMSC_LPC47B397_H +#define SUPERIO_SMSC_LPC47B397_H #define LPC47B397_FDC 0 /* Floppy */ #define LPC47B397_PP 3 /* Parallel Port */ @@ -31,4 +31,9 @@ #define LPC47B397_HWM 8 /* HW Monitor */ #define LPC47B397_RT 10 /* Runtime reg*/ -#endif +#include <arch/io.h> +#include <stdint.h> + +void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47B397_H */

1 0

Patch set updated for coreboot: 1d266ec superio/nsc/pc87417: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8078 -gerrit commit 1d266ec737d7c11e04b840225c9ab65f68292b8f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:17:54 2015 +1100 superio/nsc/pc87417: Use link-time symbols over .c inclusion Change-Id: I2efb7ab4b69bcd127b2faf54277dc229c9dcf3ea Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/superio/nsc/pc87417/Makefile.inc | 2 ++ src/superio/nsc/pc87417/early_init.c | 8 ++++---- src/superio/nsc/pc87417/early_serial.c | 8 ++------ src/superio/nsc/pc87417/pc87417.h | 12 +++++++----- src/superio/nsc/pc87417/superio.c | 1 - 9 files changed, 19 insertions(+), 20 deletions(-) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 03cdc1d..a97c3b8 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -14,7 +14,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9deaaba..474f273 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -41,7 +41,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index a2269a6..9e10360 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -47,7 +47,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index aabc826..bd82436 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -40,7 +40,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/superio/nsc/pc87417/Makefile.inc b/src/superio/nsc/pc87417/Makefile.inc index 8062a79..58d4eb5 100644 --- a/src/superio/nsc/pc87417/Makefile.inc +++ b/src/superio/nsc/pc87417/Makefile.inc @@ -20,4 +20,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c +romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87417) += superio.c diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index 42f8cd1..af7536b 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -21,19 +21,19 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87417.h" -static void pc87417_disable_dev(pnp_devfn_t dev) +void pc87417_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) +void pc87417_enable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 42ba941..69a7739 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -21,6 +21,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87417.h" void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) @@ -30,9 +32,3 @@ void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } - -void pc87417_enable_dev(pnp_devfn_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index e7d5413..4a0131b 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC87417_PC87417_H -#define SUPERIO_NSC_PC87417_PC87417_H +#ifndef SUPERIO_NSC_PC87417_H +#define SUPERIO_NSC_PC87417_H #define PC87417_FDC 0x00 /* Floppy */ #define PC87417_PP 0x01 /* Parallel Port */ @@ -114,9 +114,11 @@ #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 -#if defined(__PRE_RAM__) +#include <arch/io.h> +#include <stdint.h> + void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); +void pc87417_disable_dev(pnp_devfn_t dev); void pc87417_enable_dev(pnp_devfn_t dev); -#endif -#endif +#endif /* SUPERIO_NSC_PC87417_H */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 2295f29..15bd0ea 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -31,7 +31,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

1 0

Patch set updated for coreboot: a8993b6 superio/smsc/lpc47m10x: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8080 -gerrit commit a8993b639905bb03245c5bd5f8e502d2b75b415a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:24:14 2015 +1100 superio/smsc/lpc47m10x: Use link-time symbols over .c inclusion Change-Id: I4a3639c05231eacd016ec3873330f9844befd448 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aopen/dxplplusu/romstage.c | 3 +-- src/superio/smsc/lpc47m10x/Makefile.inc | 1 + src/superio/smsc/lpc47m10x/early_serial.c | 4 +++- src/superio/smsc/lpc47m10x/lpc47m10x.h | 11 ++++++++--- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 86470b3..8bb179a 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -29,8 +29,7 @@ #include "northbridge/intel/e7505/raminit.h" #include <device/pnp_def.h> -#include "superio/smsc/lpc47m10x/early_serial.c" - +#include <superio/smsc/lpc47m10x/lpc47m10x.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc index c5dd310..876cb0c 100644 --- a/src/superio/smsc/lpc47m10x/Makefile.inc +++ b/src/superio/smsc/lpc47m10x/Makefile.inc @@ -22,4 +22,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 1174120..59a53f2 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "lpc47m10x.h" static void pnp_enter_conf_state(pnp_devfn_t dev) @@ -40,7 +42,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index e851048..9814c8e 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47M10X_LPC47M10X_H -#define SUPERIO_SMSC_LPC47M10X_LPC47M10X_H +#ifndef SUPERIO_SMSC_LPC47M10X_H +#define SUPERIO_SMSC_LPC47M10X_H #define LPC47M10X2_FDC 0 /* Floppy */ #define LPC47M10X2_PP 3 /* Parallel Port */ @@ -34,4 +34,9 @@ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F -#endif +#include <arch/io.h> +#include <stdint.h> + +void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47M10X_H */

1 0

Patch set updated for coreboot: 688ccca superio/smsc/lpc47b272: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8081 -gerrit commit 688cccaf3695d8b9844efae34aa976c58aeb7478 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:34:03 2015 +1100 superio/smsc/lpc47b272: Use link-time symbols over .c inclusion Change-Id: Id3d5f2a120c0a933c031102f206829305da20f0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/mew-vm/romstage.c | 2 +- src/superio/smsc/lpc47b272/Makefile.inc | 1 + src/superio/smsc/lpc47b272/early_serial.c | 4 +++- src/superio/smsc/lpc47b272/lpc47b272.h | 11 ++++++++--- 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/src/mainboard/asus/mew-vm/romstage.c b/src/mainboard/asus/mew-vm/romstage.c index d2d4186..3c67af3 100644 --- a/src/mainboard/asus/mew-vm/romstage.c +++ b/src/mainboard/asus/mew-vm/romstage.c @@ -24,7 +24,7 @@ #include <device/pnp_def.h> #include <stdlib.h> #include <console/console.h> -#include "superio/smsc/lpc47b272/early_serial.c" +#include <superio/smsc/lpc47b272/lpc47b272.h> #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" #include "southbridge/intel/i82801ax/i82801ax.h" diff --git a/src/superio/smsc/lpc47b272/Makefile.inc b/src/superio/smsc/lpc47b272/Makefile.inc index 680e937..8102229 100644 --- a/src/superio/smsc/lpc47b272/Makefile.inc +++ b/src/superio/smsc/lpc47b272/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index 3624df2..88afca5 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -21,6 +21,8 @@ /* Pre-RAM driver for SMSC LPC47B272 Super I/O chip. */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "lpc47b272.h" static void pnp_enter_conf_state(pnp_devfn_t dev) @@ -42,7 +44,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b272/lpc47b272.h b/src/superio/smsc/lpc47b272/lpc47b272.h index cbfdb13..a311708 100644 --- a/src/superio/smsc/lpc47b272/lpc47b272.h +++ b/src/superio/smsc/lpc47b272/lpc47b272.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47B272_LPC47B272_H -#define SUPERIO_SMSC_LPC47B272_LPC47B272_H +#ifndef SUPERIO_SMSC_LPC47B272_H +#define SUPERIO_SMSC_LPC47B272_H #define LPC47B272_FDC 0 /* Floppy */ #define LPC47B272_PP 3 /* Parallel Port */ @@ -30,4 +30,9 @@ #define LPC47B272_MAX_CONFIG_REGISTER 0x5F -#endif +#include <arch/io.h> +#include <stdint.h> + +void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47B272_H */

1 0

Patch set updated for coreboot: 3e523bf src/superio/smsc/lpc47m10x/superio.c: Remove dead code
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8082 -gerrit commit 3e523bf17f14e376791ffedd223bf3597851030b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:28:37 2015 +1100 src/superio/smsc/lpc47m10x/superio.c: Remove dead code Remove dead debug code, we have superiotool for this reason. Restructure file to be consistent with other superio's thereby avoiding forward declarations of functions. Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/smsc/lpc47m10x/superio.c | 90 +++++++++--------------------------- 1 file changed, 22 insertions(+), 68 deletions(-) diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index 8530056..4cd9a8b 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -33,15 +33,25 @@ #include <stdlib.h> #include "lpc47m10x.h" -/* Forward declarations */ -static void enable_dev(struct device *dev); -static void lpc47m10x_init(struct device *dev); -// static void dump_pnp_device(struct device *dev); +/** + * Initialize the specified Super I/O device. + * + * Devices other than COM ports and the keyboard controller are ignored. + * For COM ports, we configure the baud rate. + * + * @param dev Pointer to structure describing a Super I/O device. + */ +static void lpc47m10x_init(struct device *dev) +{ + if (!dev->enabled) + return; -struct chip_operations superio_smsc_lpc47m10x_ops = { - CHIP_NAME("SMSC LPC47M10x Super I/O") - .enable_dev = enable_dev -}; + switch(dev->path.pnp.device) { + case LPC47M10X2_KBC: + pc_keyboard_init(); + break; + } +} static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -73,63 +83,7 @@ static void enable_dev(struct device *dev) pnp_dev_info); } -/** - * Initialize the specified Super I/O device. - * - * Devices other than COM ports and the keyboard controller are ignored. - * For COM ports, we configure the baud rate. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void lpc47m10x_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch(dev->path.pnp.device) { - case LPC47M10X2_KBC: - pc_keyboard_init(); - break; - } -} - -#if 0 -/** - * Print the values of all of the LPC47M10X2's configuration registers. - * - * NOTE: The LPC47M10X2 must be in config mode when this function is called. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void dump_pnp_device(struct device *dev) -{ - int i; - print_debug("\n"); - - for (i = 0; i <= LPC47M10X2_MAX_CONFIG_REGISTER; i++) { - u8 register_value; - - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - - /* - * Skip over 'register' that would cause exit from - * configuration mode. - */ - if (i == 0xaa) - register_value = 0xaa; - else - register_value = pnp_read_config(dev, i); - - print_debug_char(' '); - print_debug_hex8(register_value); - if ((i & 0x0f) == 0x0f) - print_debug("\n"); - } - - print_debug("\n"); -} -#endif +struct chip_operations superio_smsc_lpc47m10x_ops = { + CHIP_NAME("SMSC LPC47M10x Super I/O") + .enable_dev = enable_dev +};

1 0

Patch set updated for coreboot: 649b4c5 superio/smsc/lpc47b272/superio.c: Remove dead code
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8083 -gerrit commit 649b4c58381de9ba9b763681522591b4ac270ec5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:35:43 2015 +1100 superio/smsc/lpc47b272/superio.c: Remove dead code Remove dead debug code, we have superiotool for this reason. Restructure file to be consistent with other superio's thereby avoiding forward declarations of functions. Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/smsc/lpc47b272/superio.c | 91 +++++++++--------------------------- 1 file changed, 23 insertions(+), 68 deletions(-) diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 4fac022..ef00cc7 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -34,15 +34,26 @@ #include <stdlib.h> #include "lpc47b272.h" -/* Forward declarations */ -static void enable_dev(struct device *dev); -static void lpc47b272_init(struct device *dev); -// static void dump_pnp_device(struct device *dev); +/** + * Initialize the specified Super I/O device. + * + * Devices other than COM ports and the keyboard controller are ignored. + * For COM ports, we configure the baud rate. + * + * @param dev Pointer to structure describing a Super I/O device. + */ +static void lpc47b272_init(struct device *dev) +{ -struct chip_operations superio_smsc_lpc47b272_ops = { - CHIP_NAME("SMSC LPC47B272 Super I/O") - .enable_dev = enable_dev -}; + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + case LPC47B272_KBC: + pc_keyboard_init(); + break; + } +} static struct device_operations ops = { .read_resources = pnp_read_resources, @@ -74,63 +85,7 @@ static void enable_dev(struct device *dev) pnp_dev_info); } -/** - * Initialize the specified Super I/O device. - * - * Devices other than COM ports and the keyboard controller are ignored. - * For COM ports, we configure the baud rate. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void lpc47b272_init(struct device *dev) -{ - - if (!dev->enabled) - return; - - switch(dev->path.pnp.device) { - case LPC47B272_KBC: - pc_keyboard_init(); - break; - } -} - -#if 0 -/** - * Print the values of all of the LPC47B272's configuration registers. - * - * NOTE: The LPC47B272 must be in config mode when this function is called. - * - * @param dev Pointer to structure describing a Super I/O device. - */ -static void dump_pnp_device(struct device *dev) -{ - int i; - print_debug("\n"); - - for (i = 0; i <= LPC47B272_MAX_CONFIG_REGISTER; i++) { - u8 register_value; - - if ((i & 0x0f) == 0) { - print_debug_hex8(i); - print_debug_char(':'); - } - - /* - * Skip over 'register' that would cause exit from - * configuration mode. - */ - if (i == 0xaa) - register_value = 0xaa; - else - register_value = pnp_read_config(dev, i); - - print_debug_char(' '); - print_debug_hex8(register_value); - if ((i & 0x0f) == 0x0f) - print_debug("\n"); - } - - print_debug("\n"); -} -#endif +struct chip_operations superio_smsc_lpc47b272_ops = { + CHIP_NAME("SMSC LPC47B272 Super I/O") + .enable_dev = enable_dev +};

1 0

Patch set updated for coreboot: ea0e207 superio/smsc/lpc47n207: What the even..***.. do I write..
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8084 -gerrit commit ea0e207cbd9245b2d797660886e78d29a9d9344b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 17:21:52 2015 +1100 superio/smsc/lpc47n207: What the even..***.. do I write.. Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/samsung/lumpy/Kconfig | 1 + src/mainboard/samsung/lumpy/romstage.c | 1 - src/mainboard/samsung/stumpy/Kconfig | 1 + src/mainboard/samsung/stumpy/romstage.c | 1 - src/superio/smsc/Kconfig | 2 ++ src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/lpc47n207/Makefile.inc | 21 +++++++++++++++++++++ src/superio/smsc/lpc47n207/early_serial.c | 5 +++++ src/superio/smsc/lpc47n207/lpc47n207.h | 11 +++++++---- 9 files changed, 38 insertions(+), 6 deletions(-) diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index baf0eee..768875a 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_SMSC_MEC1308 + select SUPERIO_SMSC_LPC47N207 select DRIVERS_GENERIC_IOAPIC select INTEL_INT15 select HAVE_MRC diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index b356fa8..8568f84 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -45,7 +45,6 @@ #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> -#include "superio/smsc/lpc47n207/early_serial.c" #endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index 17484a9..e249c40 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_SANDYBRIDGE select SOUTHBRIDGE_INTEL_BD82X6X select SUPERIO_ITE_IT8772F + select SUPERIO_SMSC_LPC47N207 select HAVE_MRC select INTEL_INT15 diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 1462132..2ed185b 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -45,7 +45,6 @@ #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO #include <superio/smsc/lpc47n207/lpc47n207.h> -#include "superio/smsc/lpc47n207/early_serial.c" #endif #if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 6aaa112..34bc60c 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -30,6 +30,8 @@ config SUPERIO_SMSC_LPC47M10X bool config SUPERIO_SMSC_LPC47M15X bool +config SUPERIO_SMSC_LPC47N207 + bool config SUPERIO_SMSC_LPC47N217 bool config SUPERIO_SMSC_LPC47N227 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index a89b6ac..caa2c72 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -24,6 +24,7 @@ subdirs-y += lpc47b272 subdirs-y += lpc47b397 subdirs-y += lpc47m10x subdirs-y += lpc47m15x +subdirs-y += lpc47n207 subdirs-y += lpc47n217 subdirs-y += lpc47n227 subdirs-y += sio10n268 diff --git a/src/superio/smsc/lpc47n207/Makefile.inc b/src/superio/smsc/lpc47n207/Makefile.inc new file mode 100644 index 0000000..08e1387 --- /dev/null +++ b/src/superio/smsc/lpc47n207/Makefile.inc @@ -0,0 +1,21 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-$(CONFIG_SUPERIO_SMSC_LPC47N207) += early_serial.c diff --git a/src/superio/smsc/lpc47n207/early_serial.c b/src/superio/smsc/lpc47n207/early_serial.c index e2ae49d..fedc27a 100644 --- a/src/superio/smsc/lpc47n207/early_serial.c +++ b/src/superio/smsc/lpc47n207/early_serial.c @@ -17,6 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "lpc47n207.h" + /* * This code tries to discover the SMSC LPC47N207 superio chip which can be * connected over an LPC dongle. The chip could be bootstrap mapped to one of diff --git a/src/superio/smsc/lpc47n207/lpc47n207.h b/src/superio/smsc/lpc47n207/lpc47n207.h index 69689a4..a122465 100644 --- a/src/superio/smsc/lpc47n207/lpc47n207.h +++ b/src/superio/smsc/lpc47n207/lpc47n207.h @@ -17,9 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47N207_LPC47N207_H -#define SUPERIO_SMSC_LPC47N207_LPC47N207_H +#ifndef SUPERIO_SMSC_LPC47N207_H +#define SUPERIO_SMSC_LPC47N207_H -extern void try_enabling_LPC47N207_uart(void); +#include <arch/io.h> +#include <stdint.h> -#endif +void try_enabling_LPC47N207_uart(void); + +#endif /* SUPERIO_SMSC_LPC47N207_H */

1 0

Patch set updated for coreboot: 8257de2 superio/smsc/lpc47b397: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8079 -gerrit commit 8257de28285ccf97cf2888b623e7345f1857228e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:41:27 2015 +1100 superio/smsc/lpc47b397: Use link-time symbols over .c inclusion Change-Id: I344f2a8d2ae5f6f3fa04d79773ee1c59de69e425 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/sunw/ultra40/Kconfig | 1 + src/mainboard/sunw/ultra40/romstage.c | 2 +- src/mainboard/tyan/s2895/romstage.c | 2 +- src/superio/smsc/lpc47b397/Makefile.inc | 1 + src/superio/smsc/lpc47b397/early_serial.c | 4 +++- src/superio/smsc/lpc47b397/lpc47b397.h | 11 ++++++++--- 6 files changed, 15 insertions(+), 6 deletions(-) diff --git a/src/mainboard/sunw/ultra40/Kconfig b/src/mainboard/sunw/ultra40/Kconfig index 3fb5591..8f3ff2a 100644 --- a/src/mainboard/sunw/ultra40/Kconfig +++ b/src/mainboard/sunw/ultra40/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 select SOUTHBRIDGE_NVIDIA_CK804 + select SUPERIO_SMSC_LPC47B397 select SUPERIO_SMSC_LPC47M10X select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 7c112da..99d0dfb 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -16,7 +16,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/smsc/lpc47b397/early_serial.c" +#include <superio/smsc/lpc47b397/lpc47b397.h> #include "cpu/x86/bist.h" #include "superio/smsc/lpc47b397/early_gpio.c" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 4f0e552..0e42f76 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -15,7 +15,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/smsc/lpc47b397/early_serial.c" +#include <superio/smsc/lpc47b397/lpc47b397.h> #include "superio/smsc/lpc47b397/early_gpio.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" diff --git a/src/superio/smsc/lpc47b397/Makefile.inc b/src/superio/smsc/lpc47b397/Makefile.inc index 30101cf..d25febc 100644 --- a/src/superio/smsc/lpc47b397/Makefile.inc +++ b/src/superio/smsc/lpc47b397/Makefile.inc @@ -20,4 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 953cd4b..047145e 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -21,6 +21,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "lpc47b397.h" static void pnp_enter_conf_state(pnp_devfn_t dev) @@ -35,7 +37,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) outb(0xaa, port); } -static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b397/lpc47b397.h b/src/superio/smsc/lpc47b397/lpc47b397.h index 310084a..996b7cd 100644 --- a/src/superio/smsc/lpc47b397/lpc47b397.h +++ b/src/superio/smsc/lpc47b397/lpc47b397.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47B397_LPC47B397_H -#define SUPERIO_SMSC_LPC47B397_LPC47B397_H +#ifndef SUPERIO_SMSC_LPC47B397_H +#define SUPERIO_SMSC_LPC47B397_H #define LPC47B397_FDC 0 /* Floppy */ #define LPC47B397_PP 3 /* Parallel Port */ @@ -31,4 +31,9 @@ #define LPC47B397_HWM 8 /* HW Monitor */ #define LPC47B397_RT 10 /* Runtime reg*/ -#endif +#include <arch/io.h> +#include <stdint.h> + +void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47B397_H */

1 0

Patch set updated for coreboot: 2654051 superio/nsc/pc87417: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8078 -gerrit commit 2654051822172584e1859fc94eaae3c797dcd38a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:17:54 2015 +1100 superio/nsc/pc87417: Use link-time symbols over .c inclusion Change-Id: I2efb7ab4b69bcd127b2faf54277dc229c9dcf3ea Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/superio/nsc/pc87417/Makefile.inc | 2 ++ src/superio/nsc/pc87417/early_init.c | 6 ++++-- src/superio/nsc/pc87417/early_serial.c | 2 ++ src/superio/nsc/pc87417/pc87417.h | 12 +++++++----- src/superio/nsc/pc87417/superio.c | 1 - 9 files changed, 19 insertions(+), 12 deletions(-) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 03cdc1d..a97c3b8 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -14,7 +14,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9deaaba..474f273 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -41,7 +41,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index a2269a6..9e10360 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -47,7 +47,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index aabc826..bd82436 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -40,7 +40,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/superio/nsc/pc87417/Makefile.inc b/src/superio/nsc/pc87417/Makefile.inc index 8062a79..58d4eb5 100644 --- a/src/superio/nsc/pc87417/Makefile.inc +++ b/src/superio/nsc/pc87417/Makefile.inc @@ -20,4 +20,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c +romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87417) += superio.c diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index 42f8cd1..5f9564f 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -21,15 +21,17 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87417.h" -static void pc87417_disable_dev(pnp_devfn_t dev) +void pc87417_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) +void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 42ba941..8d554c7 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -21,6 +21,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87417.h" void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index e7d5413..4a0131b 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC87417_PC87417_H -#define SUPERIO_NSC_PC87417_PC87417_H +#ifndef SUPERIO_NSC_PC87417_H +#define SUPERIO_NSC_PC87417_H #define PC87417_FDC 0x00 /* Floppy */ #define PC87417_PP 0x01 /* Parallel Port */ @@ -114,9 +114,11 @@ #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 -#if defined(__PRE_RAM__) +#include <arch/io.h> +#include <stdint.h> + void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); +void pc87417_disable_dev(pnp_devfn_t dev); void pc87417_enable_dev(pnp_devfn_t dev); -#endif -#endif +#endif /* SUPERIO_NSC_PC87417_H */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 2295f29..15bd0ea 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -31,7 +31,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

1 0

Patch set updated for coreboot: e20e40a superio/smsc/lpc47m10x: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8080 -gerrit commit e20e40acfaa6a5d380fd0826681d42823b85ddd7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:24:14 2015 +1100 superio/smsc/lpc47m10x: Use link-time symbols over .c inclusion Change-Id: I4a3639c05231eacd016ec3873330f9844befd448 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/aopen/dxplplusu/romstage.c | 3 +-- src/superio/smsc/lpc47m10x/Makefile.inc | 1 + src/superio/smsc/lpc47m10x/early_serial.c | 4 +++- src/superio/smsc/lpc47m10x/lpc47m10x.h | 11 ++++++++--- 4 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 86470b3..8bb179a 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -29,8 +29,7 @@ #include "northbridge/intel/e7505/raminit.h" #include <device/pnp_def.h> -#include "superio/smsc/lpc47m10x/early_serial.c" - +#include <superio/smsc/lpc47m10x/lpc47m10x.h> #define SERIAL_DEV PNP_DEV(0x2e, LPC47M10X2_SP1) diff --git a/src/superio/smsc/lpc47m10x/Makefile.inc b/src/superio/smsc/lpc47m10x/Makefile.inc index c5dd310..876cb0c 100644 --- a/src/superio/smsc/lpc47m10x/Makefile.inc +++ b/src/superio/smsc/lpc47m10x/Makefile.inc @@ -22,4 +22,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += early_serial.c ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index 1174120..59a53f2 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "lpc47m10x.h" static void pnp_enter_conf_state(pnp_devfn_t dev) @@ -40,7 +42,7 @@ static void pnp_exit_conf_state(pnp_devfn_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) +void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/lpc47m10x.h b/src/superio/smsc/lpc47m10x/lpc47m10x.h index e851048..9814c8e 100644 --- a/src/superio/smsc/lpc47m10x/lpc47m10x.h +++ b/src/superio/smsc/lpc47m10x/lpc47m10x.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_SMSC_LPC47M10X_LPC47M10X_H -#define SUPERIO_SMSC_LPC47M10X_LPC47M10X_H +#ifndef SUPERIO_SMSC_LPC47M10X_H +#define SUPERIO_SMSC_LPC47M10X_H #define LPC47M10X2_FDC 0 /* Floppy */ #define LPC47M10X2_PP 3 /* Parallel Port */ @@ -34,4 +34,9 @@ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F -#endif +#include <arch/io.h> +#include <stdint.h> + +void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_SMSC_LPC47M10X_H */

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2015