coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: c7f4f05 superio/nsc/pc87417: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8078 -gerrit commit c7f4f0503ebf7c161e50b6bcfc3e76ebb05472a3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:17:54 2015 +1100 superio/nsc/pc87417: Use link-time symbols over .c inclusion Change-Id: I2efb7ab4b69bcd127b2faf54277dc229c9dcf3ea Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/broadcom/blast/romstage.c | 2 +- src/mainboard/hp/dl145_g3/romstage.c | 2 +- src/mainboard/hp/dl165_g6_fam10/romstage.c | 2 +- src/mainboard/msi/ms9185/romstage.c | 2 +- src/superio/nsc/pc87417/Makefile.inc | 2 ++ src/superio/nsc/pc87417/early_init.c | 2 ++ src/superio/nsc/pc87417/early_serial.c | 2 ++ src/superio/nsc/pc87417/pc87417.h | 11 ++++++----- src/superio/nsc/pc87417/superio.c | 1 - 9 files changed, 16 insertions(+), 10 deletions(-) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 03cdc1d..a97c3b8 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -14,7 +14,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 9deaaba..474f273 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -41,7 +41,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include <superio/serverengines/pilot/pilot.h> -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index a2269a6..9e10360 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -47,7 +47,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdfam10/reset_test.c" #include <superio/serverengines/pilot/pilot.h> -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index aabc826..bd82436 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -40,7 +40,7 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87417/early_serial.c" +#include <superio/nsc/pc87417/pc87417.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/broadcom/bcm5785/early_setup.c" diff --git a/src/superio/nsc/pc87417/Makefile.inc b/src/superio/nsc/pc87417/Makefile.inc index 8062a79..58d4eb5 100644 --- a/src/superio/nsc/pc87417/Makefile.inc +++ b/src/superio/nsc/pc87417/Makefile.inc @@ -20,4 +20,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_init.c +romstage-$(CONFIG_SUPERIO_NSC_PC87417) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87417) += superio.c diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index 42f8cd1..a7de472 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -21,6 +21,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87417.h" static void pc87417_disable_dev(pnp_devfn_t dev) diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 42ba941..8d554c7 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -21,6 +21,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87417.h" void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index e7d5413..b3bcb0b 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC87417_PC87417_H -#define SUPERIO_NSC_PC87417_PC87417_H +#ifndef SUPERIO_NSC_PC87417_H +#define SUPERIO_NSC_PC87417_H #define PC87417_FDC 0x00 /* Floppy */ #define PC87417_PP 0x01 /* Parallel Port */ @@ -114,9 +114,10 @@ #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 -#if defined(__PRE_RAM__) +#include <arch/io.h> +#include <stdint.h> + void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); void pc87417_enable_dev(pnp_devfn_t dev); -#endif -#endif +#endif /* SUPERIO_NSC_PC87417_H */ diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 2295f29..15bd0ea 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -31,7 +31,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

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New patch to review for coreboot: 20908a4 superio/nsc/pc87366: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8077 -gerrit commit 20908a48b3dae8f66af8b5415a20c13a1374d86d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:10:32 2015 +1100 superio/nsc/pc87366: Use link-time symbols over .c inclusion Change-Id: Id156ca3c9a14c5bcc4d6cdb8434ca8efdac3139a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/ibm/e325/romstage.c | 2 +- src/mainboard/ibm/e326/romstage.c | 2 +- src/superio/nsc/pc87366/Makefile.inc | 1 + src/superio/nsc/pc87366/early_serial.c | 4 +++- src/superio/nsc/pc87366/pc87366.h | 11 ++++++++--- src/superio/nsc/pc87366/superio.c | 1 - 6 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index b44668a..4e1e925 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -13,7 +13,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87366/early_serial.c" +#include <superio/nsc/pc87366/pc87366.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index c703b7a..2ac90ab 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -13,7 +13,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87366/early_serial.c" +#include <superio/nsc/pc87366/pc87366.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" diff --git a/src/superio/nsc/pc87366/Makefile.inc b/src/superio/nsc/pc87366/Makefile.inc index 451f944..37ea1d8 100644 --- a/src/superio/nsc/pc87366/Makefile.inc +++ b/src/superio/nsc/pc87366/Makefile.inc @@ -19,4 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC87366) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e663df6..6cbef41 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -20,9 +20,11 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87366.h" -static void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) +void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87366/pc87366.h b/src/superio/nsc/pc87366/pc87366.h index 8a1ede7..dea8ddf 100644 --- a/src/superio/nsc/pc87366/pc87366.h +++ b/src/superio/nsc/pc87366/pc87366.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC87366_PC87366_H -#define SUPERIO_NSC_PC87366_PC87366_H +#ifndef SUPERIO_NSC_PC87366_H +#define SUPERIO_NSC_PC87366_H #define PC87366_FDC 0x00 /* Floppy */ #define PC87366_PP 0x01 /* Parallel port */ @@ -38,4 +38,9 @@ #define PC87366_VLM 0x0D #define PC87366_TMS 0x0E -#endif +#include <arch/io.h> +#include <stdint.h> + +void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_NSC_PC87366_H */ diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index 9cfba04..9bf14fc 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -30,7 +30,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

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New patch to review for coreboot: 055f501 superio/nsc/pc97317: Use link-time symbols over .c inclusion
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8076 -gerrit commit 055f501ac1aeacff9011c8815086e7c5a5f8e546 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 16:05:59 2015 +1100 superio/nsc/pc97317: Use link-time symbols over .c inclusion Change-Id: Ia45bc7a880d0dab57c56a0452858cd26626f09df Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/compaq/deskpro_en_sff_p600/romstage.c | 2 +- src/superio/nsc/pc97317/Makefile.inc | 1 + src/superio/nsc/pc97317/early_serial.c | 4 +++- src/superio/nsc/pc97317/pc97317.h | 11 ++++++++--- src/superio/nsc/pc97317/superio.c | 1 - 5 files changed, 13 insertions(+), 6 deletions(-) diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c index feccfb7..cfda5db 100644 --- a/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c +++ b/src/mainboard/compaq/deskpro_en_sff_p600/romstage.c @@ -30,7 +30,7 @@ #include "lib/delay.c" #include "cpu/x86/bist.h" /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ -#include "superio/nsc/pc97317/early_serial.c" +#include <superio/nsc/pc97317/pc97317.h> #include <lib.h> /* FIXME: This should be PC97307 (but it's buggy at the moment)! */ diff --git a/src/superio/nsc/pc97317/Makefile.inc b/src/superio/nsc/pc97317/Makefile.inc index c8f354c..6d729cf 100644 --- a/src/superio/nsc/pc97317/Makefile.inc +++ b/src/superio/nsc/pc97317/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC97317) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index ad43010..f9bc69e 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -19,13 +19,15 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc97317.h" #define PM_DEV PNP_DEV(0x2e, PC97317_PM) #define PM_BASE 0xe8 /* The PC97317 needs clocks to be set up before the serial port will operate. */ -static void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) +void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) { /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); diff --git a/src/superio/nsc/pc97317/pc97317.h b/src/superio/nsc/pc97317/pc97317.h index 8b57fc9..6938cb4 100644 --- a/src/superio/nsc/pc97317/pc97317.h +++ b/src/superio/nsc/pc97317/pc97317.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC97317_PC97317_H -#define SUPERIO_NSC_PC97317_PC97317_H +#ifndef SUPERIO_NSC_PC97317_H +#define SUPERIO_NSC_PC97317_H #define PC97317_KBCK 0x00 /* Keyboard */ #define PC97317_KBCM 0x01 /* Mouse */ @@ -31,4 +31,9 @@ #define PC97317_GPIO 0x07 #define PC97317_PM 0x08 /* Power Management */ -#endif +#include <arch/io.h> +#include <stdint.h> + +void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_NSC_PC97317_H */ diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index b73dc7b..25b6162 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -28,7 +28,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

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Patch set updated for coreboot: f5ad5d8 superio/intel/i3100: Use link-time symbol over .c includes
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8054 -gerrit commit f5ad5d8120725d8ba48957bb1e5acc175d39a13a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 04:25:38 2015 +1100 superio/intel/i3100: Use link-time symbol over .c includes Change-Id: I83db9b189e672b0e1f25bc42b73639c375bea3e5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 1 - src/mainboard/intel/truxton/romstage.c | 1 - src/superio/intel/i3100/Makefile.inc | 1 + src/superio/intel/i3100/early_serial.c | 6 ++++-- src/superio/intel/i3100/i3100.h | 12 +++++++++--- 6 files changed, 15 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index c03c7d7..b41e0c5 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 4691b5c..959beab 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -30,7 +30,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" #include <superio/intel/i3100/i3100.h> -#include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index f750778..4c15f67 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -32,7 +32,6 @@ #include "northbridge/intel/i3100/raminit_ep80579.h" #include <superio/intel/i3100/i3100.h> #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" #include "lib/debug.c" // XXX #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index dedd419..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index 96bb550..0a3dc11 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "i3100.h" static void pnp_enter_ext_func_mode(pnp_devfn_t dev) @@ -38,14 +40,14 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) +void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) +void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..3f51a48 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H /* * Datasheet: @@ -61,4 +61,10 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +#include <arch/io.h> +#include <stdint.h> + +void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide); +void i3100_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */

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Patch set updated for coreboot: 96d692d superio/nsc/pc87360: Use link-time symbol over .c includes
by Edward O'Callaghan 04 Jan '15

04 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8053 -gerrit commit 96d692d62e80dc92f63b8dc21d23a17a12cb4c28 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 04:09:55 2015 +1100 superio/nsc/pc87360: Use link-time symbol over .c includes Change-Id: Id6d9efc93fdaff63dcaab50712ac9be35ccb42a7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/hp/e_vectra_p2706t/romstage.c | 2 +- src/superio/nsc/pc87360/Makefile.inc | 1 + src/superio/nsc/pc87360/early_serial.c | 4 +++- src/superio/nsc/pc87360/pc87360.h | 11 ++++++++--- src/superio/nsc/pc87360/superio.c | 1 - 6 files changed, 14 insertions(+), 7 deletions(-) diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 3c7eb58..137d3eb 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -12,7 +12,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87360/early_serial.c" +#include <superio/nsc/pc87360/pc87360.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index baa1995..f54e0e8 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include <console/console.h> /* TODO: It's a PC87364 actually! */ -#include "superio/nsc/pc87360/early_serial.c" +#include <superio/nsc/pc87360/pc87360.h> /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc index 579b14e..cb504f7 100644 --- a/src/superio/nsc/pc87360/Makefile.inc +++ b/src/superio/nsc/pc87360/Makefile.inc @@ -19,4 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC87360) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index 3deac3b..2790df2 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -20,9 +20,11 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "pc87360.h" -static void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) +void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h index 9843984..f006943 100644 --- a/src/superio/nsc/pc87360/pc87360.h +++ b/src/superio/nsc/pc87360/pc87360.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC87360_PC87360_H -#define SUPERIO_NSC_PC87360_PC87360_H +#ifndef SUPERIO_NSC_PC87360_H +#define SUPERIO_NSC_PC87360_H #define PC87360_FDC 0x00 /* Floppy */ #define PC87360_PP 0x01 /* Parallel port */ @@ -34,4 +34,9 @@ #define PC87360_FSCM 0x09 #define PC87360_WDT 0x0A -#endif +#include <arch/io.h> +#include <stdint.h> + +void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 58e0802..5706014 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -30,7 +30,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

1 0

New patch to review for coreboot: bf8fa4d atomic.h: Fix doxygen errors
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8075 -gerrit commit bf8fa4da34f9ba33640f9cca7bcd03be33a5210a Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:36:06 2014 -0700 atomic.h: Fix doxygen errors @v & @i need to be @param v & @param i add the @file command Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/arch/x86/include/arch/smp/atomic.h | 21 +++++++++++---------- src/include/smp/atomic.h | 22 +++++++++++++--------- 2 files changed, 24 insertions(+), 19 deletions(-) diff --git a/src/arch/x86/include/arch/smp/atomic.h b/src/arch/x86/include/arch/smp/atomic.h index 18bbae2..d7964e5 100644 --- a/src/arch/x86/include/arch/smp/atomic.h +++ b/src/arch/x86/include/arch/smp/atomic.h @@ -10,35 +10,36 @@ typedef struct { volatile int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } -/* +/** @file x86/include/arch/smp/atomic.h + * * Atomic operations that C can't guarantee us. Useful for * resource counting etc.. */ /** * atomic_read - read atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed + * Atomically reads the value of v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value + * @param v: pointer of type atomic_t + * @param i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed + * Atomically sets the value of v to i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_set(v,i) (((v)->counter) = (i)) /** * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed + * Atomically increments v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) @@ -51,9 +52,9 @@ static __inline__ __attribute__((always_inline)) void atomic_inc(atomic_t *v) /** * atomic_dec - decrement atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed + * Atomically decrements v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ static __inline__ __attribute__((always_inline)) void atomic_dec(atomic_t *v) diff --git a/src/include/smp/atomic.h b/src/include/smp/atomic.h index 44be4c5..bc50534 100644 --- a/src/include/smp/atomic.h +++ b/src/include/smp/atomic.h @@ -9,20 +9,24 @@ typedef struct { int counter; } atomic_t; #define ATOMIC_INIT(i) { (i) } /** + * @file include/smp/atomic.h + */ + +/** * atomic_read - read atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically reads the value of @v. Note that the guaranteed + * Atomically reads the value of v. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_read(v) ((v)->counter) /** * atomic_set - set atomic variable - * @v: pointer of type atomic_t - * @i: required value + * @param v: pointer of type atomic_t + * @param i: required value * - * Atomically sets the value of @v to @i. Note that the guaranteed + * Atomically sets the value of v to i. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_set(v,i) (((v)->counter) = (i)) @@ -30,9 +34,9 @@ typedef struct { int counter; } atomic_t; /** * atomic_inc - increment atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically increments @v by 1. Note that the guaranteed + * Atomically increments v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_inc(v) (((v)->counter)++) @@ -40,9 +44,9 @@ typedef struct { int counter; } atomic_t; /** * atomic_dec - decrement atomic variable - * @v: pointer of type atomic_t + * @param v: pointer of type atomic_t * - * Atomically decrements @v by 1. Note that the guaranteed + * Atomically decrements v by 1. Note that the guaranteed * useful range of an atomic_t is only 24 bits. */ #define atomic_dec(v) (((v)->counter)--)

1 0

New patch to review for coreboot: f14a4ca smihandler.c: Fix doxygen errors in southbridge_smi_handler
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8074 -gerrit commit f14a4ca4ed1a21a868195167aa07642b762199da Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:29:08 2014 -0700 smihandler.c: Fix doxygen errors in southbridge_smi_handler Correct the param to match the functions. Change-Id: Id002c549a6ba6a7be4fa5eee396769eaa2510698 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/southbridge/intel/bd82x6x/smihandler.c | 5 ++--- src/southbridge/intel/fsp_bd82x6x/smihandler.c | 3 ++- src/southbridge/intel/i82801dx/smihandler.c | 5 ++--- src/southbridge/intel/i82801gx/smihandler.c | 4 ++-- src/southbridge/intel/i82801ix/smihandler.c | 3 ++- src/southbridge/intel/ibexpeak/smihandler.c | 5 ++--- src/southbridge/intel/lynxpoint/smihandler.c | 3 --- src/southbridge/intel/sch/smihandler.c | 5 ++--- src/southbridge/via/vt8237r/smihandler.c | 3 ++- 9 files changed, 16 insertions(+), 20 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 1b8810f..45612d0 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -819,10 +819,9 @@ static smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save */ - void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { int i, dump = 0; diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 493a98e..c98e267 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -754,7 +754,8 @@ static smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 9b0c235..e5a3282 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -610,10 +610,9 @@ smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save */ - void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { int i, dump = 0; diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 4959c4d..e2505ce 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -610,8 +610,8 @@ smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 6d17621..45a09df 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -493,7 +493,8 @@ static u32 southbrigde_smi_mask_events(u32 smi_sts) /** * @brief Interrupt handler for SMI# * - * @param smm_revision revision of the smm state save map + * @param node + * @param *state_save */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index b6ca523..e2032ad 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -819,10 +819,9 @@ static smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save */ - void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { int i, dump = 0; diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 627c64f..bb13c98 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -517,10 +517,7 @@ static smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map */ - void southbridge_smi_handler(void) { int i; diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 5074138..57117c6 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -267,10 +267,9 @@ void southbridge_smi_set_eos(void) /** * @brief Interrupt handler for SMI# - * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save */ - void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) { // FIXME: the necessary magic isn't available yet. the code diff --git a/src/southbridge/via/vt8237r/smihandler.c b/src/southbridge/via/vt8237r/smihandler.c index 454636f..17cc37a 100644 --- a/src/southbridge/via/vt8237r/smihandler.c +++ b/src/southbridge/via/vt8237r/smihandler.c @@ -216,7 +216,8 @@ smi_handler_t southbridge_smi[32] = { /** * @brief Interrupt handler for SMI# * - * @param smm_revision revision of the smm state save map + * @param node + * @param state_save revision of the smm state save map */ void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save)

1 0

New patch to review for coreboot: c8ff6f7 PlatformGnbPcie.c: Fix Doxygen errors
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8073 -gerrit commit c8ff6f76c3fe38d5fa4f83b00f518c1277d97f07 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:24:07 2014 -0700 PlatformGnbPcie.c: Fix Doxygen errors Remove PeiServices param for OemInitEarly - it doesn't exist in the function. Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 1 - src/mainboard/amd/olivehill/PlatformGnbPcie.c | 1 - src/mainboard/amd/olivehillplus/PlatformGnbPcie.c | 1 - src/mainboard/amd/parmer/PlatformGnbPcie.c | 1 - src/mainboard/amd/persimmon/PlatformGnbPcie.c | 1 - src/mainboard/amd/south_station/PlatformGnbPcie.c | 1 - src/mainboard/amd/thatcher/PlatformGnbPcie.c | 1 - src/mainboard/amd/torpedo/PlatformGnbPcie.c | 1 - src/mainboard/amd/union_station/PlatformGnbPcie.c | 1 - src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 1 - src/mainboard/asrock/imb-a180/PlatformGnbPcie.c | 1 - src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 1 - src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c | 1 - src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c | 1 - src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c | 1 - src/mainboard/lenovo/g505s/PlatformGnbPcie.c | 1 - src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c | 1 - src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 1 - 19 files changed, 19 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index c3f9d9a..0ca6cbd 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -34,7 +34,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 1f5b750..f677597 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -116,7 +116,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c index 4e5382a..2ca1a8c 100644 --- a/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehillplus/PlatformGnbPcie.c @@ -110,7 +110,6 @@ const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 7ab91cd..cf57ffb 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -153,7 +153,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index c13a383..f2fe96b 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -33,7 +33,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index ca33c6b..8c24408 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -34,7 +34,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 5df2691..c642c78 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -159,7 +159,6 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index 893b48b..2c5990a 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -101,7 +101,6 @@ static const PCIe_COMPLEX_DESCRIPTOR Llano = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index 68ac8b6..ca34816 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index b591642..76e5ade 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c index da1910e..c807a6a 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c @@ -116,7 +116,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index f837925..762fe9f 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -135,7 +135,6 @@ static const PCIe_COMPLEX_DESCRIPTOR Trinity = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c index 3e86817..05d2844 100644 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c @@ -37,7 +37,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c index d48475c..66f7119 100644 --- a/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo2/PlatformGnbPcie.c @@ -110,7 +110,6 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c index 450bbd3..42e1985 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c @@ -152,7 +152,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index 66152a6..c82532f 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -34,7 +34,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * **/ diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c index 450bbd3..42e1985 100644 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c +++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c @@ -152,7 +152,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index ae79dc8..ceb7c38 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index 16d1b4a..ace22e7 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -38,7 +38,6 @@ * interface (call-out port) to provide a user hook opportunity * * Parameters: - * @param[in] **PeiServices * @param[in] *InitEarly * * @retval VOID

1 0

New patch to review for coreboot: 2ab8beb romstage.c: Fix doxygen errors
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8072 -gerrit commit 2ab8bebd66d2fcf4dd6efa977a5be56752cbe909 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:13:37 2014 -0700 romstage.c: Fix doxygen errors - Remove types from the param declarations. - list needed to be uppercase. Change-Id: I8b9ed78908e5d3e1d99e7ba2ea9013be109b8e27 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/advansus/a785e-i/romstage.c | 8 +++----- src/mainboard/amd/bimini_fam10/romstage.c | 8 +++----- src/mainboard/amd/mahogany_fam10/romstage.c | 8 +++----- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 8 +++----- src/mainboard/amd/tilapia_fam10/romstage.c | 8 +++----- src/mainboard/asus/m4a78-em/romstage.c | 8 +++----- src/mainboard/asus/m4a785-m/romstage.c | 8 +++----- src/mainboard/asus/m5a88-v/romstage.c | 8 +++----- src/mainboard/avalue/eax-785e/romstage.c | 8 +++----- src/mainboard/gigabyte/ma785gm/romstage.c | 8 +++----- src/mainboard/gigabyte/ma785gmt/romstage.c | 8 +++----- src/mainboard/gigabyte/ma78gm/romstage.c | 8 +++----- src/mainboard/hp/dl165_g6_fam10/romstage.c | 8 +++----- src/mainboard/iei/kino-780am2-fam10/romstage.c | 8 +++----- src/mainboard/jetway/pa78vm5/romstage.c | 8 +++----- src/mainboard/msi/ms9652_fam10/romstage.c | 8 +++----- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 8 +++----- src/mainboard/supermicro/h8qme_fam10/romstage.c | 8 +++----- src/mainboard/supermicro/h8scm_fam10/romstage.c | 8 +++----- src/mainboard/tyan/s2912_fam10/romstage.c | 8 +++----- 20 files changed, 60 insertions(+), 100 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 20cb703..1167bf5 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -234,11 +234,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index e6646f5..ef85df2 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -233,11 +233,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 13470e2..b940be0 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -232,11 +232,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 6388b42..df968c3 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -341,11 +341,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index f5ac2e0..c4ccc70 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -232,11 +232,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 0a03d59..9da8c6c 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -234,11 +234,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 84d2b97..dcf2b22 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -234,11 +234,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 4753bb0..a2fceda 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -231,11 +231,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 65f499b..36ce1de 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -235,11 +235,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index a0f9e76..75090d9 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -229,11 +229,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index a0f9e76..87778c6 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -229,11 +229,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index b9d27f7..b3ae326 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -232,11 +232,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index a2269a6..2eacff4 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -224,11 +224,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index e1230e5..2182a7e 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -232,11 +232,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 5121605..87af979 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -237,11 +237,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3993bae..722122d 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -250,11 +250,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index b393c34..08c7d2b 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -247,11 +247,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 24ecb5d..f46b2e6 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -311,11 +311,9 @@ post_code(0x40); * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index fdf49d8..f487d80 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -247,11 +247,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) { diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 6dae693..3e0f8f3 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -246,11 +246,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) * based on each device's unit count. * * Parameters: - * @param[in] u8 node = The node on which this chain is located - * @param[in] u8 link = The link on the host for this chain - * @param[out] u8** list = supply a pointer to a list - * @param[out] BOOL result = true to use a manual list - * false to initialize the link automatically + * @param[in] node = The node on which this chain is located + * @param[in] link = The link on the host for this chain + * @param[out] List = supply a pointer to a list */ BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) {

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New patch to review for coreboot: e017930 platform_cfg.h: Fixes for doxygen
by Martin Roth 04 Jan '15

04 Jan '15

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8071 -gerrit commit e0179305b5b7ba9c559c16d6c58fe77ec3cc2a05 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Mon Dec 29 22:08:15 2014 -0700 platform_cfg.h: Fixes for doxygen - Move @def BIOS_SIZE description to the next line - SB_GEN2 changed to SB_GPP_GEN2 - Move the SIO_HWM_BASE_ADDRESS description to the next line Change-Id: Ia3496b0108484f557627304553461932a100dfa5 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/advansus/a785e-i/platform_cfg.h | 8 +++++--- src/mainboard/amd/inagua/platform_cfg.h | 5 +++-- src/mainboard/amd/persimmon/platform_cfg.h | 5 +++-- src/mainboard/amd/south_station/platform_cfg.h | 5 +++-- src/mainboard/amd/torpedo/platform_cfg.h | 3 ++- src/mainboard/amd/union_station/platform_cfg.h | 5 +++-- src/mainboard/asrock/e350m1/platform_cfg.h | 8 +++++--- src/mainboard/asus/m5a88-v/platform_cfg.h | 8 +++++--- src/mainboard/avalue/eax-785e/platform_cfg.h | 8 +++++--- src/mainboard/gizmosphere/gizmo/platform_cfg.h | 5 +++-- src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h | 5 +++-- src/mainboard/lippert/frontrunner-af/platform_cfg.h | 5 +++-- src/mainboard/lippert/toucan-af/platform_cfg.h | 5 +++-- 13 files changed, 46 insertions(+), 29 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/platform_cfg.h b/src/mainboard/advansus/a785e-i/platform_cfg.h index 6944ab2..29f92d2 100644 --- a/src/mainboard/advansus/a785e-i/platform_cfg.h +++ b/src/mainboard/advansus/a785e-i/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/amd/inagua/platform_cfg.h b/src/mainboard/amd/inagua/platform_cfg.h index 4bd6a0e..9ca6d95 100644 --- a/src/mainboard/amd/inagua/platform_cfg.h +++ b/src/mainboard/amd/inagua/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/amd/persimmon/platform_cfg.h b/src/mainboard/amd/persimmon/platform_cfg.h index 5357370..f1b0fdc 100644 --- a/src/mainboard/amd/persimmon/platform_cfg.h +++ b/src/mainboard/amd/persimmon/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/amd/south_station/platform_cfg.h b/src/mainboard/amd/south_station/platform_cfg.h index 4bd6a0e..9ca6d95 100644 --- a/src/mainboard/amd/south_station/platform_cfg.h +++ b/src/mainboard/amd/south_station/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index de4e89d..311214c 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -25,7 +25,8 @@ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In Hudson-2, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and diff --git a/src/mainboard/amd/union_station/platform_cfg.h b/src/mainboard/amd/union_station/platform_cfg.h index 4bd6a0e..9ca6d95 100644 --- a/src/mainboard/amd/union_station/platform_cfg.h +++ b/src/mainboard/amd/union_station/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/asrock/e350m1/platform_cfg.h b/src/mainboard/asrock/e350m1/platform_cfg.h index 6944ab2..29f92d2 100644 --- a/src/mainboard/asrock/e350m1/platform_cfg.h +++ b/src/mainboard/asrock/e350m1/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/asus/m5a88-v/platform_cfg.h b/src/mainboard/asus/m5a88-v/platform_cfg.h index 6944ab2..25574b7 100644 --- a/src/mainboard/asus/m5a88-v/platform_cfg.h +++ b/src/mainboard/asus/m5a88-v/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/avalue/eax-785e/platform_cfg.h b/src/mainboard/avalue/eax-785e/platform_cfg.h index 6944ab2..25574b7 100644 --- a/src/mainboard/avalue/eax-785e/platform_cfg.h +++ b/src/mainboard/avalue/eax-785e/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -191,7 +192,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ @@ -212,7 +213,8 @@ #define GEC_CONFIG 0 /** - * @def SIO_HWM_BASE_ADDRESS Super IO HWM base address + * @def SIO_HWM_BASE_ADDRESS + * Super IO HWM base address */ #define SIO_HWM_BASE_ADDRESS 0x290 diff --git a/src/mainboard/gizmosphere/gizmo/platform_cfg.h b/src/mainboard/gizmosphere/gizmo/platform_cfg.h index 401d981..8163af3 100644 --- a/src/mainboard/gizmosphere/gizmo/platform_cfg.h +++ b/src/mainboard/gizmosphere/gizmo/platform_cfg.h @@ -26,7 +26,8 @@ #define LEGACY_FREE 1 /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -195,7 +196,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h index bbd1d14..2d946f8 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h +++ b/src/mainboard/jetway/nf81-t56n-lf/platform_cfg.h @@ -23,7 +23,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -192,7 +193,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/lippert/frontrunner-af/platform_cfg.h b/src/mainboard/lippert/frontrunner-af/platform_cfg.h index 03146d0..0c3308d 100644 --- a/src/mainboard/lippert/frontrunner-af/platform_cfg.h +++ b/src/mainboard/lippert/frontrunner-af/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -190,7 +191,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */ diff --git a/src/mainboard/lippert/toucan-af/platform_cfg.h b/src/mainboard/lippert/toucan-af/platform_cfg.h index 25b0485..29f3916 100644 --- a/src/mainboard/lippert/toucan-af/platform_cfg.h +++ b/src/mainboard/lippert/toucan-af/platform_cfg.h @@ -22,7 +22,8 @@ #define _PLATFORM_CFG_H_ /** - * @def BIOS_SIZE -> BIOS_SIZE_{1,2,4,8,16}M + * @def BIOS_SIZE + * BIOS_SIZE_{1,2,4,8,16}M * * In SB800, default ROM size is 1M Bytes, if your platform ROM * bigger than 1M you have to set the ROM size outside CIMx module and @@ -190,7 +191,7 @@ #define NB_SB_GEN2 TRUE /** - * @def SB_GEN2 + * @def SB_GPP_GEN2 * 0 - Disable * 1 - Enable */

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coreboot-gerrit January 2015