coreboot-gerrit January 2015

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New patch to review for coreboot: 87dd3da libpayload: ipq808x: introduce uart driver
by Marc Jones 04 Jan '15

04 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8061 -gerrit commit 87dd3da33a937db6ab5a54f8b2ea9d7d980ecd7b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 27 18:28:59 2014 -0700 libpayload: ipq808x: introduce uart driver This adds a UART driver for the ipq8064 controller. It still does not quite work in the receive direction - the receive FIFO returns read data in 32 bit chunks, which means that 4 keys need to be pressed before a character pops out of the driver (and it reports it as a single character). This issue is being addressed separately, the driver is being checked in to facilitate concurrent development. BUG=chrome-os-partner:27784, chrome-os-partner:29313 TEST=with deptcharge modifications in place, the AP148 board comes up to the depthcharge prompt: Starting depthcharge on storm... Original-Change-Id: Ief2cfcca73494be5c4147881144470078adcefb8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202045 Original-Reviewed-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 4499318fb9a4e663c504d7c41380ccf2aa89da29) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I3e07d7568c20c0e570222971ff219de3a6d9b7cc --- payloads/libpayload/Config.in | 5 + payloads/libpayload/configs/defconfig | 5 +- payloads/libpayload/configs/defconfig-arm | 3 +- payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/serial/ipq806x.c | 363 +++++++++++++++++++++++++++ 5 files changed, 375 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/Config.in b/payloads/libpayload/Config.in index 3c5c342..f943cb6 100644 --- a/payloads/libpayload/Config.in +++ b/payloads/libpayload/Config.in @@ -178,6 +178,11 @@ config TEGRA_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config IPQ806X_SERIAL_CONSOLE + bool "IPQ806x SOC compatible serial port driver" + depends on SERIAL_CONSOLE + default n + config PL011_SERIAL_CONSOLE bool "PL011 compatible serial port driver" depends on 8250_SERIAL_CONSOLE diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 78f3808..208bf38 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Wed Nov 12 14:25:19 2014 +# Wed Dec 31 11:36:31 2014 # # @@ -39,6 +39,8 @@ CONFIG_LP_SERIAL_CONSOLE=y CONFIG_LP_8250_SERIAL_CONSOLE=y # CONFIG_LP_S5P_SERIAL_CONSOLE is not set # CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set +# CONFIG_LP_PL011_SERIAL_CONSOLE is not set CONFIG_LP_SERIAL_IOBASE=0x3f8 # CONFIG_LP_SERIAL_SET_SPEED is not set # CONFIG_LP_SERIAL_ACS_FALLBACK is not set @@ -63,6 +65,7 @@ CONFIG_LP_STORAGE_ATA=y CONFIG_LP_STORAGE_ATAPI=y CONFIG_LP_STORAGE_AHCI=y CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y +CONFIG_LP_TIMER_RDTSC=y CONFIG_LP_USB=y CONFIG_LP_USB_UHCI=y CONFIG_LP_USB_OHCI=y diff --git a/payloads/libpayload/configs/defconfig-arm b/payloads/libpayload/configs/defconfig-arm index 83731bb..1d4fcb0 100644 --- a/payloads/libpayload/configs/defconfig-arm +++ b/payloads/libpayload/configs/defconfig-arm @@ -1,7 +1,7 @@ # # Automatically generated make config: don't edit # libpayload version: 0.2.0 -# Wed Dec 31 11:11:44 2014 +# Wed Dec 31 11:37:12 2014 # # @@ -38,6 +38,7 @@ CONFIG_LP_SERIAL_CONSOLE=y # CONFIG_LP_8250_SERIAL_CONSOLE is not set # CONFIG_LP_S5P_SERIAL_CONSOLE is not set # CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set +# CONFIG_LP_IPQ806X_SERIAL_CONSOLE is not set # CONFIG_LP_SERIAL_SET_SPEED is not set # CONFIG_LP_SERIAL_ACS_FALLBACK is not set CONFIG_LP_VIDEO_CONSOLE=y diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index d46bb11..538a8a6 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -36,6 +36,7 @@ libc-$(CONFIG_LP_SPEAKER) += speaker.c libc-$(CONFIG_LP_8250_SERIAL_CONSOLE) += serial/8250.c libc-$(CONFIG_LP_S5P_SERIAL_CONSOLE) += serial/s5p.c libc-$(CONFIG_LP_TEGRA_SERIAL_CONSOLE) += serial/tegra.c +libc-$(CONFIG_LP_IPQ806X_SERIAL_CONSOLE) += serial/ipq806x.c libc-$(CONFIG_LP_PC_KEYBOARD) += keyboard.c diff --git a/payloads/libpayload/drivers/serial/ipq806x.c b/payloads/libpayload/drivers/serial/ipq806x.c new file mode 100644 index 0000000..834389e --- /dev/null +++ b/payloads/libpayload/drivers/serial/ipq806x.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2014 Chromium OS authors + */ + +#include <libpayload.h> + +enum IPQ_UART_DM_PARITY_MODE { + IPQ_UART_DM_NO_PARITY, + IPQ_UART_DM_ODD_PARITY, + IPQ_UART_DM_EVEN_PARITY, + IPQ_UART_DM_SPACE_PARITY +}; + +/* UART Stop Bit Length */ +enum IPQ_UART_DM_STOP_BIT_LEN { + IPQ_UART_DM_SBL_9_16, + IPQ_UART_DM_SBL_1, + IPQ_UART_DM_SBL_1_9_16, + IPQ_UART_DM_SBL_2 +}; + +/* UART Bits per Char */ +enum IPQ_UART_DM_BITS_PER_CHAR { + IPQ_UART_DM_5_BPS, + IPQ_UART_DM_6_BPS, + IPQ_UART_DM_7_BPS, + IPQ_UART_DM_8_BPS +}; + +#define IPQ_UART_DM_CR(base) (((u8 *)(base)) + 0x10) +#define IPQ_UART_DM_DMEN(base) (((u8 *)(base)) + 0x3C) +#define IPQ_UART_DM_DMRX(base) (((u8 *)(base)) + 0x34) +#define IPQ_UART_DM_HCR(base) (((u8 *)(base)) + 0x24) +#define IPQ_UART_DM_IMR(base) (((u8 *)(base)) + 0x14) +#define IPQ_UART_DM_IPR(base) (((u8 *)(base)) + 0x18) +#define IPQ_UART_DM_IRDA(base) (((u8 *)(base)) + 0x38) +#define IPQ_UART_DM_MISR(base) (((u8 *)(base)) + 0x10) +#define IPQ_UART_DM_MR1(base) (((u8 *)(base)) + 0x00) +#define IPQ_UART_DM_MR2(base) (((u8 *)(base)) + 0x04) +#define IPQ_UART_DM_NO_CHARS_FOR_TX(base) (((u8 *)(base)) + 0x040) +#define IPQ_UART_DM_RF(base, x) (((u8 *)(base)) + 0x70 + 4*(x)) +#define IPQ_UART_DM_RFWR(base) (((u8 *)(base)) + 0x20) +#define IPQ_UART_DM_RX_TOTAL_SNAP(base) (((u8 *)(base)) + 0x38) +#define IPQ_UART_DM_SR(base) (((u8 *)(base)) + 0x008) +#define IPQ_UART_DM_TF(base, x) (((u8 *)(base)) + 0x70 + 4*(x)) +#define IPQ_UART_DM_TFWR(base) (((u8 *)(base)) + 0x1C) + +#define IPQ_UART_DM_TXLEV (1 << 0) +#define IPQ_UART_DM_TX_READY (1 << 7) + +#define IPQ_UART_DM_CR_CH_CMD_LSB(x) ((x & 0x0f) << 4) +#define IPQ_UART_DM_CR_CH_CMD_MSB(x) ((x >> 4 ) << 11 ) +#define IPQ_UART_DM_CR_CH_CMD(x) (IPQ_UART_DM_CR_CH_CMD_LSB(x)\ + | IPQ_UART_DM_CR_CH_CMD_MSB(x)) + +#define IPQ_UART_DM_CR_GENERAL_CMD(x) ((x) << 8) + +#define IPQ_UART_DM_8_N_1_MODE (IPQ_UART_DM_NO_PARITY | \ + (IPQ_UART_DM_SBL_1 << 2) | \ + (IPQ_UART_DM_8_BPS << 4)) +#define IPQ_UART_DM_CR_RX_ENABLE (1 << 0) +#define IPQ_UART_DM_CR_TX_ENABLE (1 << 2) +#define IPQ_UART_DM_CMD_RESET_RX IPQ_UART_DM_CR_CH_CMD(1) +#define IPQ_UART_DM_CMD_RESET_TX IPQ_UART_DM_CR_CH_CMD(2) +#define IPQ_UART_DM_CMD_RESET_ERR_STAT IPQ_UART_DM_CR_CH_CMD(3) +#define IPQ_UART_DM_CMD_RES_STALE_INT IPQ_UART_DM_CR_CH_CMD(8) +#define IPQ_UART_DM_CMD_RES_TX_ERR IPQ_UART_DM_CR_CH_CMD(10) +#define IPQ_UART_DM_GCMD_ENA_STALE_EVT IPQ_UART_DM_CR_GENERAL_CMD(5) +#define IPQ_UART_DM_RXSTALE (1 << 3) +#define IPQ_UART_DM_IMR_ENABLED (IPQ_UART_DM_TX_READY | \ + IPQ_UART_DM_TXLEV | \ + IPQ_UART_DM_RXSTALE) +#define IPQ_UART_DM_TFW_VALUE 0 +#define IPQ_UART_DM_RFW_VALUE 1 +#define IPQ_UART_DM_DMRX_DEF_VALUE 0x220 +#define IPQ_UART_DM_SR_TXEMT (1 << 3) +#define IPQ_UART_DM_SR_UART_OVERRUN (1 << 4) +#define IPQ_UART_DM_E_SUCCESS 0 +#define IPQ_UART_DM_E_INVAL 3 +#define IPQ_UART_DM_E_RX_NOT_READY 5 + +#define IPQ_UART_DM_STALE_TIMEOUT_LSB 0x0f + +static struct console_input_driver consin = {}; +static struct console_output_driver consout = {}; + +#define FIFO_DATA_SIZE 4 + +static void *base_uart_addr; + +/* + * All constants lifted from u-boot's + * board/qcom/ipq806x_cdp/ipq806x_board_param.h + */ +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base); + +/* Number of pending received characters */ +static int uart_ready_data_count; + +/* Received data as it came from 32 bit wide FIFO */ +static unsigned int uart_rx_fifo_word; + +/** + * msm_boot_uart_dm_init_rx_transfer - Init Rx transfer + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init_rx_transfer(void *uart_dm_base) +{ + /* Reset receiver */ + writel(IPQ_UART_DM_CMD_RESET_RX, + IPQ_UART_DM_CR(uart_dm_base)); + + /* Enable receiver */ + writel(IPQ_UART_DM_CR_RX_ENABLE, + IPQ_UART_DM_CR(uart_dm_base)); + writel(IPQ_UART_DM_DMRX_DEF_VALUE, + IPQ_UART_DM_DMRX(uart_dm_base)); + + /* Clear stale event */ + writel(IPQ_UART_DM_CMD_RES_STALE_INT, + IPQ_UART_DM_CR(uart_dm_base)); + + /* Enable stale event */ + writel(IPQ_UART_DM_GCMD_ENA_STALE_EVT, + IPQ_UART_DM_CR(uart_dm_base)); + + return IPQ_UART_DM_E_SUCCESS; +} + +/** + * Reads a word from the RX FIFO or returns not ready. + */ +static unsigned msm_boot_uart_dm_read(void) +{ + static int total_rx_data = 0; + static int rx_data_read = 0; + void *base = base_uart_addr; + uint32_t status_reg; + + /* RXSTALE means RX FIFO is not empty. */ + status_reg = readl(IPQ_UART_DM_MISR(base)); + if (!(status_reg & IPQ_UART_DM_RXSTALE)) + return IPQ_UART_DM_E_RX_NOT_READY; + + /* Check for Overrun error. We'll just reset Error Status */ + if (readl(IPQ_UART_DM_SR(base)) & + IPQ_UART_DM_SR_UART_OVERRUN) { + writel(IPQ_UART_DM_CMD_RESET_ERR_STAT, + IPQ_UART_DM_CR(base)); + total_rx_data = rx_data_read = 0; + msm_boot_uart_dm_init(base); + return IPQ_UART_DM_E_RX_NOT_READY; + } + + /* Clear stale event. */ + writel(IPQ_UART_DM_CMD_RES_STALE_INT, IPQ_UART_DM_CR(base)); + + /* Read UART_DM_RX_TOTAL_SNAP for actual number of bytes received */ + if (total_rx_data == 0) + total_rx_data = readl(IPQ_UART_DM_RX_TOTAL_SNAP(base)); + + /* Data available in FIFO; read a word. */ + uart_rx_fifo_word = readl(IPQ_UART_DM_RF(base, 0)); + + /* + * TODO(vbendeb): this is wrong and will be addressed shortly: there + * should be no zeros returned from the FIFO in case there are + * received characters (we don't expect to be receiving zeros). + * See http://crosbug.com/p/29313 + */ + if (uart_rx_fifo_word == 0) { + return IPQ_UART_DM_E_RX_NOT_READY; + } + + /* increment the total count of chars we've read so far */ + rx_data_read += FIFO_DATA_SIZE; + + /* Actual count of valid data in word */ + uart_ready_data_count = + ((total_rx_data < rx_data_read) ? + (FIFO_DATA_SIZE - (rx_data_read - total_rx_data)) : + FIFO_DATA_SIZE); + + /* If there are still data left in FIFO we'll read them before + * initializing RX Transfer again + */ + if (rx_data_read < total_rx_data) + return IPQ_UART_DM_E_SUCCESS; + + msm_boot_uart_dm_init_rx_transfer(base); + total_rx_data = rx_data_read = 0; + + return IPQ_UART_DM_E_SUCCESS; +} + +void serial_putchar(unsigned data) +{ + int num_of_chars = 0; + unsigned tx_data = 0; + void *base = base_uart_addr; + + if (data == '\n') { + num_of_chars++; + tx_data = '\r'; + } + + tx_data |= data << (8 * num_of_chars++); + + /* Wait until transmit FIFO is empty. */ + while (!(readl(IPQ_UART_DM_SR(base)) & + IPQ_UART_DM_SR_TXEMT)) + udelay(1); + + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + writel(num_of_chars, IPQ_UART_DM_NO_CHARS_FOR_TX(base)); + + /* And now write the character(s) */ + writel(tx_data, IPQ_UART_DM_TF(base, 0)); +} + +/* + * msm_boot_uart_dm_reset - resets UART controller + * @base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_reset(void *base) +{ + writel(IPQ_UART_DM_CMD_RESET_RX, IPQ_UART_DM_CR(base)); + writel(IPQ_UART_DM_CMD_RESET_TX, IPQ_UART_DM_CR(base)); + writel(IPQ_UART_DM_CMD_RESET_ERR_STAT, + IPQ_UART_DM_CR(base)); + writel(IPQ_UART_DM_CMD_RES_TX_ERR, IPQ_UART_DM_CR(base)); + writel(IPQ_UART_DM_CMD_RES_STALE_INT, IPQ_UART_DM_CR(base)); + + return IPQ_UART_DM_E_SUCCESS; +} + +/* + * msm_boot_uart_dm_init - initilaizes UART controller + * @uart_dm_base: UART controller base address + */ +static unsigned int msm_boot_uart_dm_init(void *uart_dm_base) +{ + /* Configure UART mode registers MR1 and MR2 */ + /* Hardware flow control isn't supported */ + writel(0x0, IPQ_UART_DM_MR1(uart_dm_base)); + + /* 8-N-1 configuration: 8 data bits - No parity - 1 stop bit */ + writel(IPQ_UART_DM_8_N_1_MODE, + IPQ_UART_DM_MR2(uart_dm_base)); + + /* Configure Interrupt Mask register IMR */ + writel(IPQ_UART_DM_IMR_ENABLED, + IPQ_UART_DM_IMR(uart_dm_base)); + + /* + * Configure Tx and Rx watermarks configuration registers + * TX watermark value is set to 0 - interrupt is generated when + * FIFO level is less than or equal to 0 + */ + writel(IPQ_UART_DM_TFW_VALUE, + IPQ_UART_DM_TFWR(uart_dm_base)); + + /* RX watermark value */ + writel(IPQ_UART_DM_RFW_VALUE, + IPQ_UART_DM_RFWR(uart_dm_base)); + + /* Configure Interrupt Programming Register */ + /* Set initial Stale timeout value */ + writel(IPQ_UART_DM_STALE_TIMEOUT_LSB, + IPQ_UART_DM_IPR(uart_dm_base)); + + /* Configure IRDA if required */ + /* Disabling IRDA mode */ + writel(0x0, IPQ_UART_DM_IRDA(uart_dm_base)); + + /* Configure hunt character value in HCR register */ + /* Keep it in reset state */ + writel(0x0, IPQ_UART_DM_HCR(uart_dm_base)); + + /* + * Configure Rx FIFO base address + * Both TX/RX shares same SRAM and default is half-n-half. + * Sticking with default value now. + * As such RAM size is (2^RAM_ADDR_WIDTH, 32-bit entries). + * We have found RAM_ADDR_WIDTH = 0x7f + */ + + /* Issue soft reset command */ + msm_boot_uart_dm_reset(uart_dm_base); + + /* Enable/Disable Rx/Tx DM interfaces */ + /* Data Mover not currently utilized. */ + writel(0, IPQ_UART_DM_DMEN(uart_dm_base)); + + /* Enable transmitter */ + writel(IPQ_UART_DM_CR_TX_ENABLE, + IPQ_UART_DM_CR(uart_dm_base)); + + /* Initialize Receive Path */ + msm_boot_uart_dm_init_rx_transfer(uart_dm_base); + + return 0; +} + +/** + * serial_havechar - checks if data available for reading + * + * Returns 1 if data available, 0 otherwise + */ +int serial_havechar(void) +{ + /* Return if data is already read */ + if (uart_ready_data_count) + return 1; + + /* Read data from the FIFO */ + if (msm_boot_uart_dm_read() != IPQ_UART_DM_E_SUCCESS) + return 0; + + return 1; +} + +/** + * ipq806x_serial_getc - reads a character + * + * Returns the character read from serial port. + */ +int serial_getchar(void) +{ + uint8_t byte; + + while (!serial_havechar()) { + /* wait for incoming data */ + } + + byte = (uint8_t)(uart_rx_fifo_word & 0xff); + uart_rx_fifo_word = uart_rx_fifo_word >> 8; + uart_ready_data_count--; + + return byte; +} + +/* For simplicity sake let's rely on coreboot initalizing the UART. */ +void serial_console_init(void) +{ + struct cb_serial *sc_ptr = lib_sysinfo.serial; + + if (!sc_ptr) + return; + + base_uart_addr = (void *) sc_ptr->baseaddr; + + consin.havekey = serial_havechar; + consin.getchar = serial_getchar; + + consout.putchar = serial_putchar; + + console_add_output_driver(&consout); + console_add_input_driver(&consin); +}

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New patch to review for coreboot: 4db4b86 libpayload: arm: add code to clear bss
by Marc Jones 04 Jan '15

04 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8060 -gerrit commit 4db4b86fb5eeb24ee06cc798ab2f2f328df1c1fe Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 27 16:16:50 2014 -0700 libpayload: arm: add code to clear bss This adds some assembly code to clear .bss segment. It might have been already cleared by the loader, but it is not guaranteed. This also helps when the program is loaded by the debugger. BUG=none TEST=observed that .bss is now initialized when the program is restarted. Verified correct boundaries of the segment. Original-Change-Id: I0aed0070da53881e4cf8c27049459040c006e765 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201784 Original-Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit c89ecee5ddfc33a438d4d1926d3756a48f3c2576) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ic0c33d2a8ad22cd23b3ccb73c603cb14ae2aab29 --- payloads/libpayload/arch/arm/head.S | 22 ++++++++++++++++++---- 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/arch/arm/head.S b/payloads/libpayload/arch/arm/head.S index c5c96ea..788e328 100644 --- a/payloads/libpayload/arch/arm/head.S +++ b/payloads/libpayload/arch/arm/head.S @@ -34,14 +34,25 @@ */ ENTRY(_entry) + /* TODO: disable interrupts */ + + /* Clear BSS */ + mov r12, #0 + ldr r2, bss_boundaries + ldr r3, bss_boundaries + 4 + cmp r2, r3 + beq no_bss + + sub r3, #4 /* Account for late condition check. */ +loop: + cmp r2, r3 + str r12, [r2], #4 + blt loop +no_bss: /* Save off the location of the coreboot tables */ ldr r1, 1f str r0, [r1] - /* TODO: disable interrupts */ - - /* TODO: Clear BSS */ - /* Setup new stack */ ldr sp, 2f @@ -59,6 +70,9 @@ ENTRY(_entry) ENDPROC(_entry) .align 4 +bss_boundaries: + .word _edata + .word _end 1: .word cb_header_ptr 2:

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Patch merged into coreboot/master: 11aaf1f ipq8064: Add work around for slow timer clock
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 11aaf1f42ad8035c2870dc50852437f5e8863061 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:18:35 2014 -0700 ipq8064: Add work around for slow timer clock Libpayload libc requires timer clock frequency to be at least 1MHz. Ipq8064 code presently provides a single option of 32kHz. Pretend to be running at 1 MHz without additional accuracy. This is a hack which will be reverted as soon as the SOC is configured to supply a faster running clock. BUG=chrome-os-partner:27784, chrome-os-partner:28880 TEST=with other changes depthcharge boots to the CLI console Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201342 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I113689191db70710e7a45ccd02d672f482343e35 Reviewed-on: http://review.coreboot.org/8004 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8004 for details. -gerrit

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Patch merged into coreboot/master: 66fdbce libpayload: Provide selfboot() external declaration in a common file
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 66fdbced5e61ad2387bfae2db7caf507fef88f37 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:37:10 2014 -0700 libpayload: Provide selfboot() external declaration in a common file The earlier compilation warning fix (chromium 7e4aa17) incorrectly assumed that selfboot() is a function defined in the cbfs driver. This is a commonly available function, it should not come from cbfs.h. BUG=none TEST=the following build command succeeds: rambi storm nyan_big Original-Change-Id: I3ef49d849168ad9dc24589cbd9ce7382052345bd Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201386 (cherry picked from commit d5090e8410530f41b9fd33e2caa1d8aa25438105) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8404fb52112b391982f954a6d06fe4b451dfcb8a Reviewed-on: http://review.coreboot.org/8003 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8003 for details. -gerrit

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Patch set updated for coreboot: 4cd6411 ipq806x: Fix casting in cbmem_top() so >=2GB can be used
by Marc Jones 04 Jan '15

04 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8059 -gerrit commit 4cd6411c13f8f17362dd1c379fae17954478c0ae Author: David Hendricks <dhendrix(a)chromium.org> Date: Fri Jun 27 13:25:02 2014 -0700 ipq806x: Fix casting in cbmem_top() so >=2GB can be used This explicitly casts CONFIG_SYS_SDRAM_BASE to an unsigned type so we don't get compilation errors when increasing CONFIG_DRAM_SIZE_MB. BUG=chrome-os-partner:29871 BRANCH=storm TEST=compilation no longer fails with DRAM_SIZE set to 1024 Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I9717c39d87682d43ec4e7a4042d9b559a1d7eedb Original-Reviewed-on: https://chromium-review.googlesource.com/206010 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit 178db896346ae8cbc5ddec5373a83688f32c62ba) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I68c11d398820684ad928bdfdd74f7a6885247333 --- src/soc/qualcomm/ipq806x/cbmem.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c index b175d6a..ecb02e4 100644 --- a/src/soc/qualcomm/ipq806x/cbmem.c +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -18,8 +18,10 @@ */ #include <cbmem.h> +#include <stddef.h> void *cbmem_top(void) { - return (void *)(CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20)); + return (void *)((uintptr_t)CONFIG_SYS_SDRAM_BASE + + (CONFIG_DRAM_SIZE_MB << 20)); }

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Patch merged into coreboot/master: 0b70bd1 ipq806x: move GPIO definitions to the proper include file
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 0b70bd13363b560039788f60e1bdd5f3727f489c Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Mon Jun 23 10:41:38 2014 -0700 ipq806x: move GPIO definitions to the proper include file When the IPQ SPI driver was ported to coreboot, a few GPIO related definitions ended up in a wrong include file. Move them to the proper place and get rid of duplicated definition of GPIO_OUT. BUG=chrome-os-partner:27784, chrome-os-partner:29871 TEST=proto0 still boots with the new firmware Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/205328 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4 Reviewed-on: http://review.coreboot.org/8058 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8058 for details. -gerrit

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Patch merged into coreboot/master: 6b33286 ipq806x: move translation table out of the way
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 6b33286e958780f52216d9b787158c9598671b88 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu Jun 12 10:02:59 2014 -0700 ipq806x: move translation table out of the way Depthcharge clears up all unused DRAM before starting Linux, and does not know the translation table location. Instead of adding an exclusion term to the memory wipe descriptor let's move the table to the top of IMEM, it is also likely to be a good location in the future, when EFS is introduced. BUG=chrome-os-partner:27782 TEST=manual . built and ran firmware on ap148 Original-Change-Id: I76546438d243076dda4d0eb3f784e0b5a8a1fa22 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203624 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit 4250f8574d6cc0bbec5ba0411f22d801f034afb8) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I12cd74e3d318b878e7703414a7ddaaed0812cb7a Reviewed-on: http://review.coreboot.org/8057 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8057 for details. -gerrit

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Patch merged into coreboot/master: 028cba9 ipq806x: Add USB support
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 028cba9266e531d9d7c5e39432bbb7eeda6398ed Author: Julius Werner <jwerner(a)chromium.org> Date: Fri May 30 18:01:44 2014 -0700 ipq806x: Add USB support This patch adds code to initialize the two DWC3 USB host controllers and their associated PHYs to the IPQ806x SoC (closely imitating the existing DWC3 implementation for Exynos5), and uses them to initialize USB on the Storm mainboard. BUG=chrome-os-partner:29375 TEST=Hack up netboot to get around missing SPI flash, load a file over TFTP. Hack a storage read into the storage attach function, dump the data and confirm that it looks right. Enable USB debugging and confirm 3.0 devices get enumerated at SuperSpeed (mostly). Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202157 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af Reviewed-on: http://review.coreboot.org/8056 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8056 for details. -gerrit

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Patch merged into coreboot/master: 96ef188 nyan_big: Update Hynix BCTs and add Kingston 2GB BCT.
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 96ef1883a7a8b95f297f99fa7409f27c0f344d88 Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Jun 10 13:46:48 2014 -0700 nyan_big: Update Hynix BCTs and add Kingston 2GB BCT. Hynix 2GB/4GB configs have been fine-tuned. Kingston 2GB config is new, uses RAMCODE 0x6. BUG=none TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my Big 2GB system (PVT1/SKU1) and it booted OK. BRANCH=nyan_big Original-Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203305 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> (cherry picked from commit e47d18d8cff50f46d0a14715b6750f7aa6d0da82) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I363db37d6a63d9f5c578e68a0149259657e1ebfd Reviewed-on: http://review.coreboot.org/8045 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8045 for details. -gerrit

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Patch merged into coreboot/master: 1e3679d tegra124: configure DP with correct pixel clock
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 1e3679ddd0fd03fdc00b50a45fc652a539b9c9a7 Author: Vince Hsu <vinceh(a)nvidia.com> Date: Wed Jun 11 17:14:05 2014 +0800 tegra124: configure DP with correct pixel clock For some panels, the plld can't provide the pixel clock that the panels wants, so we give it a good enough one. And we should calculate the dp/dc settings by the real pixel clock. BRANCH=nyan BUG=chrome-os-partner:29489 TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big). No screen flicker is observed. No sor dp fifo underflow found. Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779 Original-Signed-off-by: Vince Hsu <vinceh(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203358 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac Reviewed-on: http://review.coreboot.org/8044 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8044 for details. -gerrit

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coreboot-gerrit January 2015