coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: c1f7cbe arm: lpae: Set XN and PXN bits for noncacheable regions
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit c1f7cbe49f0023655f6f60b1d924ed5c61533806 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Fri Jun 6 17:00:10 2014 -0700 arm: lpae: Set XN and PXN bits for noncacheable regions Add XN/PXN bits to prevent cpu from fetching speculative instructions on noncacheable region. BUG=chrome-os-partner:28568 BRANCH=nyan TEST=Build and run reboot tests on nyan_big Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b Original-Reviewed-on: https://chromium-review.googlesource.com/203447 Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe Reviewed-on: http://review.coreboot.org/8043 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8043 for details. -gerrit

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Patch merged into coreboot/master: cb2351e nyan: Ignore the recovery GPIO.
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit cb2351ea1f24c89adc6b83d7efc94d00e59dcba8 Author: Todd Broch <tbroch(a)chromium.org> Date: Fri Jun 6 17:03:49 2014 -0700 nyan: Ignore the recovery GPIO. CrOS devices with Chromeos EC need only use hostevent to communicate recovery assertion to the BIOS. This CL removes wired GPIO from determining recovery as it appears under certain conditions (cold reset) the internal PU on the AP isn't strong enough and therefore the value is sometimes seen as asserted. BRANCH=none BUG=chrome-os-partner:29333 TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot. Original-Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2 Original-Signed-off-by: Todd Broch <tbroch(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202996 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit d9927bcd67b0fb069fde231314e654d727092282) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6e086cbabc884f18deb2791a0f897e332b31032f Reviewed-on: http://review.coreboot.org/8042 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8042 for details. -gerrit

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Patch set updated for coreboot: ad33de8 ipq8064: Add work around for slow timer clock
by Marc Jones 04 Jan '15

04 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8004 -gerrit commit ad33de86eef57388ad39f806284c71c44e0bfbba Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:18:35 2014 -0700 ipq8064: Add work around for slow timer clock Libpayload libc requires timer clock frequency to be at least 1MHz. Ipq8064 code presently provides a single option of 32kHz. Pretend to be running at 1 MHz without additional accuracy. This is a hack which will be reverted as soon as the SOC is configured to supply a faster running clock. BUG=chrome-os-partner:27784, chrome-os-partner:28880 TEST=with other changes depthcharge boots to the CLI console Original-Change-Id: I80ec6652bc5693a549668cd6e824e9cf5c26b182 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201342 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 466a59967b13986099106f8b44924648c1e6e6cd) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I113689191db70710e7a45ccd02d672f482343e35 --- payloads/libpayload/drivers/timer/ipq806x.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/timer/ipq806x.c b/payloads/libpayload/drivers/timer/ipq806x.c index 4edbf8e..0d70a86 100644 --- a/payloads/libpayload/drivers/timer/ipq806x.c +++ b/payloads/libpayload/drivers/timer/ipq806x.c @@ -29,13 +29,31 @@ #include <libpayload.h> +/* + * TODO(vbendeb): reverted this hack once proper timer code is in place (see + * http://crosbug.com/p/28880 for details. + */ +#define MIN_TIMER_FREQ 1000000 + uint64_t timer_hz(void) { - return CONFIG_LP_IPQ806X_TIMER_FREQ; + return (CONFIG_LP_IPQ806X_TIMER_FREQ >= MIN_TIMER_FREQ) ? + CONFIG_LP_IPQ806X_TIMER_FREQ : MIN_TIMER_FREQ; } uint64_t timer_raw_value(void) { - return readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); + uint64_t rawv = readl((void *)CONFIG_LP_IPQ806X_TIMER_REG); + + /* + * This is extremely crude, but it kicks in only for the case when the + * timer clock frequency is below 1MHz, which should never be the case + * on a properly configured system. The compiler will eliminate the + * check as long as config value exceeds 1MHz. + */ + if (CONFIG_LP_IPQ806X_TIMER_FREQ < MIN_TIMER_FREQ) + rawv *= (MIN_TIMER_FREQ / CONFIG_LP_IPQ806X_TIMER_FREQ); + + return rawv; }

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Patch set updated for coreboot: 0b5e010 libpayload: Provide selfboot() external declaration in a common file
by Marc Jones 04 Jan '15

04 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8003 -gerrit commit 0b5e01082a9b9ea2da2e81381bafbb68794415b7 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Fri May 23 14:37:10 2014 -0700 libpayload: Provide selfboot() external declaration in a common file The earlier compilation warning fix (chromium 7e4aa17) incorrectly assumed that selfboot() is a function defined in the cbfs driver. This is a commonly available function, it should not come from cbfs.h. BUG=none TEST=the following build command succeeds: rambi storm nyan_big Original-Change-Id: I3ef49d849168ad9dc24589cbd9ce7382052345bd Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201386 (cherry picked from commit d5090e8410530f41b9fd33e2caa1d8aa25438105) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I8404fb52112b391982f954a6d06fe4b451dfcb8a --- payloads/libpayload/include/cbfs.h | 3 --- payloads/libpayload/include/libpayload.h | 6 +++--- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/payloads/libpayload/include/cbfs.h b/payloads/libpayload/include/cbfs.h index c5c811c..1b5c51a 100644 --- a/payloads/libpayload/include/cbfs.h +++ b/payloads/libpayload/include/cbfs.h @@ -81,9 +81,6 @@ void *cbfs_simple_buffer_unmap(struct cbfs_simple_buffer *buffer, // Utility functions int run_address(void *f); -/* Defined in src/lib/selfboot.c */ -void selfboot(void *entry); - /* Defined in individual arch / board implementation. */ int init_default_cbfs_media(struct cbfs_media *media); diff --git a/payloads/libpayload/include/libpayload.h b/payloads/libpayload/include/libpayload.h index 1d4d0da..9781c9e 100644 --- a/payloads/libpayload/include/libpayload.h +++ b/payloads/libpayload/include/libpayload.h @@ -60,9 +60,6 @@ #ifdef CONFIG_LP_LAR #include <lar.h> #endif -#ifdef CONFIG_LP_CBFS -#include <cbfs.h> -#endif #define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MAX(a,b) ((a) > (b) ? (a) : (b)) @@ -445,4 +442,7 @@ char *readline(const char *prompt); int getline(char *buffer, int len); /** @} */ +/* Defined in arch/${ARCH}/selfboot.c */ +void selfboot(void *entry); + #endif

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Patch merged into coreboot/master: 8ec74a3 libpayload: ipq8064: Add rudimentary timer driver
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 8ec74a39fa6b5a4a216a837f1ff8f2e8c8b7436b Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed May 21 16:28:57 2014 -0700 libpayload: ipq8064: Add rudimentary timer driver This is still using the 32kHz timer coreboot uses. A finer granularity timer implementation for 806x is in the works. BUG=chrome-os-partner:27784,chrome-os-partner:28880 TEST=none yet. Original-Change-Id: Iae206749000d45040090df48199c8d86d76bbae5 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/198021 Original-Reviewed-by: Furquan Shaikh <furquan(a)chromium.org> (cherry picked from commit 8f49f752ab8f84b7c5dc189238732360e8d2aae2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ia150c974e5b66939de0b007cf7c1308c187f3289 Reviewed-on: http://review.coreboot.org/8002 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/8002 for details. -gerrit

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Patch merged into coreboot/master: 5106b9d samus: Minor fixes for P1.9 boards
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 5106b9dbb7b5cf0f61e763706c868054a1408e31 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 10 10:05:03 2014 -0700 samus: Minor fixes for P1.9 boards - Put SSD into reset on transition to S3/S5 to prevent leakage - Fix GPIO number for wlan disable used in smihandler - Enable generic hub driver in libpayload - Fix comment in devicetree about S0ix BUG=chrome-os-partner:28502 BRANCH=None TEST=Build and boot on samus Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203185 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0 Reviewed-on: http://review.coreboot.org/8048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8048 for details. -gerrit

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Patch merged into coreboot/master: ef57a22 wtm2: Fix issues with USB in firmware
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit ef57a22163519431dc0951f2ccc857f1027d7109 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 10 10:03:22 2014 -0700 wtm2: Fix issues with USB in firmware XHCI driver was not enabled in libpayload and some ports were disabled that should be enabled. The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to properly indicate unused so crossystem does not attempt to export GPIO number 255 in the kernel and trigger a warning. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f Original-CSigned-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/203184 Original-CReviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 328362469b00c9467908a7d18a031fee73753def) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434 Reviewed-on: http://review.coreboot.org/8047 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/8047 for details. -gerrit

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Patch merged into coreboot/master: 502c38f samus: Enable DDI2 hotplug
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 502c38f9df25bfaf650271d93ea90069a1d0ccd6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 2 08:36:38 2014 -0700 samus: Enable DDI2 hotplug Both DDI ports may be used on this board so it needs to be able to detect a device on either port. BUG=chrome-os-partner:28234 TEST=None (needs hardware) Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202358 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099 Reviewed-on: http://review.coreboot.org/8046 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/8046 for details. -gerrit

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Patch merged into coreboot/master: 25c6f75 samus: Update for board revision 1.9
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit 25c6f75bb29fceba7a30d170f2401241fc3428ed Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 22 08:25:36 2014 -0700 samus: Update for board revision 1.9 - Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU BUG=chrome-os-partner:28234 TEST=Boot on P1.9 Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 Reviewed-on: http://review.coreboot.org/8007 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8007 for details. -gerrit

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Patch merged into coreboot/master: fe8b788 samus: Move SPD related information to spd directory
by gerrit＠coreboot.org 04 Jan '15

04 Jan '15

the following patch was just integrated into master: commit fe8b788a12b225ae45ecb26625cfd2588d193ff3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 22 08:22:51 2014 -0700 samus: Move SPD related information to spd directory Put all the SPD related information in one place including the onboard SPD sources and the board specific parsing. BUG=chrome-os-partner:28234 TEST=Build and boot on samus Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201082 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123 Reviewed-on: http://review.coreboot.org/8006 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/8006 for details. -gerrit

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coreboot-gerrit January 2015