coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: bec2f1b Add and consistently use wrapper macro for romstage static variables
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8055 -gerrit commit bec2f1b75e701e9d55284afead8618df2f5e29e8 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jun 6 16:10:56 2014 -0700 Add and consistently use wrapper macro for romstage static variables x86 systems run their romstage as execute-in-place from flash, which prevents them from having writable data segments. In several code pieces that get linked into both romstage and ramstage, this has been worked around by using a local variable and having the 'static' storage class guarded by #ifndef __PRE_RAM__. However, x86 is the only architecture using execute-in-place (for now), so it does not make sense to impose the restriction globally. Rather than fixing the #ifdef at every occurrence, this should really be wrapped in a way that makes it easier to modify in a single place. The chromeos/cros_vpd.c file already had a nice approach for a wrapper macro, but unfortunately restricted it to one file... this patch moves it to stddef.h and employs it consistently throughout coreboot. BRANCH=nyan BUG=None TEST=Measured boot time on Nyan_Big before and after, confirmed that it gained 6ms from caching the FMAP in vboot_loader.c. Original-Change-Id: Ia53b94ab9c6a303b979db7ff20b79e14bc51f9f8 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203033 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> (cherry picked from commit c8127e4ac9811517f6147cf019ba6a948cdaa4a5) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I44dacc10214351992b775aca52d6b776a74ee922 --- src/include/stddef.h | 7 +++++++ src/lib/lzma.c | 7 +------ src/lib/timestamp.c | 2 +- src/vendorcode/google/chromeos/cros_vpd.c | 18 ++++-------------- src/vendorcode/google/chromeos/fmap.c | 5 +---- 5 files changed, 14 insertions(+), 25 deletions(-) diff --git a/src/include/stddef.h b/src/include/stddef.h index 137de04..bd6c3ba 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -38,4 +38,11 @@ typedef unsigned int wint_t; #define ROMSTAGE_CONST #endif +/* Work around non-writable data segment in execute-in-place romstage on x86. */ +#if defined(__PRE_RAM__) && CONFIG_ARCH_X86 +#define MAYBE_STATIC +#else +#define MAYBE_STATIC static +#endif + #endif /* STDDEF_H */ diff --git a/src/lib/lzma.c b/src/lib/lzma.c index ea5f15f..8efa1e6 100644 --- a/src/lib/lzma.c +++ b/src/lib/lzma.c @@ -24,12 +24,7 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst) int res; CLzmaDecoderState state; SizeT mallocneeds; -#if !defined(__PRE_RAM__) - /* in ramstage, this can go in BSS */ - static -#endif - /* in pre-ram, it must go on the stack */ - unsigned char scratchpad[15980]; + MAYBE_STATIC unsigned char scratchpad[15980]; unsigned char *cp; memcpy(properties, src, LZMA_PROPERTIES_SIZE); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index f0ee48d..f7f92cd 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -60,7 +60,7 @@ static void timestamp_real_init(tsc_t base) void timestamp_add(enum timestamp_id id, tsc_t ts_time) { struct timestamp_entry *tse; - struct timestamp_table *ts_table = NULL; + MAYBE_STATIC struct timestamp_table *ts_table = NULL; if (!boot_cpu()) return; diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index 26b01ee..df2b5bf 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -15,16 +15,6 @@ #include "lib_vpd.h" #include "vpd_tables.h" -/* - * Static variables are available in ramstage (all platforms), and romstage for - * some platforms (ex, ARM, which uses SRAM). - */ -#if defined(__PRE_RAM__) && CONFIG_ARCH_X86 -#define STATIC_VAR -#else -#define STATIC_VAR static -#endif - /* Currently we only support Google VPD 2.0, which has a fixed offset. */ enum { GOOGLE_VPD_2_0_OFFSET = 0x600, @@ -39,10 +29,10 @@ struct vpd_gets_arg { static int cros_vpd_load(uint8_t **vpd_address, int32_t *vpd_size) { - STATIC_VAR int cached = 0; - STATIC_VAR uint8_t *cached_address = NULL; - STATIC_VAR int32_t cached_size = 0; - STATIC_VAR int result = -1; + MAYBE_STATIC int cached = 0; + MAYBE_STATIC uint8_t *cached_address = NULL; + MAYBE_STATIC int32_t cached_size = 0; + MAYBE_STATIC int result = -1; struct google_vpd_info info; int32_t base; diff --git a/src/vendorcode/google/chromeos/fmap.c b/src/vendorcode/google/chromeos/fmap.c index bc56a19..8bea8f7 100644 --- a/src/vendorcode/google/chromeos/fmap.c +++ b/src/vendorcode/google/chromeos/fmap.c @@ -92,10 +92,7 @@ const struct fmap_area *find_fmap_area(const struct fmap *fmap, int find_fmap_entry(const char name[], void **pointer) { -#ifndef __PRE_RAM__ - static -#endif - const struct fmap *fmap = NULL; + MAYBE_STATIC const struct fmap *fmap = NULL; const struct fmap_area *area; void *base = NULL;

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Patch merged into coreboot/master: dafa12a intel/model_206ax: update microcode
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit dafa12adfc567e71df83a2f5924f51a595db963c Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Mon Dec 29 20:24:52 2014 +0100 intel/model_206ax: update microcode tested on ivy and sandy (t520/t420s & t530) Change-Id: Ie527e8c4804821764ecc42f7495573eff67828f7 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/7976 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7976 for details. -gerrit

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Patch merged into coreboot/master: 24a53dd ipq806x: clean up UART driver tx_byte function
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 24a53dddb9b0b545ab9208722ff7b684114b4e91 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 27 18:03:38 2014 -0700 ipq806x: clean up UART driver tx_byte function The driver as it was copied from u-boot provided a function to transmit multiple characters in one invocation. This feature was not ported to coreboot, there is no need to maintain the complexity when only one character at a time is transmitted. It is also very desirable to get rid of a 1024 byte array allocated on the stack. The array was necessary to allow to convert multiple newline characters in the transmit data flow into two character sequences CRLF. Now just a single word is enough to keep one or two characters to transmit. [EDIT km: newline translation is now part of printk] BUG=chrome-os-partner:27784 TEST=verified that coreboot with the new code prints generates console output. Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201782 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/8011 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/8011 for details. -gerrit

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New patch to review for coreboot: bc64523 superio/intel/i3100: Use link-time symbol over .c includes
by Edward O'Callaghan 03 Jan '15

03 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8054 -gerrit commit bc6452334acba936bf048d391d2d218147fd7722 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 04:25:38 2015 +1100 superio/intel/i3100: Use link-time symbol over .c includes Change-Id: I83db9b189e672b0e1f25bc42b73639c375bea3e5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 1 - src/mainboard/intel/truxton/romstage.c | 1 - src/superio/intel/i3100/Makefile.inc | 1 + src/superio/intel/i3100/early_serial.c | 4 ++-- src/superio/intel/i3100/i3100.h | 12 +++++++++--- 6 files changed, 13 insertions(+), 8 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index c03c7d7..b41e0c5 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 4691b5c..959beab 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -30,7 +30,6 @@ #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" #include <superio/intel/i3100/i3100.h> -#include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index f750778..4c15f67 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -32,7 +32,6 @@ #include "northbridge/intel/i3100/raminit_ep80579.h" #include <superio/intel/i3100/i3100.h> #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" #include "lib/debug.c" // XXX #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index dedd419..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index 96bb550..57f0e7a 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -38,14 +38,14 @@ static void pnp_exit_ext_func_mode(pnp_devfn_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) +void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) +void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..3f51a48 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H /* * Datasheet: @@ -61,4 +61,10 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +#include <arch/io.h> +#include <stdint.h> + +void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide); +void i3100_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */

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New patch to review for coreboot: fabab3b superio/nsc/pc87360: Use link-time symbol over .c includes
by Edward O'Callaghan 03 Jan '15

03 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8053 -gerrit commit fabab3b83f7dab683fb465c45166c7e5f69b7fb6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 04:09:55 2015 +1100 superio/nsc/pc87360: Use link-time symbol over .c includes Change-Id: Id6d9efc93fdaff63dcaab50712ac9be35ccb42a7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/arima/hdama/romstage.c | 2 +- src/mainboard/hp/e_vectra_p2706t/romstage.c | 2 +- src/superio/nsc/pc87360/Makefile.inc | 1 + src/superio/nsc/pc87360/early_serial.c | 3 ++- src/superio/nsc/pc87360/pc87360.h | 11 ++++++++--- src/superio/nsc/pc87360/superio.c | 1 - 6 files changed, 13 insertions(+), 7 deletions(-) diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 3c7eb58..137d3eb 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -12,7 +12,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/nsc/pc87360/early_serial.c" +#include <superio/nsc/pc87360/pc87360.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> diff --git a/src/mainboard/hp/e_vectra_p2706t/romstage.c b/src/mainboard/hp/e_vectra_p2706t/romstage.c index baa1995..f54e0e8 100644 --- a/src/mainboard/hp/e_vectra_p2706t/romstage.c +++ b/src/mainboard/hp/e_vectra_p2706t/romstage.c @@ -25,7 +25,7 @@ #include <stdlib.h> #include <console/console.h> /* TODO: It's a PC87364 actually! */ -#include "superio/nsc/pc87360/early_serial.c" +#include <superio/nsc/pc87360/pc87360.h> /* TODO: It's i810E actually! */ #include "northbridge/intel/i82810/raminit.h" #include "cpu/x86/bist.h" diff --git a/src/superio/nsc/pc87360/Makefile.inc b/src/superio/nsc/pc87360/Makefile.inc index 579b14e..cb504f7 100644 --- a/src/superio/nsc/pc87360/Makefile.inc +++ b/src/superio/nsc/pc87360/Makefile.inc @@ -19,4 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_NSC_PC87360) += early_serial.c ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index 3deac3b..fdac969 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -20,9 +20,10 @@ */ #include <arch/io.h> +#include <stdint.h> #include "pc87360.h" -static void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) +void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87360/pc87360.h b/src/superio/nsc/pc87360/pc87360.h index 9843984..f006943 100644 --- a/src/superio/nsc/pc87360/pc87360.h +++ b/src/superio/nsc/pc87360/pc87360.h @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_NSC_PC87360_PC87360_H -#define SUPERIO_NSC_PC87360_PC87360_H +#ifndef SUPERIO_NSC_PC87360_H +#define SUPERIO_NSC_PC87360_H #define PC87360_FDC 0x00 /* Floppy */ #define PC87360_PP 0x01 /* Parallel port */ @@ -34,4 +34,9 @@ #define PC87360_FSCM 0x09 #define PC87360_WDT 0x0A -#endif +#include <arch/io.h> +#include <stdint.h> + +void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase); + +#endif /* SUPERIO_NSC_PC87360_H */ diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 58e0802..5706014 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -30,7 +30,6 @@ static void init(struct device *dev) { - if (!dev->enabled) return;

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New patch to review for coreboot: 85be05c mainboard: Sanitize some superio include paths to be non-local
by Edward O'Callaghan 03 Jan '15

03 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8052 -gerrit commit 85be05cb4ba48eebc5c7cd0e5643fc6d9e490d74 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 04:17:35 2015 +1100 mainboard: Sanitize some superio include paths to be non-local This brings mainboard up to being consistent tree-wide now for all superio header path inclusions. Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/mainboard/lenovo/t60/dock.c | 2 +- src/mainboard/lenovo/x60/dock.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/supermicro/h8scm_fam10/romstage.c | 2 +- 11 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 6580ab9..7194851 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -33,7 +33,7 @@ #include <console/console.h> #include <halt.h> #include <reset.h> -#include "superio/smsc/sio1007/chip.h" +#include <superio/smsc/sio1007/chip.h> #include <fsp_util.h> #include "northbridge/intel/fsp_sandybridge/northbridge.h" #include "northbridge/intel/fsp_sandybridge/raminit.h" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 76edf7f..ffb44a0 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -30,7 +30,7 @@ #include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> -#include "superio/smsc/sio1007/chip.h" +#include <superio/smsc/sio1007/chip.h> #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index c1ee9bb..4691b5c 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,7 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 0677cf6..f750778 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,7 +30,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/early_serial.c" #include "lib/debug.c" // XXX diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index b01f8e8..8052dbc 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -24,7 +24,7 @@ #include <arch/io.h> #include <delay.h> #include "dock.h" -#include "superio/nsc/pc87384/pc87384.h" +#include <superio/nsc/pc87384/pc87384.h> #include "ec/acpi/ec.h" #include "ec/lenovo/pmh7/pmh7.h" #include "southbridge/intel/i82801gx/i82801gx.h" diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index 1f85281..1a843d9 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -26,7 +26,7 @@ #include <arch/io.h> #include "dock.h" #include "southbridge/intel/i82801gx/i82801gx.h" -#include "superio/nsc/pc87392/pc87392.h" +#include <superio/nsc/pc87392/pc87392.h> static void dlpc_write_register(int reg, int value) { diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 5b8646a..b356fa8 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -44,7 +44,7 @@ #include "option_table.h" #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO -#include "superio/smsc/lpc47n207/lpc47n207.h" +#include <superio/smsc/lpc47n207/lpc47n207.h> #include "superio/smsc/lpc47n207/early_serial.c" #endif #if CONFIG_CHROMEOS diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index f842ad2..1462132 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -44,7 +44,7 @@ #include <halt.h> #include "gpio.h" #if CONFIG_DRIVERS_UART_8250IO -#include "superio/smsc/lpc47n207/lpc47n207.h" +#include <superio/smsc/lpc47n207/lpc47n207.h> #include "superio/smsc/lpc47n207/early_serial.c" #endif #if CONFIG_CHROMEOS diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 477f1c4..c231e31 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -31,7 +31,7 @@ #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> -#include "superio/nuvoton/wpcm450/wpcm450.h" +#include <superio/nuvoton/wpcm450/wpcm450.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 6e7ad70..0bbd8bc 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -31,7 +31,7 @@ #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> -#include "superio/nuvoton/wpcm450/wpcm450.h" +#include <superio/nuvoton/wpcm450/wpcm450.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index fdf49d8..917e9e3 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -46,7 +46,7 @@ #include "southbridge/amd/sb700/sb700.h" #include "southbridge/amd/sb700/smbus.h" #include "southbridge/amd/sr5650/sr5650.h" -#include "superio/nuvoton/wpcm450/wpcm450.h" +#include <superio/nuvoton/wpcm450/wpcm450.h> #include "northbridge/amd/amdfam10/debug.c" static void activate_spd_rom(const struct mem_controller *ctrl)

1 0

Patch merged into coreboot/master: 0780d67 util/cbfstool: Fix byte-ordering for payload type field.
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 0780d67ffe8ef754ace0912114e2b1e772554990 Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri May 16 10:14:05 2014 +0800 util/cbfstool: Fix byte-ordering for payload type field. In https://chromium-review.googlesource.com/181272 the payload->type has been changed to big-endian (network ordering) but the cbfs_image is still parsing type as host ordering, which caused printing cbfs image verbosely (cbfstool imge print -v) to fail to find entry field and print numerous garbage output. Payload fields should be always parsed in big-endian (network ordering). BUG=none TEST=make; cbfstool image.bin print -v -v -v # see payloads correctly Original-Change-Id: If1ac355b8847fb54988069f694bd2f317ce49a1a Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200158 Original-Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 423f7dd28f8b071692d57401e144232d5ee2e479) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5a4694e887c7ff48d8d0713bb5808c29256141a9 Reviewed-on: http://review.coreboot.org/8005 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8005 for details. -gerrit

1 0

New patch to review for coreboot: feefc1b vendorcode/amd/agesa/fam16: Build as a static library
by Edward O'Callaghan 03 Jan '15

03 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8051 -gerrit commit feefc1b80b12725591fec7c219df8bbe8ce5ec56 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jan 4 02:13:00 2015 +1100 vendorcode/amd/agesa/fam16: Build as a static library Following the same reasoning as commit ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library Since AGESA is stage-independent, we can build it just once, and use the resulting static library in both rom and ram stages. Change-Id: I1d8c92008d2458b336fa8f51cae71c4cf29a01a7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f16kb/Makefile.inc | 417 +++++++++++++++++++++++++++- 1 file changed, 415 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/amd/agesa/f16kb/Makefile.inc b/src/vendorcode/amd/agesa/f16kb/Makefile.inc index 5ce7aee..c3071d7 100644 --- a/src/vendorcode/amd/agesa/f16kb/Makefile.inc +++ b/src/vendorcode/amd/agesa/f16kb/Makefile.inc @@ -1,7 +1,7 @@ #***************************************************************************** # -# Copyright (c) 2012, Advanced Micro Devices, Inc. -# All rights reserved. +# Copyright (c) 2012, Advanced Micro Devices, Inc. All rights reserved. +# Copyright (c) 2014, Edward O'Callaghan, <eocallaghan(a)alterapraxis.com>. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are met: @@ -84,3 +84,416 @@ export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC) CPPFLAGS_x86_32 += $(AGESA_INC) ####################################################################### + +classes-y += libagesa + +$(eval $(call create_class_compiler,libagesa,x86_32)) + +libagesa-y += Legacy/Proc/Dispatcher.c +libagesa-y += Legacy/Proc/agesaCallouts.c +libagesa-y += Legacy/Proc/hobTransfer.c +libagesa-y += Lib/amdlib.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbC6State.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbCoreAfterReset.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbCpb.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbDmi.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbEquivalenceTable.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbHtc.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbIoCstate.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbLogicalIdTables.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbMicrocodePatchTables.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbMsrTables.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbNbAfterReset.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbPciTables.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbPowerCheck.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbPowerMgmtSystemTables.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbPsi.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbPstate.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbSharedMsrTable.c +libagesa-y += Proc/CPU/Family/0x16/KB/F16KbUtilities.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16Apm.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16BrandId.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16CacheDefaults.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16Dmi.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16MmioMap.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16MsrUnknownTables.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16PciUnknownTables.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16Utilities.c +libagesa-y += Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c +libagesa-y += Proc/CPU/Feature/cpuApm.c +libagesa-y += Proc/CPU/Feature/cpuC6State.c +libagesa-y += Proc/CPU/Feature/cpuCacheFlushOnHalt.c +libagesa-y += Proc/CPU/Feature/cpuCacheInit.c +libagesa-y += Proc/CPU/Feature/cpuCdit.c +libagesa-y += Proc/CPU/Feature/cpuCoreLeveling.c +libagesa-y += Proc/CPU/Feature/cpuCpb.c +libagesa-y += Proc/CPU/Feature/cpuCrat.c +libagesa-y += Proc/CPU/Feature/cpuDmi.c +libagesa-y += Proc/CPU/Feature/cpuFeatureLeveling.c +libagesa-y += Proc/CPU/Feature/cpuFeatures.c +libagesa-y += Proc/CPU/Feature/cpuHtc.c +libagesa-y += Proc/CPU/Feature/cpuIoCstate.c +libagesa-y += Proc/CPU/Feature/cpuPsi.c +libagesa-y += Proc/CPU/Feature/cpuPstateGather.c +libagesa-y += Proc/CPU/Feature/cpuPstateLeveling.c +libagesa-y += Proc/CPU/Feature/cpuPstateTables.c +libagesa-y += Proc/CPU/Feature/cpuSlit.c +libagesa-y += Proc/CPU/Feature/cpuSrat.c +libagesa-y += Proc/CPU/Feature/cpuWhea.c +libagesa-y += Proc/CPU/S3.c +libagesa-y += Proc/CPU/Table.c +libagesa-y += Proc/CPU/cahalt.c +libagesa-y += Proc/CPU/cpuApicUtilities.c +libagesa-y += Proc/CPU/cpuBist.c +libagesa-y += Proc/CPU/cpuEarlyInit.c +libagesa-y += Proc/CPU/cpuEventLog.c +libagesa-y += Proc/CPU/cpuFamilyTranslation.c +libagesa-y += Proc/CPU/cpuGeneralServices.c +libagesa-y += Proc/CPU/cpuLateInit.c +libagesa-y += Proc/CPU/cpuMicrocodePatch.c +libagesa-y += Proc/CPU/cpuPostInit.c +libagesa-y += Proc/CPU/cpuPowerMgmt.c +libagesa-y += Proc/CPU/cpuPowerMgmtSingleSocket.c +libagesa-y += Proc/CPU/cpuWarmReset.c +libagesa-y += Proc/CPU/heapManager.c +libagesa-y += Proc/Common/AmdInitEarly.c +libagesa-y += Proc/Common/AmdInitEnv.c +libagesa-y += Proc/Common/AmdInitLate.c +libagesa-y += Proc/Common/AmdInitMid.c +libagesa-y += Proc/Common/AmdInitPost.c +libagesa-y += Proc/Common/AmdInitReset.c +libagesa-y += Proc/Common/AmdInitResume.c +libagesa-y += Proc/Common/AmdLateRunApTask.c +libagesa-y += Proc/Common/AmdS3LateRestore.c +libagesa-y += Proc/Common/AmdS3Save.c +libagesa-y += Proc/Common/CommonInits.c +libagesa-y += Proc/Common/CommonReturns.c +libagesa-y += Proc/Common/CreateStruct.c +libagesa-y += Proc/Common/S3RestoreState.c +libagesa-y += Proc/Common/S3SaveState.c +libagesa-y += Proc/Fch/Azalia/AzaliaEnv.c +libagesa-y += Proc/Fch/Azalia/AzaliaLate.c +libagesa-y += Proc/Fch/Azalia/AzaliaMid.c +libagesa-y += Proc/Fch/Azalia/AzaliaReset.c +libagesa-y += Proc/Fch/Common/AcpiLib.c +libagesa-y += Proc/Fch/Common/FchCommon.c +libagesa-y += Proc/Fch/Common/FchLib.c +libagesa-y += Proc/Fch/Common/FchPeLib.c +libagesa-y += Proc/Fch/Common/MemLib.c +libagesa-y += Proc/Fch/Common/PciLib.c +libagesa-y += Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiEnvService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiLateService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Yangtze/YangtzeHwAcpiMidService.c +libagesa-y += Proc/Fch/HwAcpi/Family/Yangtze/YangtzeSSService.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiEnv.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiLate.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiMid.c +libagesa-y += Proc/Fch/HwAcpi/HwAcpiReset.c +libagesa-y += Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmEnvService.c +libagesa-y += Proc/Fch/Hwm/Family/Yangtze/YangtzeHwmLateService.c +libagesa-y += Proc/Fch/Hwm/HwmLate.c +libagesa-y += Proc/Fch/Ide/IdeEnv.c +libagesa-y += Proc/Fch/Ide/IdeLate.c +libagesa-y += Proc/Fch/Ide/IdeMid.c +libagesa-y += Proc/Fch/Imc/Family/Yangtze/YangtzeImcService.c +libagesa-y += Proc/Fch/Imc/FchEcEnv.c +libagesa-y += Proc/Fch/Imc/FchEcLate.c +libagesa-y += Proc/Fch/Imc/FchEcMid.c +libagesa-y += Proc/Fch/Imc/ImcEnv.c +libagesa-y += Proc/Fch/Imc/ImcLate.c +libagesa-y += Proc/Fch/Imc/ImcLib.c +libagesa-y += Proc/Fch/Imc/ImcMid.c +libagesa-y += Proc/Fch/Imc/ImcReset.c +libagesa-y += Proc/Fch/Interface/Family/Yangtze/EnvDefYangtze.c +libagesa-y += Proc/Fch/Interface/Family/Yangtze/ResetDefYangtze.c +libagesa-y += Proc/Fch/Interface/FchInitEnv.c +libagesa-y += Proc/Fch/Interface/FchInitLate.c +libagesa-y += Proc/Fch/Interface/FchInitMid.c +libagesa-y += Proc/Fch/Interface/FchInitReset.c +libagesa-y += Proc/Fch/Interface/FchInitS3.c +libagesa-y += Proc/Fch/Interface/FchTaskLauncher.c +libagesa-y += Proc/Fch/Interface/InitEnvDef.c +libagesa-y += Proc/Fch/Interface/InitResetDef.c +libagesa-y += Proc/Fch/Pcie/AbEnv.c +libagesa-y += Proc/Fch/Pcie/AbLate.c +libagesa-y += Proc/Fch/Pcie/AbMid.c +libagesa-y += Proc/Fch/Pcie/AbReset.c +libagesa-y += Proc/Fch/Pcie/Family/Yangtze/YangtzeAbEnvService.c +libagesa-y += Proc/Fch/Pcie/Family/Yangtze/YangtzeAbResetService.c +libagesa-y += Proc/Fch/Pcie/Family/Yangtze/YangtzeAbService.c +libagesa-y += Proc/Fch/Pcie/PcieEnv.c +libagesa-y += Proc/Fch/Pcie/PcieLate.c +libagesa-y += Proc/Fch/Pcie/PcieMid.c +libagesa-y += Proc/Fch/Pcie/PcieReset.c +libagesa-y += Proc/Fch/Sata/AhciEnv.c +libagesa-y += Proc/Fch/Sata/AhciLate.c +libagesa-y += Proc/Fch/Sata/AhciLib.c +libagesa-y += Proc/Fch/Sata/AhciMid.c +libagesa-y += Proc/Fch/Sata/Family/Yangtze/YangtzeSataEnvService.c +libagesa-y += Proc/Fch/Sata/Family/Yangtze/YangtzeSataResetService.c +libagesa-y += Proc/Fch/Sata/Family/Yangtze/YangtzeSataService.c +libagesa-y += Proc/Fch/Sata/Ide2AhciEnv.c +libagesa-y += Proc/Fch/Sata/Ide2AhciLate.c +libagesa-y += Proc/Fch/Sata/Ide2AhciLib.c +libagesa-y += Proc/Fch/Sata/Ide2AhciMid.c +libagesa-y += Proc/Fch/Sata/RaidEnv.c +libagesa-y += Proc/Fch/Sata/RaidLate.c +libagesa-y += Proc/Fch/Sata/RaidLib.c +libagesa-y += Proc/Fch/Sata/RaidMid.c +libagesa-y += Proc/Fch/Sata/SataEnv.c +libagesa-y += Proc/Fch/Sata/SataEnvLib.c +libagesa-y += Proc/Fch/Sata/SataIdeEnv.c +libagesa-y += Proc/Fch/Sata/SataIdeLate.c +libagesa-y += Proc/Fch/Sata/SataIdeLib.c +libagesa-y += Proc/Fch/Sata/SataIdeMid.c +libagesa-y += Proc/Fch/Sata/SataLate.c +libagesa-y += Proc/Fch/Sata/SataLib.c +libagesa-y += Proc/Fch/Sata/SataMid.c +libagesa-y += Proc/Fch/Sata/SataReset.c +libagesa-y += Proc/Fch/Sd/Family/Yangtze/YangtzeSdEnvService.c +libagesa-y += Proc/Fch/Sd/Family/Yangtze/YangtzeSdResetService.c +libagesa-y += Proc/Fch/Sd/Family/Yangtze/YangtzeSdService.c +libagesa-y += Proc/Fch/Sd/SdEnv.c +libagesa-y += Proc/Fch/Sd/SdLate.c +libagesa-y += Proc/Fch/Sd/SdMid.c +libagesa-y += Proc/Fch/Spi/Family/Yangtze/YangtzeLpcEnvService.c +libagesa-y += Proc/Fch/Spi/Family/Yangtze/YangtzeLpcResetService.c +libagesa-y += Proc/Fch/Spi/LpcEnv.c +libagesa-y += Proc/Fch/Spi/LpcLate.c +libagesa-y += Proc/Fch/Spi/LpcMid.c +libagesa-y += Proc/Fch/Spi/LpcReset.c +libagesa-y += Proc/Fch/Spi/SpiEnv.c +libagesa-y += Proc/Fch/Spi/SpiLate.c +libagesa-y += Proc/Fch/Spi/SpiMid.c +libagesa-y += Proc/Fch/Spi/SpiReset.c +libagesa-y += Proc/Fch/Usb/EhciEnv.c +libagesa-y += Proc/Fch/Usb/EhciLate.c +libagesa-y += Proc/Fch/Usb/EhciMid.c +libagesa-y += Proc/Fch/Usb/EhciReset.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeEhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeEhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeEhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeOhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeOhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeOhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeXhciEnvService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeXhciLateService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeXhciMidService.c +libagesa-y += Proc/Fch/Usb/Family/Yangtze/YangtzeXhciResetService.c +libagesa-y += Proc/Fch/Usb/OhciEnv.c +libagesa-y += Proc/Fch/Usb/OhciLate.c +libagesa-y += Proc/Fch/Usb/OhciMid.c +libagesa-y += Proc/Fch/Usb/OhciReset.c +libagesa-y += Proc/Fch/Usb/UsbEnv.c +libagesa-y += Proc/Fch/Usb/UsbLate.c +libagesa-y += Proc/Fch/Usb/UsbMid.c +libagesa-y += Proc/Fch/Usb/UsbReset.c +libagesa-y += Proc/Fch/Usb/XhciEnv.c +libagesa-y += Proc/Fch/Usb/XhciLate.c +libagesa-y += Proc/Fch/Usb/XhciMid.c +libagesa-y += Proc/Fch/Usb/XhciReset.c +libagesa-y += Proc/GNB/Common/GnbLibFeatures.c +libagesa-y += Proc/GNB/GnbInitAtEarly.c +libagesa-y += Proc/GNB/GnbInitAtEnv.c +libagesa-y += Proc/GNB/GnbInitAtLate.c +libagesa-y += Proc/GNB/GnbInitAtMid.c +libagesa-y += Proc/GNB/GnbInitAtPost.c +libagesa-y += Proc/GNB/GnbInitAtReset.c +libagesa-y += Proc/GNB/GnbInitAtS3Save.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLib.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibCpuAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibHeap.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibIoAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibMemAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPci.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +libagesa-y += Proc/GNB/Modules/GnbCommonLib/GnbTimerLib.c +libagesa-y += Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +libagesa-y += Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigEnv.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigMid.c +libagesa-y += Proc/GNB/Modules/GnbGfxConfig/GfxConfigPost.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxCardInfo.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GfxEnumConnectors.c +libagesa-y += Proc/GNB/Modules/GnbGfxInitLibV1/GnbGfxInitLibV1.c +libagesa-y += Proc/GNB/Modules/GnbGfxIntTableV3/GfxIntegratedInfoTable.c +libagesa-y += Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c +libagesa-y += Proc/GNB/Modules/GnbGfxIntTableV3/GfxPwrPlayTable.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/AlibKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxEnvInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxGmcInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxIntegratedInfoTableKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxLibKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxMidInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxPostInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxSamuInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GfxTablesKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbEarlyInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbEnvInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbIommuTablesKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbMidInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbPostInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbRegisterAccKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbTablesKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbUraKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/GnbUraTokenMapKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieComplexDataKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieConfigKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieEarlyInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieEnvInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieLibKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieMidInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PciePostInitKB.c +libagesa-y += Proc/GNB/Modules/GnbInitKB/PcieTablesKB.c +libagesa-y += Proc/GNB/Modules/GnbIoapic/GnbIoapic.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV4/GnbNbInitLibV4.c +libagesa-y += Proc/GNB/Modules/GnbNbInitLibV5/GnbNbInitLibV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieAlibV2/PcieAlibV2.c +libagesa-y += Proc/GNB/Modules/GnbPcieAspm/PcieAspm.c +libagesa-y += Proc/GNB/Modules/GnbPcieClkPm/PcieClkPm.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/GnbHandleLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigData.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieConfigLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c +libagesa-y += Proc/GNB/Modules/GnbPcieConfig/PcieMapTopology.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieAspmBlackList.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePifServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PciePortServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTimer.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV1/PcieWrapperRegAcc.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PciePortServicesV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV4/PcieWrapperServicesV4.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV5/PciePhyServicesV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV5/PciePifServicesV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV5/PciePortServicesV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV5/PcieSiliconServicesV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV5/PcieTopologyServicesV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieInitLibV5/PcieWrapperServicesV5.c +libagesa-y += Proc/GNB/Modules/GnbPcieMaxPayload/PcieMaxPayload.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV2/PcieTrainingV2.c +libagesa-y += Proc/GNB/Modules/GnbPcieTrainingV2/PcieWorkaroundsV2.c +libagesa-y += Proc/GNB/Modules/GnbSSocketLib/GnbSSocketLib.c +libagesa-y += Proc/GNB/Modules/GnbSbLib/GnbSbLib.c +libagesa-y += Proc/GNB/Modules/GnbSbLib/GnbSbPcie.c +libagesa-y += Proc/GNB/Modules/GnbScsLibV1/GnbScsLibV1.c +libagesa-y += Proc/GNB/Modules/GnbSmuLibV7/GnbSmuInitLibV7.c +libagesa-y += Proc/GNB/Modules/GnbSview/GnbSview.c +libagesa-y += Proc/GNB/Modules/GnbTable/GnbTable.c +libagesa-y += Proc/GNB/Modules/GnbUraLibV1/GnbUraLibV1.c +libagesa-y += Proc/HT/Fam16/htNbFam16.c +libagesa-y += Proc/HT/Fam16/htNbUtilitiesFam16.c +libagesa-y += Proc/HT/htFeat.c +libagesa-y += Proc/HT/htInterface.c +libagesa-y += Proc/HT/htInterfaceCoherent.c +libagesa-y += Proc/HT/htInterfaceGeneral.c +libagesa-y += Proc/HT/htInterfaceNonCoherent.c +libagesa-y += Proc/HT/htMain.c +libagesa-y += Proc/HT/htNb.c +libagesa-y += Proc/HT/htNotify.c +libagesa-y += Proc/IDS/Debug/IdsDebug.c +libagesa-y += Proc/IDS/Debug/IdsDebugPrint.c +libagesa-y += Proc/IDS/Debug/IdsDpHdtout.c +libagesa-y += Proc/IDS/Debug/IdsDpSerial.c +libagesa-y += Proc/IDS/Family/0x16/KB/IdsF16KbAllService.c +libagesa-y += Proc/IDS/Library/IdsLib.c +libagesa-y += Proc/Mem/Ardk/ma.c +libagesa-y += Proc/Mem/Feat/CSINTLV/mfcsi.c +libagesa-y += Proc/Mem/Feat/DMI/mfDMI.c +libagesa-y += Proc/Mem/Feat/ECC/mfecc.c +libagesa-y += Proc/Mem/Feat/ECC/mfemp.c +libagesa-y += Proc/Mem/Feat/EXCLUDIMM/mfdimmexclud.c +libagesa-y += Proc/Mem/Feat/IDENDIMM/mfidendimm.c +libagesa-y += Proc/Mem/Feat/LVDDR3/mflvddr3.c +libagesa-y += Proc/Mem/Feat/MEMCLR/mfmemclr.c +libagesa-y += Proc/Mem/Feat/ODTHERMAL/mfodthermal.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfParallelTraining.c +libagesa-y += Proc/Mem/Feat/PARTRN/mfStandardTraining.c +libagesa-y += Proc/Mem/Feat/RDWR2DTRAINING/KB/mfRdWr2DKb.c +libagesa-y += Proc/Mem/Feat/RDWR2DTRAINING/mfRdDqs2DTraining.c +libagesa-y += Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DEyeRimSearch.c +libagesa-y += Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DPatternGeneration.c +libagesa-y += Proc/Mem/Feat/RDWR2DTRAINING/mfRdWr2DTraining.c +libagesa-y += Proc/Mem/Feat/S3/mfs3.c +libagesa-y += Proc/Mem/Feat/TABLE/mftds.c +libagesa-y += Proc/Mem/Main/KB/mmflowkb.c +libagesa-y += Proc/Mem/Main/mdef.c +libagesa-y += Proc/Mem/Main/merrhdl.c +libagesa-y += Proc/Mem/Main/minit.c +libagesa-y += Proc/Mem/Main/mm.c +libagesa-y += Proc/Mem/Main/mmConditionalPso.c +libagesa-y += Proc/Mem/Main/mmEcc.c +libagesa-y += Proc/Mem/Main/mmExcludeDimm.c +libagesa-y += Proc/Mem/Main/mmLvDdr3.c +libagesa-y += Proc/Mem/Main/mmMemClr.c +libagesa-y += Proc/Mem/Main/mmMemRestore.c +libagesa-y += Proc/Mem/Main/mmNodeInterleave.c +libagesa-y += Proc/Mem/Main/mmOnlineSpare.c +libagesa-y += Proc/Mem/Main/mmParallelTraining.c +libagesa-y += Proc/Mem/Main/mmStandardTraining.c +libagesa-y += Proc/Mem/Main/mmUmaAlloc.c +libagesa-y += Proc/Mem/Main/mmflow.c +libagesa-y += Proc/Mem/Main/mu.c +libagesa-y += Proc/Mem/Main/muc.c +libagesa-y += Proc/Mem/NB/KB/mndctkb.c +libagesa-y += Proc/Mem/NB/KB/mnflowkb.c +libagesa-y += Proc/Mem/NB/KB/mnidendimmkb.c +libagesa-y += Proc/Mem/NB/KB/mnkb.c +libagesa-y += Proc/Mem/NB/KB/mnmctkb.c +libagesa-y += Proc/Mem/NB/KB/mnotkb.c +libagesa-y += Proc/Mem/NB/KB/mnphykb.c +libagesa-y += Proc/Mem/NB/KB/mnregkb.c +libagesa-y += Proc/Mem/NB/KB/mns3kb.c +libagesa-y += Proc/Mem/NB/mn.c +libagesa-y += Proc/Mem/NB/mnS3.c +libagesa-y += Proc/Mem/NB/mndct.c +libagesa-y += Proc/Mem/NB/mnfeat.c +libagesa-y += Proc/Mem/NB/mnflow.c +libagesa-y += Proc/Mem/NB/mnmct.c +libagesa-y += Proc/Mem/NB/mnphy.c +libagesa-y += Proc/Mem/NB/mnreg.c +libagesa-y += Proc/Mem/NB/mntrain3.c +libagesa-y += Proc/Mem/Ps/KB/FT3/mpSkbft3.c +libagesa-y += Proc/Mem/Ps/KB/mpSkb3.c +libagesa-y += Proc/Mem/Ps/KB/mpUkb3.c +libagesa-y += Proc/Mem/Ps/KB/mpkb3.c +libagesa-y += Proc/Mem/Ps/mp.c +libagesa-y += Proc/Mem/Ps/mpmaxfreq.c +libagesa-y += Proc/Mem/Ps/mpmr0.c +libagesa-y += Proc/Mem/Ps/mpodtpat.c +libagesa-y += Proc/Mem/Ps/mprtt.c +libagesa-y += Proc/Mem/Ps/mps2d.c +libagesa-y += Proc/Mem/Ps/mpsao.c +libagesa-y += Proc/Mem/Tech/DDR3/mt3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtot3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtrci3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtsdi3.c +libagesa-y += Proc/Mem/Tech/DDR3/mtspd3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttecc3.c +libagesa-y += Proc/Mem/Tech/DDR3/mttwl3.c +libagesa-y += Proc/Mem/Tech/mt.c +libagesa-y += Proc/Mem/Tech/mthdi.c +libagesa-y += Proc/Mem/Tech/mttEdgeDetect.c +libagesa-y += Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c +libagesa-y += Proc/Mem/Tech/mttRdDqs2DTraining.c +libagesa-y += Proc/Mem/Tech/mttdimbt.c +libagesa-y += Proc/Mem/Tech/mttecc.c +libagesa-y += Proc/Mem/Tech/mtthrc.c +libagesa-y += Proc/Mem/Tech/mtthrcSeedTrain.c +libagesa-y += Proc/Mem/Tech/mttml.c +libagesa-y += Proc/Mem/Tech/mttoptsrc.c +libagesa-y += Proc/Mem/Tech/mttsrc.c + +$(obj)/libagesa.fam16kb.a: $$(libagesa-objs) + @printf " AGESA $(subst $(obj)/,,$(@))\n" + ar rcs $@ $+ + +romstage-libs += $(obj)/libagesa.fam16kb.a +ramstage-libs += $(obj)/libagesa.fam16kb.a

1 0

Patch set updated for coreboot: 7034bb9 hp/abm: Add new mainboard
by Kyösti Mälkki 03 Jan '15

03 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6116 -gerrit commit 7034bb9761a69c47e644b1aa7cfff11f17d21eae Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jun 5 11:49:04 2014 -0600 hp/abm: Add new mainboard The hp/abm board is used in network/server applications. Notes: - The hp/abm board is headless and therefore does not define CONFIG_GFXUMA, and does not require a video bios. - The micro USB connector on the board edge is connected to COM4 (i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3. - If you are using SeaBIOS it would also need to be configured to use the UART at I/O=2E8h. - This board has been tested with headless installed versions of Ubuntu 12.10 and Fedora 19. Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/hp/Kconfig | 3 + src/mainboard/hp/abm/BiosCallOuts.c | 256 +------------------------------- src/mainboard/hp/abm/Kconfig | 31 ++-- src/mainboard/hp/abm/OptionsIds.h | 5 +- src/mainboard/hp/abm/PlatformGnbPcie.c | 9 +- src/mainboard/hp/abm/acpi/mainboard.asl | 7 +- src/mainboard/hp/abm/acpi/usb_oc.asl | 2 +- src/mainboard/hp/abm/board_info.txt | 5 + src/mainboard/hp/abm/buildOpts.c | 28 ++-- src/mainboard/hp/abm/cmos.layout | 2 +- src/mainboard/hp/abm/devicetree.cb | 82 ++++------ src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/abm/irq_tables.c | 2 +- src/mainboard/hp/abm/mainboard.c | 93 +++++++++++- src/mainboard/hp/abm/mptable.c | 2 +- src/mainboard/hp/abm/romstage.c | 49 +++--- 16 files changed, 187 insertions(+), 391 deletions(-) diff --git a/src/mainboard/hp/Kconfig b/src/mainboard/hp/Kconfig index 4b391ad..3efd1dd 100644 --- a/src/mainboard/hp/Kconfig +++ b/src/mainboard/hp/Kconfig @@ -3,6 +3,8 @@ if VENDOR_HP choice prompt "Mainboard model" +config BOARD_HP_ABM + bool "ABM" config BOARD_HP_DL145_G1 bool "ProLiant DL145 G1" config BOARD_HP_DL145_G3 @@ -17,6 +19,7 @@ config BOARD_HP_PAVILION_M6_1035DX endchoice +source "src/mainboard/hp/abm/Kconfig" source "src/mainboard/hp/dl145_g1/Kconfig" source "src/mainboard/hp/dl145_g3/Kconfig" source "src/mainboard/hp/dl165_g6_fam10/Kconfig" diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 53b6871..d55bc06 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/azalia.h> #include "AGESA.h" #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> @@ -48,257 +48,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /** - * CODEC Initialization Table for Azalia HD Audio using Realtek ALC662 chip - */ -static const CODEC_ENTRY Alc662_VerbTbl[] = -{ - { 0x14, /*01014010*/ /* Port D - green headphone jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_LINEOUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_GREEN << 12) - | (1 << 4) - | (0 << 0) - }, - { 0x15, /*0x90170120*/ /* Port A - white speaker header */ - (AZALIA_PINCFG_PORT_FIXED << 30) - | (AZALIA_PINCFG_LOCATION_INTERNAL << 24) - | (AZALIA_PINCFG_DEVICE_SPEAKER << 20) - | (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16) - | (AZALIA_PINCFG_COLOR_WHITE << 12) - | (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) - | (2 << 4) - | (0 << 0) - }, - { 0x16, 0x411111F0 }, /* Port G - not connected */ - { 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_PINK << 12) - | (4 << 4) - | (0 << 0) - }, - { 0x19, /*0x02A19050*/ /* Port F - front panel header mic */ - (AZALIA_PINCFG_PORT_NC << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_PINK << 12) - | (5 << 4) - | (0 << 0) - }, - { 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */ - (AZALIA_PINCFG_PORT_NC << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_LINEIN << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_BLUE << 12) - | (4 << 4) - | (0xF << 0) - }, - { 0x1B, /*0x02214030*/ /* Port E - front panel line-out */ - (AZALIA_PINCFG_PORT_NC << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) - | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_GREEN << 12) - | (3 << 4) - | (0 << 0) - }, - { 0x1C, 0x411111F0 }, /* CD-in - Not Connected */ - { 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */ - { 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */ - { 0xFF, 0xFFFFFFFF }, -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0662, (CODEC_ENTRY*)Alc662_VerbTbl}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* imb_a180 Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -#if 0 -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /* temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* imb_a180 FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* imb_a180 FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommand way */ -#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - -#else /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - -#endif /* CONFIG_HUDSON_IMC_FWM */ -} -#endif - -/** * Fch Oem setting callback * * Configure platform specific Hudson device, @@ -318,12 +67,9 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList; /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ - //oem_fan_control(FchParams_env); /* XHCI configuration */ FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index f88ce04..83ce7a8 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -1,7 +1,8 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012-2014 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,29 +18,27 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_ASROCK_IMB_A180 +if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_WINBOND_W83627UHG + select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA + select BOARD_ROMSIZE_KB_8192 config MAINBOARD_DIR string - default asrock/imb-a180 + default hp/abm config MAINBOARD_PART_NUMBER string - default "IMB-A180" + default "ABM" config HW_MEM_HOLE_SIZEK hex @@ -57,20 +56,8 @@ config IRQ_SLOT_COUNT int default 11 -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config HUDSON_LEGACY_FREE bool - default y - -# bit 1,0 - pin 0 -# bit 3,2 - pin 1 -# bit 5,4 - pin 2 -# bit 7,6 - pin 3 -config AZ_PIN - hex - default 0x2 + default n -endif # BOARD_ASROCK_IMB_A180 +endif # BOARD_HP_ABM diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h index 0a1d328..5880030 100644 --- a/src/mainboard/hp/abm/OptionsIds.h +++ b/src/mainboard/hp/abm/OptionsIds.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /** @@ -64,4 +65,4 @@ //#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80 -#endif +#endif /* _OPTION_IDS_H_ */ diff --git a/src/mainboard/hp/abm/PlatformGnbPcie.c b/src/mainboard/hp/abm/PlatformGnbPcie.c index da1910e..36dfb13 100644 --- a/src/mainboard/hp/abm/PlatformGnbPcie.c +++ b/src/mainboard/hp/abm/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,16 +89,10 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { }, /* DP1 to FCH */ { - 0, + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) - }, }; static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { diff --git a/src/mainboard/hp/abm/acpi/mainboard.asl b/src/mainboard/hp/abm/acpi/mainboard.asl index 05523fb..ca3fd6e 100644 --- a/src/mainboard/hp/abm/acpi/mainboard.asl +++ b/src/mainboard/hp/abm/acpi/mainboard.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,7 +35,4 @@ Name(PMOD, One) /* Assume APIC */ /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} + Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl index 7b5b1c6..4d9af01 100644 --- a/src/mainboard/hp/abm/acpi/usb_oc.asl +++ b/src/mainboard/hp/abm/acpi/usb_oc.asl @@ -41,7 +41,7 @@ Name(UOM9, 6) /* USB Overcurrent GPEs */ -#if 0 /* TODO: Update for imba180 */ +#if 0 /* TODO: Update */ Method(UCOC, 0) { Sleep(20) Store(0x13,CMTI) diff --git a/src/mainboard/hp/abm/board_info.txt b/src/mainboard/hp/abm/board_info.txt new file mode 100644 index 0000000..38fedd5 --- /dev/null +++ b/src/mainboard/hp/abm/board_info.txt @@ -0,0 +1,5 @@ +Category: mini +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 06199e0..8ceb3e6 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,7 +77,7 @@ #define BLDOPT_REMOVE_SRAT FALSE //TRUE #define BLDOPT_REMOVE_SLIT FALSE //TRUE #define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE @@ -153,7 +154,7 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE @@ -344,11 +345,20 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33 -GPIO_CONTROL imba180_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, +GPIO_CONTROL hp_abm_gpio[] = { + { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED + { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID + { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH + { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT + { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L + { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC + { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L + { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT + { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT + { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0]) // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product @@ -441,11 +451,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A), - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS (LAYERS_4), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), + MOTHER_BOARD_LAYERS (LAYERS_6), - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index f6b5806..5520564 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -15,7 +15,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #***************************************************************************** entries diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index 6d6875d..eb18a05 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2013 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -28,76 +29,55 @@ chip northbridge/amd/agesa/family16kb/root_complex chip northbridge/amd/agesa/family16kb # CPU side of HT root complex chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 off end # unused + device pci 2.2 on end # GPP0: NIC + device pci 2.3 on end # GPP1: NIC + device pci 2.4 off end # GPP2: unused + device pci 2.5 off end # GPP3: unused end #chip northbridge/amd/agesa/family16kb chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627uhg - device pnp 2e.0 off end # FDC - device pnp 2e.1 off end # LPT1 - device pnp 2e.2 on # COM1 + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + device pnp 4e.0 off end # FDC + device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 4e.3 on # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # KEYBRD - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HWMON - device pnp 2e.c off end # PECI - device pnp 2e.d on # COM4 + device pnp 4e.7 off end # GPIO + device pnp 4e.8 off end # GPIO/WDT + device pnp 4e.f off end # GPIO + device pnp 4e.10 off end # COM3 used by port 80 + device pnp 4e.11 on # COM4 io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.e on # COM5 - io 0x60 = 0x3e0 - irq 0x70 = 4 - end - device pnp 2e.f on # COM6 - io 0x60 = 0x2e0 - irq 0x70 = 3 - end - end # w83627uhg - end # LPC 0x439d - device pci 14.7 on end # SD + device pnp 4e.14 off end # PORT80 + register "irq_trigger_type" = "0" # 0 edge, 1 level + end # nct5104d + end #LPC + device pci 14.7 off end # SD + device pci 16.0 on end # USB + device pci 16.2 on end # USB end #chip southbridge/amd/hudson device pci 18.0 on end @@ -108,10 +88,8 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 18.5 on end register "spdAddrLookup" = " { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index cecaa59..d2d8122 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* DefinitionBlock Statement */ diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index c1c25ba..22ed1ab 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index cf02528..adb7093 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,16 +22,97 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> +#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <northbridge/amd/agesa/family16kb/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */ + [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */ + [0x40] = 0x0B,0x0B, /* IDE, SATA */ +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */ + [0x40] = 0x11,0x13, /* IDE, SATA */ +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCIB: 14.4 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/* TODO: mainboard specific SB AGESA callback */ +void set_pcie_reset(void) +{ +} + +/* TODO: mainboard specific SB AGESA callback */ +void set_pcie_dereset(void) +{ +} /********************************************** - * enable the dedicated function in mainboard. + * Enable the dedicated functions of the board. **********************************************/ static void mainboard_enable(device_t dev) { @@ -38,6 +120,9 @@ static void mainboard_enable(device_t dev) if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index d9ca7b7..629888a 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 1ba1104..5e3044a 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <stdint.h> @@ -31,29 +32,21 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" -#include "cbmem.h" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627uhg/w83627uhg.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> +#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u32 *addr32; - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - //outb(0xD2, 0xcd6); - //outb(0x00, 0xcd7); amd_initmmio(); @@ -65,27 +58,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + outb(0x01, 0xcd7); - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; t32 = *addr32; - t32 &= 0xfff8ffff; + t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + t32 |= 0x00010000; // Set bit 16 for 25MHz *addr32 = t32; - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + /* Enable Auxiliary OSCOUT1/OSCOUT2 */ addr32 = (u32 *)0xfed80e40; t32 = *addr32; - t32 &= 0xffffbffb; + t32 &= 0xffffff7b; // clear 2, 7 *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); - /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } @@ -98,11 +92,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); - post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38);

1 0

Patch set updated for coreboot: 9c66e12 hp/abm: Add new mainboard (incrementally)
by Kyösti Mälkki 03 Jan '15

03 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6116 -gerrit commit 9c66e12ba21db05e13f234121917939fbedd5ec6 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Thu Jun 5 11:49:04 2014 -0600 hp/abm: Add new mainboard (incrementally) The hp/abm board is used in network/server applications. Notes: - The hp/abm board is headless and therefore does not define CONFIG_GFXUMA, and does not require a video bios. - The micro USB connector on the board edge is connected to COM4 (i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3. - If you are using SeaBIOS it would also need to be configured to use the UART at I/O=2E8h. - This board has been tested with headless installed versions of Ubuntu 12.10 and Fedora 19. Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/hp/abm/BiosCallOuts.c | 256 +------------------------------- src/mainboard/hp/abm/Kconfig | 31 ++-- src/mainboard/hp/abm/OptionsIds.h | 5 +- src/mainboard/hp/abm/PlatformGnbPcie.c | 9 +- src/mainboard/hp/abm/acpi/mainboard.asl | 7 +- src/mainboard/hp/abm/acpi/usb_oc.asl | 2 +- src/mainboard/hp/abm/board_info.txt | 5 + src/mainboard/hp/abm/buildOpts.c | 28 ++-- src/mainboard/hp/abm/cmos.layout | 2 +- src/mainboard/hp/abm/devicetree.cb | 82 ++++------ src/mainboard/hp/abm/dsdt.asl | 2 +- src/mainboard/hp/abm/irq_tables.c | 2 +- src/mainboard/hp/abm/mainboard.c | 93 +++++++++++- src/mainboard/hp/abm/mptable.c | 2 +- src/mainboard/hp/abm/romstage.c | 50 +++---- 15 files changed, 184 insertions(+), 392 deletions(-) diff --git a/src/mainboard/hp/abm/BiosCallOuts.c b/src/mainboard/hp/abm/BiosCallOuts.c index 53b6871..d55bc06 100644 --- a/src/mainboard/hp/abm/BiosCallOuts.c +++ b/src/mainboard/hp/abm/BiosCallOuts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/azalia.h> #include "AGESA.h" #include "amdlib.h" #include <northbridge/amd/agesa/BiosCallOuts.h> @@ -48,257 +48,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); /** - * CODEC Initialization Table for Azalia HD Audio using Realtek ALC662 chip - */ -static const CODEC_ENTRY Alc662_VerbTbl[] = -{ - { 0x14, /*01014010*/ /* Port D - green headphone jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_LINEOUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_GREEN << 12) - | (1 << 4) - | (0 << 0) - }, - { 0x15, /*0x90170120*/ /* Port A - white speaker header */ - (AZALIA_PINCFG_PORT_FIXED << 30) - | (AZALIA_PINCFG_LOCATION_INTERNAL << 24) - | (AZALIA_PINCFG_DEVICE_SPEAKER << 20) - | (AZALIA_PINCFG_CONN_OTHER_ANALOG << 16) - | (AZALIA_PINCFG_COLOR_WHITE << 12) - | (AZALIA_PINCFG_MISC_IGNORE_PRESENCE << 8) - | (2 << 4) - | (0 << 0) - }, - { 0x16, 0x411111F0 }, /* Port G - not connected */ - { 0x18, /*0x01A19040*/ /* Port B - pink headphone jack */ - (AZALIA_PINCFG_PORT_JACK << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_PINK << 12) - | (4 << 4) - | (0 << 0) - }, - { 0x19, /*0x02A19050*/ /* Port F - front panel header mic */ - (AZALIA_PINCFG_PORT_NC << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) - | (AZALIA_PINCFG_DEVICE_MICROPHONE << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_PINK << 12) - | (5 << 4) - | (0 << 0) - }, - { 0x1A, /*0x0181304F*/ /* Port C - NL blue headphone jack */ - (AZALIA_PINCFG_PORT_NC << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_REAR) << 24) - | (AZALIA_PINCFG_DEVICE_LINEIN << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_BLUE << 12) - | (4 << 4) - | (0xF << 0) - }, - { 0x1B, /*0x02214030*/ /* Port E - front panel line-out */ - (AZALIA_PINCFG_PORT_NC << 30) - | ((AZALIA_PINCFG_LOCATION_EXTERNAL | AZALIA_PINCFG_LOCATION_FRONT) << 24) - | (AZALIA_PINCFG_DEVICE_HP_OUT << 20) - | (AZALIA_PINCFG_CONN_MINI_HEADPHONE_JACK << 16) - | (AZALIA_PINCFG_COLOR_GREEN << 12) - | (3 << 4) - | (0 << 0) - }, - { 0x1C, 0x411111F0 }, /* CD-in - Not Connected */ - { 0x1D, 0x411111F0 }, /* PC Beep - Not Connected */ - { 0x1E, 0x411111F0 }, /* S/PDIF - Not connected */ - { 0xFF, 0xFFFFFFFF }, -}; - -static const CODEC_TBL_LIST CodecTableList[] = -{ - {0x10ec0662, (CODEC_ENTRY*)Alc662_VerbTbl}, - {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} -}; - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF - -/* imb_a180 Hardware Monitor Fan Control - * Hardware limitation: - * HWM failed to read the input temperture vi I2C, - * if other software switch the I2C switch by mistake or intention. - * We recommend to using IMC to control Fans, instead of HWM. - */ -#if 0 -static void oem_fan_control(FCH_DATA_BLOCK *FchParams) -{ - FCH_HWM_FAN_CTR oem_factl[5] = { - /* temperature input, fan mode, frequency, low_duty, med_duty, multiplier, lowtemp, medtemp, hightemp, LinearRange, LinearHoldCount */ - /* imb_a180 FanOUT0 Fan header J32 */ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - /* imb_a180 FanOUT1 Fan header J31*/ - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - {FAN_INPUT_INTERNAL_DIODE, (FAN_STEPMODE | FAN_POLARITY_HIGH), FREQ_100HZ, 40, 60, 0, 40, 65, 85, 0, 0}, - }; - LibAmdMemCopy ((VOID *)(FchParams->Hwm.HwmFanControl), &oem_factl, (sizeof (FCH_HWM_FAN_CTR) * 5), FchParams->StdHeader); - - /* Enable IMC fan control. the recommand way */ -#if defined CONFIG_HUDSON_IMC_FWM && (CONFIG_HUDSON_IMC_FWM == 1) - /* HwMonitorEnable = TRUE && HwmFchtsiAutoOpll ==FALSE to call FchECfancontrolservice */ - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = FALSE;/* 0 disable, 1 enable TSI Auto Polling */ - - FchParams->Imc.ImcEnable = TRUE; - FchParams->Hwm.HwmControl = 1; /* 1 IMC, 0 HWM */ - FchParams->Imc.ImcEnableOverWrite = 1; /* 2 disable IMC , 1 enable IMC, 0 following hw strap setting */ - - LibAmdMemFill(&(FchParams->Imc.EcStruct), 0, sizeof(FCH_EC), FchParams->StdHeader); - - /* Thermal Zone Parameter */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg2 = 0x00; //BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg3 = 0x00;//6 | BIT3; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone0MsgReg9 = 0; - - /* IMC Fan Policy temperature thresholds */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg2 = 0;///80; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg3 = 0; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone0MsgRegB = 0x00; - - /* IMC Fan Policy PWM Settings */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg1 = 0x00; /* Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone0MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg1 = 0x01; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg2 = 0x55;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg3 = 0x17; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg6 = 0x90; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone1MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg1 = 0x01; /* zone */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg2 = 60; /*AC0 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg3 = 40; /*AC1 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg4 = 0; /*AC2 threshold in Celsius */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg5 = 0; /*AC3 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg6 = 0; /*AC4 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg7 = 0; /*AC5 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg8 = 0; /*AC6 threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgReg9 = 0; /*AC7 lowest threshold in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegA = 0; /*critical threshold* in Celsius, 0xFF is not define */ - FchParams->Imc.EcStruct.MsgFun83Zone1MsgRegB = 0x00; - - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg1 = 0x01; /*Zone */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg2 = 0; /* AL0 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg3 = 0; /* AL1 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg4 = 0; /* AL2 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg5 = 0x00; /* AL3 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg6 = 0x00; /* AL4 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg7 = 0x00; /* AL5 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg8 = 0x00; /* AL6 percentage */ - FchParams->Imc.EcStruct.MsgFun85Zone1MsgReg9 = 0x00; /* AL7 percentage */ - - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg1 = 0x2; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg6 = 0x98; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg7 = 2; - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg8 = 5; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone2MsgReg9 = 0; - - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg0 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg1 = 0x3; /* Zone */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg2 = 0x0;//BIT0 | BIT2 | BIT5; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg3 = 0x0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg4 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg5 = 0x00; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg6 = 0x0; /* SMBUS Address for SMBUS based temperature sensor such as SB-TSI and ADM1032 */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg7 = 0; - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg8 = 0; /* PWM steping rate in unit of PWM level percentage */ - FchParams->Imc.EcStruct.MsgFun81Zone3MsgReg9 = 0; - - /* IMC Function */ - FchParams->Imc.EcStruct.IMCFUNSupportBitMap = 0x333;//BIT0 | BIT4 |BIT8; - - /* NOTE: - * FchInitLateHwm will overwrite the EcStruct with EcDefaultMassege, - * AGESA put EcDefaultMassege as global data in ROM, so we can't overwride it. - * so we remove it from AGESA code. Please Seee FchInitLateHwm. - */ - -#else /* HWM fan control, the way not recommand */ - FchParams->Imc.ImcEnable = FALSE; - FchParams->Hwm.HwMonitorEnable = TRUE; - FchParams->Hwm.HwmFchtsiAutoPoll = TRUE;/* 1 enable, 0 disable TSI Auto Polling */ - -#endif /* CONFIG_HUDSON_IMC_FWM */ -} -#endif - -/** * Fch Oem setting callback * * Configure platform specific Hudson device, @@ -318,12 +67,9 @@ static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST*)CodecTableList; /* Azalia Controller Front Panel OEM Table Pointer */ /* Fan Control */ - //oem_fan_control(FchParams_env); /* XHCI configuration */ FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); diff --git a/src/mainboard/hp/abm/Kconfig b/src/mainboard/hp/abm/Kconfig index f88ce04..83ce7a8 100644 --- a/src/mainboard/hp/abm/Kconfig +++ b/src/mainboard/hp/abm/Kconfig @@ -1,7 +1,8 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012-2014 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,29 +18,27 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # -if BOARD_ASROCK_IMB_A180 +if BOARD_HP_ABM config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE - select SUPERIO_WINBOND_W83627UHG + select SUPERIO_NUVOTON_NCT5104D select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES - select BOARD_ROMSIZE_KB_4096 - select GFXUMA + select BOARD_ROMSIZE_KB_8192 config MAINBOARD_DIR string - default asrock/imb-a180 + default hp/abm config MAINBOARD_PART_NUMBER string - default "IMB-A180" + default "ABM" config HW_MEM_HOLE_SIZEK hex @@ -57,20 +56,8 @@ config IRQ_SLOT_COUNT int default 11 -config ONBOARD_VGA_IS_PRIMARY - bool - default y - config HUDSON_LEGACY_FREE bool - default y - -# bit 1,0 - pin 0 -# bit 3,2 - pin 1 -# bit 5,4 - pin 2 -# bit 7,6 - pin 3 -config AZ_PIN - hex - default 0x2 + default n -endif # BOARD_ASROCK_IMB_A180 +endif # BOARD_HP_ABM diff --git a/src/mainboard/hp/abm/OptionsIds.h b/src/mainboard/hp/abm/OptionsIds.h index 0a1d328..5880030 100644 --- a/src/mainboard/hp/abm/OptionsIds.h +++ b/src/mainboard/hp/abm/OptionsIds.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /** @@ -64,4 +65,4 @@ //#define IDSOPT_HOST_HDT FALSE //#define IDS_DEBUG_PORT 0x80 -#endif +#endif /* _OPTION_IDS_H_ */ diff --git a/src/mainboard/hp/abm/PlatformGnbPcie.c b/src/mainboard/hp/abm/PlatformGnbPcie.c index da1910e..36dfb13 100644 --- a/src/mainboard/hp/abm/PlatformGnbPcie.c +++ b/src/mainboard/hp/abm/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -88,16 +89,10 @@ static const PCIe_DDI_DESCRIPTOR DdiList [] = { }, /* DP1 to FCH */ { - 0, + DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2) }, - /* DP2 to HDMI1/DP */ - { - DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 16, 19), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeCrt, Aux3, Hdp3) - }, }; static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { diff --git a/src/mainboard/hp/abm/acpi/mainboard.asl b/src/mainboard/hp/abm/acpi/mainboard.asl index 05523fb..ca3fd6e 100644 --- a/src/mainboard/hp/abm/acpi/mainboard.asl +++ b/src/mainboard/hp/abm/acpi/mainboard.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -35,7 +35,4 @@ Name(PMOD, One) /* Assume APIC */ /* AcpiGpe0Blk */ OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) - Field(GP0B, ByteAcc, NoLock, Preserve) { - , 11, - USBS, 1, -} + Field(GP0B, ByteAcc, NoLock, Preserve) { , 11, USBS, 1, } diff --git a/src/mainboard/hp/abm/acpi/usb_oc.asl b/src/mainboard/hp/abm/acpi/usb_oc.asl index 7b5b1c6..4d9af01 100644 --- a/src/mainboard/hp/abm/acpi/usb_oc.asl +++ b/src/mainboard/hp/abm/acpi/usb_oc.asl @@ -41,7 +41,7 @@ Name(UOM9, 6) /* USB Overcurrent GPEs */ -#if 0 /* TODO: Update for imba180 */ +#if 0 /* TODO: Update */ Method(UCOC, 0) { Sleep(20) Store(0x13,CMTI) diff --git a/src/mainboard/hp/abm/board_info.txt b/src/mainboard/hp/abm/board_info.txt new file mode 100644 index 0000000..38fedd5 --- /dev/null +++ b/src/mainboard/hp/abm/board_info.txt @@ -0,0 +1,5 @@ +Category: mini +ROM package: SOIC8 +ROM protocol: SPI +ROM socketed: y +Flashrom support: y diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 06199e0..8ceb3e6 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -76,7 +77,7 @@ #define BLDOPT_REMOVE_SRAT FALSE //TRUE #define BLDOPT_REMOVE_SLIT FALSE //TRUE #define BLDOPT_REMOVE_WHEA FALSE //TRUE -#define BLDOPT_REMOVE_CRAT TRUE +#define BLDOPT_REMOVE_CRAT TRUE #define BLDOPT_REMOVE_CDIT TRUE #define BLDOPT_REMOVE_DMI TRUE //#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE @@ -153,7 +154,7 @@ #define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul #define BLDCFG_1GB_ALIGN FALSE #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED -#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO +#define BLDCFG_UMA_ALLOCATION_MODE UMA_NONE #define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled #define BLDCFG_IOMMU_SUPPORT FALSE #define OPTION_GFX_INIT_SVIEW FALSE @@ -344,11 +345,20 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE //#define BLDCFG_IR_PIN_CONTROL 0x33 -GPIO_CONTROL imba180_gpio[] = { - {183, Function1, GpioIn | GpioOutEnB | PullUpB}, +GPIO_CONTROL hp_abm_gpio[] = { + { 45, Function2, GpioOutEnB | Sticky }, // Signal input APU_SD_LED + { 49, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_UID + { 50, Function2, PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_HEALTH + { 51, Function2, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_ABM_LED_FAULT + { 57, Function2, GpioOutEnB | Sticky }, // Signal input SATA_PRSNT_L + { 58, Function2, GpioOutEnB | Sticky }, // Signal i/o APU_HDMI_CEC + { 64, Function2, GpioOutEnB | Sticky }, // Signal input SWC_APU_INT_L + { 68, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL1_PRSNT + { 69, Function0, GpioOutEnB | Sticky }, // Signal input CNTRL2_PRSNT + { 71, Function0, GpioOut | PullUpB | PullDown | Sticky }, // Signal output APU_PROCHOT_L_R {-1} }; -//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0]) +#define BLDCFG_FCH_GPIO_CONTROL_LIST (&hp_abm_gpio[0]) // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product @@ -441,11 +451,11 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A), - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 1), - MOTHER_BOARD_LAYERS (LAYERS_4), + NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, ONE_DIMM), + NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, ONE_DIMM), + MOTHER_BOARD_LAYERS (LAYERS_6), - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), /* TODO: bit2map, bit3map */ ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08), CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00), diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index f6b5806..5520564 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -15,7 +15,7 @@ # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software -# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA #***************************************************************************** entries diff --git a/src/mainboard/hp/abm/devicetree.cb b/src/mainboard/hp/abm/devicetree.cb index 6d6875d..eb18a05 100644 --- a/src/mainboard/hp/abm/devicetree.cb +++ b/src/mainboard/hp/abm/devicetree.cb @@ -2,6 +2,7 @@ # This file is part of the coreboot project. # # Copyright (C) 2013 Advanced Micro Devices, Inc. +# Copyright (C) 2014 Sage Electronic Engineering, LLC # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -28,76 +29,55 @@ chip northbridge/amd/agesa/family16kb/root_complex chip northbridge/amd/agesa/family16kb # CPU side of HT root complex chip northbridge/amd/agesa/family16kb # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # mPCIe slot - device pci 2.3 on end # Realtek NIC - device pci 2.4 on end # Edge Connector - device pci 2.5 on end # Edge Connector + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 off end # unused + device pci 2.2 on end # GPP0: NIC + device pci 2.3 on end # GPP1: NIC + device pci 2.4 off end # GPP2: unused + device pci 2.5 off end # GPP3: unused end #chip northbridge/amd/agesa/family16kb chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus - device pci 10.0 on end # XHCI HC0 device pci 11.0 on end # SATA device pci 12.0 on end # USB device pci 12.2 on end # USB device pci 13.0 on end # USB device pci 13.2 on end # USB device pci 14.0 on # SM - chip drivers/generic/generic #dimm 0-0-0 + chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end end # SM - device pci 14.2 on end # HDA 0x4383 - device pci 14.3 on - chip superio/winbond/w83627uhg - device pnp 2e.0 off end # FDC - device pnp 2e.1 off end # LPT1 - device pnp 2e.2 on # COM1 + device pci 14.2 off end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/nuvoton/nct5104d + device pnp 4e.0 off end # FDC + device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 on # COM2 + device pnp 4e.3 on # COM2 io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 2e.5 on # KEYBRD - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 on # COM3 - io 0x60 = 0x3e8 - irq 0x70 = 4 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO - device pnp 2e.a off end # ACPI - device pnp 2e.b off end # HWMON - device pnp 2e.c off end # PECI - device pnp 2e.d on # COM4 + device pnp 4e.7 off end # GPIO + device pnp 4e.8 off end # GPIO/WDT + device pnp 4e.f off end # GPIO + device pnp 4e.10 off end # COM3 used by port 80 + device pnp 4e.11 on # COM4 io 0x60 = 0x2e8 irq 0x70 = 3 end - device pnp 2e.e on # COM5 - io 0x60 = 0x3e0 - irq 0x70 = 4 - end - device pnp 2e.f on # COM6 - io 0x60 = 0x2e0 - irq 0x70 = 3 - end - end # w83627uhg - end # LPC 0x439d - device pci 14.7 on end # SD + device pnp 4e.14 off end # PORT80 + register "irq_trigger_type" = "0" # 0 edge, 1 level + end # nct5104d + end #LPC + device pci 14.7 off end # SD + device pci 16.0 on end # USB + device pci 16.2 on end # USB end #chip southbridge/amd/hudson device pci 18.0 on end @@ -108,10 +88,8 @@ chip northbridge/amd/agesa/family16kb/root_complex device pci 18.5 on end register "spdAddrLookup" = " { - { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses - { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + { {0xA0, 0x00}, {0x00, 0x00}, }, // socket 0 - Channel 0 - 8-bit SPD addresses }" - end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family16kb/root_complex diff --git a/src/mainboard/hp/abm/dsdt.asl b/src/mainboard/hp/abm/dsdt.asl index cecaa59..d2d8122 100644 --- a/src/mainboard/hp/abm/dsdt.asl +++ b/src/mainboard/hp/abm/dsdt.asl @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ /* DefinitionBlock Statement */ diff --git a/src/mainboard/hp/abm/irq_tables.c b/src/mainboard/hp/abm/irq_tables.c index c1c25ba..22ed1ab 100644 --- a/src/mainboard/hp/abm/irq_tables.c +++ b/src/mainboard/hp/abm/irq_tables.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> diff --git a/src/mainboard/hp/abm/mainboard.c b/src/mainboard/hp/abm/mainboard.c index cf02528..adb7093 100644 --- a/src/mainboard/hp/abm/mainboard.c +++ b/src/mainboard/hp/abm/mainboard.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,16 +22,97 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/amd/mtrr.h> -#include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include <cpu/amd/agesa/s3_resume.h> #include <northbridge/amd/agesa/agesawrapper.h> +#include <southbridge/amd/amd_pci_util.h> +#include <southbridge/amd/agesa/hudson/pci_devs.h> +#include <northbridge/amd/agesa/family16kb/pci_devs.h> + +void set_pcie_reset(void); +void set_pcie_dereset(void); + +/*********************************************************** + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + * + * These values are used by the PCI configuration space, + * MP Tables. TODO: Make ACPI use these values too. + */ +static const u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = { + [0x00] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A,0x0B, /* INTA# - INTH# */ + [0x08] = 0x00,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x1F,0x1F,0x1F,0x0A,0x1F,0x1F,0x1F,0x0A, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerfMon, SD */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ + [0x30] = 0x0A,0x0B,0x0A,0x0B,0x0A,0x0B,0x0A, /* USB Devs 18/19/20/22 INTA-C */ + [0x40] = 0x0B,0x0B, /* IDE, SATA */ +}; + +static const u8 mainboard_intr_data[FCH_INT_TABLE_SIZE] = { + [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ + [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x10, /* SCI, SMBUS0, ASF, HDA, FC, GEC, PerMon, SD */ + [0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F, /* IMC INT0 - 5 */ + [0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12, /* USB Devs 18/19/22/20 INTA-C */ + [0x40] = 0x11,0x13, /* IDE, SATA */ +}; + +/* + * This table defines the index into the picr/intr_data + * tables for each device. Any enabled device and slot + * that uses hardware interrupts should have an entry + * in this table to define its index into the FCH + * PCI_INTR register 0xC00/0xC01. This index will define + * the interrupt that it should use. Putting PIRQ_A into + * the PIN A index for a device will tell that device to + * use PIC IRQ 10 if it uses PIN A for its hardware INT. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + /* {PCI_devfn, {PIN A, PIN B, PIN C, PIN D}}, */ + {GFX_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_NC, PIRQ_NC}}, /* VGA: 01.0 */ + {NB_PCIE_PORT2_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.2 */ + {NB_PCIE_PORT3_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.3 */ + {NB_PCIE_PORT4_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.4 */ + {NB_PCIE_PORT5_DEVFN, {PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D}}, /* NIC: 02.5 */ + {SATA_DEVFN, {PIRQ_SATA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SATA: 11.0 */ + {OHCI1_DEVFN, {PIRQ_OHCI1, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI1: 12.0 */ + {EHCI1_DEVFN, {PIRQ_NC, PIRQ_EHCI1, PIRQ_NC, PIRQ_NC}}, /* EHCI1: 12.2 */ + {OHCI2_DEVFN, {PIRQ_OHCI2, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI2: 13.0 */ + {EHCI2_DEVFN, {PIRQ_NC, PIRQ_EHCI2, PIRQ_NC, PIRQ_NC}}, /* EHCI2: 13.2 */ + {SMBUS_DEVFN, {PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SMBUS: 14.0 */ + {HDA_DEVFN, {PIRQ_HDA, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* HDA: 14.2 */ + {SB_PCI_PORT_DEVFN, {PIRQ_H, PIRQ_E, PIRQ_F, PIRQ_G}}, /* PCIB: 14.4 */ + {SD_DEVFN, {PIRQ_SD, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* SD: 14.7 */ + {OHCI3_DEVFN, {PIRQ_OHCI3, PIRQ_NC, PIRQ_NC, PIRQ_NC}}, /* OHCI3: 16.0 */ + {EHCI3_DEVFN, {PIRQ_NC, PIRQ_EHCI3, PIRQ_NC, PIRQ_NC}}, /* EHCI3: 16.2 */ +}; + +/* PIRQ Setup */ +static void pirq_setup(void) +{ + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = sizeof(mainboard_pirq_data) / sizeof(struct pirq_struct); + intr_data_ptr = mainboard_intr_data; + picr_data_ptr = mainboard_picr_data; +} + +/* TODO: mainboard specific SB AGESA callback */ +void set_pcie_reset(void) +{ +} + +/* TODO: mainboard specific SB AGESA callback */ +void set_pcie_dereset(void) +{ +} /********************************************** - * enable the dedicated function in mainboard. + * Enable the dedicated functions of the board. **********************************************/ static void mainboard_enable(device_t dev) { @@ -38,6 +120,9 @@ static void mainboard_enable(device_t dev) if (acpi_is_wakeup_s3()) agesawrapper_fchs3earlyrestore(); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index d9ca7b7..629888a 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -14,7 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <console/console.h> diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 1ba1104..40572c1 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -14,14 +15,13 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <stdint.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,29 +31,21 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include "cpu/x86/bist.h" -#include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" -#include "cpu/amd/agesa/s3_resume.h" -#include "cbmem.h" -#include <superio/winbond/common/winbond.h> -#include <superio/winbond/w83627uhg/w83627uhg.h> - -#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <southbridge/amd/agesa/hudson/hudson.h> +#include <cpu/amd/agesa/s3_resume.h> +#include <cbmem.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct5104d/nct5104d.h> +#define SERIAL_DEV PNP_DEV(0x4E, NCT5104D_SP4) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u32 *addr32; - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA - * even though the register is not documented in the Kabini BKDG. - * Otherwise the serial output is bad code. - */ - //outb(0xD2, 0xcd6); - //outb(0x00, 0xcd7); amd_initmmio(); @@ -65,27 +57,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); - outb(0x1, 0xcd7); + outb(0x01, 0xcd7); - /* Set auxiliary output clock frequency on OSCOUT1 pin to be 48MHz */ + /* Set auxiliary output clock frequency on OSCOUT1 pin to be 25MHz */ + /* Set auxiliary output clock frequency on OSCOUT2 pin to be 48MHz */ addr32 = (u32 *)0xfed80e28; t32 = *addr32; - t32 &= 0xfff8ffff; + t32 &= 0xffc0ffff; // Clr bits [21:19] & [18:16] + t32 |= 0x00010000; // Set bit 16 for 25MHz *addr32 = t32; - /* Enable Auxiliary Clock1, disable FCH 14 MHz OscClk */ + /* Enable Auxiliary OSCOUT1/OSCOUT2 */ addr32 = (u32 *)0xfed80e40; t32 = *addr32; - t32 &= 0xffffbffb; + t32 &= 0xffffff7b; // clear 2, 7 *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); post_code(0x31); - /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - + nct5104d_enable_uartd(SERIAL_DEV); + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); } @@ -98,11 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ - int i; - for(i = 0; i < 200000; i++) - val = inb(0xcd6); - post_code(0x37); agesawrapper_amdinitreset(); post_code(0x38);

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coreboot-gerrit January 2015