coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 15c98b0 storm/ipq8064: add dynamic CBMEM support
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 15c98b021771d10c4bb98e5b0e8cb910cd0c1f7d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 14:45:56 2014 -0700 storm/ipq8064: add dynamic CBMEM support Squashed the correction patch with the original to avoid confusion in coreboot.org review. All what's needed apart from configuring the feature is to provide a function which would report the top of DRAM address. BUG=chrome-os-partner:27784 TEST=manual . with all other patches applied, the image proceeds all the way to trying to download 'fallback/payload'. Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3 Original-Reviewed-on: https://chromium-review.googlesource.com/197897 (cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> storm: initialize dynamic cbmem properly Dynamic cbmem support has been enabled on storm, but the proper initialization at romstage is missing. Proper DRAM base address definition is also necessary so that CBMEM is placed in the correct address range (presently at the top of DRAM). BUG=chrome-os-partner:27784 TEST=build boot coreboot on ap148, observe the following in the console output: Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5 coreboot table: 256 bytes. CBMEM ROOT 0. 5ffff000 00001000 COREBOOT 1. 5fffd000 00002000 Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199674 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74 Reviewed-on: http://review.coreboot.org/7996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/7996 for details. -gerrit

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Patch merged into coreboot/master: f325434 ipq8064: Configure storm bootblock to run
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit f3254348a118f2d2b666fc84a31c1ceb6881bbc5 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 30 14:09:36 2014 -0700 ipq8064: Configure storm bootblock to run This adds necessary configuration options to enable bootblock on Storm to read the rombase image from the SPI flash. BUG=chrome-os-partner:27784 TEST=manual . after this change is applied, the AP148 boots coreboot from the Spansion SPI flash device: coreboot-4.0 Thu May 1 14:25:34 PDT 2014 starting... Exception handlers installed. SF: Detected S25FL128S_256K with page size 10000, total 2000000 CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001 coreboot-4.0 Thu May 1 14:25:34 PDT 2014 booting... Exception handlers installed. ... Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197801 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 73d72df228e3c6154d8836b0af6d94df91c88bf4) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67 Reviewed-on: http://review.coreboot.org/7995 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/7995 for details. -gerrit

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Patch merged into coreboot/master: 572795b lenovo/t420s: Add new port.
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 572795bf0877627e77526fe505ad6e6158093fbc Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Mon Dec 29 19:57:29 2014 +0100 lenovo/t420s: Add new port. This is based on x220 and t520. Tested on i7 model with usb3. There is no support for nvidia gpu and optimus. Change-Id: I6ca9436ccec3024095d02078e5e450147841e463 Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> Reviewed-on: http://review.coreboot.org/7974 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin(a)das-labor.org> Reviewed-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/7974 for details. -gerrit

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New patch to review for coreboot: 524e710 inteltool: add `-s` to dump spi bar and bios_cntl registers
by Alexander Couzens 03 Jan '15

03 Jan '15

Alexander Couzens (lynxis(a)fe80.eu) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8049 -gerrit commit 524e710c7b07be3cc68981d9afaef364d14b556a Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sat Jan 3 02:52:10 2015 +0100 inteltool: add `-s` to dump spi bar and bios_cntl registers Change-Id: I3bb5dc23885af8c992456ee5e4bd374cd4b813bf Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> --- util/inteltool/Makefile | 2 +- util/inteltool/inteltool.8 | 3 + util/inteltool/inteltool.c | 15 +++- util/inteltool/inteltool.h | 1 + util/inteltool/spi.c | 220 +++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 238 insertions(+), 3 deletions(-) diff --git a/util/inteltool/Makefile b/util/inteltool/Makefile index 98848b1..f846672 100644 --- a/util/inteltool/Makefile +++ b/util/inteltool/Makefile @@ -27,7 +27,7 @@ PREFIX ?= /usr/local CFLAGS ?= -O2 -g -Wall -W LDFLAGS += -lpci -lz -OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o +OBJS = inteltool.o cpu.o gpio.o rootcmplx.o powermgt.o memory.o pcie.o amb.o ivy_memory.o spi.o OS_ARCH = $(shell uname) ifeq ($(OS_ARCH), Darwin) diff --git a/util/inteltool/inteltool.8 b/util/inteltool/inteltool.8 index 9db4df7..5956bcd 100644 --- a/util/inteltool/inteltool.8 +++ b/util/inteltool/inteltool.8 @@ -29,6 +29,9 @@ Dump I/O Controller Hub (ICH) southbridge GPIO registers. .B "\-r, \-\-rcba" Dump I/O Controller Hub (ICH) southbridge RCBA registers. .TP +.B "\-s, \-\-spi" +Dump I/O Controller Hub (ICH) southbridge SPI registers and bios control. +.TP .B "\-p, \-\-pmbase" Dump I/O Controller Hub (ICH) southbridge PMBASE registers. .TP diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index ffed606..38ab061 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -209,10 +209,11 @@ void print_version(void) void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMa]\n", name); + printf("usage: %s [-vh?gGrpmedPMas]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" + " -s | --spi: dump southbridge spi and bios_cntrl registers\n" " -g | --gpio: dump southbridge GPIO registers\n" " -G | --gpio-diffs: show GPIO differences from defaults\n" " -r | --rcba: dump southbridge RCBA registers\n" @@ -240,6 +241,7 @@ int main(int argc, char *argv[]) int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; + int dump_spi = 0; int show_gpio_diffs = 0; static struct option long_options[] = { @@ -255,11 +257,12 @@ int main(int argc, char *argv[]) {"pciexpress", 0, 0, 'P'}, {"msrs", 0, 0, 'M'}, {"ambs", 0, 0, 'A'}, + {"spi", 0, 0, 's'}, {"all", 0, 0, 'a'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaA", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAs", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -304,10 +307,14 @@ int main(int argc, char *argv[]) dump_pciexbar = 1; dump_coremsrs = 1; dump_ambs = 1; + dump_spi = 1; break; case 'A': dump_ambs = 1; break; + case 's': + dump_spi = 1; + break; case 'h': case '?': default: @@ -454,6 +461,10 @@ int main(int argc, char *argv[]) if (dump_ambs) { print_ambs(nb, pacc); } + + if (dump_spi) { + print_spi(sb); + } /* Clean up */ pci_free_dev(nb); // pci_free_dev(sb); // TODO: glibc detected "double free or corruption" diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 1db9e63..3f22641 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -203,4 +203,5 @@ int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); int print_ambs(struct pci_dev *nb, struct pci_access *pacc); +int print_spi(struct pci_dev *sb); void ivybridge_dump_timings(void); diff --git a/util/inteltool/spi.c b/util/inteltool/spi.c new file mode 100644 index 0000000..f5745dc --- /dev/null +++ b/util/inteltool/spi.c @@ -0,0 +1,220 @@ + +#include <stdio.h> +#include <stdlib.h> +#include "inteltool.h" + +static const io_register_t pch_bios_cntl_registers[] = { + { 0x0, 1, "BIOSWE - write enable" }, + { 0x1, 1, "BLE - lock enable" }, + { 0x2, 2, "SPI Read configuration" }, + { 0x4, 1, "TopSwapStatus" }, + { 0x5, 1, "SMM Bios Write Protect Disable" }, + { 0x6, 2, "reserved" }, +}; + +#define SPIBAR 0x3800 + +static const io_register_t spi_bar_registers[] = { + { SPIBAR + 0x00, 4, "BFPR - BIOS Flash primary region" }, + { SPIBAR + 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" }, + { SPIBAR + 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" }, + { SPIBAR + 0x08, 4, "FADDR - Flash Address" }, + { SPIBAR + 0x0c, 4, "Reserved" }, + { SPIBAR + 0x10, 4, "FDATA0" }, + /* { SPIBAR + 0x14, 4, "FDATAN" }, */ + /* data .. up to 0x4f*/ + { SPIBAR + 0x50, 4, "FRACC - Flash REgion Access Permissions" }, + { SPIBAR + 0x54, 4, "Flash Region 0" }, + { SPIBAR + 0x58, 4, "Flash Region 1" }, + { SPIBAR + 0x5c, 4, "Flash Region 2" }, + { SPIBAR + 0x60, 4, "Flash Region 3" }, + { SPIBAR + 0x64, 4, "Flash Region 4" }, + { SPIBAR + 0x74, 4, "FPR0 Flash Protected Range 0" }, + { SPIBAR + 0x78, 4, "FPR0 Flash Protected Range 1" }, + { SPIBAR + 0x7c, 4, "FPR0 Flash Protected Range 2" }, + { SPIBAR + 0x80, 4, "FPR0 Flash Protected Range 3" }, + { SPIBAR + 0x84, 4, "FPR0 Flash Protected Range 4" }, + { SPIBAR + 0x90, 1, "SSFSTS - Software Sequencing Flash Status" }, + { SPIBAR + 0x91, 3, "SSFSTS - Software Sequencing Flash Status" }, + { SPIBAR + 0x94, 2, "PREOP - Prefix opcode Configuration" }, + { SPIBAR + 0x96, 2, "OPTYPE - Opcode Type Configuration" }, + { SPIBAR + 0x98, 8, "OPMENU - Opcode Menu Configuration" }, + { SPIBAR + 0xa0, 1, "BBAR - BIOS Base Address Configuration" }, + { SPIBAR + 0xb0, 4, "FDOC - Flash Descriptor Observability Control" }, + { SPIBAR + 0xb8, 4, "Reserved" }, + { SPIBAR + 0xc0, 4, "AFC - Additional Flash Control" }, + { SPIBAR + 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" }, + { SPIBAR + 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" }, + { SPIBAR + 0xd0, 4, "FPB - Flash Partition Boundary" }, +}; + +int print_bioscntl(struct pci_dev *sb) +{ + int i, size = 0; + unsigned char bios_cntl = 0xff; + const io_register_t *bios_cntl_register = NULL; + + printf("\n============= SPI / BIOS CNTL =============\n\n"); + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: + bios_cntl = pci_read_byte(sb, 0xdc); + bios_cntl_register = pch_bios_cntl_registers; + size = ARRAY_SIZE(pch_bios_cntl_registers); + break; + default: + printf("Error: Dumping SPI on this southbridge is not (yet) supported.\n"); + return 1; + } + + printf("BIOS_CNTL = 0x%04x (IO)\n\n", bios_cntl); + + if (bios_cntl_register) { + for (i = 0; i < size; i++) { + unsigned int val = bios_cntl >> bios_cntl_register[i].addr; + val &= ((1 << bios_cntl_register[i].size) -1); + printf("0x%04x = %s\n", val, bios_cntl_register[i].name); + } + } + + return 0; +} + +int print_spibar(struct pci_dev *sb) { + int i, size = 0, rcba_size = 0x4000; + volatile uint8_t *rcba; + uint32_t rcba_phys; + const io_register_t *spi_register = NULL; + + printf("\n============= SPI Bar ==============\n\n"); + + switch (sb->device_id) { + case PCI_DEVICE_ID_INTEL_ICH6: + case PCI_DEVICE_ID_INTEL_ICH7: + case PCI_DEVICE_ID_INTEL_ICH7M: + case PCI_DEVICE_ID_INTEL_ICH7DH: + case PCI_DEVICE_ID_INTEL_ICH7MDH: + case PCI_DEVICE_ID_INTEL_ICH8: + case PCI_DEVICE_ID_INTEL_ICH8M: + case PCI_DEVICE_ID_INTEL_ICH9DH: + case PCI_DEVICE_ID_INTEL_ICH9DO: + case PCI_DEVICE_ID_INTEL_ICH9R: + case PCI_DEVICE_ID_INTEL_ICH9: + case PCI_DEVICE_ID_INTEL_ICH9M: + case PCI_DEVICE_ID_INTEL_ICH9ME: + case PCI_DEVICE_ID_INTEL_ICH10R: + case PCI_DEVICE_ID_INTEL_NM10: + case PCI_DEVICE_ID_INTEL_I63XX: + case PCI_DEVICE_ID_INTEL_3400: + case PCI_DEVICE_ID_INTEL_3420: + case PCI_DEVICE_ID_INTEL_3450: + case PCI_DEVICE_ID_INTEL_3400_DESKTOP: + case PCI_DEVICE_ID_INTEL_3400_MOBILE: + case PCI_DEVICE_ID_INTEL_3400_MOBILE_SFF: + case PCI_DEVICE_ID_INTEL_B55_A: + case PCI_DEVICE_ID_INTEL_B55_B: + case PCI_DEVICE_ID_INTEL_H55: + case PCI_DEVICE_ID_INTEL_H57: + case PCI_DEVICE_ID_INTEL_HM55: + case PCI_DEVICE_ID_INTEL_HM57: + case PCI_DEVICE_ID_INTEL_P55: + case PCI_DEVICE_ID_INTEL_PM55: + case PCI_DEVICE_ID_INTEL_Q57: + case PCI_DEVICE_ID_INTEL_QM57: + case PCI_DEVICE_ID_INTEL_QS57: + case PCI_DEVICE_ID_INTEL_Z68: + case PCI_DEVICE_ID_INTEL_P67: + case PCI_DEVICE_ID_INTEL_UM67: + case PCI_DEVICE_ID_INTEL_HM65: + case PCI_DEVICE_ID_INTEL_H67: + case PCI_DEVICE_ID_INTEL_HM67: + case PCI_DEVICE_ID_INTEL_Q65: + case PCI_DEVICE_ID_INTEL_QS67: + case PCI_DEVICE_ID_INTEL_Q67: + case PCI_DEVICE_ID_INTEL_QM67: + case PCI_DEVICE_ID_INTEL_B65: + case PCI_DEVICE_ID_INTEL_C202: + case PCI_DEVICE_ID_INTEL_C204: + case PCI_DEVICE_ID_INTEL_C206: + case PCI_DEVICE_ID_INTEL_H61: + case PCI_DEVICE_ID_INTEL_Z77: + case PCI_DEVICE_ID_INTEL_Z75: + case PCI_DEVICE_ID_INTEL_Q77: + case PCI_DEVICE_ID_INTEL_Q75: + case PCI_DEVICE_ID_INTEL_B75: + case PCI_DEVICE_ID_INTEL_H77: + case PCI_DEVICE_ID_INTEL_C216: + case PCI_DEVICE_ID_INTEL_QM77: + case PCI_DEVICE_ID_INTEL_QS77: + case PCI_DEVICE_ID_INTEL_HM77: + case PCI_DEVICE_ID_INTEL_UM77: + case PCI_DEVICE_ID_INTEL_HM76: + case PCI_DEVICE_ID_INTEL_HM75: + case PCI_DEVICE_ID_INTEL_HM70: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM: + case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE: + rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; + size = ARRAY_SIZE(spi_bar_registers); + spi_register = spi_bar_registers; + break; + case PCI_DEVICE_ID_INTEL_ICH: + case PCI_DEVICE_ID_INTEL_ICH0: + case PCI_DEVICE_ID_INTEL_ICH2: + case PCI_DEVICE_ID_INTEL_ICH4: + case PCI_DEVICE_ID_INTEL_ICH4M: + case PCI_DEVICE_ID_INTEL_ICH5: + printf("This southbridge does not have RCBA.\n"); + return 1; + default: + printf("Error: Dumping RCBA on this southbridge is not (yet) supported.\n"); + return 1; + } + + rcba = map_physical(rcba_phys, rcba_size); + if (rcba == NULL) { + perror("Error mapping RCBA"); + exit(1); + } + + for (i = 0; i < size; i++) { + switch(spi_register[i].size) { + case 1: + printf("0x%08x = %s\n", *(uint8_t *)(rcba + spi_register[i].addr), spi_register[i].name); + break; + case 2: + printf("0x%08x = %s\n", *(uint16_t *)(rcba + spi_register[i].addr), spi_register[i].name); + break; + case 4: + printf("0x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), spi_register[i].name); + break; + case 8: + printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), *(uint32_t *)(rcba + spi_register[i].addr + 4), spi_register[i].name); + break; + } + } + + unmap_physical((void *)rcba, rcba_size); + return 0; +} + +int print_spi(struct pci_dev *sb) { + return (print_bioscntl(sb) || print_spibar(sb)); +} +

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Patch merged into coreboot/master: c619c41 blaze: change ramcode 1000/1001/1010 to use 792MHz bct
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit c619c418901a282201b552d81453fe741b29e819 Author: Neil Chen <neilc(a)nvidia.com> Date: Thu May 29 18:20:17 2014 +0800 blaze: change ramcode 1000/1001/1010 to use 792MHz bct This change updates the cfg file for Hynix/Micron/Samsung 4GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202059 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c Reviewed-on: http://review.coreboot.org/8008 Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8008 for details. -gerrit

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Patch set updated for coreboot: ecddc82 util/cbfstool: Fix byte-ordering for payload type field.
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8005 -gerrit commit ecddc82683b4bb31d8c20b49c9a40d8542f4c88d Author: Hung-Te Lin <hungte(a)chromium.org> Date: Fri May 16 10:14:05 2014 +0800 util/cbfstool: Fix byte-ordering for payload type field. In https://chromium-review.googlesource.com/181272 the payload->type has been changed to big-endian (network ordering) but the cbfs_image is still parsing type as host ordering, which caused printing cbfs image verbosely (cbfstool imge print -v) to fail to find entry field and print numerous garbage output. Payload fields should be always parsed in big-endian (network ordering). BUG=none TEST=make; cbfstool image.bin print -v -v -v # see payloads correctly Original-Change-Id: If1ac355b8847fb54988069f694bd2f317ce49a1a Original-Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200158 Original-Reviewed-by: Ronald Minnich <rminnich(a)chromium.org> (cherry picked from commit 423f7dd28f8b071692d57401e144232d5ee2e479) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5a4694e887c7ff48d8d0713bb5808c29256141a9 --- util/cbfstool/cbfs_image.c | 64 +++++++++++++++++++++++++++------------------- 1 file changed, 38 insertions(+), 26 deletions(-) diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 1a522bd..6775b06 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -153,6 +153,22 @@ void cbfs_put_header(void *dest, const struct cbfs_header *header) xdr_be.put32(&outheader, header->architecture); } +static void cbfs_decode_payload_segment(struct cbfs_payload_segment *output, + struct cbfs_payload_segment *input) +{ + struct buffer seg = { + .data = (void *)input, + .size = sizeof(*input), + }; + output->type = xdr_be.get32(&seg); + output->compression = xdr_be.get32(&seg); + output->offset = xdr_be.get32(&seg); + output->load_addr = xdr_be.get64(&seg); + output->len = xdr_be.get32(&seg); + output->mem_len = xdr_be.get32(&seg); + assert(seg.size == 0); +} + void cbfs_get_header(struct cbfs_header *header, const void *src) { struct buffer outheader; @@ -596,40 +612,35 @@ static int cbfs_print_stage_info(struct cbfs_stage *stage, FILE* fp) return 0; } -/* Return 1 when segment is of type PAYLOAD_SEGMENT_ENTRY. */ -static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *seg_be, - FILE *fp) +static int cbfs_print_decoded_payload_segment_info( + struct cbfs_payload_segment *seg, FILE *fp) { - struct cbfs_payload_segment payload; - - xdr_get_seg(&payload, seg_be); - - switch(payload.type) { + /* The input (seg) must be already decoded by + * cbfs_decode_payload_segment. + */ + switch (seg->type) { case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: fprintf(fp, " %s (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d)\n", - (payload.type == PAYLOAD_SEGMENT_CODE ? + (seg->type == PAYLOAD_SEGMENT_CODE ? "code " : "data"), lookup_name_by_type(types_cbfs_compression, - payload.compression, + seg->compression, "(unknown)"), - payload.offset, - payload.load_addr, - payload.len, payload.mem_len); + seg->offset, seg->load_addr, seg->len, + seg->mem_len); break; case PAYLOAD_SEGMENT_ENTRY: fprintf(fp, " entry (0x%" PRIx64 ")\n", - payload.load_addr); - return 1; + seg->load_addr); break; case PAYLOAD_SEGMENT_BSS: fprintf(fp, " BSS (address 0x%016" PRIx64 ", " "length 0x%x)\n", - payload.load_addr, - payload.len); + seg->load_addr, seg->len); break; case PAYLOAD_SEGMENT_PARAMS: @@ -639,14 +650,12 @@ static int cbfs_print_payload_segment_info(struct cbfs_payload_segment *seg_be, default: fprintf(fp, " 0x%x (%s compression, offset: 0x%x, " "load: 0x%" PRIx64 ", length: %d/%d\n", - payload.type, + seg->type, lookup_name_by_type(types_cbfs_compression, - payload.compression, + seg->compression, "(unknown)"), - payload.offset, - payload.load_addr, - payload.len, - payload.mem_len); + seg->offset, seg->load_addr, seg->len, + seg->mem_len); break; } return 0; @@ -692,10 +701,13 @@ int cbfs_print_entry_info(struct cbfs_image *image, struct cbfs_file *entry, payload = (struct cbfs_payload_segment *) CBFS_SUBHEADER(entry); while (payload) { - /* Stop when PAYLOAD_SEGMENT_ENTRY seen. */ - if (cbfs_print_payload_segment_info(payload, - fp)) + struct cbfs_payload_segment seg; + cbfs_decode_payload_segment(&seg, payload); + cbfs_print_decoded_payload_segment_info( + &seg, fp); + if (seg.type == PAYLOAD_SEGMENT_ENTRY) break; + else payload ++; } break;

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Patch set updated for coreboot: 6e9b068 ipq8064: add SOC initialization skeleton
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8000 -gerrit commit 6e9b0684f6e3745e3a16c1678e1aaa1f75da9610 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 13 17:47:57 2014 -0700 ipq8064: add SOC initialization skeleton The main benefit of adding this skeleton is the addition of the correct memory map to CBMEM. Attempts to load depthcharge do not fail because of unavailability of the bounce buffer. BUG=chrome-os-partner:27784 TEST=boot updated firmware on AP148, observe CPU: Qualcomm 8064 in the ramstage console output as well as not failing to load depthcharge any more. Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199675 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013 --- src/soc/qualcomm/ipq806x/Makefile.inc | 1 + src/soc/qualcomm/ipq806x/soc.c | 49 +++++++++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 91cdd93..f6acbed 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -34,6 +34,7 @@ romstage-y += cbmem.c ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c +ramstage-y += soc.c ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += timer.c ramstage-$(CONFIG_DRIVERS_UART) += uart.c diff --git a/src/soc/qualcomm/ipq806x/soc.c b/src/soc/qualcomm/ipq806x/soc.c new file mode 100644 index 0000000..53f5716 --- /dev/null +++ b/src/soc/qualcomm/ipq806x/soc.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> + +static void soc_read_resources(device_t dev) +{ + ram_resource(dev, 0, CONFIG_SYS_SDRAM_BASE/KiB, + CONFIG_DRAM_SIZE_MB * (1 << 10)); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Qualcomm 8064\n"); +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_qualcomm_ipq806x_ops = { + CHIP_NAME("SOC Qualcomm 8064") + .enable_dev = enable_soc_dev, +};

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Patch set updated for coreboot: 927bc2d storm: Put the page table at a correct address
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8019 -gerrit commit 927bc2d5dc272c156847f55a68e0aea33180cf8d Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Jun 4 17:38:51 2014 -0700 storm: Put the page table at a correct address The recently introduced page table location value is wrong, it overlaps with other areas of the code. This patch fixes the location, a more robust scheme is needed for memory layout management. BUG=none TEST=manual . occasional random failures disappear after this patch is applied Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202641 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> (cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7afcab42db259e53541fb991b36d680fc2186304 --- src/soc/qualcomm/ipq806x/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 19d5236..2298fc0 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -72,6 +72,6 @@ config CBFS_CACHE_SIZE config TTB_BUFFER hex "memory address for page tables" - default 0x405f0000 + default 0x405c0000 endif

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Patch set updated for coreboot: d0f5210 storm: modify memory layout
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8012 -gerrit commit d0f5210fbeaa000555bcc3d786109cac907da653 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed May 28 10:49:51 2014 -0700 storm: modify memory layout This is an interim change (before EFS is enabled), align ROM and RAM stages so that they have enough room and do not step over each other. BUG=chrome-os-partner:27784 TEST=manual . booted coreboot successfully on ap148 Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202046 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 3752c16..19d5236 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -44,11 +44,11 @@ config BOOTBLOCK_BASE config ROMSTAGE_BASE hex - default 0x40608000 + default 0x40620000 config RAMSTAGE_BASE hex - default 0x4060c000 + default 0x40640000 config SYS_SDRAM_BASE hex

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Patch set updated for coreboot: 522ea9d soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8009 -gerrit commit 522ea9dea1c8d7890bdc2da0b787ad35b77e4e1d Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Tue May 13 13:49:42 2014 -0700 soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc. Define a base address for page table entries. Place it 64KB below the bootblock loading address. BUG=chrome-os-partner:28467 TEST=verified that the page tables are being populated at this address. Also observed that the SPI driver takes 900 ns to process a byte as opposed to 1.5 us in case caching is not enabled. Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200332 (cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 4f081f0..3752c16 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -70,4 +70,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000 +config TTB_BUFFER + hex "memory address for page tables" + default 0x405f0000 + endif

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coreboot-gerrit January 2015