coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: b97fe07 storm: enable early console
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7997 -gerrit commit b97fe07b4be267f73600fe3c325989ead01121f6 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 13 17:11:30 2014 -0700 storm: enable early console Include the required modules in romstage and enable early console. BUG=chrome-os-partner:27784 TEST=observe the romstage prompt in the console output: coreboot-4.0 romstage Tue May 13 17:08:58 PDT 2014 starting... Original-Change-Id: Ie3853b9afc53246e6eb997f279ccd4dbb08f748b Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199673 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 6e643d3425ee226b3ebfbf329b35e7017f83d0c3) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ibdc695da634356988b3e551b0a9e4be2e129ccb4 --- src/mainboard/google/storm/Makefile.inc | 1 + src/mainboard/google/storm/romstage.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/google/storm/Makefile.inc b/src/mainboard/google/storm/Makefile.inc index 17f9676..4a47c9e 100644 --- a/src/mainboard/google/storm/Makefile.inc +++ b/src/mainboard/google/storm/Makefile.inc @@ -20,6 +20,7 @@ bootblock-y += cdp.c romstage-y += romstage.c +romstage-y += cdp.c ramstage-y += mainboard.c ramstage-y += cdp.c diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index 10632d8..99cc90b 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -26,6 +26,7 @@ void main(void) { void *entry; + console_init(); cbmem_initialize_empty(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");

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Patch set updated for coreboot: 911c1b5 mainboard/storm: setup mmu in storm mainboard_init
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8010 -gerrit commit 911c1b5526f4fbe43150f3fc1a7b4a77a97a6df7 Author: Deepa Dinamani <deepad(a)codeaurora.org> Date: Thu May 15 17:14:12 2014 -0700 mainboard/storm: setup mmu in storm mainboard_init enable protection of zero page access, provide for uncached device memory range, and protect against access outside of DRAM except to device registers. BUG=chrome-os-partner:28467 TEST=verified mmu.pagetable.list output: _______address___________|_physical________________|sec|_d_|_size____|_permissions____________________|_glb|_shr|_pageflags______________________| C:00000000--000FFFFF| | | | | | | | | C:00100000--3FFFFFFF| A:00:00100000--3FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:40000000--428FFFFF| A:00:40000000--428FFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | C:42900000--43CFFFFF| A:00:42900000--43CFFFFF| ns| 00| 00100000| P:readwrite U:readwrite notexec| yes| no | strongly ordered | C:43D00000--5FFFFFFF| A:00:43D00000--5FFFFFFF| ns| 00| 00100000| P:readwrite U:readwrite exec | yes| no | write-back/no write alloc | Original-Change-Id: If9beb10938841aead5105d662f0aef741995d708 Original-Signed-off-by: Deepa Dinamani <deepad(a)codeaurora.org> Original-Reviewed-on: https://chromium-review.googlesource.com/200341 Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> (cherry picked from commit 09dd137453d8c6f1b60692b01226498e22f34fb2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Conflicts: src/mainboard/google/storm/mainboard.c Change-Id: Idff7e3f0bc5903933e9f1b980f595666380696d1 --- src/mainboard/google/storm/mainboard.c | 38 ++++++++++++++++++++++++++++++++-- 1 file changed, 36 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/storm/mainboard.c b/src/mainboard/google/storm/mainboard.c index 0b0182f..1e622f4 100644 --- a/src/mainboard/google/storm/mainboard.c +++ b/src/mainboard/google/storm/mainboard.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright 2013 Google Inc. + * Copyright 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,11 +17,45 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <device/device.h> +#include <arch/cache.h> #include <boot/coreboot_tables.h> +#include <device/device.h> + +#define TO_MB(x) ((x)>>20) + +/* convenient shorthand (in MB) */ +#define DRAM_START TO_MB(CONFIG_SYS_SDRAM_BASE) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) +#define DRAM_END (DRAM_START + DRAM_SIZE) + +/* DMA memory for drivers */ +#define DMA_START TO_MB(CONFIG_DRAM_DMA_START) +#define DMA_SIZE TO_MB(CONFIG_DRAM_DMA_SIZE) + +static void setup_mmu(void) +{ + dcache_mmu_disable(); + + /* Map Device memory. */ + mmu_config_range(0, DRAM_START, DCACHE_OFF); + /* Disable Page 0 for trapping NULL pointer references. */ + mmu_disable_range(0, 1); + /* Map DRAM memory */ + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + /* Map DMA memory */ + if (DMA_SIZE) + mmu_config_range(DMA_START, DMA_SIZE, DCACHE_OFF); + + mmu_disable_range(DRAM_END, 4096 - DRAM_END); + + mmu_init(); + + dcache_mmu_enable(); +} static void mainboard_init(device_t dev) { + setup_mmu(); } static void mainboard_enable(device_t dev)

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Patch set updated for coreboot: 426068d ipq806x: clean up UART driver tx_byte function
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8011 -gerrit commit 426068d9431371492389181825bf09bb759ea992 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue May 27 18:03:38 2014 -0700 ipq806x: clean up UART driver tx_byte function The driver as it was copied from u-boot provided a function to transmit multiple characters in one invocation. This feature was not ported to coreboot, there is no need to maintain the complexity when only one character at a time is transmitted. It is also very desirable to get rid of a 1024 byte array allocated on the stack. The array was necessary to allow to convert multiple newline characters in the transmit data flow into two character sequences CRLF. Now just a single word is enough to keep one or two characters to transmit. BUG=chrome-os-partner:27784 TEST=verified that coreboot with the new code prints generates console output. Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201782 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Trevor Bourget <tbourget(a)codeaurora.org> (cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e --- src/soc/qualcomm/ipq806x/include/ipq_uart.h | 9 --- src/soc/qualcomm/ipq806x/uart.c | 121 +++++----------------------- 2 files changed, 18 insertions(+), 112 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/include/ipq_uart.h b/src/soc/qualcomm/ipq806x/include/ipq_uart.h index da943b9..90ca704 100644 --- a/src/soc/qualcomm/ipq806x/include/ipq_uart.h +++ b/src/soc/qualcomm/ipq806x/include/ipq_uart.h @@ -38,15 +38,6 @@ ((value << (32 - end_pos))\ >> (32 - (end_pos - start_pos))) - -#define PACK_CHARS_INTO_WORDS(a, cnt, word) { \ - word = 0; \ - int j; \ - for(j=0; j < (int)cnt; j++) { \ - word |= (a[j] & 0xff)<< (j * 8);\ - } \ - } - extern void __udelay(unsigned long usec); diff --git a/src/soc/qualcomm/ipq806x/uart.c b/src/soc/qualcomm/ipq806x/uart.c index f7b5d02..e09bd0f 100644 --- a/src/soc/qualcomm/ipq806x/uart.c +++ b/src/soc/qualcomm/ipq806x/uart.c @@ -192,108 +192,32 @@ msm_boot_uart_dm_read(unsigned int *data, int *count, int wait) } #endif -/** - * msm_boot_uart_replace_lr_with_cr - replaces "\n" with "\r\n" - * @data_in: characters to be converted - * @num_of_chars: no. of characters - * @data_out: location where converted chars are stored - * - * Replace linefeed char "\n" with carriage return + linefeed - * "\r\n". Currently keeping it simple than efficient. - */ -static unsigned int -msm_boot_uart_replace_lr_with_cr(unsigned char *data_in, - int num_of_chars, - char *data_out, int *num_of_chars_out) +void uart_tx_byte(int idx, unsigned char data) { - int i = 0, j = 0; - - if ((data_in == NULL) || (data_out == NULL) || (num_of_chars < 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - for (i = 0, j = 0; i < num_of_chars; i++, j++) { - if (data_in[i] == '\n') - data_out[j++] = '\r'; - - data_out[j] = data_in[i]; - } - - *num_of_chars_out = j; - - return MSM_BOOT_UART_DM_E_SUCCESS; -} - -/** - * msm_boot_uart_dm_write - transmit data - * @data: data to transmit - * @num_of_chars: no. of bytes to transmit - * - * Writes the data to the TX FIFO. If no space is available blocks - * till space becomes available. - */ -static unsigned int -msm_boot_uart_dm_write(unsigned char *data, unsigned int num_of_chars) -{ - unsigned int tx_word_count = 0; - unsigned int tx_char_left = 0, tx_char = 0; - unsigned int tx_word = 0; - int i = 0; - char *tx_data = NULL; - char new_data[1024]; + int num_of_chars = 1; + unsigned tx_data = 0; unsigned int base = uart_board_param.uart_dm_base; - if ((data == NULL) || (num_of_chars <= 0)) - return MSM_BOOT_UART_DM_E_INVAL; - - /* Replace line-feed (/n) with carriage-return + line-feed (/r/n) */ - msm_boot_uart_replace_lr_with_cr(data, num_of_chars, new_data, &i); - - tx_data = new_data; - num_of_chars = i; - - /* Write to NO_CHARS_FOR_TX register number of characters - * to be transmitted. However, before writing TX_FIFO must - * be empty as indicated by TX_READY interrupt in IMR register - */ - /* Check if transmit FIFO is empty. - * If not we'll wait for TX_READY interrupt. */ - - if (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & MSM_BOOT_UART_DM_SR_TXEMT)) { - while (!(readl_i(MSM_BOOT_UART_DM_ISR(base)) & - MSM_BOOT_UART_DM_TX_READY)) - udelay(1); + /* Add CR to every LF. */ + if (data == '\n') { + num_of_chars++; + tx_data = '\r' | ('\n' << 8); + } else { + tx_data = data; } - /* We are here. FIFO is ready to be written. */ - /* Write number of characters to be written */ - writel_i(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); - - /* Clear TX_READY interrupt */ - writel_i(MSM_BOOT_UART_DM_GCMD_RES_TX_RDY_INT, - MSM_BOOT_UART_DM_CR(base)); - - /* We use four-character word FIFO. So we need to divide data into - * four characters and write in UART_DM_TF register */ - tx_word_count = (num_of_chars % 4) ? ((num_of_chars / 4) + 1) : - (num_of_chars / 4); - tx_char_left = num_of_chars; - - for (i = 0; i < (int)tx_word_count; i++) { - tx_char = (tx_char_left < 4) ? tx_char_left : 4; - PACK_CHARS_INTO_WORDS(tx_data, tx_char, tx_word); - - /* Wait till TX FIFO has space */ + /* Wait until transmit FIFO is empty. */ while (!(readl_i(MSM_BOOT_UART_DM_SR(base)) & - MSM_BOOT_UART_DM_SR_TXRDY)) + MSM_BOOT_UART_DM_SR_TXEMT)) udelay(1); + /* + * TX FIFO is ready to accept new character(s). First write number of + * characters to be transmitted. + */ + writel_i(num_of_chars, MSM_BOOT_UART_DM_NO_CHARS_FOR_TX(base)); - /* TX FIFO has space. Write the chars */ - writel_i(tx_word, MSM_BOOT_UART_DM_TF(base, 0)); - tx_char_left = num_of_chars - (i + 1) * 4; - tx_data = tx_data + 4; - } - - return MSM_BOOT_UART_DM_E_SUCCESS; + /* And now write the character(s) */ + writel_i(tx_data, MSM_BOOT_UART_DM_TF(base, 0)); } /* @@ -419,15 +343,6 @@ uint32_t uartmem_getbaseaddr(void) #endif /** - * uart_tx_byte - transmits a character - * @c: character to transmit - */ -void uart_tx_byte(int idx, unsigned char c) -{ - msm_boot_uart_dm_write(&c, 1); -} - -/** * uart_tx_flush - transmits a string of data * @s: string to transmit */

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Patch set updated for coreboot: dc3cfd7 ipq8064: Configure storm bootblock to run
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7995 -gerrit commit dc3cfd734fa3a5a3d8c7ae5b21e3ba1e48659008 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 30 14:09:36 2014 -0700 ipq8064: Configure storm bootblock to run This adds necessary configuration options to enable bootblock on Storm to read the rombase image from the SPI flash. BUG=chrome-os-partner:27784 TEST=manual . after this change is applied, the AP148 boots coreboot from the Spansion SPI flash device: coreboot-4.0 Thu May 1 14:25:34 PDT 2014 starting... Exception handlers installed. SF: Detected S25FL128S_256K with page size 10000, total 2000000 CBFS: loading stage fallback/romstage @ 0x40608000 (7788 bytes), entry @ 0x40608001 coreboot-4.0 Thu May 1 14:25:34 PDT 2014 booting... Exception handlers installed. ... Original-Change-Id: I9d5e10d6e9f5b60bad5ea71003ea53d8c84ae188 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197801 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 73d72df228e3c6154d8836b0af6d94df91c88bf4) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I509e6da15559c790f129d457d6e463ef90a5dc67 --- src/soc/qualcomm/ipq806x/Kconfig | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 09e1c1e..63d1019 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -17,11 +17,11 @@ config BOOTBLOCK_ROM_OFFSET config CBFS_HEADER_ROM_OFFSET hex "offset of master CBFS header in ROM" - default 0x224000 + default 0x228000 config CBFS_ROM_OFFSET hex "offset of CBFS data in ROM" - default 0x224080 + default 0x228080 config MBN_ENCAPSULATION depends on USE_BLOBS @@ -41,6 +41,15 @@ config BOOTBLOCK_BASE hex "256K bytes left for TZBSP" default 0x40600000 +config ROMSTAGE_BASE + hex + default 0x40608000 + +config RAMSTAGE_BASE + hex + default 0x4060c000 + + config STACK_TOP hex default 0x40600000 @@ -49,4 +58,12 @@ config STACK_BOTTOM hex default 0x405fc000 +config CBFS_CACHE_ADDRESS + hex "memory address to put CBFS cache data" + default 0x405e6000 + +config CBFS_CACHE_SIZE + hex "size of CBFS cache data" + default 0x00016000 + endif

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Patch set updated for coreboot: 57c83f4 storm/ipq8064: add dynamic CBMEM support
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7996 -gerrit commit 57c83f4911a4c4f9022b7bd5f476ee3f1157c6b2 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 14:45:56 2014 -0700 storm/ipq8064: add dynamic CBMEM support Squashed the correction patch with the original to avoid confusion in coreboot.org review. All what's needed apart from configuring the feature is to provide a function which would report the top of DRAM address. BUG=chrome-os-partner:27784 TEST=manual . with all other patches applied, the image proceeds all the way to trying to download 'fallback/payload'. Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3 Original-Reviewed-on: https://chromium-review.googlesource.com/197897 (cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> storm: initialize dynamic cbmem properly Dynamic cbmem support has been enabled on storm, but the proper initialization at romstage is missing. Proper DRAM base address definition is also necessary so that CBMEM is placed in the correct address range (presently at the top of DRAM). BUG=chrome-os-partner:27784 TEST=build boot coreboot on ap148, observe the following in the console output: Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5 coreboot table: 256 bytes. CBMEM ROOT 0. 5ffff000 00001000 COREBOOT 1. 5fffd000 00002000 Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199674 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74 --- src/mainboard/google/storm/Kconfig | 2 +- src/mainboard/google/storm/romstage.c | 3 +++ src/soc/qualcomm/ipq806x/Kconfig | 4 ++++ src/soc/qualcomm/ipq806x/Makefile.inc | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 25 +++++++++++++++++++++++++ 5 files changed, 35 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 3f7cbd6..4c90c4e 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -38,6 +38,6 @@ config MAINBOARD_PART_NUMBER config DRAM_SIZE_MB int - default 2048 + default 512 endif # BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index cf78e44..10632d8 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -19,12 +19,15 @@ #include <arch/stages.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> void main(void) { void *entry; + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); } diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 63d1019..4f081f0 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -6,6 +6,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select ARM_LPAE select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING @@ -49,6 +50,9 @@ config RAMSTAGE_BASE hex default 0x4060c000 +config SYS_SDRAM_BASE + hex + default 0x40000000 config STACK_TOP hex diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 94c7cb9..91cdd93 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -29,7 +29,9 @@ romstage-y += gpio.c romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-y += cbmem.c +ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c new file mode 100644 index 0000000..b175d6a --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20)); +}

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Patch merged into coreboot/master: 0e2d9b6 storm: ipq8064: enable CBFS SPI wrapper
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 0e2d9b63d764ad5e62c662875497b3af5993d0ba Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 19:37:18 2014 -0700 storm: ipq8064: enable CBFS SPI wrapper This change forces storm platform to use the common CBFS SPI wrapper, which makes the SOC specific CBFS code unnecessary and requires including SPI controller support in all coreboot stages. BUG=chrome-os-partner:27784 TEST=manual . with this change and the rest of the patches coreboot on AP148 comes up all the way to attempting to boot the payload (reading earlier stages from the SPI flash along the way). Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197932 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2 Reviewed-on: http://review.coreboot.org/7994 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/7994 for details. -gerrit

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Patch merged into coreboot/master: 20d3d53 ipq8084: provide monotonic us timer
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 20d3d53433fa37eec5b573722f253c7f15d12c52 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Thu May 1 15:24:32 2014 -0700 ipq8084: provide monotonic us timer This service is required by various coreboot code modules. It looks like the 8064 SOC does not provide anything better than a 32 KHz free running counter (it is used in u-boot for us timer as well). Let's use this for now. BUG=chrome-os-partner:27784 TEST=manual . with the rest of the patches applied AP148 boots all the way to trying to start the payload. Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/197896 (cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Id37ed21193db67ceee11a795713c34ef26383380 Reviewed-on: http://review.coreboot.org/7993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/7993 for details. -gerrit

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Patch merged into coreboot/master: 989e12b arm: Fix stored PC value when handling exceptions
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 989e12bb6387bd06037805dcefa249d998b55b74 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed May 14 14:53:18 2014 -0700 arm: Fix stored PC value when handling exceptions ARM processors save the PC value in the Link Register when they handle and exception, but they store it with an added offset (depending on the exception type). In order to make crashes easier to read and correctly support more complicated handlers in libpayload, this patch adjusts the saved PC value on exception entry to correct for that offset. (Note: The value that we now store is what ARM calls the "preferred return address". For most exceptions this is the faulting instruction, but for software interrupts (SWI) it is the instruction after that. This is the way most programs like GDB expect the stored PC address to work, so let's leave it at that.) Numbers taken from the Architecture Reference Manual at the end of section B1.8.3. BRANCH=none BUG=chrome-os-partner:18390 TEST=Provoked a data abort and an undefined instruction in both coreboot and depthcharge, confirmed that the PC address was spot on. Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/199844 Original-Reviewed-by: Stefan Reinauer <reinauer(a)chromium.org> Original-Reviewed-by: Vincent Palatin <vpalatin(a)chromium.org> (cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6 Reviewed-on: http://review.coreboot.org/7992 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7992 for details. -gerrit

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Patch merged into coreboot/master: 739e6a8 elog: Add function to log boot reason in ChromeOS case
by gerrit＠coreboot.org 03 Jan '15

03 Jan '15

the following patch was just integrated into master: commit 739e6a84aa9ccacf54db3da6c1e0777cb86ebea5 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue May 13 20:28:49 2014 -0700 elog: Add function to log boot reason in ChromeOS case This adds a generic helper function for adding boot reason in the ChromeOS case. If vboot is enabled, it will use information passed in via the vboot handoff table in cbmem to determine mode and reason in the case of recovery. BUG=chromium:373467 BRANCH=nyan TEST=built along with follow-up CL and booted on Big under various modes, verified entry was added to eventlog with "mosys eventlog list" Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b Original-Reviewed-on: https://chromium-review.googlesource.com/199690 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75 Reviewed-on: http://review.coreboot.org/7991 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7991 for details. -gerrit

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New patch to review for coreboot: eac3413 samus: Minor fixes for P1.9 boards
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8048 -gerrit commit eac3413f0cff28f25ec4550c08b800515a26981d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 10 10:05:03 2014 -0700 samus: Minor fixes for P1.9 boards - Put SSD into reset on transition to S3/S5 to prevent leakage - Fix GPIO number for wlan disable used in smihandler - Enable generic hub driver in libpayload - Fix comment in devicetree about S0ix BUG=chrome-os-partner:28502 BRANCH=None TEST=Build and boot on samus Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/203185 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0 --- src/mainboard/google/samus/devicetree.cb | 2 +- src/mainboard/google/samus/smihandler.c | 8 ++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index ce13a1d..95ab44b 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -52,7 +52,7 @@ chip soc/intel/broadwell # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013b0000" - # Enable S0ix + # Disable S0ix for now register "s0ix_enable" = "0" device cpu_cluster 0 on diff --git a/src/mainboard/google/samus/smihandler.c b/src/mainboard/google/samus/smihandler.c index b43b46a..932d606 100644 --- a/src/mainboard/google/samus/smihandler.c +++ b/src/mainboard/google/samus/smihandler.c @@ -32,8 +32,8 @@ #include <broadwell/smm.h> #include "ec.h" -/* GPIO46 controls the WLAN_DISABLE_L signal. */ -#define GPIO_WLAN_DISABLE_L 46 +#define GPIO_SSD_RESET_L 47 +#define GPIO_WLAN_DISABLE_L 42 #define GPIO_LTE_DISABLE_L 59 int mainboard_io_trap_handler(int smif) @@ -103,6 +103,8 @@ void mainboard_smi_sleep(u8 slp_typ) 1, USB_CHARGE_MODE_DISABLED); } + /* Put SSD in reset to prevent leak. */ + set_gpio(GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S3. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */ @@ -119,6 +121,8 @@ void mainboard_smi_sleep(u8 slp_typ) 1, USB_CHARGE_MODE_DISABLED); } + /* Put SSD in reset to prevent leak. */ + set_gpio(GPIO_SSD_RESET_L, 0); /* Prevent leak from standby rail to WLAN rail in S5. */ set_gpio(GPIO_WLAN_DISABLE_L, 0); /* Disable LTE */

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coreboot-gerrit January 2015