coreboot-gerrit January 2015

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: a3b4738 wtm2: Fix issues with USB in firmware
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8047 -gerrit commit a3b47380533a3da18e8ac141c64e7d7ef1f20945 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jun 10 10:03:22 2014 -0700 wtm2: Fix issues with USB in firmware XHCI driver was not enabled in libpayload and some ports were disabled that should be enabled. The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to properly indicate unused so crossystem does not attempt to export GPIO number 255 in the kernel and trigger a warning. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f Original-CSigned-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-CReviewed-on: https://chromium-review.googlesource.com/203184 Original-CReviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 328362469b00c9467908a7d18a031fee73753def) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434 --- src/mainboard/intel/wtm2/acpi/chromeos.asl | 6 +++--- src/mainboard/intel/wtm2/pei_data.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/wtm2/acpi/chromeos.asl b/src/mainboard/intel/wtm2/acpi/chromeos.asl index 40ffcf0..4cd6ded 100644 --- a/src/mainboard/intel/wtm2/acpi/chromeos.asl +++ b/src/mainboard/intel/wtm2/acpi/chromeos.asl @@ -18,7 +18,7 @@ */ Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery - Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer - Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect + Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // recovery + Package () { 0x0002, 0, 0xFFFFFFFF, "PCH-LP" }, // developer + Package () { 0x0003, 0, 0xFFFFFFFF, "PCH-LP" }, // firmware write protect }) diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c index a33dddf..e67d8e5 100644 --- a/src/mainboard/intel/wtm2/pei_data.c +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -47,11 +47,11 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) USB_PORT_FRONT_PANEL); pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); - pei_data_usb2_port(pei_data, 7, 0x40, 0, USB_OC_PIN_SKIP, + pei_data_usb2_port(pei_data, 7, 0x40, 1, USB_OC_PIN_SKIP, USB_PORT_FRONT_PANEL); pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); }

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New patch to review for coreboot: f9268b2 samus: Enable DDI2 hotplug
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8046 -gerrit commit f9268b23c63c60dd4e581d2622af31268b8e820d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jun 2 08:36:38 2014 -0700 samus: Enable DDI2 hotplug Both DDI ports may be used on this board so it needs to be able to detect a device on either port. BUG=chrome-os-partner:28234 TEST=None (needs hardware) Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202358 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099 --- src/mainboard/google/samus/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 8810c47..ce13a1d 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -3,12 +3,12 @@ chip soc/intel/broadwell # Enable eDP Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" - # Disable DDI2 Hotplug - register "gpu_dp_c_hotplug" = "0x00" - # Enable DDI1 Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" + # Enable DDI2 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + # Set backlight PWM values for eDP register "gpu_cpu_backlight" = "0x00000200" register "gpu_pch_backlight" = "0x04000000"

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Patch set updated for coreboot: 6251212 samus: Move SPD related information to spd directory
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8006 -gerrit commit 62512125679ab2b81be532b60c889e25d33e7572 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 22 08:22:51 2014 -0700 samus: Move SPD related information to spd directory Put all the SPD related information in one place including the onboard SPD sources and the board specific parsing. BUG=chrome-os-partner:28234 TEST=Build and boot on samus Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201082 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123 --- src/mainboard/google/samus/Makefile.inc | 31 +----- src/mainboard/google/samus/elpida_4Gb.spd.hex | 16 --- src/mainboard/google/samus/elpida_8Gb.spd.hex | 16 --- src/mainboard/google/samus/empty.spd.hex | 16 --- src/mainboard/google/samus/romstage.c | 2 +- src/mainboard/google/samus/samsung_4Gb.spd.hex | 16 --- src/mainboard/google/samus/samsung_8Gb.spd.hex | 16 --- src/mainboard/google/samus/spd.c | 121 --------------------- src/mainboard/google/samus/spd.h | 43 -------- src/mainboard/google/samus/spd/Makefile.inc | 46 ++++++++ src/mainboard/google/samus/spd/elpida_4Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/elpida_8Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/empty.spd.hex | 16 +++ src/mainboard/google/samus/spd/samsung_4Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/samsung_8Gb.spd.hex | 16 +++ src/mainboard/google/samus/spd/spd.c | 121 +++++++++++++++++++++ src/mainboard/google/samus/spd/spd.h | 43 ++++++++ 17 files changed, 293 insertions(+), 274 deletions(-) diff --git a/src/mainboard/google/samus/Makefile.inc b/src/mainboard/google/samus/Makefile.inc index f23352f..502204e 100644 --- a/src/mainboard/google/samus/Makefile.inc +++ b/src/mainboard/google/samus/Makefile.inc @@ -17,6 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +subdirs-y += spd + ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c romstage-y += chromeos.c @@ -26,32 +28,3 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c romstage-y += pei_data.c ramstage-y += pei_data.c - -## DIMM SPD for on-board memory -romstage-y += spd.c -SPD_BIN = $(obj)/spd.bin - -# Order of names in SPD_SOURCES is important! -# { GPIO69, GPIO68, GPIO67 } -SPD_SOURCES = empty # 0: { 0, 0, 0 } -SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } -SPD_SOURCES += empty # 2: { 0, 1, 0 } -SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } -SPD_SOURCES += empty # 4: { 1, 0, 0 } -SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } -SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } -SPD_SOURCES += empty # 7: { 1, 1, 1 } - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do echo -e -n "\\x$$c"; \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := 0xab diff --git a/src/mainboard/google/samus/elpida_4Gb.spd.hex b/src/mainboard/google/samus/elpida_4Gb.spd.hex deleted file mode 100644 index e73ba62..0000000 --- a/src/mainboard/google/samus/elpida_4Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/elpida_8Gb.spd.hex b/src/mainboard/google/samus/elpida_8Gb.spd.hex deleted file mode 100644 index b790943..0000000 --- a/src/mainboard/google/samus/elpida_8Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 -45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 -20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/empty.spd.hex b/src/mainboard/google/samus/empty.spd.hex deleted file mode 100644 index 9ec39f1..0000000 --- a/src/mainboard/google/samus/empty.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index f0609c8..9af4ffb 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -26,7 +26,7 @@ #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> -#include "spd.h" +#include <mainboard/google/samus/spd/spd.h> #include "gpio.h" void mainboard_romstage_entry(struct romstage_params *rp) diff --git a/src/mainboard/google/samus/samsung_4Gb.spd.hex b/src/mainboard/google/samus/samsung_4Gb.spd.hex deleted file mode 100644 index 8821050..0000000 --- a/src/mainboard/google/samus/samsung_4Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 -4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/samsung_8Gb.spd.hex b/src/mainboard/google/samus/samsung_8Gb.spd.hex deleted file mode 100644 index a7a1409..0000000 --- a/src/mainboard/google/samus/samsung_8Gb.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 -69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 -4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 -20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd.c b/src/mainboard/google/samus/spd.c deleted file mode 100644 index 4371da9..0000000 --- a/src/mainboard/google/samus/spd.c +++ /dev/null @@ -1,121 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <broadwell/gpio.h> -#include <broadwell/pei_data.h> -#include <broadwell/romstage.h> -#include "gpio.h" -#include "spd.h" - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " - "density %d Mb\n", banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - int spd_gpio[3]; - int spd_index; - int spd_file_len; - struct cbfs_file *spd_file; - - spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); - spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); - spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); - - spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; - - printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", - spd_index, - SPD_GPIO_BIT2, spd_gpio[2], - SPD_GPIO_BIT1, spd_gpio[1], - SPD_GPIO_BIT0, spd_gpio[0]); - - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); - if (!spd_file) - die("SPD data not found."); - spd_file_len = ntohl(spd_file->len); - - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], - ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], - ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/google/samus/spd.h b/src/mainboard/google/samus/spd.h deleted file mode 100644 index 98180fa..0000000 --- a/src/mainboard/google/samus/spd.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef MAINBOARD_SPD_H -#define MAINBOARD_SPD_H - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - -/* Samus board memory configuration GPIOs */ -#define SPD_GPIO_BIT0 67 -#define SPD_GPIO_BIT1 68 -#define SPD_GPIO_BIT2 69 - -struct pei_data; -void mainboard_fill_spd_data(struct pei_data *pei_data); - -#endif diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc new file mode 100644 index 0000000..657a09d --- /dev/null +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -0,0 +1,46 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +# { GPIO69, GPIO68, GPIO67 } +SPD_SOURCES = empty # 0: { 0, 0, 0 } +SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } +SPD_SOURCES += empty # 2: { 0, 1, 0 } +SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } +SPD_SOURCES += empty # 4: { 1, 0, 0 } +SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } +SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } +SPD_SOURCES += empty # 7: { 1, 1, 1 } + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) + +# Include spd rom data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do echo -e -n "\\x$$c"; \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := 0xab diff --git a/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex b/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex new file mode 100644 index 0000000..e73ba62 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_4Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex b/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex new file mode 100644 index 0000000..b790943 --- /dev/null +++ b/src/mainboard/google/samus/spd/elpida_8Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/empty.spd.hex b/src/mainboard/google/samus/spd/empty.spd.hex new file mode 100644 index 0000000..9ec39f1 --- /dev/null +++ b/src/mainboard/google/samus/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex b/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex new file mode 100644 index 0000000..8821050 --- /dev/null +++ b/src/mainboard/google/samus/spd/samsung_4Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 +4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex b/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex new file mode 100644 index 0000000..a7a1409 --- /dev/null +++ b/src/mainboard/google/samus/spd/samsung_8Gb.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 F0 0A 3C 3C 01 40 83 01 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c new file mode 100644 index 0000000..331fc6d --- /dev/null +++ b/src/mainboard/google/samus/spd/spd.c @@ -0,0 +1,121 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/byteorder.h> +#include <cbfs.h> +#include <console/console.h> +#include <string.h> +#include <broadwell/gpio.h> +#include <broadwell/pei_data.h> +#include <broadwell/romstage.h> +#include <mainboard/google/samus/gpio.h> +#include <mainboard/google/samus/spd/spd.h> + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " + "density %d Mb\n", banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + int spd_gpio[3]; + int spd_index; + int spd_file_len; + struct cbfs_file *spd_file; + + spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); + spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); + spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + + spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", + spd_index, + SPD_GPIO_BIT2, spd_gpio[2], + SPD_GPIO_BIT1, spd_gpio[1], + SPD_GPIO_BIT0, spd_gpio[0]); + + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + if (!spd_file) + die("SPD data not found."); + spd_file_len = ntohl(spd_file->len); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Assume same memory in both channels */ + spd_index *= SPD_LEN; + memcpy(pei_data->spd_data[0][0], + ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[1][0], + ((char*)CBFS_SUBHEADER(spd_file)) + spd_index, SPD_LEN); + + mainboard_print_spd_info(pei_data->spd_data[0][0]); +} diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h new file mode 100644 index 0000000..98180fa --- /dev/null +++ b/src/mainboard/google/samus/spd/spd.h @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Samus board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 67 +#define SPD_GPIO_BIT1 68 +#define SPD_GPIO_BIT2 69 + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif

1 0

Patch set updated for coreboot: fbc9ea1 samus: Update for board revision 1.9
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8007 -gerrit commit fbc9ea1c2a08134f93c61a89a34fbd814c9f50e1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu May 22 08:25:36 2014 -0700 samus: Update for board revision 1.9 - Update GPIO map - Update SPD for new memory and 4-bit table decode - Enable USB3 port 3 and 4 (shared with PCIe port 1) - Enable PCIe port 3 and disable port 1 - Enable SerialIO ACPI mode for devices - Disable S0ix for now to prevent use of C10 - Special handling for memory with broadwell CPU BUG=chrome-os-partner:28234 TEST=Boot on P1.9 Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201083 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6 --- .../google/samus/acpi/haswell_pci_irqs.asl | 91 ----------- src/mainboard/google/samus/acpi/mainboard.asl | 169 ++++++++++++++++----- src/mainboard/google/samus/devicetree.cb | 15 +- src/mainboard/google/samus/gpio.h | 30 ++-- src/mainboard/google/samus/mainboard.c | 66 +------- src/mainboard/google/samus/onboard.h | 70 --------- src/mainboard/google/samus/pei_data.c | 22 +-- src/mainboard/google/samus/romstage.c | 18 ++- src/mainboard/google/samus/spd/Makefile.inc | 26 ++-- src/mainboard/google/samus/spd/hynix_4Gb.spd.hex | 18 +++ src/mainboard/google/samus/spd/hynix_8Gb.spd.hex | 18 +++ src/mainboard/google/samus/spd/spd.c | 11 +- src/mainboard/google/samus/spd/spd.h | 1 + 13 files changed, 246 insertions(+), 309 deletions(-) diff --git a/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl b/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 336a1ac..0000000 --- a/src/mainboard/google/samus/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for Haswell ULT */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, 0, 23 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // Audio DSP (Smart Sound) 0:13.0 - Package() { 0x0013ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/samus/acpi/mainboard.asl b/src/mainboard/google/samus/acpi/mainboard.asl index 72bff6c..5a052b9 100644 --- a/src/mainboard/google/samus/acpi/mainboard.asl +++ b/src/mainboard/google/samus/acpi/mainboard.asl @@ -1,12 +1,11 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,21 +14,17 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <mainboard/google/samus/onboard.h> - Scope (\_SB) { Device (LID0) { - Name(_HID, EisaId("PNP0C0D")) - Method(_LID, 0) + Name (_HID, EisaId("PNP0C0D")) + Method (_LID, 0) { - Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS) - Return (\LIDS) + Return (\_SB.PCI0.LPCB.EC0.LIDS) } // There is no GPIO for LID, the EC pulses WAKE# pin instead. @@ -44,49 +39,149 @@ Scope (\_SB) Device (TPAD) { - Name (_ADR, 0x0) + Name (_HID, EisaId("PNP0C0E")) Name (_UID, 1) + Name (_PRW, Package() { 13, 0x3 }) // GPIO13 + } - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source + Device (TSCR) + { Name (_HID, EisaId("PNP0C0E")) + Name (_UID, 2) + Name (_PRW, Package() { 14, 0x3 }) // GPIO14 + } +} + +Scope (\_SB.PCI0.I2C0) +{ + Device (ATPB) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad Bootloader") + Name (_UID, 1) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */ Name (_CRS, ResourceTemplate() { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TRACKPAD_IRQ - } + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) - VendorShort (ADDR) - { - BOARD_TRACKPAD_I2C_ADDR - } + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } }) - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } } - Device (TSCR) + Device (ATPA) { - Name (_ADR, 0x0) + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") Name (_UID, 2) - - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */ Name (_CRS, ResourceTemplate() { - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_TOUCHSCREEN_IRQ + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) + + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Edge, ActiveLow) { 27 } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } + } + } +} + +Scope (\_SB.PCI0.I2C1) +{ + Device (ATSB) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen Bootloader") + Name (_UID, 4) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ - VendorShort (ADDR) - { - BOARD_TOUCHSCREEN_I2C_ADDR + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } + } + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Edge, ActiveLow) { 28 } }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } } } diff --git a/src/mainboard/google/samus/devicetree.cb b/src/mainboard/google/samus/devicetree.cb index 3e87eca..8810c47 100644 --- a/src/mainboard/google/samus/devicetree.cb +++ b/src/mainboard/google/samus/devicetree.cb @@ -43,16 +43,17 @@ chip soc/intel/broadwell register "gpe0_en_4" = "0x00000000" register "sata_port_map" = "0x1" - register "sio_acpi_mode" = "0" + register "sio_acpi_mode" = "1" - # Force enable ASPM for PCIe Port 1 - register "pcie_port_force_aspm" = "0x01" + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP - register "icc_clock_disable" = "0x013e0000" + register "icc_clock_disable" = "0x013b0000" # Enable S0ix - register "s0ix_enable" = "1" + register "s0ix_enable" = "0" device cpu_cluster 0 on device lapic 0 on end @@ -77,9 +78,9 @@ chip soc/intel/broadwell device pci 17.0 off end # SDIO device pci 19.0 off end # GbE device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 + device pci 1c.0 off end # PCIe Port #1 device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 + device pci 1c.2 on end # PCIe Port #3 device pci 1c.3 off end # PCIe Port #4 device pci 1c.4 off end # PCIe Port #5 device pci 1c.5 off end # PCIe Port #6 diff --git a/src/mainboard/google/samus/gpio.h b/src/mainboard/google/samus/gpio.h index c98be4d..f68ecdf 100644 --- a/src/mainboard/google/samus/gpio.h +++ b/src/mainboard/google/samus/gpio.h @@ -34,7 +34,7 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ - PCH_GPIO_IRQ_EDGE, /* 9: NFC_INT (GPIO IRQ) */ + PCH_GPIO_PIRQ, /* 9: NFC_INT (PIRQ) */ PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ PCH_GPIO_UNUSED, /* 11: UNUSED */ PCH_GPIO_UNUSED, /* 12: UNUSED */ @@ -43,9 +43,9 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ PCH_GPIO_INPUT, /* 16: PCH_WP */ PCH_GPIO_UNUSED, /* 17: UNUSED */ - PCH_GPIO_NATIVE, /* 18: PCIE_WLAN_CLKREQ_L */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ PCH_GPIO_UNUSED, /* 19: UNUSED */ - PCH_GPIO_UNUSED, /* 20: UNUSED */ + PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */ PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */ PCH_GPIO_UNUSED, /* 22: UNUSED */ PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */ @@ -69,12 +69,12 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */ PCH_GPIO_OUT_HIGH, /* 42: WLAN_DISABLE_L */ PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */ - PCH_GPIO_OUT_HIGH, /* 44: CODEC_LDOENA */ - PCH_GPIO_PIRQ, /* 45: ACCEL_INT (PIRQW) */ - PCH_GPIO_PIRQ, /* 46: CODEC_INT_L (PIRQO) */ - PCH_GPIO_PIRQ, /* 47: ACCEL_GYRO_INT (PIRQP) */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_PIRQ, /* 45: DSP_INT (PIRQN) */ + PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L (PIRQO) */ + PCH_GPIO_OUT_HIGH, /* 47: SSD_RESET_L */ PCH_GPIO_UNUSED, /* 48: UNUSED */ - PCH_GPIO_INPUT, /* 49: HDMI_CEC */ + PCH_GPIO_UNUSED, /* 49: UNUSED */ PCH_GPIO_UNUSED, /* 50: UNUSED */ PCH_GPIO_UNUSED, /* 51: UNUSED */ PCH_GPIO_INPUT, /* 52: SIM_DET */ @@ -88,10 +88,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 60: UNUSED */ PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ - PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SS5_L */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ PCH_GPIO_OUT_LOW, /* 64: NFC_FW_UPDATE */ - PCH_GPIO_INPUT, /* 65: MINIDP_PWR_FLT_L */ - PCH_GPIO_OUT_HIGH, /* 66: MINIDP_PWR_EN */ + PCH_GPIO_UNUSED, /* 65: UNUSED */ + PCH_GPIO_INPUT, /* 66: RAM_ID3 */ PCH_GPIO_INPUT, /* 67: RAM_ID0 */ PCH_GPIO_INPUT, /* 68: RAM_ID1 */ PCH_GPIO_INPUT, /* 69: RAM_ID2 */ @@ -116,10 +116,10 @@ static const struct gpio_config mainboard_gpio_config[] = { PCH_GPIO_UNUSED, /* 88: UNUSED */ PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */ PCH_GPIO_UNUSED, /* 90: UNUSED */ - PCH_GPIO_NATIVE, /* 91: NATIVE: UART0_PCHRX_BTTX */ - PCH_GPIO_NATIVE, /* 92: NATIVE: UART0_PCHTX_BTRX */ - PCH_GPIO_NATIVE, /* 93: NATIVE: UART0_PCHRTS_BTCTS_L */ - PCH_GPIO_NATIVE, /* 94: NATIVE: UART0_PCHCTS_BTRTS_L */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ PCH_GPIO_END }; diff --git a/src/mainboard/google/samus/mainboard.c b/src/mainboard/google/samus/mainboard.c index fdc7d78..89303b9 100644 --- a/src/mainboard/google/samus/mainboard.c +++ b/src/mainboard/google/samus/mainboard.c @@ -33,73 +33,14 @@ #include <arch/interrupt.h> #include <boot/coreboot_tables.h> #include "ec.h" -#include "onboard.h" -static void mainboard_init(device_t dev) +void mainboard_suspend_resume(void) { - mainboard_ec_init(); } -static int mainboard_smbios_data(device_t dev, int *handle, - unsigned long *current) +static void mainboard_init(device_t dev) { - int len = 0; - - len += smbios_write_type41( - current, handle, - BOARD_TRACKPAD_NAME, /* name */ - BOARD_TRACKPAD_IRQ, /* instance */ - BOARD_TRACKPAD_I2C_BUS, /* segment */ - BOARD_TRACKPAD_I2C_ADDR, /* bus */ - BOARD_TRACKPAD_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_TOUCHSCREEN_NAME, /* name */ - BOARD_TOUCHSCREEN_IRQ, /* instance */ - BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ - BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ - BOARD_TOUCHSCREEN_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_CODEC_NAME, /* name */ - BOARD_CODEC_IRQ, /* instance */ - BOARD_CODEC_I2C_BUS, /* segment */ - BOARD_CODEC_I2C_ADDR, /* bus */ - BOARD_CODEC_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_NFC_NAME, /* name */ - BOARD_NFC_IRQ, /* instance */ - BOARD_NFC_I2C_BUS, /* segment */ - BOARD_NFC_I2C_ADDR, /* bus */ - BOARD_NFC_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_ACCEL_NAME, /* name */ - BOARD_ACCEL_IRQ, /* instance */ - BOARD_ACCEL_I2C_BUS, /* segment */ - BOARD_ACCEL_I2C_ADDR, /* bus */ - BOARD_ACCEL_IRQ_TYPE, /* device */ - 0); /* function */ - - len += smbios_write_type41( - current, handle, - BOARD_ACCEL_GYRO_NAME, /* name */ - BOARD_ACCEL_GYRO_IRQ, /* instance */ - BOARD_ACCEL_GYRO_I2C_BUS, /* segment */ - BOARD_ACCEL_GYRO_I2C_ADDR, /* bus */ - BOARD_ACCEL_GYRO_IRQ_TYPE, /* device */ - 0); /* function */ - - return len; + mainboard_ec_init(); } // mainboard_enable is executed as first thing after @@ -108,7 +49,6 @@ static int mainboard_smbios_data(device_t dev, int *handle, static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->get_smbios_data = mainboard_smbios_data; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0); } diff --git a/src/mainboard/google/samus/onboard.h b/src/mainboard/google/samus/onboard.h deleted file mode 100644 index d47d3c9..0000000 --- a/src/mainboard/google/samus/onboard.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -#define BOARD_PIRQ_INTERRUPT 0 -#define BOARD_GPIO_INTERRUPT 1 -#define BOARD_GPIO_OFFSET 162 -#define GPIO_INTERRUPT(x) (BOARD_GPIO_OFFSET + (x)) - -#define BOARD_TRACKPAD_NAME "trackpad" -#define BOARD_TRACKPAD_IRQ 27 /* PIRQL */ -#define BOARD_TRACKPAD_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_TRACKPAD_WAKE_GPIO 13 /* GPIO13 */ -#define BOARD_TRACKPAD_I2C_BUS 1 /* I2C0 */ -#define BOARD_TRACKPAD_I2C_ADDR 0x4b - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ 28 /* PIRQM */ -#define BOARD_TOUCHSCREEN_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */ -#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* I2C1 */ -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b - -#define BOARD_CODEC_NAME "codec" -#define BOARD_CODEC_IRQ 30 /* PIRQO */ -#define BOARD_CODEC_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_CODEC_WAKE_GPIO 46 /* GPIO46 */ -#define BOARD_CODEC_I2C_BUS 1 /* I2C0 */ -#define BOARD_CODEC_I2C_ADDR 0x1a - -#define BOARD_NFC_NAME "nfc" -#define BOARD_NFC_IRQ GPIO_INTERRUPT(9) -#define BOARD_NFC_IRQ_TYPE BOARD_GPIO_INTERRUPT -#define BOARD_NFC_WAKE_GPIO 9 /* GPIO9 */ -#define BOARD_NFC_I2C_BUS 1 /* I2C0 */ -#define BOARD_NFC_I2C_ADDR 0x28 - -#define BOARD_ACCEL_NAME "accel" -#define BOARD_ACCEL_IRQ 29 /* PIRQN */ -#define BOARD_ACCEL_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_ACCEL_WAKE_GPIO 45 /* GPIO45 */ -#define BOARD_ACCEL_I2C_BUS 2 /* I2C1 */ -#define BOARD_ACCEL_I2C_ADDR 0x0e - -#define BOARD_ACCEL_GYRO_NAME "accel_gyro" -#define BOARD_ACCEL_GYRO_IRQ 31 /* PIRQP */ -#define BOARD_ACCEL_GYRO_IRQ_TYPE BOARD_PIRQ_INTERRUPT -#define BOARD_ACCEL_GYRO_WAKE_GPIO 47 /* GPIO47 */ -#define BOARD_ACCEL_GYRO_I2C_BUS 2 /* I2C1 */ -#define BOARD_ACCEL_GYRO_I2C_ADDR 0x6b - -#endif diff --git a/src/mainboard/google/samus/pei_data.c b/src/mainboard/google/samus/pei_data.c index c4e9c0b..04b86e0 100644 --- a/src/mainboard/google/samus/pei_data.c +++ b/src/mainboard/google/samus/pei_data.c @@ -51,15 +51,15 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) /* P1: HOST PORT */ pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, USB_PORT_BACK_PANEL); - /* P2: EMPTY */ - pei_data_usb2_port(pei_data, 2, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P2: RAIDEN */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P3: SD CARD */ - pei_data_usb2_port(pei_data, 3, 0x0040, 0, USB_OC_PIN_SKIP, + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); - /* P4: EMPTY */ - pei_data_usb2_port(pei_data, 4, 0x0000, 0, USB_OC_PIN_SKIP, - USB_PORT_SKIP); + /* P4: RAIDEN */ + pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); /* P5: WWAN */ pei_data_usb2_port(pei_data, 5, 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_INTERNAL); @@ -74,8 +74,8 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data_usb3_port(pei_data, 0, 1, 0, 0); /* P2: HOST PORT */ pei_data_usb3_port(pei_data, 1, 1, 1, 0); - /* P3: EMPTY */ - pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); - /* P4: SD CARD */ - pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); + /* P3: RAIDEN */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4: RAIDEN */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); } diff --git a/src/mainboard/google/samus/romstage.c b/src/mainboard/google/samus/romstage.c index 9af4ffb..9594287 100644 --- a/src/mainboard/google/samus/romstage.c +++ b/src/mainboard/google/samus/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,12 +22,13 @@ #include <console/console.h> #include <string.h> #include <ec/google/chromeec/ec.h> +#include <broadwell/cpu.h> //#include <broadwell/gpio.h> #include <broadwell/pei_data.h> #include <broadwell/pei_wrapper.h> #include <broadwell/romstage.h> #include <mainboard/google/samus/spd/spd.h> -#include "gpio.h" +#include <mainboard/google/samus/gpio.h> void mainboard_romstage_entry(struct romstage_params *rp) { @@ -35,6 +36,9 @@ void mainboard_romstage_entry(struct romstage_params *rp) post_code(0x32); + printk(BIOS_INFO, "MLB: board version %d\n", + google_chromeec_get_board_version()); + /* Ensure the EC is in the right mode for recovery */ google_chromeec_early_init(); @@ -47,6 +51,16 @@ void mainboard_romstage_entry(struct romstage_params *rp) mainboard_fill_spd_data(&pei_data); rp->pei_data = &pei_data; + /* + * http://crosbug.com/p/29117 + * Limit Broadwell SKU to 1333MHz and disable channel 1 + */ + if (cpu_family_model() == BROADWELL_FAMILY_ULT) { + pei_data.max_ddr3_freq = 1333; + pei_data.dimm_channel1_disabled = 3; + memset(pei_data.spd_data[1][0], 0, SPD_LEN); + } + romstage_common(rp); /* diff --git a/src/mainboard/google/samus/spd/Makefile.inc b/src/mainboard/google/samus/spd/Makefile.inc index 657a09d..ccce912 100644 --- a/src/mainboard/google/samus/spd/Makefile.inc +++ b/src/mainboard/google/samus/spd/Makefile.inc @@ -21,15 +21,23 @@ romstage-y += spd.c SPD_BIN = $(obj)/spd.bin -# { GPIO69, GPIO68, GPIO67 } -SPD_SOURCES = empty # 0: { 0, 0, 0 } -SPD_SOURCES += elpida_4Gb # 1: { 0, 0, 1 } -SPD_SOURCES += empty # 2: { 0, 1, 0 } -SPD_SOURCES += elpida_8Gb # 3: { 0, 1, 1 } -SPD_SOURCES += empty # 4: { 1, 0, 0 } -SPD_SOURCES += samsung_8Gb # 5: { 1, 0, 1 } -SPD_SOURCES += samsung_4Gb # 6: { 1, 1, 0 } -SPD_SOURCES += empty # 7: { 1, 1, 1 } +# { GPIO66, GPIO69, GPIO68, GPIO67 } +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += empty # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += empty # 0b0011 +SPD_SOURCES += empty # 0b0100 +SPD_SOURCES += empty # 0b0101 +SPD_SOURCES += samsung_4Gb # 0b0110 +SPD_SOURCES += empty # 0b0111 +SPD_SOURCES += hynix_4Gb # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += samsung_8Gb # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += hynix_8Gb # 0b1100 +SPD_SOURCES += empty # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += empty # 0b1111 SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex new file mode 100644 index 0000000..c63c303 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_4Gb.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3-S8B 8Gb(x32, 2CS) +# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex new file mode 100644 index 0000000..14002c1 --- /dev/null +++ b/src/mainboard/google/samus/spd/hynix_8Gb.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNN8JTMLAR-NTM LPDDR3-S8B 16Gb(x32, 2CS) +# banks 8, ranks 2, rows 15, columns 10, density 8192 Mb, x32 +92 11 F1 03 05 19 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 +48 39 43 43 4E 4E 4E 38 4A 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/samus/spd/spd.c b/src/mainboard/google/samus/spd/spd.c index 331fc6d..0409302 100644 --- a/src/mainboard/google/samus/spd/spd.c +++ b/src/mainboard/google/samus/spd/spd.c @@ -80,7 +80,7 @@ static void mainboard_print_spd_info(uint8_t spd[]) /* Copy SPD data for on-board memory */ void mainboard_fill_spd_data(struct pei_data *pei_data) { - int spd_gpio[3]; + int spd_gpio[4]; int spd_index; int spd_file_len; struct cbfs_file *spd_file; @@ -88,11 +88,14 @@ void mainboard_fill_spd_data(struct pei_data *pei_data) spd_gpio[0] = get_gpio(SPD_GPIO_BIT0); spd_gpio[1] = get_gpio(SPD_GPIO_BIT1); spd_gpio[2] = get_gpio(SPD_GPIO_BIT2); + spd_gpio[3] = get_gpio(SPD_GPIO_BIT3); - spd_index = spd_gpio[2] << 2 | spd_gpio[1] << 1 | spd_gpio[0]; + spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | + (spd_gpio[1] << 1) | spd_gpio[0]; - printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d GPIO%d=%d)\n", - spd_index, + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " + "GPIO%d=%d GPIO%d=%d)\n", spd_index, + SPD_GPIO_BIT3, spd_gpio[3], SPD_GPIO_BIT2, spd_gpio[2], SPD_GPIO_BIT1, spd_gpio[1], SPD_GPIO_BIT0, spd_gpio[0]); diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index 98180fa..77540af 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -36,6 +36,7 @@ #define SPD_GPIO_BIT0 67 #define SPD_GPIO_BIT1 68 #define SPD_GPIO_BIT2 69 +#define SPD_GPIO_BIT3 66 struct pei_data; void mainboard_fill_spd_data(struct pei_data *pei_data);

1 0

Patch set updated for coreboot: 3b03f71 wtm2: Convert to use soc/intel/broadwell
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8001 -gerrit commit 3b03f714a9b0f6f2cb08838e7c34adf5c6a733e0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 14 17:03:15 2014 -0700 wtm2: Convert to use soc/intel/broadwell Convert wtm2 board to use the broadwell soc chipset. BUG=chrome-os-partner:28234 TEST=Build and boot on wtm2 with haswell and broadwell CQ-DEPEND=CL:201067 CQ-DEPEND=CL:*164226 Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/201070 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> (cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda --- src/mainboard/intel/wtm2/Kconfig | 18 +- src/mainboard/intel/wtm2/Makefile.inc | 3 + src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl | 75 -------- src/mainboard/intel/wtm2/acpi/thermal.asl | 21 +-- src/mainboard/intel/wtm2/acpi_tables.c | 75 +------- src/mainboard/intel/wtm2/chromeos.c | 2 +- src/mainboard/intel/wtm2/devicetree.cb | 118 +++++-------- src/mainboard/intel/wtm2/dsdt.asl | 22 ++- src/mainboard/intel/wtm2/fadt.c | 112 +----------- src/mainboard/intel/wtm2/gpio.h | 196 ++++++++++----------- src/mainboard/intel/wtm2/mainboard.c | 3 - src/mainboard/intel/wtm2/mainboard_smi.c | 30 +--- src/mainboard/intel/wtm2/pei_data.c | 57 ++++++ src/mainboard/intel/wtm2/romstage.c | 129 ++------------ 14 files changed, 273 insertions(+), 588 deletions(-) diff --git a/src/mainboard/intel/wtm2/Kconfig b/src/mainboard/intel/wtm2/Kconfig index c868e73..7b4565f 100644 --- a/src/mainboard/intel/wtm2/Kconfig +++ b/src/mainboard/intel/wtm2/Kconfig @@ -2,10 +2,7 @@ if BOARD_INTEL_WTM2 config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_INTEL_SOCKET_RPGA989 - select NORTHBRIDGE_INTEL_HASWELL - select SOUTHBRIDGE_INTEL_LYNXPOINT - select INTEL_LYNXPOINT_LP + select SOC_INTEL_BROADWELL select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE @@ -16,6 +13,16 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MONOTONIC_TIMER_MSR select INTEL_INT15 + select CHROMEOS_RAMOOPS_DYNAMIC + +config VBOOT_RAMSTAGE_INDEX + hex + default 0x1 + +config VBOOT_REFCODE_INDEX + hex + default 0x2 + config MAINBOARD_DIR string default intel/wtm2 @@ -24,9 +31,6 @@ config MAINBOARD_PART_NUMBER string default "WHITETIP MOUNTAIN 2" -config MMCONF_BASE_ADDRESS - hex - default 0xf0000000 config MAX_CPUS int diff --git a/src/mainboard/intel/wtm2/Makefile.inc b/src/mainboard/intel/wtm2/Makefile.inc index e519bb2..cbd993e 100644 --- a/src/mainboard/intel/wtm2/Makefile.inc +++ b/src/mainboard/intel/wtm2/Makefile.inc @@ -24,3 +24,6 @@ ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += graphics.c ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += intel_dp.c smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c + +romstage-y += pei_data.c +ramstage-y += pei_data.c diff --git a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl deleted file mode 100644 index d91f9a4..0000000 --- a/src/mainboard/intel/wtm2/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,75 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 20 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 16 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 21 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 16 }, - Package() { 0x0015ffff, 1, 0, 17 }, - Package() { 0x0015ffff, 2, 0, 18 }, - Package() { 0x0015ffff, 3, 0, 19 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/intel/wtm2/acpi/thermal.asl b/src/mainboard/intel/wtm2/acpi/thermal.asl index 36310e4..7a15302 100644 --- a/src/mainboard/intel/wtm2/acpi/thermal.asl +++ b/src/mainboard/intel/wtm2/acpi/thermal.asl @@ -18,6 +18,7 @@ */ // Thermal Zone +#include "../thermal.h" Scope (\_TZ) { @@ -68,41 +69,41 @@ Scope (\_TZ) Method (_AC0) { If (LLessEqual (\FLVL, 0)) { - Return (CTOK (\F0OF)) + Return (CTOK (FAN0_THRESHOLD_OFF)) } Else { - Return (CTOK (\F0ON)) + Return (CTOK (FAN0_THRESHOLD_ON)) } } Method (_AC1) { If (LLessEqual (\FLVL, 1)) { - Return (CTOK (\F1OF)) + Return (CTOK (FAN1_THRESHOLD_OFF)) } Else { - Return (CTOK (\F1ON)) + Return (CTOK (FAN1_THRESHOLD_ON)) } } Method (_AC2) { If (LLessEqual (\FLVL, 2)) { - Return (CTOK (\F2OF)) + Return (CTOK (FAN2_THRESHOLD_OFF)) } Else { - Return (CTOK (\F2ON)) + Return (CTOK (FAN2_THRESHOLD_ON)) } } Method (_AC3) { If (LLessEqual (\FLVL, 3)) { - Return (CTOK (\F3OF)) + Return (CTOK (FAN3_THRESHOLD_OFF)) } Else { - Return (CTOK (\F3ON)) + Return (CTOK (FAN3_THRESHOLD_ON)) } } Method (_AC4) { If (LLessEqual (\FLVL, 4)) { - Return (CTOK (\F4OF)) + Return (CTOK (FAN4_THRESHOLD_OFF)) } Else { - Return (CTOK (\F4ON)) + Return (CTOK (FAN4_THRESHOLD_ON)) } } diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 20814ab..b6c0f9a 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -29,67 +29,26 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <vendorcode/google/chromeos/gnvs.h> - -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/nvs.h> +#include <broadwell/acpi.h> +#include <broadwell/nvs.h> #include "thermal.h" -static void acpi_update_thermal_table(global_nvs_t *gnvs) -{ - gnvs->f4of = FAN4_THRESHOLD_OFF; - gnvs->f4on = FAN4_THRESHOLD_ON; - gnvs->f4pw = FAN4_PWM; - - gnvs->f3of = FAN3_THRESHOLD_OFF; - gnvs->f3on = FAN3_THRESHOLD_ON; - gnvs->f3pw = FAN3_PWM; - - gnvs->f2of = FAN2_THRESHOLD_OFF; - gnvs->f2on = FAN2_THRESHOLD_ON; - gnvs->f2pw = FAN2_PWM; - - gnvs->f1of = FAN1_THRESHOLD_OFF; - gnvs->f1on = FAN1_THRESHOLD_ON; - gnvs->f1pw = FAN1_PWM; - - gnvs->f0of = FAN0_THRESHOLD_OFF; - gnvs->f0on = FAN0_THRESHOLD_ON; - gnvs->f0pw = FAN0_PWM; - - gnvs->tcrt = CRITICAL_TEMPERATURE; - gnvs->tpsv = PASSIVE_TEMPERATURE; - gnvs->tmax = MAX_TEMPERATURE; -} - void acpi_create_gnvs(global_nvs_t *gnvs) { + acpi_init_gnvs(gnvs); + /* Enable USB ports in S3 */ gnvs->s3u0 = 1; - gnvs->s3u1 = 1; /* Disable USB ports in S5 */ gnvs->s5u0 = 0; - gnvs->s5u1 = 0; /* TPM Present */ gnvs->tpmp = 1; - /* IGD Displays */ - gnvs->ndid = 3; - gnvs->did[0] = 0x80000100; - gnvs->did[1] = 0x80000240; - gnvs->did[2] = 0x80000410; - gnvs->did[3] = 0x80000410; - gnvs->did[4] = 0x00000005; - -#if CONFIG_CHROMEOS - /* Emerald Lake has no EC (?) */ - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; -#endif - - acpi_update_thermal_table(gnvs); + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tmax = MAX_TEMPERATURE; } unsigned long acpi_fill_madt(unsigned long current) @@ -101,23 +60,5 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} - -unsigned long acpi_fill_slit(unsigned long current) -{ - // Not implemented - return current; -} - -unsigned long acpi_fill_srat(unsigned long current) -{ - /* No NUMA, no SRAT */ - return current; + return acpi_madt_irq_overrides(current); } diff --git a/src/mainboard/intel/wtm2/chromeos.c b/src/mainboard/intel/wtm2/chromeos.c index 1461a15..fe469f7 100644 --- a/src/mainboard/intel/wtm2/chromeos.c +++ b/src/mainboard/intel/wtm2/chromeos.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <southbridge/intel/lynxpoint/pch.h> +#include <broadwell/gpio.h> /* Compile-time settings for developer and recovery mode. */ #define DEV_MODE_SETTING 1 diff --git a/src/mainboard/intel/wtm2/devicetree.cb b/src/mainboard/intel/wtm2/devicetree.cb index 2790cb9..54b2bff 100644 --- a/src/mainboard/intel/wtm2/devicetree.cb +++ b/src/mainboard/intel/wtm2/devicetree.cb @@ -1,4 +1,4 @@ -chip northbridge/intel/haswell +chip soc/intel/broadwell # Enable DisplayPort 1 Hotplug with 6ms pulse register "gpu_dp_d_hotplug" = "0x06" @@ -9,80 +9,58 @@ chip northbridge/intel/haswell # Enable DVI Hotplug with 6ms pulse register "gpu_dp_b_hotplug" = "0x06" - device cpu_cluster 0 on - chip cpu/intel/socket_rPGA989 - device lapic 0 on end - end - chip cpu/intel/haswell - # Magic APIC ID to locate this chip - device lapic 0xACAC off end + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" - register "c1_battery" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_battery" = "9" # ACPI(C2) = MWAIT(C7S) - register "c3_battery" = "12" # ACPI(C3) = MWAIT(C10) + register "alt_gp_smi_en" = "0x0000" + register "gpe0_en_1" = "0x00000400" + register "gpe0_en_2" = "0x00000000" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" - register "c1_acpower" = "2" # ACPI(C1) = MWAIT(C1E) - register "c2_acpower" = "9" # ACPI(C2) = MWAIT(C7S) - register "c3_acpower" = "12" # ACPI(C3) = MWAIT(C10) - end - end + register "sata_port_map" = "0x2" + register "sio_acpi_mode" = "1" + device cpu_cluster 0 on + device lapic 0 on end + end device domain 0 on device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller - - chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - register "alt_gp_smi_en" = "0x0000" - register "gpe0_en_1" = "0x00000400" - register "gpe0_en_2" = "0x00000000" - register "gpe0_en_3" = "0x00000000" - register "gpe0_en_4" = "0x00000000" - - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" - register "sata_port_map" = "0x2" - - register "sio_acpi_mode" = "1" - register "sio_i2c0_voltage" = "0" # 3.3V - register "sio_i2c1_voltage" = "0" # 3.3V - - device pci 13.0 on end # Smart Sound Audio DSP - device pci 14.0 on end # USB3 XHCI - device pci 15.0 on end # Serial I/O DMA - device pci 15.1 on end # I2C0 - device pci 15.2 on end # I2C1 - device pci 15.3 on end # GSPI0 - device pci 15.4 on end # GSPI1 - device pci 15.5 on end # UART0 - device pci 15.6 on end # UART1 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 17.0 on end # SDIO - device pci 19.0 on end # GbE - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1d.0 on end # USB2 EHCI - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller - device pci 1f.3 on end # SMBus - device pci 1f.6 on end # Thermal - end + device pci 03.0 on end # mini-hd audio + device pci 13.0 off end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 off end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus + device pci 1f.6 on end # Thermal end end diff --git a/src/mainboard/intel/wtm2/dsdt.asl b/src/mainboard/intel/wtm2/dsdt.asl index 112a47a..b920cd4 100644 --- a/src/mainboard/intel/wtm2/dsdt.asl +++ b/src/mainboard/intel/wtm2/dsdt.asl @@ -33,26 +33,32 @@ DefinitionBlock( #include "acpi/platform.asl" // global NVS and variables - #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <soc/intel/broadwell/acpi/globalnvs.asl> // General Purpose Events //#include "acpi/gpe.asl" - #include "acpi/thermal.asl" - - #include "../../../cpu/intel/haswell/acpi/cpu.asl" + // CPU + #include <soc/intel/broadwell/acpi/cpu.asl> Scope (\_SB) { Device (PCI0) { - #include <northbridge/intel/haswell/acpi/haswell.asl> - #include <southbridge/intel/lynxpoint/acpi/pch.asl> + #include <soc/intel/broadwell/acpi/systemagent.asl> + #include <soc/intel/broadwell/acpi/pch.asl> } } + // Thermal handler + #include "acpi/thermal.asl" + + // Chrome OS specific #include "acpi/chromeos.asl" #include <vendorcode/google/chromeos/acpi/chromeos.asl> - /* Chipset specific sleep states */ - #include <southbridge/intel/lynxpoint/acpi/sleepstates.asl> + // Chipset specific sleep states + #include <soc/intel/broadwell/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/intel/wtm2/fadt.c b/src/mainboard/intel/wtm2/fadt.c index 7afbbfa..a8811d2 100644 --- a/src/mainboard/intel/wtm2/fadt.c +++ b/src/mainboard/intel/wtm2/fadt.c @@ -18,20 +18,16 @@ */ #include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/pch.h> +#include <broadwell/acpi.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) { acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); memset((void *) fadt, 0, sizeof(acpi_fadt_t)); memcpy(header->signature, "FACP", 4); header->length = sizeof(acpi_fadt_t); - header->revision = 3; + header->revision = 5; memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); memcpy(header->asl_compiler_id, ASLC, 4); @@ -42,114 +38,12 @@ void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) fadt->model = 1; fadt->preferred_pm_profile = PM_MOBILE; - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; fadt->x_firmware_ctl_l = (unsigned long)facs; fadt->x_firmware_ctl_h = 0; fadt->x_dsdt_l = (unsigned long)dsdt; fadt->x_dsdt_h = 0; - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; + acpi_fill_in_fadt(fadt); header->checksum = acpi_checksum((void *) fadt, header->length); diff --git a/src/mainboard/intel/wtm2/gpio.h b/src/mainboard/intel/wtm2/gpio.h index 884fd66..47272b8 100644 --- a/src/mainboard/intel/wtm2/gpio.h +++ b/src/mainboard/intel/wtm2/gpio.h @@ -20,105 +20,105 @@ #ifndef INTEL_WTM2_GPIO_H #define INTEL_WTM2_GPIO_H -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <broadwell/gpio.h> -static const struct pch_lp_gpio_map mainboard_gpio_map[] = { - LP_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ - LP_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ - LP_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ - LP_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ - LP_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ - LP_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ - LP_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ - LP_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ - LP_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ - LP_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ - LP_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ - LP_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ - LP_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ - LP_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ - LP_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ - LP_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ - LP_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ - LP_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ - LP_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ - LP_GPIO_INPUT, /* 19: EC_IN_RW */ - LP_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ - LP_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ - LP_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ - LP_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ - LP_GPIO_OUT_LOW, /* 24: ME_PG_LED */ - LP_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ - LP_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ - LP_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ - LP_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ - LP_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ - LP_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ - LP_GPIO_NATIVE, /* 31: AC_PRESENT_R */ - LP_GPIO_NATIVE, /* 32: PM_CKRUN_N */ - LP_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ - LP_GPIO_INPUT, /* 34: ESATA_DET_N */ - LP_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ - LP_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ - LP_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ - LP_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ - LP_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ - LP_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ - LP_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ - LP_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ - LP_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ - LP_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ - LP_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ - LP_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ - LP_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ - LP_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ - LP_GPIO_INPUT, /* 49: COMBO_JD */ - LP_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ - LP_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ - LP_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ - LP_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ - LP_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ - LP_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ - LP_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ - LP_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ - LP_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ - LP_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ - LP_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ - LP_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ - LP_GPIO_NATIVE, /* 62: SUS_CK */ - LP_GPIO_NATIVE, /* 63: SLP_S5_R_N */ - LP_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ - LP_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ - LP_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ - LP_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ - LP_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ - LP_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ - LP_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ - LP_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ - LP_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ - LP_GPIO_NATIVE, /* 73: PCH_NOT_N */ - LP_GPIO_NATIVE, /* 74: SML1_DATA */ - LP_GPIO_NATIVE, /* 75: SML1_CK */ - LP_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ - LP_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ - LP_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ - LP_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ - LP_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ - LP_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ - LP_GPIO_NATIVE, /* 82: H_RCIN_N */ - LP_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ - LP_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ - LP_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ - LP_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ - LP_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ - LP_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ - LP_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ - LP_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ - LP_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ - LP_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ - LP_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ - LP_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ - LP_GPIO_END +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_NATIVE, /* 0: LPSS_UART1_RXD */ + PCH_GPIO_NATIVE, /* 1: LPSS_UART1_TXD */ + PCH_GPIO_NATIVE, /* 2: LPSS_UART1_RTS_N_R */ + PCH_GPIO_NATIVE, /* 3: LPSS_UART1_CTS_N */ + PCH_GPIO_NATIVE, /* 4: LPSS_I2C0_SDA_R */ + PCH_GPIO_NATIVE, /* 5: LPSS_I2C0_SCL */ + PCH_GPIO_NATIVE, /* 6: LPSS_I2C1_SDA */ + PCH_GPIO_NATIVE, /* 7: LPSS_I2C1_SCL */ + PCH_GPIO_UNUSED, /* 8: NGFF_SLTA_WIFI_WAKE_N */ + PCH_GPIO_UNUSED, /* 9: ACCEL_INT2_MCP */ + PCH_GPIO_ACPI_SCI, /* 10: SMC_RUNTIME_SCI_N */ + PCH_GPIO_UNUSED, /* 11: AMB_THRM_R_N */ + PCH_GPIO_NATIVE, /* 12: PM_LANPHY_ENABLE */ + PCH_GPIO_OUT_HIGH, /* 13: USB32_P0_PWREN */ + PCH_GPIO_IRQ_EDGE, /* 14: SH_INT_ACCEL_DRDY_USB_INT_N */ + PCH_GPIO_OUT_HIGH, /* 15: LAN_PWREN_N */ + PCH_GPIO_OUT_HIGH, /* 16: LAN_RST_N */ + PCH_GPIO_OUT_LOW, /* 17: CRIT_TEMP_REP_R_N */ + PCH_GPIO_UNUSED, /* 18: TBT_FORCE_PWR */ + PCH_GPIO_INPUT, /* 19: EC_IN_RW */ + PCH_GPIO_NATIVE, /* 20: CK_REQ_P2_NGFFSLTA_N_R */ + PCH_GPIO_NATIVE, /* 21: CK_PCIE_LAN_REQ_N */ + PCH_GPIO_NATIVE, /* 22: CK_REQ_P4_TBT_N */ + PCH_GPIO_NATIVE, /* 23: CK_REQ_P5_N */ + PCH_GPIO_OUT_LOW, /* 24: ME_PG_LED */ + PCH_GPIO_INPUT, /* 25: USB_WAKEOUT_N */ + PCH_GPIO_IRQ_EDGE, /* 26: NFC_IRQ_MGP5 */ + PCH_GPIO_ACPI_SCI, /* 27: SMC_WAKE_SCI_N */ + PCH_GPIO_OUT_LOW, /* 28: PCH_NFC_RESET */ + PCH_GPIO_NATIVE, /* 29: PCH_SLP_WLAN_N */ + PCH_GPIO_NATIVE, /* 30: SUS_PWR_ACK_R */ + PCH_GPIO_NATIVE, /* 31: AC_PRESENT_R */ + PCH_GPIO_NATIVE, /* 32: PM_CKRUN_N */ + PCH_GPIO_OUT_LOW, /* 33: SATA0_PHYSLP */ + PCH_GPIO_INPUT, /* 34: ESATA_DET_N */ + PCH_GPIO_INPUT, /* 35: SATA_DIRECT_PRSNT_R_N */ + PCH_GPIO_INPUT, /* 36: NGFF_SSD_SATA2_PCIE1_DET_N */ + PCH_GPIO_INPUT, /* 37: NGFF_SSD_SATA3_PCIE0_DET_N */ + PCH_GPIO_OUT_LOW, /* 38: SATA1_PHYSLP_DIRECT */ + PCH_GPIO_ACPI_SMI, /* 39: SMC_EXTSMI_N_R */ + PCH_GPIO_NATIVE, /* 40: USB_OC_0_1_R_N */ + PCH_GPIO_NATIVE, /* 41: USB_OC_2_6_R_N */ + PCH_GPIO_INPUT, /* 42: TBT_CIO_PLUG_SMI_N_R */ + PCH_GPIO_OUT_HIGH, /* 43: USB32_P1_PWREN */ + PCH_GPIO_INPUT, /* 44: SENSOR_HUB_RST_N */ + PCH_GPIO_INPUT, /* 45: GYRO_INT2_MCP_R */ + PCH_GPIO_OUT_HIGH, /* 46: SNSR_HUB_PWREN */ + PCH_GPIO_IRQ_EDGE, /* 47: SPI_TPM_HDR_IRQ_N */ + PCH_GPIO_OUT_HIGH, /* 48: PCIE_TBT_RST_N */ + PCH_GPIO_INPUT, /* 49: COMBO_JD */ + PCH_GPIO_IRQ_EDGE, /* 50: TOUCH_PANEL_INTR_N */ + PCH_GPIO_OUT_HIGH, /* 51: PCH_WIFI_RF_KILL_N */ + PCH_GPIO_OUT_HIGH, /* 52: TOUCH_PNL_RST_N_R */ + PCH_GPIO_INPUT, /* 53: SNSR_HUB_I2C_WAKE / ALS_INT_MCP */ + PCH_GPIO_ACPI_SCI, /* 54: NGFF_SLTB_SSD_MC_WAKE_N */ + PCH_GPIO_IRQ_EDGE, /* 55: TOUCHPAD_INTR_N */ + PCH_GPIO_INPUT, /* 56: NGFF_SLTB_WWAN_SSD_DET1 */ + PCH_GPIO_OUT_HIGH, /* 57: NGFF_SLTB_WWAN_PWREN */ + PCH_GPIO_OUT_LOW, /* 58: SLATEMODE_HALLOUT_R */ + PCH_GPIO_OUT_HIGH, /* 59: USB2_CAM_PWREN */ + PCH_GPIO_OUT_LOW, /* 60: USB_CR_PWREN_N */ + PCH_GPIO_NATIVE, /* 61: PM_SUS_STAT_N */ + PCH_GPIO_NATIVE, /* 62: SUS_CK */ + PCH_GPIO_NATIVE, /* 63: SLP_S5_R_N */ + PCH_GPIO_NATIVE, /* 64: LPSS_SDIO_CLK_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 65: LPSS_SDIO_CMD_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 66: LPSS_SDIO_D0_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 67: LPSS_SDIO_D1_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 68: LPSS_SDIO_D2_CMNHDR_R */ + PCH_GPIO_NATIVE, /* 69: LPSS_SDIO_D3_CMNHDR_R1 */ + PCH_GPIO_NATIVE, /* 70: NGFF_SLTA_WIFI_PWREN_N_R */ + PCH_GPIO_OUT_HIGH, /* 71: MPHY_PWREN */ + PCH_GPIO_NATIVE, /* 72: PM_BATLOW_R_N */ + PCH_GPIO_NATIVE, /* 73: PCH_NOT_N */ + PCH_GPIO_NATIVE, /* 74: SML1_DATA */ + PCH_GPIO_NATIVE, /* 75: SML1_CK */ + PCH_GPIO_OUT_HIGH, /* 76: PCH_AUDIO_PWR_R */ + PCH_GPIO_OUT_LOW, /* 77: PC_SLTB_SSD_RST_N_R */ + PCH_GPIO_INPUT, /* 78: PM_EXTTS0_EC_N */ + PCH_GPIO_IRQ_EDGE, /* 79: SIO1007_IRQ_N */ + PCH_GPIO_INPUT, /* 80: PM_EXTTS1_R_N */ + PCH_GPIO_NATIVE, /* 81: PCH_HDA_SPKR */ + PCH_GPIO_NATIVE, /* 82: H_RCIN_N */ + PCH_GPIO_NATIVE, /* 83: LPSS_GSPI0_CS_R_N */ + PCH_GPIO_NATIVE, /* 84: LPSS_GSPI0_CLK_R */ + PCH_GPIO_NATIVE, /* 85: LPSS_GSPI0_MISO_R */ + PCH_GPIO_NATIVE, /* 86: LPSS_GSPI0_MOSI_BBS0_R */ + PCH_GPIO_NATIVE, /* 87: LPSS_GSPI1_CS_R_N */ + PCH_GPIO_NATIVE, /* 88: LPSS_GSPI1_CLK_R */ + PCH_GPIO_NATIVE, /* 89: LPSS_GSPI1_MISO_R */ + PCH_GPIO_OUT_LOW, /* 90: NGFF_SLTA_WIFI_RST_N */ + PCH_GPIO_NATIVE, /* 91: LPSS_UART0_RXD */ + PCH_GPIO_NATIVE, /* 92: LPSS_UART0_TXD */ + PCH_GPIO_NATIVE, /* 93: LPSS_UART0_RTS_N */ + PCH_GPIO_NATIVE, /* 94: LPSS_UART0_CTS_N */ + PCH_GPIO_END }; #endif diff --git a/src/mainboard/intel/wtm2/mainboard.c b/src/mainboard/intel/wtm2/mainboard.c index a6839fc..92d0307 100644 --- a/src/mainboard/intel/wtm2/mainboard.c +++ b/src/mainboard/intel/wtm2/mainboard.c @@ -31,7 +31,6 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> -#include <southbridge/intel/lynxpoint/pch.h> void mainboard_suspend_resume(void) { @@ -39,8 +38,6 @@ void mainboard_suspend_resume(void) outb(0xcb, 0xb2); } - - // mainboard_enable is executed as first thing after // enumerate_buses(). diff --git a/src/mainboard/intel/wtm2/mainboard_smi.c b/src/mainboard/intel/wtm2/mainboard_smi.c index bcc94d6..bec0b61 100644 --- a/src/mainboard/intel/wtm2/mainboard_smi.c +++ b/src/mainboard/intel/wtm2/mainboard_smi.c @@ -20,11 +20,8 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> +#include <broadwell/nvs.h> +#include <broadwell/smm.h> int mainboard_io_trap_handler(int smif) { @@ -46,26 +43,3 @@ int mainboard_io_trap_handler(int smif) //gnvs->smif = 0; return 1; } - -#define APMC_FINALIZE 0xcb - -static int mainboard_finalized = 0; - -int mainboard_smi_apmc(u8 apmc) -{ - switch (apmc) { - case APMC_FINALIZE: - if (mainboard_finalized) { - printk(BIOS_DEBUG, "SMI#: Already finalized\n"); - return 0; - } - - intel_pch_finalize_smm(); - intel_northbridge_haswell_finalize_smm(); - intel_cpu_haswell_finalize_smm(); - - mainboard_finalized = 1; - break; - } - return 0; -} diff --git a/src/mainboard/intel/wtm2/pei_data.c b/src/mainboard/intel/wtm2/pei_data.c new file mode 100644 index 0000000..a33dddf --- /dev/null +++ b/src/mainboard/intel/wtm2/pei_data.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <broadwell/gpio.h> +#include <broadwell/pei_data.h> +#include <broadwell/pei_wrapper.h> + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* One installed DIMM per channel */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + + pei_data->spd_addresses[0] = 0xa2; + pei_data->spd_addresses[2] = 0xa2; + + pei_data_usb2_port(pei_data, 0, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 1, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 2, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 3, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 4, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 5, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 6, 0x40, 1, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + pei_data_usb2_port(pei_data, 7, 0x40, 0, USB_OC_PIN_SKIP, + USB_PORT_FRONT_PANEL); + + pei_data_usb3_port(pei_data, 0, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 1, 1, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 2, 0, USB_OC_PIN_SKIP, 0); + pei_data_usb3_port(pei_data, 3, 0, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/intel/wtm2/romstage.c b/src/mainboard/intel/wtm2/romstage.c index b831244..41bef93 100644 --- a/src/mainboard/intel/wtm2/romstage.c +++ b/src/mainboard/intel/wtm2/romstage.c @@ -18,123 +18,28 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <stddef.h> #include <console/console.h> -#include "cpu/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/haswell.h" -#include "northbridge/intel/haswell/raminit.h" -#include "southbridge/intel/lynxpoint/pch.h" -#include "southbridge/intel/lynxpoint/lp_gpio.h" +#include <stdint.h> +#include <string.h> +#include <broadwell/gpio.h> +#include <broadwell/pei_data.h> +#include <broadwell/pei_wrapper.h> +#include <broadwell/romstage.h> #include "gpio.h" -const struct rcba_config_instruction rcba_config[] = { - - /* - * GFX INTA -> PIRQA (MSI) - * D28IP_P1IP WLAN INTA -> PIRQB - * D28IP_P4IP ETH0 INTB -> PIRQC - * D29IP_E1P EHCI1 INTA -> PIRQD - * D20IP_XHCI XHCI INTA -> PIRQA - * D31IP_SIP SATA INTA -> PIRQF (MSI) - * D31IP_SMIP SMBUS INTB -> PIRQG - * D31IP_TTIP THRT INTC -> PIRQH - * D27IP_ZIP HDA INTA -> PIRQG (MSI) - */ - - /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IR, (INTA << D20IP_XHCI)), - - /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQA, 0, 0, 0)), - - /* Disable unused devices (board specific) */ - RCBA_RMW_REG_32(FD, ~0, PCH_DISABLE_ALWAYS), +void mainboard_romstage_entry(struct romstage_params *rp) +{ + struct pei_data pei_data; - RCBA_END_CONFIG, -}; + post_code(0x32); -void mainboard_romstage_entry(unsigned long bist) -{ - struct pei_data pei_data = { - .pei_version = PEI_VERSION, - .mchbar = DEFAULT_MCHBAR, - .dmibar = DEFAULT_DMIBAR, - .epbar = DEFAULT_EPBAR, - .pciexbar = DEFAULT_PCIEXBAR, - .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, - .hpet_address = HPET_ADDR, - .rcba = DEFAULT_RCBA, - .pmbase = DEFAULT_PMBASE, - .gpiobase = DEFAULT_GPIOBASE, - .temp_mmio_base = 0xfed08000, - .system_type = 5, /* ULT */ - .tseg_size = CONFIG_SMM_TSEG_SIZE, - .spd_addresses = { 0xa2, 0x00, 0xa2, 0x00 }, - .ec_present = 1, - // 0 = leave channel enabled - // 1 = disable dimm 0 on channel - // 2 = disable dimm 1 on channel - // 3 = disable dimm 0+1 on channel - .dimm_channel0_disabled = 2, - .dimm_channel1_disabled = 2, - .max_ddr3_freq = 1600, - .usb2_ports = { - /* Length, Enable, OCn# */ - { 0x40, 1, USB_OC_PIN_SKIP, /* P0: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P1: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P2: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P3: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P4: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P5: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 1, USB_OC_PIN_SKIP, /* P6: */ - USB_PORT_FRONT_PANEL }, - { 0x40, 0, USB_OC_PIN_SKIP, /* P7: */ - USB_PORT_FRONT_PANEL }, - }, - .usb3_ports = { - /* Enable, OCn# */ - { 1, USB_OC_PIN_SKIP }, /* P1; */ - { 1, USB_OC_PIN_SKIP }, /* P2; */ - { 1, USB_OC_PIN_SKIP }, /* P3; */ - { 1, USB_OC_PIN_SKIP }, /* P4; */ - }, - }; + /* Initialize GPIOs */ + init_gpios(mainboard_gpio_config); - struct romstage_params romstage_params = { - .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], - .bist = bist, - .copy_spd = NULL, - }; + /* Fill out PEI DATA */ + memset(&pei_data, 0, sizeof(pei_data)); + mainboard_fill_pei_data(&pei_data); + rp->pei_data = &pei_data; - /* Call into the real romstage main with this board's attributes. */ - romstage_common(&romstage_params); + romstage_common(rp); }

1 0

New patch to review for coreboot: aebfb15 nyan_big: Update Hynix BCTs and add Kingston 2GB BCT.
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8045 -gerrit commit aebfb153156c71ac23c83ec961ab9a99aaeb8d2f Author: Tom Warren <twarren(a)nvidia.com> Date: Tue Jun 10 13:46:48 2014 -0700 nyan_big: Update Hynix BCTs and add Kingston 2GB BCT. Hynix 2GB/4GB configs have been fine-tuned. Kingston 2GB config is new, uses RAMCODE 0x6. BUG=none TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my Big 2GB system (PVT1/SKU1) and it booted OK. BRANCH=nyan_big Original-Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314 Original-Signed-off-by: Tom Warren <twarren(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203305 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> (cherry picked from commit e47d18d8cff50f46d0a14715b6750f7aa6d0da82) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I363db37d6a63d9f5c578e68a0149259657e1ebfd --- .../google/nyan_big/bct/sdram-hynix-2GB-792.inc | 60 ++-- .../google/nyan_big/bct/sdram-hynix-4GB-792.inc | 96 +++---- .../google/nyan_big/bct/sdram-kingston-2GB-792.inc | 311 +++++++++++++++++++++ src/mainboard/google/nyan_big/sdram_configs.c | 36 ++- 4 files changed, 405 insertions(+), 98 deletions(-) diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc index 3020002..67a0cd4 100644 --- a/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-2GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from sdram-0001-792-2GB.cfg; do not edit. */ +{ /* generated from Nike_0224_2GB__ODTCTT_792Mhz_V02.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -66,7 +66,7 @@ .EmcRdv = 0x00000018, .EmcRdvMask = 0x0000001a, .EmcQpop = 0x0000000f, - .EmcCtt = 0x00000000, + .EmcCtt = 0x00000007, .EmcCttDuration = 0x00000004, .EmcRefresh = 0x000017e2, .EmcBurstRefreshNum = 0x00000000, @@ -87,13 +87,13 @@ .EmcTClkStable = 0x00000008, .EmcTClkStop = 0x00000008, .EmcTRefBw = 0x00001822, - .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg5 = 0x104ab198, .EmcFbioCfg6 = 0x00000000, .EmcFbioSpare = 0x00000000, .EmcCfgRsv = 0xff00ff00, .EmcMrs = 0x80000d71, .EmcEmrs = 0x80100002, - .EmcEmrs2 = 0x80200018, + .EmcEmrs2 = 0x80200418, .EmcEmrs3 = 0x80300000, .EmcMrw1 = 0x00000000, .EmcMrw2 = 0x00000000, @@ -108,7 +108,7 @@ .EmcMrsWaitCnt = 0x00f8000c, .EmcMrsWaitCnt2 = 0x00f8000c, .EmcCfg = 0x73300000, - .EmcCfg2 = 0x0000089d, + .EmcCfg2 = 0x0080089d, .EmcCfgPipe = 0x00004080, .EmcDbg = 0x01000c00, .EmcCmdQ = 0x10004408, @@ -119,22 +119,22 @@ .EmcCfgDigDllPeriod = 0x00008000, .EmcDevSelect = 0x00000002, .EmcSelDpdCtrl = 0x00040000, - .EmcDllXformDqs0 = 0x00000008, - .EmcDllXformDqs1 = 0x00000008, - .EmcDllXformDqs2 = 0x00000008, - .EmcDllXformDqs3 = 0x00000008, - .EmcDllXformDqs4 = 0x00000008, - .EmcDllXformDqs5 = 0x00000008, - .EmcDllXformDqs6 = 0x00000008, - .EmcDllXformDqs7 = 0x00000008, - .EmcDllXformDqs8 = 0x00000008, - .EmcDllXformDqs9 = 0x00000008, - .EmcDllXformDqs10 = 0x00000008, - .EmcDllXformDqs11 = 0x00000008, - .EmcDllXformDqs12 = 0x00000008, - .EmcDllXformDqs13 = 0x00000008, - .EmcDllXformDqs14 = 0x00000008, - .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformDqs0 = 0x00000005, + .EmcDllXformDqs1 = 0x00000005, + .EmcDllXformDqs2 = 0x00000005, + .EmcDllXformDqs3 = 0x00000005, + .EmcDllXformDqs4 = 0x00000005, + .EmcDllXformDqs5 = 0x00000005, + .EmcDllXformDqs6 = 0x00000005, + .EmcDllXformDqs7 = 0x00000005, + .EmcDllXformDqs8 = 0x00000005, + .EmcDllXformDqs9 = 0x00000005, + .EmcDllXformDqs10 = 0x00000005, + .EmcDllXformDqs11 = 0x00000005, + .EmcDllXformDqs12 = 0x00000005, + .EmcDllXformDqs13 = 0x00000005, + .EmcDllXformDqs14 = 0x00000005, + .EmcDllXformDqs15 = 0x00000005, .EmcDllXformQUse0 = 0x00000000, .EmcDllXformQUse1 = 0x00000000, .EmcDllXformQUse2 = 0x00000000, @@ -173,17 +173,17 @@ .EmcDliTrimTxDqs13 = 0x00000007, .EmcDliTrimTxDqs14 = 0x00000009, .EmcDliTrimTxDqs15 = 0x00000008, - .EmcDllXformDq0 = 0x0000000e, - .EmcDllXformDq1 = 0x0000000e, - .EmcDllXformDq2 = 0x0000000e, - .EmcDllXformDq3 = 0x0000000e, - .EmcDllXformDq4 = 0x0000000e, - .EmcDllXformDq5 = 0x0000000e, - .EmcDllXformDq6 = 0x0000000e, - .EmcDllXformDq7 = 0x0000000e, + .EmcDllXformDq0 = 0x0000000a, + .EmcDllXformDq1 = 0x0000000a, + .EmcDllXformDq2 = 0x0000000a, + .EmcDllXformDq3 = 0x0000000a, + .EmcDllXformDq4 = 0x0000000a, + .EmcDllXformDq5 = 0x0000000a, + .EmcDllXformDq6 = 0x0000000a, + .EmcDllXformDq7 = 0x0000000a, .WarmBootWait = 0x00000002, .EmcCttTermCtrl = 0x00000802, - .EmcOdtWrite = 0x00000000, + .EmcOdtWrite = 0x80000005, .EmcOdtRead = 0x00000000, .EmcZcalInterval = 0x00020000, .EmcZcalWaitCnt = 0x00000042, diff --git a/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc index 5c8d09c..4b556fd 100644 --- a/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc +++ b/src/mainboard/google/nyan_big/bct/sdram-hynix-4GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */ +{ /* generated from Nike_PVT_ODT_CTT_4GB_792MHz_V16.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -32,19 +32,19 @@ .EmcPinProgramWait = 0x00000001, .EmcPinExtraWait = 0x00000000, .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x00000025, + .EmcRc = 0x00000024, .EmcRfc = 0x00000114, .EmcRfcSlr = 0x00000000, - .EmcRas = 0x0000001a, - .EmcRp = 0x00000007, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, .EmcR2r = 0x00000000, .EmcW2w = 0x00000000, .EmcR2w = 0x00000008, .EmcW2r = 0x0000000d, .EmcR2p = 0x00000004, .EmcW2p = 0x00000013, - .EmcRdRcd = 0x00000009, - .EmcWrRcd = 0x00000009, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, .EmcRrd = 0x00000003, .EmcRext = 0x00000002, .EmcWext = 0x00000000, @@ -66,7 +66,7 @@ .EmcRdv = 0x00000018, .EmcRdvMask = 0x0000001a, .EmcQpop = 0x0000000f, - .EmcCtt = 0x00000000, + .EmcCtt = 0x00000007, .EmcCttDuration = 0x00000004, .EmcRefresh = 0x000017e2, .EmcBurstRefreshNum = 0x00000000, @@ -87,13 +87,13 @@ .EmcTClkStable = 0x00000008, .EmcTClkStop = 0x00000008, .EmcTRefBw = 0x00001822, - .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg5 = 0x104ab198, .EmcFbioCfg6 = 0x00000000, .EmcFbioSpare = 0x00000000, .EmcCfgRsv = 0xff00ff00, .EmcMrs = 0x00000d71, .EmcEmrs = 0x00100002, - .EmcEmrs2 = 0x00200018, + .EmcEmrs2 = 0x00200418, .EmcEmrs3 = 0x00300000, .EmcMrw1 = 0x00000000, .EmcMrw2 = 0x00000000, @@ -105,10 +105,10 @@ .EmcExtraModeRegWriteEnable = 0x00000000, .EmcMrwResetCommand = 0x00000000, .EmcMrwResetNInitWait = 0x00000000, - .EmcMrsWaitCnt = 0x006f000c, - .EmcMrsWaitCnt2 = 0x006f000c, + .EmcMrsWaitCnt = 0x006f000e, + .EmcMrsWaitCnt2 = 0x006f000e, .EmcCfg = 0x73300000, - .EmcCfg2 = 0x0000089d, + .EmcCfg2 = 0x0080089d, .EmcCfgPipe = 0x00004080, .EmcDbg = 0x01000c00, .EmcCmdQ = 0x10004408, @@ -119,22 +119,22 @@ .EmcCfgDigDllPeriod = 0x00008000, .EmcDevSelect = 0x00000000, .EmcSelDpdCtrl = 0x00040000, - .EmcDllXformDqs0 = 0x00000008, - .EmcDllXformDqs1 = 0x00000008, - .EmcDllXformDqs2 = 0x00000008, - .EmcDllXformDqs3 = 0x00000008, - .EmcDllXformDqs4 = 0x00000008, - .EmcDllXformDqs5 = 0x00000008, - .EmcDllXformDqs6 = 0x00000008, - .EmcDllXformDqs7 = 0x00000008, - .EmcDllXformDqs8 = 0x00000008, - .EmcDllXformDqs9 = 0x00000008, - .EmcDllXformDqs10 = 0x00000008, - .EmcDllXformDqs11 = 0x00000008, - .EmcDllXformDqs12 = 0x00000008, - .EmcDllXformDqs13 = 0x00000008, - .EmcDllXformDqs14 = 0x00000008, - .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformDqs0 = 0x007fc007, + .EmcDllXformDqs1 = 0x007fc008, + .EmcDllXformDqs2 = 0x007f400c, + .EmcDllXformDqs3 = 0x007fc007, + .EmcDllXformDqs4 = 0x007f4006, + .EmcDllXformDqs5 = 0x007f8004, + .EmcDllXformDqs6 = 0x007f8005, + .EmcDllXformDqs7 = 0x007f8004, + .EmcDllXformDqs8 = 0x007fc007, + .EmcDllXformDqs9 = 0x007fc008, + .EmcDllXformDqs10 = 0x007f400c, + .EmcDllXformDqs11 = 0x007fc007, + .EmcDllXformDqs12 = 0x007f4006, + .EmcDllXformDqs13 = 0x007f8004, + .EmcDllXformDqs14 = 0x007f8005, + .EmcDllXformDqs15 = 0x007f8004, .EmcDllXformQUse0 = 0x00000000, .EmcDllXformQUse1 = 0x00000000, .EmcDllXformQUse2 = 0x00000000, @@ -157,21 +157,21 @@ .EmcDllXformQUse13 = 0x00000000, .EmcDllXformQUse14 = 0x00000000, .EmcDllXformQUse15 = 0x00000000, - .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs0 = 0x00000006, .EmcDliTrimTxDqs1 = 0x00000008, .EmcDliTrimTxDqs2 = 0x00000005, .EmcDliTrimTxDqs3 = 0x00000009, - .EmcDliTrimTxDqs4 = 0x00000009, + .EmcDliTrimTxDqs4 = 0x00000006, .EmcDliTrimTxDqs5 = 0x00000007, - .EmcDliTrimTxDqs6 = 0x00000009, - .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x00000006, + .EmcDliTrimTxDqs7 = 0x00000006, .EmcDliTrimTxDqs8 = 0x00000008, .EmcDliTrimTxDqs9 = 0x00000008, .EmcDliTrimTxDqs10 = 0x00000005, .EmcDliTrimTxDqs11 = 0x00000009, - .EmcDliTrimTxDqs12 = 0x00000009, + .EmcDliTrimTxDqs12 = 0x00000006, .EmcDliTrimTxDqs13 = 0x00000007, - .EmcDliTrimTxDqs14 = 0x00000009, + .EmcDliTrimTxDqs14 = 0x00000006, .EmcDliTrimTxDqs15 = 0x00000008, .EmcDllXformDq0 = 0x0000000e, .EmcDllXformDq1 = 0x0000000e, @@ -183,7 +183,7 @@ .EmcDllXformDq7 = 0x0000000e, .WarmBootWait = 0x00000002, .EmcCttTermCtrl = 0x00000802, - .EmcOdtWrite = 0x00000000, + .EmcOdtWrite = 0x80000005, .EmcOdtRead = 0x00000000, .EmcZcalInterval = 0x00020000, .EmcZcalWaitCnt = 0x00000042, @@ -227,8 +227,8 @@ .EmcXm2DqsPadCtrl = 0x770c1414, .EmcXm2DqsPadCtrl2 = 0x0120113d, .EmcXm2DqsPadCtrl3 = 0x61861820, - .EmcXm2DqsPadCtrl4 = 0x00514514, - .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl4 = 0x00492492, + .EmcXm2DqsPadCtrl5 = 0x00492492, .EmcXm2DqsPadCtrl6 = 0x61861800, .EmcXm2DqPadCtrl = 0x770c2990, .EmcXm2DqPadCtrl2 = 0x00000000, @@ -241,15 +241,15 @@ .EmcXm2VttGenPadCtrl3 = 0x016eeeee, .EmcAcpdControl = 0x00000000, .EmcSwizzleRank0ByteCfg = 0x00003120, - .EmcSwizzleRank0Byte0 = 0x25143067, - .EmcSwizzleRank0Byte1 = 0x45367102, - .EmcSwizzleRank0Byte2 = 0x47106253, - .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, .EmcSwizzleRank1ByteCfg = 0x00003120, - .EmcSwizzleRank1Byte0 = 0x71546032, - .EmcSwizzleRank1Byte1 = 0x35104276, - .EmcSwizzleRank1Byte2 = 0x27043615, - .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, .EmcDsrVttgenDrv = 0x0606003f, .EmcTxdsrvttgen = 0x00000000, .EmcBgbiasCtl0 = 0x00000000, @@ -264,7 +264,7 @@ .McEmemArbCfg = 0x0e00000b, .McEmemArbOutstandingReq = 0x80000040, .McEmemArbTimingRcd = 0x00000004, - .McEmemArbTimingRp = 0x00000004, + .McEmemArbTimingRp = 0x00000005, .McEmemArbTimingRc = 0x00000013, .McEmemArbTimingRas = 0x0000000c, .McEmemArbTimingFaw = 0x0000000f, @@ -276,7 +276,7 @@ .McEmemArbTimingR2W = 0x00000006, .McEmemArbTimingW2R = 0x00000008, .McEmemArbDaTurns = 0x08060202, - .McEmemArbDaCovers = 0x00150c13, + .McEmemArbDaCovers = 0x00170e13, .McEmemArbMisc0 = 0x746c2414, .McEmemArbMisc1 = 0x70000f02, .McEmemArbRing1Throttle = 0x001f0000, @@ -301,7 +301,7 @@ .EmcCaTrainingEnable = 0x00000000, .EmcCaTrainingTimingCntl1 = 0x1f7df7df, .EmcCaTrainingTimingCntl2 = 0x0000001f, - .SwizzleRankByteEncode = 0x0000006f, + .SwizzleRankByteEncode = 0x0000000b, .BootRomPatchControl = 0x00000000, .BootRomPatchData = 0x00000000, .McMtsCarveoutBom = 0xfff00000, diff --git a/src/mainboard/google/nyan_big/bct/sdram-kingston-2GB-792.inc b/src/mainboard/google/nyan_big/bct/sdram-kingston-2GB-792.inc new file mode 100644 index 0000000..5f1c117 --- /dev/null +++ b/src/mainboard/google/nyan_big/bct/sdram-kingston-2GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from Nike_2GB_Kin_792Mhz_ODTCTT_V06_0507.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000000, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cc, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000007, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c6, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d6, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab198, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x80000d71, + .EmcEmrs = 0x80100002, + .EmcEmrs2 = 0x80200418, + .EmcEmrs3 = 0x80300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00f8000c, + .EmcMrsWaitCnt2 = 0x00f8000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0080089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000002, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000009, + .EmcDllXformDqs1 = 0x00000009, + .EmcDllXformDqs2 = 0x00000009, + .EmcDllXformDqs3 = 0x00000007, + .EmcDllXformDqs4 = 0x00000006, + .EmcDllXformDqs5 = 0x00000006, + .EmcDllXformDqs6 = 0x007fc009, + .EmcDllXformDqs7 = 0x00000006, + .EmcDllXformDqs8 = 0x00000009, + .EmcDllXformDqs9 = 0x00000009, + .EmcDllXformDqs10 = 0x00000009, + .EmcDllXformDqs11 = 0x00000007, + .EmcDllXformDqs12 = 0x00000006, + .EmcDllXformDqs13 = 0x00000007, + .EmcDllXformDqs14 = 0x00000009, + .EmcDllXformDqs15 = 0x00000007, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x00034002, + .EmcDllXformAddr1 = 0x00034002, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x00034002, + .EmcDllXformAddr4 = 0x00034002, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000009, + .EmcDliTrimTxDqs4 = 0x00000009, + .EmcDliTrimTxDqs5 = 0x00000007, + .EmcDliTrimTxDqs6 = 0x00000009, + .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000009, + .EmcDliTrimTxDqs12 = 0x00000009, + .EmcDliTrimTxDqs13 = 0x00000007, + .EmcDliTrimTxDqs14 = 0x00000009, + .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x80000005, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x80000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x00000000, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x80000d71, + .EmcWarmBootMrsExtra = 0x80100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fff2f97, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x004d34d3, + .EmcXm2DqsPadCtrl5 = 0x004d34d3, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x25143067, + .EmcSwizzleRank0Byte1 = 0x45367102, + .EmcSwizzleRank0Byte2 = 0x47106253, + .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x71546032, + .EmcSwizzleRank1Byte1 = 0x35104276, + .EmcSwizzleRank1Byte2 = 0x27043615, + .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000000, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00000800, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x734c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000006f, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_big/sdram_configs.c b/src/mainboard/google/nyan_big/sdram_configs.c index 2aaace4..748b6dc 100644 --- a/src/mainboard/google/nyan_big/sdram_configs.c +++ b/src/mainboard/google/nyan_big/sdram_configs.c @@ -21,27 +21,23 @@ #include <soc/nvidia/tegra124/sdram.h> #include "sdram_configs.h" -/* - * Note for board bring up, we've temporarily filled SDRAM table with - * hynix-2GB-204 configuration (except the hynix-4GB-204 entry for 0100). - */ static struct sdram_params sdram_configs[] = { -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0000 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0001 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0010 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0011 */ -#include "bct/sdram-hynix-4GB-204.inc" /* ram_code = 0100 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0101 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0110 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 0111 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1000 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1001 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1010 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1100 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1101 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1110 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1111 */ +#include "bct/sdram-unused.inc" /* ram_code = 0000 */ +#include "bct/sdram-hynix-2GB-792.inc" /* ram_code = 0001 */ +#include "bct/sdram-unused.inc" /* ram_code = 0010 */ +#include "bct/sdram-unused.inc" /* ram_code = 0011 */ +#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 0100 */ +#include "bct/sdram-unused.inc" /* ram_code = 0101 */ +#include "bct/sdram-kingston-2GB-792.inc" /* ram_code = 0110 */ +#include "bct/sdram-unused.inc" /* ram_code = 0111 */ +#include "bct/sdram-unused.inc" /* ram_code = 1000 */ +#include "bct/sdram-unused.inc" /* ram_code = 1001 */ +#include "bct/sdram-unused.inc" /* ram_code = 1010 */ +#include "bct/sdram-unused.inc" /* ram_code = 1011 */ +#include "bct/sdram-unused.inc" /* ram_code = 1100 */ +#include "bct/sdram-unused.inc" /* ram_code = 1101 */ +#include "bct/sdram-unused.inc" /* ram_code = 1110 */ +#include "bct/sdram-unused.inc" /* ram_code = 1111 */ }; const struct sdram_params *get_sdram_config()

1 0

New patch to review for coreboot: 329c621 tegra124: configure DP with correct pixel clock
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8044 -gerrit commit 329c621ce7e2f3afa366ba3f2a1f5c372042e670 Author: Vince Hsu <vinceh(a)nvidia.com> Date: Wed Jun 11 17:14:05 2014 +0800 tegra124: configure DP with correct pixel clock For some panels, the plld can't provide the pixel clock that the panels wants, so we give it a good enough one. And we should calculate the dp/dc settings by the real pixel clock. BRANCH=nyan BUG=chrome-os-partner:29489 TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big). No screen flicker is observed. No sor dp fifo underflow found. Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779 Original-Signed-off-by: Vince Hsu <vinceh(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/203358 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac --- src/soc/nvidia/tegra124/clock.c | 23 +++++++++++++++-------- src/soc/nvidia/tegra124/display.c | 9 +++++++-- src/soc/nvidia/tegra124/include/soc/clock.h | 2 +- 3 files changed, 23 insertions(+), 11 deletions(-) diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index c5b06f4..af2f96a 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -295,8 +295,14 @@ static void graphics_pll(void) */ } -/* Init PLLD clock source. */ -int +/* + * Init PLLD clock source. + * + * @frequency: the requested plld frequency + * + * Return the plld frequency if success, otherwise return 0. + */ +u32 clock_display(u32 frequency) { /** @@ -314,7 +320,7 @@ clock_display(u32 frequency) */ struct pllpad_dividers plld = { 0 }; u32 ref = clock_get_pll_input_khz() * 1000, m, n, p = 0; - u32 cf, vco; + u32 cf, vco, rounded_rate = frequency; u32 diff, best_diff; const u32 max_m = 1 << 5, max_n = 1 << 10, max_p = 1 << 3, mhz = 1000 * 1000, min_vco = 500 * mhz, max_vco = 1000 * mhz, @@ -326,7 +332,7 @@ clock_display(u32 frequency) if (vco < min_vco || vco > max_vco) { printk(BIOS_ERR, "%s: Cannot find out a supported VCO" " for Frequency (%u).\n", __func__, frequency); - return -1; + return 0; } plld.p = p; @@ -367,18 +373,19 @@ clock_display(u32 frequency) plld.cpcon = 12; if (best_diff) { - printk(BIOS_ERR, "%s: Failed to match output frequency %u, " + printk(BIOS_WARNING, "%s: Failed to match output frequency %u, " "best difference is %u.\n", __func__, frequency, best_diff); + rounded_rate = (ref / plld.m * plld.n) >> plld.p; } printk(BIOS_DEBUG, "%s: PLLD=%u ref=%u, m/n/p/cpcon=%u/%u/%u/%u\n", - __func__, (ref / plld.m * plld.n) >> plld.p, ref, plld.m, plld.n, - plld.p, plld.cpcon); + __func__, rounded_rate, ref, plld.m, plld.n, plld.p, plld.cpcon); init_pll(&clk_rst->plld_base, &clk_rst->plld_misc, plld, (PLLUD_MISC_LOCK_ENABLE | PLLD_MISC_CLK_ENABLE)); - return 0; + + return rounded_rate; } /* Initialize the UART and put it on CLK_M so we can use it during clock_init(). diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index 9ad76f0..6f6790d 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -221,6 +221,7 @@ void display_startup(device_t dev) struct display_controller *disp_ctrl = (void *)config->display_controller; struct pwm_controller *pwm = (void *)TEGRA_PWM_BASE; struct tegra_dc *dc = &dc_data; + u32 plld_rate; /* init dc */ dc->base = (void *)TEGRA_ARM_DISPLAYA; @@ -282,10 +283,14 @@ void display_startup(device_t dev) * and PIXEL_CLK_DIVIDER are zero (divide by 1). See the * update_display_mode() for detail. */ - if (clock_display(config->pixel_clock * 2)) { + plld_rate = clock_display(config->pixel_clock * 2); + if (plld_rate == 0) { printk(BIOS_ERR, "dc: clock init failed\n"); return; - }; + } else if (plld_rate != config->pixel_clock * 2) { + printk(BIOS_WARNING, "dc: plld rounded to %u\n", plld_rate); + config->pixel_clock = plld_rate / 2; + } /* Init dc */ if (tegra_dc_init(disp_ctrl)) { diff --git a/src/soc/nvidia/tegra124/include/soc/clock.h b/src/soc/nvidia/tegra124/include/soc/clock.h index 73274a5..ffe9a4e 100644 --- a/src/soc/nvidia/tegra124/include/soc/clock.h +++ b/src/soc/nvidia/tegra124/include/soc/clock.h @@ -279,7 +279,7 @@ enum clock_source { /* Careful: Not true for all sources, always check TRM! */ int clock_get_osc_khz(void); int clock_get_pll_input_khz(void); -int clock_display(u32 frequency); +u32 clock_display(u32 frequency); void clock_early_uart(void); void clock_external_output(int clk_id); void clock_sdram(u32 m, u32 n, u32 p, u32 setup, u32 ph45, u32 ph90,

1 0

New patch to review for coreboot: b4f1ed9 arm: lpae: Set XN and PXN bits for noncacheable regions
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8043 -gerrit commit b4f1ed92af6d17805d45296aec704f396f5eeaf5 Author: Jimmy Zhang <jimmzhang(a)nvidia.com> Date: Fri Jun 6 17:00:10 2014 -0700 arm: lpae: Set XN and PXN bits for noncacheable regions Add XN/PXN bits to prevent cpu from fetching speculative instructions on noncacheable region. BUG=chrome-os-partner:28568 BRANCH=nyan TEST=Build and run reboot tests on nyan_big Signed-off-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b Original-Reviewed-on: https://chromium-review.googlesource.com/203447 Original-Tested-by: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Commit-Queue: Jimmy Zhang <jimmzhang(a)nvidia.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> (cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe --- src/arch/arm/armv7/mmu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 1b5957c..bd12946 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -42,7 +42,7 @@ /* See B3.6.2 of ARMv7 Architecture Reference Manual */ /* TODO: Utilize the contiguous hint flag */ #define ATTR_BASE (\ - 0ULL << 54 | /* PN. 0:Not restricted */ \ + 0ULL << 54 | /* XN. 0:Not restricted */ \ 0ULL << 53 | /* PXN. 0:Not restricted */ \ 1 << 10 | /* AF. 1:Accessed. This is to prevent access \ * fault when accessed for the first time */ \ @@ -51,7 +51,8 @@ 0 << 1 | /* block/table. 0:block entry */ \ 1 << 0 /* validity. 1:valid */ \ ) -#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2)) +#define ATTR_NC (ATTR_BASE | (MAIR_INDX_NC << 2) | \ + (1ULL << 53) | (1ULL << 54)) #define ATTR_WT (ATTR_BASE | (MAIR_INDX_WT << 2)) #define ATTR_WB (ATTR_BASE | (MAIR_INDX_WB << 2))

1 0

New patch to review for coreboot: facd5fc nyan: Ignore the recovery GPIO.
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8042 -gerrit commit facd5fc99b0fea5594ce29417b58d138248b4429 Author: Todd Broch <tbroch(a)chromium.org> Date: Fri Jun 6 17:03:49 2014 -0700 nyan: Ignore the recovery GPIO. CrOS devices with Chromeos EC need only use hostevent to communicate recovery assertion to the BIOS. This CL removes wired GPIO from determining recovery as it appears under certain conditions (cold reset) the internal PU on the AP isn't strong enough and therefore the value is sometimes seen as asserted. BRANCH=none BUG=chrome-os-partner:29333 TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot. Original-Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2 Original-Signed-off-by: Todd Broch <tbroch(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/202996 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit d9927bcd67b0fb069fde231314e654d727092282) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6e086cbabc884f18deb2791a0f897e332b31032f --- src/mainboard/google/nyan/chromeos.c | 4 ---- src/mainboard/google/nyan_big/chromeos.c | 4 ---- src/mainboard/google/nyan_blaze/chromeos.c | 4 ---- 3 files changed, 12 deletions(-) diff --git a/src/mainboard/google/nyan/chromeos.c b/src/mainboard/google/nyan/chromeos.c index 6377fb2..c4d98b7 100644 --- a/src/mainboard/google/nyan/chromeos.c +++ b/src/mainboard/google/nyan/chromeos.c @@ -84,10 +84,6 @@ int get_recovery_mode_switch(void) { uint32_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO - return 1; - ec_events = google_chromeec_get_events_b(); return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); diff --git a/src/mainboard/google/nyan_big/chromeos.c b/src/mainboard/google/nyan_big/chromeos.c index 298fd6a..054abf6 100644 --- a/src/mainboard/google/nyan_big/chromeos.c +++ b/src/mainboard/google/nyan_big/chromeos.c @@ -84,10 +84,6 @@ int get_recovery_mode_switch(void) { uint32_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO - return 1; - ec_events = google_chromeec_get_events_b(); return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY)); diff --git a/src/mainboard/google/nyan_blaze/chromeos.c b/src/mainboard/google/nyan_blaze/chromeos.c index 16f0c98..da017ea 100644 --- a/src/mainboard/google/nyan_blaze/chromeos.c +++ b/src/mainboard/google/nyan_blaze/chromeos.c @@ -88,10 +88,6 @@ int get_recovery_mode_switch(void) { uint32_t ec_events; - /* The GPIO is active low. */ - if (!gpio_get_in_value(GPIO(Q7))) // RECMODE_GPIO - return 1; - ec_events = google_chromeec_get_events_b(); return !!(ec_events & EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));

1 0

Patch set updated for coreboot: f968200 blaze: change ramcode 1000/1001/1010 to use 792MHz bct
by Marc Jones 03 Jan '15

03 Jan '15

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8008 -gerrit commit f968200aecefb96854bd8adeef1683a3dea6a2f9 Author: Neil Chen <neilc(a)nvidia.com> Date: Thu May 29 18:20:17 2014 +0800 blaze: change ramcode 1000/1001/1010 to use 792MHz bct This change updates the cfg file for Hynix/Micron/Samsung 4GB, 792MHz DRAM based on the data generated by t124_emc_reg_tool. BUG=none BRANCH=blaze TEST=emerged coreboot, booted successfully into kernel. Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6 Original-Signed-off-by: Neil Chen <neilc(a)nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/202059 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Original-Reviewed-by: Tom Warren <twarren(a)nvidia.com> (cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c --- .../google/nyan_blaze/bct/sdram-hynix-4GB-792.inc | 92 +++--- .../google/nyan_blaze/bct/sdram-micron-4GB-792.inc | 311 +++++++++++++++++++++ .../nyan_blaze/bct/sdram-samsung-4GB-792.inc | 311 +++++++++++++++++++++ src/mainboard/google/nyan_blaze/sdram_configs.c | 6 +- 4 files changed, 671 insertions(+), 49 deletions(-) diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc index 5c8d09c..6afd3b7 100644 --- a/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc +++ b/src/mainboard/google/nyan_blaze/bct/sdram-hynix-4GB-792.inc @@ -1,4 +1,4 @@ -{ /* generated from sdram-0100-792-4GB.cfg; do not edit. */ +{ /* generated from Hynix_4GB_H5TC8G63AFR_PBA_792MHz_release.cfg; do not edit. */ .MemoryType = NvBootMemoryType_Ddr3, .PllMInputDivider = 0x00000001, .PllMFeedbackDivider = 0x00000042, @@ -24,7 +24,7 @@ .EmcBctSpare11 = 0x00000000, .EmcClockSource = 0x80000000, .EmcAutoCalInterval = 0x001fffff, - .EmcAutoCalConfig = 0xa1430000, + .EmcAutoCalConfig = 0xa1430404, .EmcAutoCalConfig2 = 0x00000000, .EmcAutoCalConfig3 = 0x00000000, .EmcAutoCalWait = 0x00000190, @@ -32,19 +32,19 @@ .EmcPinProgramWait = 0x00000001, .EmcPinExtraWait = 0x00000000, .EmcTimingControlWait = 0x00000000, - .EmcRc = 0x00000025, + .EmcRc = 0x00000024, .EmcRfc = 0x00000114, .EmcRfcSlr = 0x00000000, - .EmcRas = 0x0000001a, - .EmcRp = 0x00000007, + .EmcRas = 0x00000019, + .EmcRp = 0x0000000a, .EmcR2r = 0x00000000, .EmcW2w = 0x00000000, .EmcR2w = 0x00000008, .EmcW2r = 0x0000000d, .EmcR2p = 0x00000004, .EmcW2p = 0x00000013, - .EmcRdRcd = 0x00000009, - .EmcWrRcd = 0x00000009, + .EmcRdRcd = 0x0000000a, + .EmcWrRcd = 0x0000000a, .EmcRrd = 0x00000003, .EmcRext = 0x00000002, .EmcWext = 0x00000000, @@ -105,8 +105,8 @@ .EmcExtraModeRegWriteEnable = 0x00000000, .EmcMrwResetCommand = 0x00000000, .EmcMrwResetNInitWait = 0x00000000, - .EmcMrsWaitCnt = 0x006f000c, - .EmcMrsWaitCnt2 = 0x006f000c, + .EmcMrsWaitCnt = 0x006f000e, + .EmcMrsWaitCnt2 = 0x006f000e, .EmcCfg = 0x73300000, .EmcCfg2 = 0x0000089d, .EmcCfgPipe = 0x00004080, @@ -123,18 +123,18 @@ .EmcDllXformDqs1 = 0x00000008, .EmcDllXformDqs2 = 0x00000008, .EmcDllXformDqs3 = 0x00000008, - .EmcDllXformDqs4 = 0x00000008, - .EmcDllXformDqs5 = 0x00000008, - .EmcDllXformDqs6 = 0x00000008, - .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs4 = 0x00000006, + .EmcDllXformDqs5 = 0x00000006, + .EmcDllXformDqs6 = 0x00000006, + .EmcDllXformDqs7 = 0x007F8008, .EmcDllXformDqs8 = 0x00000008, .EmcDllXformDqs9 = 0x00000008, .EmcDllXformDqs10 = 0x00000008, .EmcDllXformDqs11 = 0x00000008, - .EmcDllXformDqs12 = 0x00000008, - .EmcDllXformDqs13 = 0x00000008, - .EmcDllXformDqs14 = 0x00000008, - .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformDqs12 = 0x00000006, + .EmcDllXformDqs13 = 0x00000006, + .EmcDllXformDqs14 = 0x00000006, + .EmcDllXformDqs15 = 0x007F8008, .EmcDllXformQUse0 = 0x00000000, .EmcDllXformQUse1 = 0x00000000, .EmcDllXformQUse2 = 0x00000000, @@ -143,11 +143,11 @@ .EmcDllXformQUse5 = 0x00000000, .EmcDllXformQUse6 = 0x00000000, .EmcDllXformQUse7 = 0x00000000, - .EmcDllXformAddr0 = 0x00034000, - .EmcDllXformAddr1 = 0x00034000, + .EmcDllXformAddr0 = 0x0002c000, + .EmcDllXformAddr1 = 0x0002c000, .EmcDllXformAddr2 = 0x00000000, - .EmcDllXformAddr3 = 0x00034000, - .EmcDllXformAddr4 = 0x00034000, + .EmcDllXformAddr3 = 0x0002c000, + .EmcDllXformAddr4 = 0x0002c000, .EmcDllXformAddr5 = 0x00000000, .EmcDllXformQUse8 = 0x00000000, .EmcDllXformQUse9 = 0x00000000, @@ -160,19 +160,19 @@ .EmcDliTrimTxDqs0 = 0x00000008, .EmcDliTrimTxDqs1 = 0x00000008, .EmcDliTrimTxDqs2 = 0x00000005, - .EmcDliTrimTxDqs3 = 0x00000009, - .EmcDliTrimTxDqs4 = 0x00000009, - .EmcDliTrimTxDqs5 = 0x00000007, - .EmcDliTrimTxDqs6 = 0x00000009, - .EmcDliTrimTxDqs7 = 0x00000008, + .EmcDliTrimTxDqs3 = 0x00000008, + .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs5 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x0000000a, + .EmcDliTrimTxDqs7 = 0x0000000a, .EmcDliTrimTxDqs8 = 0x00000008, .EmcDliTrimTxDqs9 = 0x00000008, .EmcDliTrimTxDqs10 = 0x00000005, - .EmcDliTrimTxDqs11 = 0x00000009, - .EmcDliTrimTxDqs12 = 0x00000009, - .EmcDliTrimTxDqs13 = 0x00000007, - .EmcDliTrimTxDqs14 = 0x00000009, - .EmcDliTrimTxDqs15 = 0x00000008, + .EmcDliTrimTxDqs11 = 0x00000008, + .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs13 = 0x00000008, + .EmcDliTrimTxDqs14 = 0x0000000a, + .EmcDliTrimTxDqs15 = 0x0000000a, .EmcDllXformDq0 = 0x0000000e, .EmcDllXformDq1 = 0x0000000e, .EmcDllXformDq2 = 0x0000000e, @@ -226,30 +226,30 @@ .EmcXm2CmdPadCtrl5 = 0x00111111, .EmcXm2DqsPadCtrl = 0x770c1414, .EmcXm2DqsPadCtrl2 = 0x0120113d, - .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl3 = 0x69A69A20, .EmcXm2DqsPadCtrl4 = 0x00514514, - .EmcXm2DqsPadCtrl5 = 0x00514514, - .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqsPadCtrl5 = 0x00514510, + .EmcXm2DqsPadCtrl6 = 0x69A69A00, .EmcXm2DqPadCtrl = 0x770c2990, .EmcXm2DqPadCtrl2 = 0x00000000, .EmcXm2DqPadCtrl3 = 0x00000000, .EmcXm2ClkPadCtrl = 0x77ffc085, - .EmcXm2ClkPadCtrl2 = 0x00000101, + .EmcXm2ClkPadCtrl2 = 0x00000202, .EmcXm2CompPadCtrl = 0x81f1f108, .EmcXm2VttGenPadCtrl = 0x07070004, .EmcXm2VttGenPadCtrl2 = 0x00000000, .EmcXm2VttGenPadCtrl3 = 0x016eeeee, .EmcAcpdControl = 0x00000000, .EmcSwizzleRank0ByteCfg = 0x00003120, - .EmcSwizzleRank0Byte0 = 0x25143067, - .EmcSwizzleRank0Byte1 = 0x45367102, - .EmcSwizzleRank0Byte2 = 0x47106253, - .EmcSwizzleRank0Byte3 = 0x04362175, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, .EmcSwizzleRank1ByteCfg = 0x00003120, - .EmcSwizzleRank1Byte0 = 0x71546032, - .EmcSwizzleRank1Byte1 = 0x35104276, - .EmcSwizzleRank1Byte2 = 0x27043615, - .EmcSwizzleRank1Byte3 = 0x72306145, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, .EmcDsrVttgenDrv = 0x0606003f, .EmcTxdsrvttgen = 0x00000000, .EmcBgbiasCtl0 = 0x00000000, @@ -264,7 +264,7 @@ .McEmemArbCfg = 0x0e00000b, .McEmemArbOutstandingReq = 0x80000040, .McEmemArbTimingRcd = 0x00000004, - .McEmemArbTimingRp = 0x00000004, + .McEmemArbTimingRp = 0x00000005, .McEmemArbTimingRc = 0x00000013, .McEmemArbTimingRas = 0x0000000c, .McEmemArbTimingFaw = 0x0000000f, @@ -276,7 +276,7 @@ .McEmemArbTimingR2W = 0x00000006, .McEmemArbTimingW2R = 0x00000008, .McEmemArbDaTurns = 0x08060202, - .McEmemArbDaCovers = 0x00150c13, + .McEmemArbDaCovers = 0x00170e13, .McEmemArbMisc0 = 0x746c2414, .McEmemArbMisc1 = 0x70000f02, .McEmemArbRing1Throttle = 0x001f0000, @@ -301,7 +301,7 @@ .EmcCaTrainingEnable = 0x00000000, .EmcCaTrainingTimingCntl1 = 0x1f7df7df, .EmcCaTrainingTimingCntl2 = 0x0000001f, - .SwizzleRankByteEncode = 0x0000006f, + .SwizzleRankByteEncode = 0x0000000b, .BootRomPatchControl = 0x00000000, .BootRomPatchData = 0x00000000, .McMtsCarveoutBom = 0xfff00000, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc new file mode 100644 index 0000000..5a7b6be --- /dev/null +++ b/src/mainboard/google/nyan_blaze/bct/sdram-micron-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from Micron_4GB_MT41K512M16TNA-125_792MHz.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xA1430404, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x000000cc, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x000000c6, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x000000d6, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x00b6000c, + .EmcMrsWaitCnt2 = 0x00b6000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000008, + .EmcDllXformDqs1 = 0x00000008, + .EmcDllXformDqs2 = 0x00000008, + .EmcDllXformDqs3 = 0x00000008, + .EmcDllXformDqs4 = 0x00000008, + .EmcDllXformDqs5 = 0x00000008, + .EmcDllXformDqs6 = 0x00000008, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000008, + .EmcDllXformDqs9 = 0x00000008, + .EmcDllXformDqs10 = 0x00000008, + .EmcDllXformDqs11 = 0x00000008, + .EmcDllXformDqs12 = 0x00000008, + .EmcDllXformDqs13 = 0x00000008, + .EmcDllXformDqs14 = 0x00000008, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0002c000, + .EmcDllXformAddr1 = 0x0002c000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0002c000, + .EmcDllXformAddr4 = 0x0002c000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000008, + .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs5 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x0000000a, + .EmcDliTrimTxDqs7 = 0x0000000a, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000008, + .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs13 = 0x00000008, + .EmcDliTrimTxDqs14 = 0x0000000a, + .EmcDliTrimTxDqs15 = 0x0000000a, + .EmcDllXformDq0 = 0x0000000e, + .EmcDllXformDq1 = 0x0000000e, + .EmcDllXformDq2 = 0x0000000e, + .EmcDllXformDq3 = 0x0000000e, + .EmcDllXformDq4 = 0x0000000e, + .EmcDllXformDq5 = 0x0000000e, + .EmcDllXformDq6 = 0x0000000e, + .EmcDllXformDq7 = 0x0000000e, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61861820, + .EmcXm2DqsPadCtrl4 = 0x00514514, + .EmcXm2DqsPadCtrl5 = 0x00514514, + .EmcXm2DqsPadCtrl6 = 0x61861800, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000202, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x734c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000000b, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc new file mode 100644 index 0000000..f8c3a5f --- /dev/null +++ b/src/mainboard/google/nyan_blaze/bct/sdram-samsung-4GB-792.inc @@ -0,0 +1,311 @@ +{ /* generated from Samsung_4GB_K4B8G1646Q_792MHz_release.cfg; do not edit. */ + .MemoryType = NvBootMemoryType_Ddr3, + .PllMInputDivider = 0x00000001, + .PllMFeedbackDivider = 0x00000042, + .PllMStableTime = 0x0000012c, + .PllMSetupControl = 0x00000000, + .PllMSelectDiv2 = 0x00000000, + .PllMPDLshiftPh45 = 0x00000001, + .PllMPDLshiftPh90 = 0x00000001, + .PllMPDLshiftPh135 = 0x00000001, + .PllMKCP = 0x00000000, + .PllMKVCO = 0x00000000, + .EmcBctSpare0 = 0x00000000, + .EmcBctSpare1 = 0x00000000, + .EmcBctSpare2 = 0x00000000, + .EmcBctSpare3 = 0x00000000, + .EmcBctSpare4 = 0x00000000, + .EmcBctSpare5 = 0x00000000, + .EmcBctSpare6 = 0x00000000, + .EmcBctSpare7 = 0x00000000, + .EmcBctSpare8 = 0x00000000, + .EmcBctSpare9 = 0x00000000, + .EmcBctSpare10 = 0x00000000, + .EmcBctSpare11 = 0x00000000, + .EmcClockSource = 0x80000000, + .EmcAutoCalInterval = 0x001fffff, + .EmcAutoCalConfig = 0xa1430707, + .EmcAutoCalConfig2 = 0x00000000, + .EmcAutoCalConfig3 = 0x00000000, + .EmcAutoCalWait = 0x00000190, + .EmcAdrCfg = 0x00000001, + .EmcPinProgramWait = 0x00000001, + .EmcPinExtraWait = 0x00000000, + .EmcTimingControlWait = 0x00000000, + .EmcRc = 0x00000025, + .EmcRfc = 0x00000114, + .EmcRfcSlr = 0x00000000, + .EmcRas = 0x0000001a, + .EmcRp = 0x00000009, + .EmcR2r = 0x00000000, + .EmcW2w = 0x00000000, + .EmcR2w = 0x00000008, + .EmcW2r = 0x0000000d, + .EmcR2p = 0x00000004, + .EmcW2p = 0x00000013, + .EmcRdRcd = 0x00000009, + .EmcWrRcd = 0x00000009, + .EmcRrd = 0x00000004, + .EmcRext = 0x00000002, + .EmcWext = 0x00000000, + .EmcWdv = 0x00000006, + .EmcWdvMask = 0x00000006, + .EmcQUse = 0x0000000b, + .EmcQuseWidth = 0x00000002, + .EmcIbdly = 0x00000000, + .EmcEInput = 0x00000002, + .EmcEInputDuration = 0x0000000d, + .EmcPutermExtra = 0x00080000, + .EmcPutermWidth = 0x00000004, + .EmcPutermAdj = 0x00000000, + .EmcCdbCntl1 = 0x00000000, + .EmcCdbCntl2 = 0x00000000, + .EmcCdbCntl3 = 0x00000000, + .EmcQRst = 0x00000001, + .EmcQSafe = 0x00000014, + .EmcRdv = 0x00000018, + .EmcRdvMask = 0x0000001a, + .EmcQpop = 0x0000000f, + .EmcCtt = 0x00000000, + .EmcCttDuration = 0x00000004, + .EmcRefresh = 0x000017e2, + .EmcBurstRefreshNum = 0x00000000, + .EmcPreRefreshReqCnt = 0x000005f8, + .EmcPdEx2Wr = 0x00000003, + .EmcPdEx2Rd = 0x00000011, + .EmcPChg2Pden = 0x00000001, + .EmcAct2Pden = 0x00000000, + .EmcAr2Pden = 0x0000010d, + .EmcRw2Pden = 0x00000018, + .EmcTxsr = 0x0000011e, + .EmcTxsrDll = 0x00000200, + .EmcTcke = 0x00000005, + .EmcTckesr = 0x00000006, + .EmcTpd = 0x00000005, + .EmcTfaw = 0x0000001d, + .EmcTrpab = 0x00000000, + .EmcTClkStable = 0x00000008, + .EmcTClkStop = 0x00000008, + .EmcTRefBw = 0x00001822, + .EmcFbioCfg5 = 0x104ab098, + .EmcFbioCfg6 = 0x00000000, + .EmcFbioSpare = 0x00000000, + .EmcCfgRsv = 0xff00ff00, + .EmcMrs = 0x00000d71, + .EmcEmrs = 0x00100002, + .EmcEmrs2 = 0x00200018, + .EmcEmrs3 = 0x00300000, + .EmcMrw1 = 0x00000000, + .EmcMrw2 = 0x00000000, + .EmcMrw3 = 0x00000000, + .EmcMrw4 = 0x00000000, + .EmcMrwExtra = 0x00000000, + .EmcWarmBootMrwExtra = 0x00000000, + .EmcWarmBootExtraModeRegWriteEnable = 0x00000000, + .EmcExtraModeRegWriteEnable = 0x00000000, + .EmcMrwResetCommand = 0x00000000, + .EmcMrwResetNInitWait = 0x00000000, + .EmcMrsWaitCnt = 0x006f000c, + .EmcMrsWaitCnt2 = 0x006f000c, + .EmcCfg = 0x73300000, + .EmcCfg2 = 0x0000089d, + .EmcCfgPipe = 0x00004080, + .EmcDbg = 0x01000c00, + .EmcCmdQ = 0x10004408, + .EmcMc2EmcQ = 0x06000404, + .EmcDynSelfRefControl = 0x80003012, + .AhbArbitrationXbarCtrlMemInitDone = 0x00000001, + .EmcCfgDigDll = 0xe00700b1, + .EmcCfgDigDllPeriod = 0x00008000, + .EmcDevSelect = 0x00000000, + .EmcSelDpdCtrl = 0x00040000, + .EmcDllXformDqs0 = 0x00000009, + .EmcDllXformDqs1 = 0x0000000a, + .EmcDllXformDqs2 = 0x00000009, + .EmcDllXformDqs3 = 0x0000000a, + .EmcDllXformDqs4 = 0x0000000b, + .EmcDllXformDqs5 = 0x0000000a, + .EmcDllXformDqs6 = 0x0000000b, + .EmcDllXformDqs7 = 0x00000008, + .EmcDllXformDqs8 = 0x00000009, + .EmcDllXformDqs9 = 0x0000000a, + .EmcDllXformDqs10 = 0x00000009, + .EmcDllXformDqs11 = 0x0000000a, + .EmcDllXformDqs12 = 0x0000000b, + .EmcDllXformDqs13 = 0x0000000a, + .EmcDllXformDqs14 = 0x0000000b, + .EmcDllXformDqs15 = 0x00000008, + .EmcDllXformQUse0 = 0x00000000, + .EmcDllXformQUse1 = 0x00000000, + .EmcDllXformQUse2 = 0x00000000, + .EmcDllXformQUse3 = 0x00000000, + .EmcDllXformQUse4 = 0x00000000, + .EmcDllXformQUse5 = 0x00000000, + .EmcDllXformQUse6 = 0x00000000, + .EmcDllXformQUse7 = 0x00000000, + .EmcDllXformAddr0 = 0x0002c000, + .EmcDllXformAddr1 = 0x0002c000, + .EmcDllXformAddr2 = 0x00000000, + .EmcDllXformAddr3 = 0x0002c000, + .EmcDllXformAddr4 = 0x0002c000, + .EmcDllXformAddr5 = 0x00000000, + .EmcDllXformQUse8 = 0x00000000, + .EmcDllXformQUse9 = 0x00000000, + .EmcDllXformQUse10 = 0x00000000, + .EmcDllXformQUse11 = 0x00000000, + .EmcDllXformQUse12 = 0x00000000, + .EmcDllXformQUse13 = 0x00000000, + .EmcDllXformQUse14 = 0x00000000, + .EmcDllXformQUse15 = 0x00000000, + .EmcDliTrimTxDqs0 = 0x00000008, + .EmcDliTrimTxDqs1 = 0x00000008, + .EmcDliTrimTxDqs2 = 0x00000005, + .EmcDliTrimTxDqs3 = 0x00000008, + .EmcDliTrimTxDqs4 = 0x0000000a, + .EmcDliTrimTxDqs5 = 0x00000008, + .EmcDliTrimTxDqs6 = 0x0000000a, + .EmcDliTrimTxDqs7 = 0x0000000a, + .EmcDliTrimTxDqs8 = 0x00000008, + .EmcDliTrimTxDqs9 = 0x00000008, + .EmcDliTrimTxDqs10 = 0x00000005, + .EmcDliTrimTxDqs11 = 0x00000008, + .EmcDliTrimTxDqs12 = 0x0000000a, + .EmcDliTrimTxDqs13 = 0x00000008, + .EmcDliTrimTxDqs14 = 0x0000000a, + .EmcDliTrimTxDqs15 = 0x0000000a, + .EmcDllXformDq0 = 0x0000000c, + .EmcDllXformDq1 = 0x0000000c, + .EmcDllXformDq2 = 0x0000000c, + .EmcDllXformDq3 = 0x0000000c, + .EmcDllXformDq4 = 0x0000000c, + .EmcDllXformDq5 = 0x0000000c, + .EmcDllXformDq6 = 0x0000000c, + .EmcDllXformDq7 = 0x0000000c, + .WarmBootWait = 0x00000002, + .EmcCttTermCtrl = 0x00000802, + .EmcOdtWrite = 0x00000000, + .EmcOdtRead = 0x00000000, + .EmcZcalInterval = 0x00020000, + .EmcZcalWaitCnt = 0x00000042, + .EmcZcalMrwCmd = 0x00000000, + .EmcMrsResetDll = 0x00000000, + .EmcZcalInitDev0 = 0x80000011, + .EmcZcalInitDev1 = 0x40000011, + .EmcZcalInitWait = 0x00000001, + .EmcZcalWarmColdBootEnables = 0x00000003, + .EmcMrwLpddr2ZcalWarmBoot = 0x040a00ab, + .EmcZqCalDdr3WarmBoot = 0x00000000, + .EmcZcalWarmBootWait = 0x00000001, + .EmcMrsWarmBootEnable = 0x00000001, + .EmcMrsResetDllWait = 0x00000000, + .EmcMrsExtra = 0x00000d71, + .EmcWarmBootMrsExtra = 0x00100002, + .EmcEmrsDdr2DllEnable = 0x00000000, + .EmcMrsDdr2DllReset = 0x00000000, + .EmcEmrsDdr2OcdCalib = 0x00000000, + .EmcDdr2Wait = 0x00000000, + .EmcClkenOverride = 0x00000000, + .McDisExtraSnapLevels = 0x00000000, + .EmcExtraRefreshNum = 0x00000002, + .EmcClkenOverrideAllWarmBoot = 0x00000000, + .McClkenOverrideAllWarmBoot = 0x00000000, + .EmcCfgDigDllPeriodWarmBoot = 0x00000003, + .PmcVddpSel = 0x00000002, + .PmcVddpSelWait = 0x00000002, + .PmcDdrPwr = 0x00000003, + .PmcDdrCfg = 0x00002002, + .PmcIoDpd3Req = 0x4fffffff, + .PmcIoDpd3ReqWait = 0x00000000, + .PmcRegShort = 0x00000000, + .PmcNoIoPower = 0x00000000, + .PmcPorDpdCtrlWait = 0x00000000, + .EmcXm2CmdPadCtrl = 0x100002a0, + .EmcXm2CmdPadCtrl2 = 0x770c0000, + .EmcXm2CmdPadCtrl3 = 0x050c0000, + .EmcXm2CmdPadCtrl4 = 0x00000000, + .EmcXm2CmdPadCtrl5 = 0x00111111, + .EmcXm2DqsPadCtrl = 0x770c1414, + .EmcXm2DqsPadCtrl2 = 0x0120113d, + .EmcXm2DqsPadCtrl3 = 0x61869a20, + .EmcXm2DqsPadCtrl4 = 0x00596596, + .EmcXm2DqsPadCtrl5 = 0x00596596, + .EmcXm2DqsPadCtrl6 = 0x69969900, + .EmcXm2DqPadCtrl = 0x770c2990, + .EmcXm2DqPadCtrl2 = 0x00000000, + .EmcXm2DqPadCtrl3 = 0x00000000, + .EmcXm2ClkPadCtrl = 0x77ffc085, + .EmcXm2ClkPadCtrl2 = 0x00000202, + .EmcXm2CompPadCtrl = 0x81f1f108, + .EmcXm2VttGenPadCtrl = 0x07070004, + .EmcXm2VttGenPadCtrl2 = 0x00000000, + .EmcXm2VttGenPadCtrl3 = 0x016eeeee, + .EmcAcpdControl = 0x00000000, + .EmcSwizzleRank0ByteCfg = 0x00003120, + .EmcSwizzleRank0Byte0 = 0x01643752, + .EmcSwizzleRank0Byte1 = 0x34675021, + .EmcSwizzleRank0Byte2 = 0x63170254, + .EmcSwizzleRank0Byte3 = 0x14065327, + .EmcSwizzleRank1ByteCfg = 0x00003120, + .EmcSwizzleRank1Byte0 = 0x73541062, + .EmcSwizzleRank1Byte1 = 0x10637254, + .EmcSwizzleRank1Byte2 = 0x62043715, + .EmcSwizzleRank1Byte3 = 0x73015624, + .EmcDsrVttgenDrv = 0x0606003f, + .EmcTxdsrvttgen = 0x00000000, + .EmcBgbiasCtl0 = 0x00000000, + .McEmemAdrCfg = 0x00000001, + .McEmemAdrCfgDev0 = 0x00080303, + .McEmemAdrCfgDev1 = 0x00080303, + .McEmemAdrCfgBankMask0 = 0x00001248, + .McEmemAdrCfgBankMask1 = 0x00002490, + .McEmemAdrCfgBankMask2 = 0x00000920, + .McEmemAdrCfgBankSwizzle3 = 0x00000001, + .McEmemCfg = 0x00001000, + .McEmemArbCfg = 0x0e00000b, + .McEmemArbOutstandingReq = 0x80000040, + .McEmemArbTimingRcd = 0x00000004, + .McEmemArbTimingRp = 0x00000005, + .McEmemArbTimingRc = 0x00000013, + .McEmemArbTimingRas = 0x0000000c, + .McEmemArbTimingFaw = 0x0000000f, + .McEmemArbTimingRrd = 0x00000002, + .McEmemArbTimingRap2Pre = 0x00000003, + .McEmemArbTimingWap2Pre = 0x0000000c, + .McEmemArbTimingR2R = 0x00000002, + .McEmemArbTimingW2W = 0x00000002, + .McEmemArbTimingR2W = 0x00000006, + .McEmemArbTimingW2R = 0x00000008, + .McEmemArbDaTurns = 0x08060202, + .McEmemArbDaCovers = 0x00160d13, + .McEmemArbMisc0 = 0x746c2414, + .McEmemArbMisc1 = 0x70000f02, + .McEmemArbRing1Throttle = 0x001f0000, + .McEmemArbOverride = 0x10000000, + .McEmemArbOverride1 = 0x00000000, + .McEmemArbRsv = 0xff00ff00, + .McClkenOverride = 0x00000000, + .McStatControl = 0x00000000, + .McDisplaySnapRing = 0x00000003, + .McVideoProtectBom = 0xfff00000, + .McVideoProtectBomAdrHi = 0x00000000, + .McVideoProtectSizeMb = 0x00000000, + .McVideoProtectVprOverride = 0xe4bac743, + .McVideoProtectVprOverride1 = 0x00000013, + .McVideoProtectGpuOverride0 = 0x00000000, + .McVideoProtectGpuOverride1 = 0x00000000, + .McSecCarveoutBom = 0xfff00000, + .McSecCarveoutAdrHi = 0x00000000, + .McSecCarveoutSizeMb = 0x00000000, + .McVideoProtectWriteAccess = 0x00000000, + .McSecCarveoutProtectWriteAccess = 0x00000000, + .EmcCaTrainingEnable = 0x00000000, + .EmcCaTrainingTimingCntl1 = 0x1f7df7df, + .EmcCaTrainingTimingCntl2 = 0x0000001f, + .SwizzleRankByteEncode = 0x0000000b, + .BootRomPatchControl = 0x00000000, + .BootRomPatchData = 0x00000000, + .McMtsCarveoutBom = 0xfff00000, + .McMtsCarveoutAdrHi = 0x00000000, + .McMtsCarveoutSizeMb = 0x00000000, + .McMtsCarveoutRegCtrl = 0x00000000, +}, diff --git a/src/mainboard/google/nyan_blaze/sdram_configs.c b/src/mainboard/google/nyan_blaze/sdram_configs.c index 74f32fa..6fb517d 100644 --- a/src/mainboard/google/nyan_blaze/sdram_configs.c +++ b/src/mainboard/google/nyan_blaze/sdram_configs.c @@ -30,9 +30,9 @@ static struct sdram_params sdram_configs[] = { #include "bct/sdram-unused.inc" /* ram_code = 0101 */ #include "bct/sdram-unused.inc" /* ram_code = 0110 */ #include "bct/sdram-unused.inc" /* ram_code = 0111 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1000 */ -#include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1001 */ -#include "bct/sdram-samsung-4GB-204.inc" /* ram_code = 1010 */ +#include "bct/sdram-hynix-4GB-792.inc" /* ram_code = 1000 */ +#include "bct/sdram-micron-4GB-792.inc" /* ram_code = 1001 */ +#include "bct/sdram-samsung-4GB-792.inc" /* ram_code = 1010 */ #include "bct/sdram-hynix-2GB-204.inc" /* ram_code = 1011 */ #include "bct/sdram-unused.inc" /* ram_code = 1100 */ #include "bct/sdram-unused.inc" /* ram_code = 1101 */

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coreboot-gerrit January 2015