coreboot-gerrit January 2015

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Patch set updated for coreboot: 2da1715 amd/agesa/family12/northbridge.c: Indent (tab) fix
by Edward O'Callaghan 02 Jan '15

02 Jan '15

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8015 -gerrit commit 2da1715e6e77d17325b44e4cb5d42e423b60a9e4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Jan 1 03:49:47 2015 +1100 amd/agesa/family12/northbridge.c: Indent (tab) fix Trivial; Use tab over space for indent. Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family12/northbridge.c | 634 +++++++++++------------ 1 file changed, 312 insertions(+), 322 deletions(-) diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index fe9cd72..a3b3493 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -58,223 +58,217 @@ static device_t get_node_pci(u32 nodeid, u32 fn) static void get_fx_devs(void) { - int i; - for(i = 0; i < FX_DEVS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } -} + int i; + for(i = 0; i < FX_DEVS; i++) { + __f0_dev[i] = get_node_pci(i, 0); + __f1_dev[i] = get_node_pci(i, 1); + __f2_dev[i] = get_node_pci(i, 2); + __f4_dev[i] = get_node_pci(i, 4); + if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) + fx_devs = i+1; + } + if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) + die("Cannot find 0:0x18.[0|1]\n"); +} static u32 f1_read_config32(unsigned reg) { - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} + if (fx_devs == 0) + get_fx_devs(); + return pci_read_config32(__f1_dev[0], reg); +} static void f1_write_config32(unsigned reg, u32 value) { - int i; - if (fx_devs == 0) - get_fx_devs(); - for(i = 0; i < fx_devs; i++) { - device_t dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } + int i; + if (fx_devs == 0) + get_fx_devs(); + for(i = 0; i < fx_devs; i++) { + device_t dev = __f1_dev[i]; + if (dev && dev->enabled) { + pci_write_config32(dev, reg, value); + } + } } - static u32 amdfam12_nodeid(device_t dev) { - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); - return (dev->path.pci.devfn >> 3) - CONFIG_CDB; + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s\n",__func__); + return (dev->path.pci.devfn >> 3) - CONFIG_CDB; } - #include "amdfam12_conf.c" - static void northbridge_init(device_t dev) { - printk(BIOS_DEBUG, "Northbridge init\n"); + printk(BIOS_DEBUG, "Northbridge init\n"); } static void set_vga_enable_reg(u32 nodeid, u32 linkn) { - u32 val; + u32 val; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - val = 1 | (nodeid<<4) | (linkn<<12); - /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, - 0x3c0:0x3df */ - f1_write_config32(0xf4, val); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + val = 1 | (nodeid<<4) | (linkn<<12); + /* it will routing (1)mmio 0xa0000:0xbffff (2) io 0x3b0:0x3bb, + 0x3c0:0x3df */ + f1_write_config32(0xf4, val); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static int reg_useable(unsigned reg, device_t goal_dev, unsigned goal_nodeid, unsigned goal_link) { - struct resource *res; - unsigned nodeid, link = 0; - int result; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - res = 0; - for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - device_t dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for(link = 0; !res && (link < 8); link++) { - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - } - result = 2; - if (res) { - result = 0; - if ( (goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); - return result; + struct resource *res; + unsigned nodeid, link = 0; + int result; + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + res = 0; + for(nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { + device_t dev = __f0_dev[nodeid]; + if (!dev) + continue; + for(link = 0; !res && (link < 8); link++) { + res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); + } + } + result = 2; + if (res) { + result = 0; + if ( (goal_link == (link - 1)) && + (goal_nodeid == (nodeid - 1)) && + (res->flags <= 1)) { + result = 1; + } + } + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + return result; } static struct resource *amdfam12_find_iopair(device_t dev, unsigned nodeid, unsigned link) { - struct resource *resource; - u32 result, reg; - resource = 0; - reg = 0; - result = reg_useable(0xc0, dev, nodeid, link); - if (result >= 1) { - /* I have been allocated this one */ - reg = 0xc0; - } + struct resource *resource; + u32 result, reg; + resource = 0; + reg = 0; + result = reg_useable(0xc0, dev, nodeid, link); + if (result >= 1) { + /* I have been allocated this one */ + reg = 0xc0; + } - //Ext conf space - if(!reg) { - //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range - u32 index = get_io_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 - } + //Ext conf space + if(!reg) { + //because of Extend conf space, we will never run out of reg, but we need one index to differ them. so same node and same link can have multi range + u32 index = get_io_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 + } - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; + return resource; } static struct resource *amdfam12_find_mempair(device_t dev, u32 nodeid, u32 link) { - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for(reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result == 1) { - /* I have been allocated this one */ - break; - } - else if (result > 1) { - /* I have a free register pair */ - free_reg = reg; - } - } - if (reg > 0xb8) { - reg = free_reg; - } + struct resource *resource; + u32 free_reg, reg; + resource = 0; + free_reg = 0; + for(reg = 0x80; reg <= 0xb8; reg += 0x8) { + int result; + result = reg_useable(reg, dev, nodeid, link); + if (result == 1) { + /* I have been allocated this one */ + break; + } + else if (result > 1) { + /* I have a free register pair */ + free_reg = reg; + } + } + if (reg > 0xb8) { + reg = free_reg; + } - //Ext conf space - if(!reg) { - //because of Extend conf space, we will never run out of reg, - // but we need one index to differ them. so same node and - // same link can have multi range - u32 index = get_mmio_addr_index(nodeid, link); - reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + //Ext conf space + if(!reg) { + //because of Extend conf space, we will never run out of reg, + // but we need one index to differ them. so same node and + // same link can have multi range + u32 index = get_mmio_addr_index(nodeid, link); + reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 + } - } - resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); - return resource; + resource = new_resource(dev, IOINDEX(0x1000 + reg, link)); + return resource; } static void amdfam12_link_read_bases(device_t dev, u32 nodeid, u32 link) { - struct resource *resource; + struct resource *resource; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - /* Initialize the io space constraints on the current bus */ - resource = amdfam12_find_iopair(dev, nodeid, link); - if (resource) { - u32 align; - align = log2(HT_IO_HOST_ALIGN); - resource->base = 0; - resource->size = 0; - resource->align = align; - resource->gran = align; - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + /* Initialize the io space constraints on the current bus */ + resource = amdfam12_find_iopair(dev, nodeid, link); + if (resource) { + u32 align; + align = log2(HT_IO_HOST_ALIGN); + resource->base = 0; + resource->size = 0; + resource->align = align; + resource->gran = align; + resource->limit = 0xffffUL; + resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; + } - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam12_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } + /* Initialize the prefetchable memory constraints on the current bus */ + resource = amdfam12_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; + resource->flags |= IORESOURCE_BRIDGE; + } - /* Initialize the memory constraints on the current bus */ - resource = amdfam12_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + /* Initialize the memory constraints on the current bus */ + resource = amdfam12_find_mempair(dev, nodeid, link); + if (resource) { + resource->base = 0; + resource->size = 0; + resource->align = log2(HT_MEM_HOST_ALIGN); + resource->gran = log2(HT_MEM_HOST_ALIGN); + resource->limit = 0xffffffffffULL; + resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; + } + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static u32 my_find_pci_tolm(struct bus *bus, u32 tolm) { - struct resource *min; - min = 0; - search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); - if (min && tolm > min->base) { - tolm = min->base; - } - return tolm; + struct resource *min; + min = 0; + search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); + if (min && tolm > min->base) { + tolm = min->base; + } + return tolm; } #if CONFIG_HW_MEM_HOLE_SIZEK != 0 struct hw_mem_hole_info { - unsigned hole_startk; - int node_id; + unsigned hole_startk; + int node_id; }; static struct hw_mem_hole_info get_hw_mem_hole_info(void) @@ -325,69 +319,67 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) static void read_resources(device_t dev) { - u32 nodeid; - struct bus *link; + u32 nodeid; + struct bus *link; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - nodeid = amdfam12_nodeid(dev); - for(link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam12_link_read_bases(dev, nodeid, link->link_num); - } - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + nodeid = amdfam12_nodeid(dev); + for(link = dev->link_list; link; link = link->next) { + if (link->children) { + amdfam12_link_read_bases(dev, nodeid, link->link_num); + } + } + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } -static void set_resource(device_t dev, struct resource *resource, - u32 nodeid) +static void set_resource(device_t dev, struct resource *resource, u32 nodeid) { - resource_t rbase, rend; - unsigned reg, link_num; - char buf[50]; + resource_t rbase, rend; + unsigned reg, link_num; + char buf[50]; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) { - return; - } + /* Make certain the resource has actually been set */ + if (!(resource->flags & IORESOURCE_ASSIGNED)) { + return; + } - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) { - return; - } + /* If I have already stored this resource don't worry about it */ + if (resource->flags & IORESOURCE_STORED) { + return; + } - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; + /* Only handle PCI memory and IO resources */ + if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) + return; - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) { - return; - } - /* Get the base address */ - rbase = resource->base; + /* Ensure I am actually looking at a resource of function 1 */ + if ((resource->index & 0xffff) < 0x1000) { + return; + } + /* Get the base address */ + rbase = resource->base; - /* Get the limit (rounded up) */ - rend = resource_end(resource); + /* Get the limit (rounded up) */ + rend = resource_end(resource); - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); + /* Get the register and link */ + reg = resource->index & 0xfff; // 4k + link_num = IOINDEX_LINK(resource->index); - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1) ;// [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof (buf), " <node %x link %x>", - nodeid, link_num); - report_resource_stored(dev, resource, buf); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + if (resource->flags & IORESOURCE_IO) { + set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); + } + else if (resource->flags & IORESOURCE_MEM) { + set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, 1); // [39:8] + } + resource->flags |= IORESOURCE_STORED; + snprintf(buf, sizeof (buf), " <node %x link %x>", nodeid, link_num); + report_resource_stored(dev, resource, buf); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -397,87 +389,85 @@ extern device_t vga_pri; // the primary vga device, defined in device.c static void create_vga_resource(device_t dev, unsigned nodeid) { - struct bus *link; +struct bus *link; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); +printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { + /* find out which link the VGA card is connected, + * we only deal with the 'first' vga card */ + for (link = dev->link_list; link; link = link->next) { + if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { #if CONFIG_CONSOLE_VGA_MULTI - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if((vga_pri->bus->secondary >= link->secondary ) && - (vga_pri->bus->secondary <= link->subordinate ) - ) + printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, + link->secondary,link->subordinate); + /* We need to make sure the vga_pri is under the link */ + if((vga_pri->bus->secondary >= link->secondary ) && + (vga_pri->bus->secondary <= link->subordinate )) #endif - break; - } - } + break; // XXX this break looks questionable + } + } - /* no VGA card installed */ - if (link == NULL) - return; + /* no VGA card installed */ + if (link == NULL) + return; - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); - set_vga_enable_reg(nodeid, link->link_num); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); + set_vga_enable_reg(nodeid, link->link_num); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void set_resources(device_t dev) { - unsigned nodeid; - struct bus *bus; - struct resource *res; + unsigned nodeid; + struct bus *bus; + struct resource *res; - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - /* Find the nodeid */ - nodeid = amdfam12_nodeid(dev); + /* Find the nodeid */ + nodeid = amdfam12_nodeid(dev); - create_vga_resource(dev, nodeid); + create_vga_resource(dev, nodeid); - /* Set each resource we have found */ - for(res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } + /* Set each resource we have found */ + for(res = dev->resource_list; res; res = res->next) { + set_resource(dev, res, nodeid); + } - for(bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + for(bus = dev->link_list; bus; bus = bus->next) { + if (bus->children) + assign_resources(bus); + } + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint32_t topmem = (uint32_t) bsp_topmem(); - uint32_t sys_mem; - - /* refer to UMA Size Consideration in Family12h BKDG. */ - /* Please reference MemNGetUmaSizeLN () */ - /* - * Total system memory UMASize - * >= 2G 512M - * >=1G 256M - * <1G 64M - */ - sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size - if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { - uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ - } else if (sys_mem >= 0x40000000) { - uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ - } else { - uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ - printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", - __func__, uma_memory_size, uma_memory_base); + uint32_t topmem = (uint32_t) bsp_topmem(); + uint32_t sys_mem; + + /* refer to UMA Size Consideration in Family12h BKDG. */ + /* Please reference MemNGetUmaSizeLN () */ + /* + * Total system memory UMASize + * >= 2G 512M + * >=1G 256M + * <1G 64M + */ + sys_mem = topmem + 0x1000000; // Ignore 16MB allocated for C6 when finding UMA size + if ((bsp_topmem2()>>32) || (sys_mem >= 0x80000000)) { + uma_memory_size = 0x20000000; /* >= 2G memory, 512M recommended UMA */ + } else if (sys_mem >= 0x40000000) { + uma_memory_size = 0x10000000; /* >= 1G memory, 256M recommended UMA */ + } else { + uma_memory_size = 0x4000000; /* <1G memory, 64M recommended UMA */ + } + uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); #endif } @@ -768,35 +758,35 @@ static void domain_enable_resources(device_t dev) static void cpu_bus_read_resources(device_t dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); #if CONFIG_MMCONF_SUPPORT - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + struct resource *resource = new_resource(dev, 0xc0010058); + resource->base = CONFIG_MMCONF_BASE_ADDRESS; + resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; #endif - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); + struct resource *resource = find_resource(dev, 0xc0010058); - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } - pci_dev_set_resources(dev); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + if (resource) { + report_resource_stored(dev, resource, " <mmconfig>"); + } + pci_dev_set_resources(dev); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } static void cpu_bus_init(device_t dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - initialize_cpus(dev->link_list); - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + initialize_cpus(dev->link_list); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -911,27 +901,27 @@ static unsigned long agesa_write_acpi_tables(unsigned long current, static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, - .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .enable = 0, - .ops_pci = 0, + .read_resources = read_resources, + .set_resources = set_resources, + .acpi_fill_ssdt_generator = northbridge_fill_ssdt_generator, + .write_acpi_tables = agesa_write_acpi_tables, + .enable_resources = pci_dev_enable_resources, + .init = northbridge_init, + .enable = 0, + .ops_pci = 0, }; static const struct pci_driver northbridge_driver __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = 0x1705, + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1705, }; struct chip_operations northbridge_amd_agesa_family12_ops = { - CHIP_NAME("AMD Family 12h Northbridge") - .enable_dev = 0, + CHIP_NAME("AMD Family 12h Northbridge") + .enable_dev = 0, }; @@ -939,48 +929,48 @@ struct chip_operations northbridge_amd_agesa_family12_ops = { static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, - .init = NULL, - .scan_bus = pci_domain_scan_bus, + .read_resources = domain_read_resources, + .set_resources = domain_set_resources, + .enable_resources = domain_enable_resources, + .init = NULL, + .scan_bus = pci_domain_scan_bus, }; static struct device_operations cpu_bus_ops = { - .read_resources = cpu_bus_read_resources, - .set_resources = cpu_bus_set_resources, - .enable_resources = NULL, - .init = cpu_bus_init, - .scan_bus = 0, + .read_resources = cpu_bus_read_resources, + .set_resources = cpu_bus_set_resources, + .enable_resources = NULL, + .init = cpu_bus_init, + .scan_bus = 0, }; static void root_complex_enable_dev(struct device *dev) { - printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - static int done = 0; + printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); + static int done = 0; /* Do not delay UMA setup, as a device on the PCI bus may evaluate the global uma_memory variables already in its enable function. */ - if (!done) { - setup_bsp_ramtop(); - setup_uma_memory(); - done = 1; - } + if (!done) { + setup_bsp_ramtop(); + setup_uma_memory(); + done = 1; + } - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } - printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); + /* Set the operations if it is a special bus type */ + if (dev->path.type == DEVICE_PATH_DOMAIN) { + dev->ops = &pci_domain_ops; + } + else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { + dev->ops = &cpu_bus_ops; + } + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } struct chip_operations northbridge_amd_agesa_family12_root_complex_ops = { - CHIP_NAME("AMD Family 12h Root Complex") - .enable_dev = root_complex_enable_dev, + CHIP_NAME("AMD Family 12h Root Complex") + .enable_dev = root_complex_enable_dev, };

1 0

Patch merged into coreboot/master: e8897c4 soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.
by gerrit＠coreboot.org 01 Jan '15

01 Jan '15

the following patch was just integrated into master: commit e8897c45a80394f3eaab42d2805c4bae97732b8c Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Dec 31 19:44:22 2014 -0800 soc/riscv: Fix typo in src/soc/ucb/Makefile.inc. riscv builds again. Change-Id: I4caaee49c3eaa948540a916f684dd4e1ed9c9011 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/8026 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/8026 for details. -gerrit

1 0

Patch set updated for coreboot: 4022eec soc/riscv: Fix typo in src/soc/ucb/Makefile.inc.
by Ronald G. Minnich 01 Jan '15

01 Jan '15

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8026 -gerrit commit 4022eec43b6588fb289e3975741681f295dd8c67 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Dec 31 19:44:22 2014 -0800 soc/riscv: Fix typo in src/soc/ucb/Makefile.inc. riscv builds again. Change-Id: I4caaee49c3eaa948540a916f684dd4e1ed9c9011 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/soc/ucb/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/ucb/Makefile.inc b/src/soc/ucb/Makefile.inc index 35bc728..fe40742 100644 --- a/src/soc/ucb/Makefile.inc +++ b/src/soc/ucb/Makefile.inc @@ -1 +1 @@ -subdirs-$(CONFIG_CPU_UCB_RISCV) += riscv +subdirs-$(CONFIG_SOC_UCB_RISCV) += riscv

1 0

Patch merged into coreboot/master: 922b3ca ARM: Fix ARM_LPAE to not be selectable as a menu item.
by gerrit＠coreboot.org 01 Jan '15

01 Jan '15

the following patch was just integrated into master: commit 922b3ca8e515f0b3079ba4dfc9bc778102b48089 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Dec 31 19:47:08 2014 -0800 ARM: Fix ARM_LPAE to not be selectable as a menu item. It was showing up as a menu item and it should not. Change-Id: I448f683fbf4187b11821381332f971b1daea29f8 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/8027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/8027 for details. -gerrit

1 0

Patch set updated for coreboot: 728f3ce lenovo/t410s: Add new port.
by Nicolas Reinecke 01 Jan '15

01 Jan '15

Nicolas Reinecke (nr(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7975 -gerrit commit 728f3ce2902e7ea3b0002c2302c8af9a95e7d575 Author: Nicolas Reinecke <nr(a)das-labor.org> Date: Mon Dec 29 20:17:36 2014 +0100 lenovo/t410s: Add new port. Based on x201. untested - go steffanct ;) Change-Id: Iacee1e8c217ac621b0a2b51be280b7237a6e7c2a Signed-off-by: Nicolas Reinecke <nr(a)das-labor.org> --- src/ec/acpi/Makefile.inc | 1 + src/mainboard/lenovo/Kconfig | 6 + src/mainboard/lenovo/t410s/Kconfig | 48 ++++ src/mainboard/lenovo/t410s/Makefile.inc | 23 ++ src/mainboard/lenovo/t410s/acpi/dock.asl | 79 ++++++ src/mainboard/lenovo/t410s/acpi/ec.asl | 26 ++ src/mainboard/lenovo/t410s/acpi/gpe.asl | 30 +++ src/mainboard/lenovo/t410s/acpi/platform.asl | 148 ++++++++++++ src/mainboard/lenovo/t410s/acpi/superio.asl | 1 + src/mainboard/lenovo/t410s/acpi_tables.c | 61 +++++ src/mainboard/lenovo/t410s/board_info.txt | 5 + src/mainboard/lenovo/t410s/cmos.default | 18 ++ src/mainboard/lenovo/t410s/cmos.layout | 157 ++++++++++++ src/mainboard/lenovo/t410s/devicetree.cb | 167 +++++++++++++ src/mainboard/lenovo/t410s/dock.c | 71 ++++++ src/mainboard/lenovo/t410s/dock.h | 26 ++ src/mainboard/lenovo/t410s/dsdt.asl | 96 ++++++++ src/mainboard/lenovo/t410s/gpio.h | 345 +++++++++++++++++++++++++++ src/mainboard/lenovo/t410s/hda_verb.c | 81 +++++++ src/mainboard/lenovo/t410s/mainboard.c | 146 ++++++++++++ src/mainboard/lenovo/t410s/romstage.c | 314 ++++++++++++++++++++++++ src/mainboard/lenovo/t410s/smi.h | 26 ++ src/mainboard/lenovo/t410s/smihandler.c | 222 +++++++++++++++++ 23 files changed, 2097 insertions(+) diff --git a/src/ec/acpi/Makefile.inc b/src/ec/acpi/Makefile.inc index b39aaa2..624d3d6 100644 --- a/src/ec/acpi/Makefile.inc +++ b/src/ec/acpi/Makefile.inc @@ -1,3 +1,4 @@ ramstage-y += ec.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ec.c romstage-$(CONFIG_BOARD_LENOVO_X201) += ec.c +romstage-$(CONFIG_BOARD_LENOVO_T410S) += ec.c diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 30b1d36..3cbfd13 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -32,6 +32,11 @@ config BOARD_LENOVO_X230 help Lenovo X230 laptop. Consult wiki for details. +config BOARD_LENOVO_T410S + bool "ThinkPad T410s" + help + Lenovo T410s laptop. Consult wiki for details. + config BOARD_LENOVO_T420S bool "ThinkPad T420s" help @@ -67,6 +72,7 @@ source "src/mainboard/lenovo/x200/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x220/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" +source "src/mainboard/lenovo/t410s/Kconfig" source "src/mainboard/lenovo/t420s/Kconfig" source "src/mainboard/lenovo/t520/Kconfig" source "src/mainboard/lenovo/t530/Kconfig" diff --git a/src/mainboard/lenovo/t410s/Kconfig b/src/mainboard/lenovo/t410s/Kconfig new file mode 100644 index 0000000..d8abc6e --- /dev/null +++ b/src/mainboard/lenovo/t410s/Kconfig @@ -0,0 +1,48 @@ +if BOARD_LENOVO_T410S + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select SYSTEM_TYPE_LAPTOP + select NORTHBRIDGE_INTEL_NEHALEM + select SOUTHBRIDGE_INTEL_IBEXPEAK + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select DRIVERS_ICS_954309 + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select INTEL_INT15 + select HAVE_ACPI_RESUME + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG + +config MAINBOARD_DIR + string + default lenovo/t410s + +config MAINBOARD_PART_NUMBER + string + default "ThinkPad T410s" + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_RESET_GATE_GPIO + int + default 10 + +config MAX_CPUS + int + default 4 + +config CPU_ADDR_BITS + int + default 36 + +endif diff --git a/src/mainboard/lenovo/t410s/Makefile.inc b/src/mainboard/lenovo/t410s/Makefile.inc new file mode 100644 index 0000000..eb099f3 --- /dev/null +++ b/src/mainboard/lenovo/t410s/Makefile.inc @@ -0,0 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += dock.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c +romstage-y += dock.c +ramstage-y += dock.c diff --git a/src/mainboard/lenovo/t410s/acpi/dock.asl b/src/mainboard/lenovo/t410s/acpi/dock.asl new file mode 100644 index 0000000..ffcb47f --- /dev/null +++ b/src/mainboard/lenovo/t410s/acpi/dock.asl @@ -0,0 +1,79 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" + +Scope (\_SB) +{ + Device(DOCK) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_DCK, 1, NotSerialized) + { + if (Arg0) { + /* connect dock */ + Store (1, \GP28) + Store (1, \_SB.PCI0.LPCB.EC.DKR1) + Store (1, \_SB.PCI0.LPCB.EC.DKR2) + Store (1, \_SB.PCI0.LPCB.EC.DKR3) + } else { + /* disconnect dock */ + Store (0, \GP28) + Store (0, \_SB.PCI0.LPCB.EC.DKR1) + Store (0, \_SB.PCI0.LPCB.EC.DKR2) + Store (0, \_SB.PCI0.LPCB.EC.DKR3) + } + Xor(Arg0, \_SB.PCI0.LPCB.EC.DKR1, Local0) + Return (Local0) + } + + Method(_STA, 0, NotSerialized) + { + Return (\_SB.PCI0.LPCB.EC.DKR1) + } + } +} + +Scope(\_SB.PCI0.LPCB.EC) +{ + Method(_Q18, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q45, 0, NotSerialized) + { + Notify(\_SB.DOCK, 3) + } + + Method(_Q58, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) + } + + Method(_Q37, 0, NotSerialized) + { + Notify(\_SB.DOCK, 0) + } +} diff --git a/src/mainboard/lenovo/t410s/acpi/ec.asl b/src/mainboard/lenovo/t410s/acpi/ec.asl new file mode 100644 index 0000000..4b3e72c --- /dev/null +++ b/src/mainboard/lenovo/t410s/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t410s/acpi/gpe.asl b/src/mainboard/lenovo/t410s/acpi/gpe.asl new file mode 100644 index 0000000..b160b50 --- /dev/null +++ b/src/mainboard/lenovo/t410s/acpi/gpe.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" +Scope (\_GPE) +{ + Method(_L18, 0, NotSerialized) + { + /* Read EC register to clear wake status */ + Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) + } +} diff --git a/src/mainboard/lenovo/t410s/acpi/platform.asl b/src/mainboard/lenovo/t410s/acpi/platform.asl new file mode 100644 index 0000000..492ab57 --- /dev/null +++ b/src/mainboard/lenovo/t410s/acpi/platform.asl @@ -0,0 +1,148 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* These come from the dynamically created CPU SSDT */ +External(PDC0) +External(PDC1) + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, /* APM command */ + APMS, 8 /* APM status */ +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + \_SB.PCI0.LPCB.EC.MUTE(1) + \_SB.PCI0.LPCB.EC.USBP(0) +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Not implemented. */ + Return(Package(){0,0}) +} + +/* System Bus */ + +Scope(\_SB) +{ + /* This method is placed on the top level, so we can make sure it's the + * first executed _INI method. + */ + Method(_INI, 0) + { + /* The DTS data in NVS is probably not up to date. + * Update temperature values and make sure AP thermal + * interrupts can happen + */ + + /* TRAP(71) */ /* TODO */ + + /* Determine the Operating System and save the value in OSYS. + * We have to do this in order to be able to work around + * certain windows bugs. + * + * OSYS value | Operating System + * -----------+------------------ + * 2000 | Windows 2000 + * 2001 | Windows XP(+SP1) + * 2002 | Windows XP SP2 + * 2006 | Windows Vista + * ???? | Windows 7 + */ + + /* Let's assume we're running at least Windows 2000 */ + Store (2000, OSYS) + + If (CondRefOf(_OSI, Local0)) { + If (_OSI("Windows 2001")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001 SP2")) { + Store (2002, OSYS) + } + + If (_OSI("Windows 2001.1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2001.1 SP1")) { + Store (2001, OSYS) + } + + If (_OSI("Windows 2006")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006.1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2006 SP1")) { + Store (2006, OSYS) + } + + If (_OSI("Windows 2009")) { + Store (2009, OSYS) + } + + If (_OSI("Windows 2012")) { + Store (2012, OSYS) + } + } + } +} diff --git a/src/mainboard/lenovo/t410s/acpi/superio.asl b/src/mainboard/lenovo/t410s/acpi/superio.asl new file mode 100644 index 0000000..03b65bc --- /dev/null +++ b/src/mainboard/lenovo/t410s/acpi/superio.asl @@ -0,0 +1 @@ +#include <drivers/pc80/ps2_controller.asl> diff --git a/src/mainboard/lenovo/t410s/acpi_tables.c b/src/mainboard/lenovo/t410s/acpi_tables.c new file mode 100644 index 0000000..f1de013 --- /dev/null +++ b/src/mainboard/lenovo/t410s/acpi_tables.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <southbridge/intel/ibexpeak/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + /* Not implemented */ + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} diff --git a/src/mainboard/lenovo/t410s/board_info.txt b/src/mainboard/lenovo/t410s/board_info.txt new file mode 100644 index 0000000..689ca8f --- /dev/null +++ b/src/mainboard/lenovo/t410s/board_info.txt @@ -0,0 +1,5 @@ +Category: laptop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: n diff --git a/src/mainboard/lenovo/t410s/cmos.default b/src/mainboard/lenovo/t410s/cmos.default new file mode 100644 index 0000000..29eb509 --- /dev/null +++ b/src/mainboard/lenovo/t410s/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +trackpoint=Enable +fn_ctrl_swap=Disable +sticky_fn=Disable +power_management_beeps=Enable +low_battery_beep=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/t410s/cmos.layout b/src/mainboard/lenovo/t410s/cmos.layout new file mode 100644 index 0000000..cba457f --- /dev/null +++ b/src/mainboard/lenovo/t410s/cmos.layout @@ -0,0 +1,157 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2013 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode + +#422 2 r 0 unused + +# coreboot config options: northbridge +424 3 e 10 gfx_uma_size + +#427 557 r 0 unused + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M + +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/lenovo/t410s/devicetree.cb b/src/mainboard/lenovo/t410s/devicetree.cb new file mode 100644 index 0000000..19449c1 --- /dev/null +++ b/src/mainboard/lenovo/t410s/devicetree.cb @@ -0,0 +1,167 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2009 coresystems GmbH +## Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> +## +## This program is free software; you can redistribute it and/or +## modify it under the terms of the GNU General Public License as +## published by the Free Software Foundation; version 2 of +## the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, +## MA 02110-1301 USA +## + +chip northbridge/intel/nehalem + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "1" + register "gpu_panel_power_up_delay" = "50" + register "gpu_panel_power_down_delay" = "10" + register "gpu_panel_power_backlight_on_delay" = "300" + register "gpu_panel_power_backlight_off_delay" = "0" + register "gpu_cpu_backlight" = "0x58d" + register "gpu_pch_backlight" = "0x061a061a" + register "gfx.use_spread_spectrum_clock" = "1" + register "gfx.lvds_dual_channel" = "1" + register "gfx.link_frequency_270_mhz" = "1" + register "gfx.lvds_num_lanes" = "4" + + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa6" + register "config1" = "0x07" + register "config2" = "0xa0" + register "config3" = "0xe6" + + register "beepmask0" = "0xfe" + register "beepmask1" = "0x96" + register "has_power_management_beeps" = "1" + + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xf4" + register "event5_enable" = "0x3c" + register "event6_enable" = "0x87" + register "event7_enable" = "0x89" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x83" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x2d" + end + + device cpu_cluster 0 on + chip cpu/intel/model_2065x + device lapic 0 on end + end + end + + device domain 0 on + device pci 00.0 on # Host bridge + subsystemid 0x17aa 0x2193 + end + device pci 02.0 on # VGA controller + subsystemid 0x17aa 0x21c1 + end + chip southbridge/intel/ibexpeak + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "gpi1_routing" = "2" + register "gpi13_routing" = "2" + # 0:HDD Bay 1:ODD Bay 5:Docking 6:eSATA Combo Connector + register "sata_port_map" = "0x33" + + register "gpe0_en" = "0x20022046" + register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen3_dec" = "0x1c1681" + register "gen4_dec" = "0x040069" + + register "p_cnt_throttling_supported" = "1" + register "c2_latency" = "1" + register "docking_supported" = "1" + + register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }" + + device pci 16.0 off end # MEI + device pci 16.2 on # IDE/SATA + subsystemid 0x17aa 0x2161 + end + + device pci 19.0 on # Ethernet + subsystemid 0x17aa 0x2153 + end + + device pci 1a.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + + device pci 1b.0 on # Audio Controller + subsystemid 0x17aa 0x215e + end + + device pci 1c.0 on end # PCIe Port #1 (wwan) + device pci 1c.1 on end # PCIe Port #2 (wlan) + device pci 1c.2 on end # PCIe Port #3 (wusb) + device pci 1c.3 on end # PCIe Port #4 (ExpressCard) + + device pci 1d.0 on # USB2 EHCI + subsystemid 0x17aa 0x2163 + end + device pci 1f.0 on # PCI-LPC bridge + subsystemid 0x17aa 0x2166 + end + device pci 1f.2 on # IDE/SATA + subsystemid 0x17aa 0x2168 + end + device pci 1f.3 on # SMBUS + subsystemid 0x17aa 0x2167 + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end + device pci 1f.6 on # Thermal Subsystem + subsystemid 0x17aa 0x2190 + end + end + end +end diff --git a/src/mainboard/lenovo/t410s/dock.c b/src/mainboard/lenovo/t410s/dock.c new file mode 100644 index 0000000..9bc5102 --- /dev/null +++ b/src/mainboard/lenovo/t410s/dock.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pci.h> +#include <delay.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <ec/lenovo/h8/h8.h> +#include <ec/acpi/ec.h> +#include "dock.h" + +void h8_mainboard_init_dock(void) +{ + if (dock_present()) { + printk(BIOS_DEBUG, "dock is connected\n"); + dock_connect(); + } else + printk(BIOS_DEBUG, "dock is not connected\n"); +} + +void dock_connect(void) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + ec_set_bit(0x02, 0); + ec_set_bit(0x1a, 0); + ec_set_bit(0xfe, 4); + + outl(inl(gpiobase + 0x0c) | (1 << 28), gpiobase + 0x0c); +} + +void dock_disconnect(void) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + + ec_clr_bit(0x02, 0); + ec_clr_bit(0x1a, 0); + ec_clr_bit(0xfe, 4); + + outl(inl(gpiobase + 0x0c) & ~(1 << 28), gpiobase + 0x0c); +} + +int dock_present(void) +{ + u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc; + u8 st = inb(gpiobase + 0x0c); + + return ((st >> 3) & 7) != 7; +} diff --git a/src/mainboard/lenovo/t410s/dock.h b/src/mainboard/lenovo/t410s/dock.h new file mode 100644 index 0000000..f20515d --- /dev/null +++ b/src/mainboard/lenovo/t410s/dock.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef THINKPAD_T410S_DOCK_H +#define THINKPAD_T410S_DOCK_H + +extern void dock_connect(void); +extern void dock_disconnect(void); +extern int dock_present(void); +#endif diff --git a/src/mainboard/lenovo/t410s/dsdt.asl b/src/mainboard/lenovo/t410s/dsdt.asl new file mode 100644 index 0000000..6caa162 --- /dev/null +++ b/src/mainboard/lenovo/t410s/dsdt.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define EC_LENOVO_H8_ME_WORKAROUND 1 +#define HAVE_LCD_SCREEN 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x03, /* DSDT revision: ACPI v3.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20130325 /* OEM revision */ +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + + /* global NVS and variables */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + /* General Purpose Events */ + #include "acpi/gpe.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/nehalem/acpi/nehalem.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + Device (UNCR) + { + Name (_BBN, 0xFF) + Name (_ADR, 0x00) + Name (RID, 0x00) + Name (_HID, EisaId ("PNP0A03")) + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* Granularity */ + 0x00FF, /* Range Minimum */ + 0x00FF, /* Range Maximum */ + 0x0000, /* Translation Offset */ + 0x0001, /* Length */ + ,, ) + }) + Device (SAD) + { + Name (_ADR, 0x01) + Name (RID, 0x00) + OperationRegion (SADC, PCI_Config, 0x00, 0x0100) + Field (SADC, DWordAcc, NoLock, Preserve) + { + Offset (0x40), + PAM0, 8, + PAM1, 8, + PAM2, 8, + PAM3, 8, + PAM4, 8, + PAM5, 8, + PAM6, 8 + } + } + } + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/i82801gx/acpi/sleepstates.asl> + + /* Dock support code */ + #include "acpi/dock.asl" +} diff --git a/src/mainboard/lenovo/t410s/gpio.h b/src/mainboard/lenovo/t410s/gpio.h new file mode 100644 index 0000000..7d0a1cb --- /dev/null +++ b/src/mainboard/lenovo/t410s/gpio.h @@ -0,0 +1,345 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef LENOVO_T410S_GPIO_H +#define LENOVO_T410S_GPIO_H + +#include "southbridge/intel/bd82x6x/gpio.h" + +const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_GPIO, + .gpio3 = GPIO_MODE_GPIO, + .gpio4 = GPIO_MODE_GPIO, + .gpio5 = GPIO_MODE_GPIO, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_GPIO, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_GPIO, + .gpio22 = GPIO_MODE_GPIO, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_GPIO, + .gpio31 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio2 = GPIO_DIR_INPUT, + .gpio3 = GPIO_DIR_INPUT, + .gpio4 = GPIO_DIR_INPUT, + .gpio5 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio9 = GPIO_DIR_INPUT, + .gpio10 = GPIO_DIR_OUTPUT, + .gpio11 = GPIO_DIR_INPUT, + .gpio12 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio14 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio18 = GPIO_DIR_INPUT, + .gpio19 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_INPUT, + .gpio21 = GPIO_DIR_INPUT, + .gpio22 = GPIO_DIR_OUTPUT, + .gpio23 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio25 = GPIO_DIR_INPUT, + .gpio26 = GPIO_DIR_INPUT, + .gpio27 = GPIO_DIR_OUTPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio30 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio0 = GPIO_LEVEL_HIGH, + .gpio1 = GPIO_LEVEL_HIGH, + .gpio2 = GPIO_LEVEL_LOW, + .gpio3 = GPIO_LEVEL_HIGH, + .gpio4 = GPIO_LEVEL_HIGH, + .gpio5 = GPIO_LEVEL_HIGH, + .gpio6 = GPIO_LEVEL_HIGH, + .gpio7 = GPIO_LEVEL_HIGH, + .gpio8 = GPIO_LEVEL_HIGH, + .gpio9 = GPIO_LEVEL_HIGH, + .gpio10 = GPIO_LEVEL_HIGH, + .gpio11 = GPIO_LEVEL_HIGH, + .gpio12 = GPIO_LEVEL_HIGH, + .gpio13 = GPIO_LEVEL_HIGH, + .gpio14 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_HIGH, + .gpio16 = GPIO_LEVEL_HIGH, + .gpio17 = GPIO_LEVEL_HIGH, + .gpio18 = GPIO_LEVEL_HIGH, + .gpio19 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio21 = GPIO_LEVEL_HIGH, + .gpio22 = GPIO_LEVEL_LOW, + .gpio23 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_HIGH, + .gpio25 = GPIO_LEVEL_HIGH, + .gpio26 = GPIO_LEVEL_HIGH, + .gpio27 = GPIO_LEVEL_HIGH, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, + .gpio30 = GPIO_LEVEL_HIGH, + .gpio31 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio24 = GPIO_RESET_RSMRST, + .gpio30 = GPIO_RESET_RSMRST, +}; + +const struct pch_gpio_set1 pch_gpio_set1_blink = { + .gpio18 = GPIO_NO_BLINK, +}; + +const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio0 = GPIO_INVERT, + .gpio1 = GPIO_INVERT, + .gpio2 = GPIO_NO_INVERT, + .gpio3 = GPIO_NO_INVERT, + .gpio4 = GPIO_NO_INVERT, + .gpio5 = GPIO_NO_INVERT, + .gpio6 = GPIO_NO_INVERT, + .gpio7 = GPIO_NO_INVERT, + .gpio8 = GPIO_NO_INVERT, + .gpio9 = GPIO_NO_INVERT, + .gpio10 = GPIO_NO_INVERT, + .gpio11 = GPIO_NO_INVERT, + .gpio12 = GPIO_NO_INVERT, + .gpio13 = GPIO_INVERT, + .gpio14 = GPIO_NO_INVERT, + .gpio15 = GPIO_NO_INVERT, + .gpio16 = GPIO_NO_INVERT, + .gpio17 = GPIO_NO_INVERT, + .gpio18 = GPIO_NO_INVERT, + .gpio19 = GPIO_NO_INVERT, + .gpio20 = GPIO_NO_INVERT, + .gpio21 = GPIO_NO_INVERT, + .gpio22 = GPIO_NO_INVERT, + .gpio23 = GPIO_NO_INVERT, + .gpio24 = GPIO_NO_INVERT, + .gpio25 = GPIO_NO_INVERT, + .gpio26 = GPIO_NO_INVERT, + .gpio27 = GPIO_NO_INVERT, + .gpio28 = GPIO_NO_INVERT, + .gpio29 = GPIO_NO_INVERT, + .gpio30 = GPIO_NO_INVERT, + .gpio31 = GPIO_NO_INVERT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_NATIVE, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_GPIO, + .gpio37 = GPIO_MODE_GPIO, + .gpio38 = GPIO_MODE_GPIO, + .gpio39 = GPIO_MODE_GPIO, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_GPIO, + .gpio42 = GPIO_MODE_GPIO, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_NATIVE, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_GPIO, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_INPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio36 = GPIO_DIR_INPUT, + .gpio37 = GPIO_DIR_INPUT, + .gpio38 = GPIO_DIR_INPUT, + .gpio39 = GPIO_DIR_INPUT, + .gpio40 = GPIO_DIR_INPUT, + .gpio41 = GPIO_DIR_OUTPUT, + .gpio42 = GPIO_DIR_OUTPUT, + .gpio43 = GPIO_DIR_INPUT, + .gpio44 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_INPUT, + .gpio46 = GPIO_DIR_INPUT, + .gpio47 = GPIO_DIR_INPUT, + .gpio48 = GPIO_DIR_INPUT, + .gpio49 = GPIO_DIR_OUTPUT, + .gpio50 = GPIO_DIR_OUTPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_OUTPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_OUTPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio56 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_INPUT, + .gpio58 = GPIO_DIR_INPUT, + .gpio59 = GPIO_DIR_INPUT, + .gpio60 = GPIO_DIR_INPUT, + .gpio61 = GPIO_DIR_OUTPUT, + .gpio62 = GPIO_DIR_OUTPUT, + .gpio63 = GPIO_DIR_OUTPUT, +}; + +const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio34 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_HIGH, + .gpio36 = GPIO_LEVEL_HIGH, + .gpio37 = GPIO_LEVEL_LOW, + .gpio38 = GPIO_LEVEL_HIGH, + .gpio39 = GPIO_LEVEL_LOW, + .gpio40 = GPIO_LEVEL_HIGH, + .gpio41 = GPIO_LEVEL_HIGH, + .gpio42 = GPIO_LEVEL_HIGH, + .gpio43 = GPIO_LEVEL_HIGH, + .gpio44 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio46 = GPIO_LEVEL_HIGH, + .gpio47 = GPIO_LEVEL_HIGH, + .gpio48 = GPIO_LEVEL_LOW, + .gpio49 = GPIO_LEVEL_LOW, + .gpio50 = GPIO_LEVEL_LOW, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio52 = GPIO_LEVEL_LOW, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio54 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, + .gpio56 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_LOW, + .gpio58 = GPIO_LEVEL_HIGH, + .gpio59 = GPIO_LEVEL_HIGH, + .gpio60 = GPIO_LEVEL_HIGH, + .gpio61 = GPIO_LEVEL_HIGH, + .gpio62 = GPIO_LEVEL_HIGH, + .gpio63 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_NATIVE, + .gpio69 = GPIO_MODE_NATIVE, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_NATIVE, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio64 = GPIO_DIR_OUTPUT, + .gpio65 = GPIO_DIR_OUTPUT, + .gpio66 = GPIO_DIR_OUTPUT, + .gpio67 = GPIO_DIR_OUTPUT, + .gpio68 = GPIO_DIR_OUTPUT, + .gpio69 = GPIO_DIR_OUTPUT, + .gpio70 = GPIO_DIR_OUTPUT, + .gpio71 = GPIO_DIR_OUTPUT, + .gpio72 = GPIO_DIR_INPUT, + .gpio73 = GPIO_DIR_INPUT, + .gpio74 = GPIO_DIR_INPUT, + .gpio75 = GPIO_DIR_INPUT, +}; + +const struct pch_gpio_set3 pch_gpio_set3_level = { + .gpio64 = GPIO_LEVEL_HIGH, + .gpio65 = GPIO_LEVEL_HIGH, + .gpio66 = GPIO_LEVEL_HIGH, + .gpio67 = GPIO_LEVEL_HIGH, + .gpio68 = GPIO_LEVEL_LOW, + .gpio69 = GPIO_LEVEL_LOW, + .gpio70 = GPIO_LEVEL_LOW, + .gpio71 = GPIO_LEVEL_LOW, + .gpio72 = GPIO_LEVEL_HIGH, + .gpio73 = GPIO_LEVEL_HIGH, + .gpio74 = GPIO_LEVEL_HIGH, + .gpio75 = GPIO_LEVEL_HIGH, +}; + +const struct pch_gpio_map t410s_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .reset = &pch_gpio_set1_reset, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + }, +}; + +#endif diff --git a/src/mainboard/lenovo/t410s/hda_verb.c b/src/mainboard/lenovo/t410s/hda_verb.c new file mode 100644 index 0000000..8a308a5 --- /dev/null +++ b/src/mainboard/lenovo/t410s/hda_verb.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License, + * or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x14F15069, /* Codec Vendor / Device ID: Conexant CX20585 */ + 0x17AA21A4, /* Subsystem ID */ + 0x0000000B, /* Number of 4 dword sets */ + + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x17AA21A4), + + /* NID 0x19: Headphone jack. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x042110F0), + + /* NID 0x1A: Dock mic jack. */ + AZALIA_PIN_CFG(0x0, 0x1A, 0x61A190F0), + + /* NID 0x1B: Mic jack. */ + AZALIA_PIN_CFG(0x0, 0x1B, 0x04A110F0), + + /* NID 0x1C: Dock headphone jack. */ + AZALIA_PIN_CFG(0x0, 0x1C, 0x612140F0), + + /* NID 0x1D: EAPD detect. */ + AZALIA_PIN_CFG(0x0, 0x1D, 0x40F001F0), + + /* NID 0x1E */ + AZALIA_PIN_CFG(0x0, 0x1E, 0x40F001F0), + + /* NID 0x1F */ + AZALIA_PIN_CFG(0x0, 0x1F, 0x901701F0), + + /* NID 0x20 */ + AZALIA_PIN_CFG(0x0, 0x20, 0x40F001F0), + + /* NID 0x22 */ + AZALIA_PIN_CFG(0x0, 0x22, 0x40F001F0), + + /* NID 0x23: Internal mic boost volume. */ + AZALIA_PIN_CFG(0x0, 0x23, 0x90A601F0), + + 0x80862804, /* Codec Vendor / Device ID: Intel Ibexpeak HDMI. */ + 0x17aa21b5, /* Subsystem ID */ + 0x00000004, /* Number of 4 dword sets */ + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x17aa21b5 */ + AZALIA_SUBVENDOR(0x3, 0x17AA21B5), + + /* NID 0x04. */ + AZALIA_PIN_CFG(0x3, 0x04, 0x18560010), + + /* NID 0x05. */ + AZALIA_PIN_CFG(0x3, 0x05, 0x18560020), + + /* NID 0x06. */ + AZALIA_PIN_CFG(0x3, 0x06, 0x18560030), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/t410s/mainboard.c b/src/mainboard/lenovo/t410s/mainboard.c new file mode 100644 index 0000000..e30f796 --- /dev/null +++ b/src/mainboard/lenovo/t410s/mainboard.c @@ -0,0 +1,146 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <delay.h> +#include <string.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <ec/lenovo/pmh7/pmh7.h> +#include <ec/acpi/ec.h> +#include <ec/lenovo/h8/h8.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <southbridge/intel/bd82x6x/pch.h> + +#include <pc80/mc146818rtc.h> +#include <arch/x86/include/arch/acpigen.h> +#include <drivers/intel/gma/int15.h> +#include <arch/interrupt.h> +#include <pc80/keyboard.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <smbios.h> +#include <version.h> +#include <drivers/lenovo/lenovo.h> +#include "dock.h" + +static acpi_cstate_t cst_entries[] = { + {1, 1, 1000, {0x7f, 1, 2, {0}, 1, 0}}, + {2, 1, 500, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV2, 0}}, + {2, 17, 250, {0x01, 8, 0, {0}, DEFAULT_PMBASE + LV3, 0}}, +}; + +int get_cst_entries(acpi_cstate_t **entries) +{ + *entries = cst_entries; + return ARRAY_SIZE(cst_entries); +} + +const char *smbios_mainboard_bios_version(void) +{ + static char *s = NULL; + + /* Satisfy thinkpad_acpi. */ + if (strlen(CONFIG_LOCALVERSION)) + return "CBET4000 " CONFIG_LOCALVERSION; + + if (s != NULL) + return s; + s = strconcat("CBET4000 ", coreboot_version); + return s; +} + +static void mainboard_init(device_t dev) +{ + printk(BIOS_SPEW, "starting SPI configuration\n"); + + /* Configure SPI. */ + RCBA32(0x3800) = 0x07ff0500; + RCBA32(0x3804) = 0x3f046008; + RCBA32(0x3808) = 0x0058efc0; + RCBA32(0x384c) = 0x92000000; + RCBA32(0x3850) = 0x00000a0b; + RCBA32(0x3858) = 0x07ff0500; + RCBA32(0x385c) = 0x04ff0003; + RCBA32(0x3860) = 0x00020001; + RCBA32(0x3864) = 0x00000fff; + RCBA32(0x3874) = 0; + RCBA32(0x3890) = 0xf8400000; + RCBA32(0x3894) = 0x143b5006; + RCBA32(0x3898) = 0x05200302; + RCBA32(0x389c) = 0x0601209f; + RCBA32(0x38b0) = 0x00000004; + RCBA32(0x38b4) = 0x03040002; + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + RCBA32(0x3804) = 0x3f04e008; + + printk(BIOS_SPEW, "SPI configured\n"); + /* This sneaked in here, because X201 SuperIO chip isn't really + connected to anything and hence we don't init it. + */ + pc_keyboard_init(); +} + +static void fill_ssdt(void) +{ +} + +static void mainboard_enable(device_t dev) +{ + device_t dev0; + u16 pmbase; + + dev->ops->init = mainboard_init; + dev->ops->acpi_fill_ssdt_generator = fill_ssdt; + + pmbase = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), + PMBASE) & 0xff80; + + printk(BIOS_SPEW, " ... pmbase = 0x%04x\n", pmbase); + + outl(0, pmbase + SMI_EN); + + enable_lapic(); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_BASE, + DEFAULT_GPIOBASE | 1); + pci_write_config8(dev_find_slot(0, PCI_DEVFN(0x1f, 0)), GPIO_CNTL, + 0x10); + + /* If we're resuming from suspend, blink suspend LED */ + dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + ec_write(0x0c, 0xc7); + + install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t410s/romstage.c b/src/mainboard/lenovo/t410s/romstage.c new file mode 100644 index 0000000..0bb46bc --- /dev/null +++ b/src/mainboard/lenovo/t410s/romstage.c @@ -0,0 +1,314 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (C) 2013 Vladimir Serbinenko <phcoder(a)gmail.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ + +#include <stdint.h> +#include <string.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <lib.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/x86/bist.h> +#include <ec/acpi/ec.h> +#include <delay.h> +#include <timestamp.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include <arch/early_variables.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <northbridge/intel/nehalem/nehalem.h> +#include <northbridge/intel/nehalem/raminit.h> +#include <southbridge/intel/ibexpeak/me.h> +#include <cpu/intel/romstage.h> +#include "gpio.h" +#include "dock.h" + +static void pch_enable_lpc(void) +{ + /* X201 EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN | GAMEL_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); + pci_write_config32(PCH_LPC_DEV, 0xdc, 0x8); + + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); + + pci_write_config32(PCH_LPC_DEV, ETR3, + pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); +} + +static void rcba_config(void) +{ + southbridge_configure_default_intmap(); + + static const u32 rcba_dump3[] = { + /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, + /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, + /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, + /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, + /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, + /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, + /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, + /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, + /* 3410 */ 0x00000c61, 0x00000000, 0x16f41fe1, 0xbf4f001f, + /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, + /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, + /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, + /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, + /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, + /* 3530 */ 0x2000055f, 0x2000055f, 0x00000000, 0x00000000, + /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, + /* 3570 */ 0x02000772, 0x17000f87, 0x1800ff4f, 0x0001d630, + /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, + /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, + /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, + /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 36d0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, + /* 36e0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, + /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + /* 3710 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, + }; + unsigned i; + for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { + RCBA32(4 * i + 0x3310) = rcba_dump3[i]; + (void)RCBA32(4 * i + 0x3310); + } +} + +static inline void write_acpi32(u32 addr, u32 val) +{ + outl(val, DEFAULT_PMBASE | addr); +} + +static inline void write_acpi16(u32 addr, u16 val) +{ + outw(val, DEFAULT_PMBASE | addr); +} + +static inline u32 read_acpi32(u32 addr) +{ + return inl(DEFAULT_PMBASE | addr); +} + +static inline u16 read_acpi16(u32 addr) +{ + return inw(DEFAULT_PMBASE | addr); +} + +static void set_fsb_frequency(void) +{ + u8 block[5]; + u16 fsbfreq = 62879; + smbus_block_read(0x69, 0, 5, block); + block[0] = fsbfreq; + block[1] = fsbfreq >> 8; + + smbus_block_write(0x69, 0, 5, block); +} + +void main(unsigned long bist) +{ + u32 reg32; + int s3resume = 0; + const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; + + timestamp_init(rdtsc()); + + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + nehalem_early_initialization(NEHALEM_MOBILE); + + pch_enable_lpc(); + + /* Enable USB Power. We need to do it early for usbdebug to work. */ + ec_set_bit(0x3b, 4); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + setup_pch_gpios(&t410s_gpio_map); + + + /* This should probably go away. Until now it is required + * and mainboard specific + */ + rcba_config(); + + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Read PM1_CNT */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); + if (((reg32 >> 10) & 7) == 5) { + u8 reg8; + reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + printk(BIOS_DEBUG, "a2: %02x\n", reg8); + if (!(reg8 & 0x20)) { + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); + } else { + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + } else { + printk(BIOS_DEBUG, + "Resume from S3 detected, but disabled.\n"); + } + } + } + + /* Enable SMBUS. */ + enable_smbus(); + + outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, + DEFAULT_GPIOBASE | 0x3a); + outb(0x50, 0x15ec); + outb(inb(0x15ee) & 0x70, 0x15ee); + + write_acpi16(0x2, 0x0); + write_acpi32(0x28, 0x0); + write_acpi32(0x2c, 0x0); + if (!s3resume) { + read_acpi32(0x4); + read_acpi32(0x20); + read_acpi32(0x34); + write_acpi16(0x0, 0x900); + write_acpi32(0x20, 0xffff7ffe); + write_acpi32(0x34, 0x56974); + pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, + pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); + } + + early_thermal_init(); + + timestamp_add_now(TS_BEFORE_INITRAM); + + chipset_init(s3resume); + + set_fsb_frequency(); + + raminit(s3resume, spd_addrmap); + + timestamp_add_now(TS_AFTER_INITRAM); + + intel_early_me_status(); + + if (s3resume) { + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + reg32 = inl(DEFAULT_PMBASE + 0x04); + outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + if (s3resume) { + void *resume_backup_memory; + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + if (resume_backup_memory) + memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, + HIGH_MEMORY_SAVE); + + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + quick_ram_check(); + } +#endif + + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/mainboard/lenovo/t410s/smi.h b/src/mainboard/lenovo/t410s/smi.h new file mode 100644 index 0000000..d63780a --- /dev/null +++ b/src/mainboard/lenovo/t410s/smi.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef MAINBOARD_LENOVO_T410S_SMI_H +#define MAINBOARD_LENOVO_T410S_SMI_H + +#define SMI_DOCK_CONNECT 0x01 +#define SMI_DOCK_DISCONNECT 0x02 + +#endif diff --git a/src/mainboard/lenovo/t410s/smihandler.c b/src/mainboard/lenovo/t410s/smihandler.c new file mode 100644 index 0000000..85de208 --- /dev/null +++ b/src/mainboard/lenovo/t410s/smihandler.c @@ -0,0 +1,222 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/ibexpeak/nvs.h> +#include <southbridge/intel/ibexpeak/pch.h> +#include <southbridge/intel/ibexpeak/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_2065x/model_2065x.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include "dock.h" +#include "smi.h" + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + switch (smif) { + case SMI_DOCK_CONNECT: + ec_clr_bit(0x03, 2); + udelay(250000); + dock_connect(); + ec_set_bit(0x03, 2); + /* set dock LED to indicate status */ + ec_write(0x0c, 0x09); + ec_write(0x0c, 0x88); + break; + + case SMI_DOCK_DISCONNECT: + ec_clr_bit(0x03, 2); + dock_disconnect(); + break; + + default: + return 0; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 1; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + case 0x18: + /* Fn-F9 key */ + case 0x27: + /* Power loss */ + case 0x50: + /* Undock Key */ + mainboard_io_trap_handler(SMI_DOCK_DISCONNECT); + break; + case 0x37: + case 0x58: + /* Dock Event */ + mainboard_io_trap_handler(SMI_DOCK_CONNECT); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 1)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_2065x_finalize_smm(); + + mainboard_finalized = 1; + break; + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + default: + break; + } + return 0; +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + if (slp_typ == 3) { + u8 ec_wake = ec_read(0x32); + /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ + if (ec_wake & 0x14) { + u32 gpe_rout; + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + + /* Enable EC WAKE GPE. */ + outl(inl(pmbase + GPE0_EN) | (1 << 29), pmbase + GPE0_EN); + gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT); + /* Redirect EC WAKE GPE to SCI. */ + gpe_rout &= ~(3 << 26); + gpe_rout |= (2 << 26); + pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout); + } + } +}

1 0

New patch to review for coreboot: be00b0c [NOTFORMERGE] google/storm DYNAMIC_CBMEM
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8034 -gerrit commit be00b0c1e88d10980e152dba2531a71509fcf2ba Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jan 1 14:36:29 2015 +0200 [NOTFORMERGE] google/storm DYNAMIC_CBMEM Change-Id: I7e13093a038164185a1ab5909e2395e9844e8d50 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/storm/Kconfig | 2 +- src/mainboard/google/storm/romstage.c | 3 +++ src/soc/qualcomm/ipq806x/Kconfig | 5 +++++ src/soc/qualcomm/ipq806x/Makefile.inc | 2 ++ src/soc/qualcomm/ipq806x/cbmem.c | 25 +++++++++++++++++++++++++ 5 files changed, 36 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index a2bf740..1eb8c7e 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -35,6 +35,6 @@ config MAINBOARD_PART_NUMBER config DRAM_SIZE_MB int - default 2048 + default 512 endif # BOARD_GOOGLE_STORM diff --git a/src/mainboard/google/storm/romstage.c b/src/mainboard/google/storm/romstage.c index cf78e44..10632d8 100644 --- a/src/mainboard/google/storm/romstage.c +++ b/src/mainboard/google/storm/romstage.c @@ -19,12 +19,15 @@ #include <arch/stages.h> #include <cbfs.h> +#include <cbmem.h> #include <console/console.h> void main(void) { void *entry; + cbmem_initialize_empty(); + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); stage_exit(entry); } diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 09e1c1e..2e21168 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -6,6 +6,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select ARM_LPAE select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING @@ -41,6 +42,10 @@ config BOOTBLOCK_BASE hex "256K bytes left for TZBSP" default 0x40600000 +config SYS_SDRAM_BASE + hex + default 0x40000000 + config STACK_TOP hex default 0x40600000 diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 639b9d9..8212106 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -29,8 +29,10 @@ romstage-y += clock.c romstage-y += gpio.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c +romstage-$(CONFIG_DYNAMIC_CBMEM) += cbmem.c ramstage-y += cbfs.c +ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-y += timer.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c new file mode 100644 index 0000000..b175d6a --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20)); +}

1 0

Patch set updated for coreboot: a30c40d CBMEM: Always use DYNAMIC_CBMEM
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7851 -gerrit commit a30c40d1f87c55e0e749024326e54db199c67287 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 28 11:24:19 2014 +0200 CBMEM: Always use DYNAMIC_CBMEM Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 10 +- src/arch/x86/boot/cbmem.c | 21 -- src/arch/x86/boot/tables.c | 9 +- src/cpu/allwinner/a10/Kconfig | 1 - src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/haswell/romstage.c | 5 +- src/cpu/ti/am335x/Kconfig | 1 - src/include/cbmem.h | 31 --- src/include/rmodule.h | 2 - src/lib/Makefile.inc | 13 +- src/lib/cbmem.c | 288 ---------------------- src/lib/rmodule.c | 8 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 - src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 - src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 4 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 2 - src/soc/nvidia/tegra124/Kconfig | 1 - src/soc/samsung/exynos5250/Kconfig | 1 - src/soc/samsung/exynos5420/Kconfig | 1 - src/soc/ucb/riscv/Kconfig | 1 - 30 files changed, 7 insertions(+), 408 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 73cd803..fd9ceca 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,14 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config DYNAMIC_CBMEM - bool - default n - help - Instead of reserving a static amount of CBMEM space the CBMEM - area grows dynamically. CBMEM can be used both in romstage (after - memory initialization) and ramstage. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -200,7 +192,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) + depends on (RELOCATABLE_MODULES && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 7d7ec3d..82bbe3f 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -26,21 +26,6 @@ #include <console/cbmem_console.h> #include <timestamp.h> -#if !CONFIG_DYNAMIC_CBMEM -void get_cbmem_table(uint64_t *base, uint64_t *size) -{ - uint64_t top_of_ram = get_top_of_ram(); - - if (top_of_ram >= HIGH_MEMORY_SIZE) { - *base = top_of_ram - HIGH_MEMORY_SIZE; - *size = HIGH_MEMORY_SIZE; - } else { - *base = 0; - *size = 0; - } -} -#endif /* !DYNAMIC_CBMEM */ - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -52,11 +37,7 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); -#if !CONFIG_DYNAMIC_CBMEM - cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); -#else cbmem_set_top((void*)(uintptr_t)ramtop); -#endif } #endif /* !__PRE_RAM__ */ @@ -66,13 +47,11 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) return 0; } -#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } -#endif #endif /* LATE_CBMEM_INIT */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index c2265ea..712f66f 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -101,11 +101,8 @@ void write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_HAVE_ACPI_TABLES -#if CONFIG_DYNAMIC_CBMEM #define MAX_ACPI_SIZE (144 * 1024) -#else -#define MAX_ACPI_SIZE (45 * 1024) -#endif + post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ @@ -199,11 +196,7 @@ void write_tables(void) /* FIXME: The high_table_base parameter is not reference when tables are high, * or high_table_pointer >1 MB. */ -#if CONFIG_DYNAMIC_CBMEM u64 fixme_high_tables_base = 0; -#else - u64 fixme_high_tables_base = (u32)get_cbmem_toc(); -#endif /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index b7b435f..2bf32ec 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM # The "eGON.BT0" header takes 32 bytes config BOOTBLOCK_BASE diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 9b0edfc..e9cbe43 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 2f891ad..5cd4c65 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 0597363..37ae5b3 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SMM_MODULES select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE - select DYNAMIC_CBMEM select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1af5259..50150cf 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -75,14 +75,11 @@ static inline u32 *stack_push(u32 *stack, u32 value) static unsigned long choose_top_of_stack(void) { unsigned long stack_top; -#if CONFIG_DYNAMIC_CBMEM + /* cbmem_add() does a find() before add(). */ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; -#else - stack_top = CONFIG_RAMTOP; -#endif return stack_top; } diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index eb60ad1..fae527d 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,7 +6,6 @@ config CPU_TI_AM335X select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM bool default n diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b1f3b5e..ea81fd0 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -118,8 +118,6 @@ struct cbmem_id_to_name { struct cbmem_entry; -#if CONFIG_DYNAMIC_CBMEM - /* * The dynamic cbmem infrastructure allows for growing cbmem dynamically as * things are added. It requires an external function, cbmem_top(), to be @@ -171,35 +169,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#else /* !CONFIG_DYNAMIC_CBMEM */ - -/* Allocation with static CBMEM is resolved at build time. We start - * with 128kB and conditionally add some of the most greedy CBMEM - * table entries. - */ -#define _CBMEM_SZ_MINIMAL ( 128 * 1024 ) - -#define _CBMEM_SZ_TOTAL \ - (_CBMEM_SZ_MINIMAL + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE + \ - HIGH_MEMORY_SAVE + HIGH_MEMORY_SCRATCH) - -#define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - -#ifndef __PRE_RAM__ -void cbmem_late_set_table(uint64_t base, uint64_t size); -#endif - -void get_cbmem_table(uint64_t *base, uint64_t *size); -struct cbmem_entry *get_cbmem_toc(void); - -static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) -{ - return NULL; -} -#endif /* CONFIG_DYNAMIC_CBMEM */ - -/* Common API between cbmem and dynamic cbmem. */ - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/include/rmodule.h b/src/include/rmodule.h index d229cf8..76b855a 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -54,7 +54,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, /* Support for loading rmodule stages. This API is only available when * using dynamic cbmem because it uses the dynamic cbmem API to obtain * the backing store region for the stage. */ -#if CONFIG_DYNAMIC_CBMEM struct cbfs_stage; struct cbmem_entry; @@ -70,7 +69,6 @@ struct rmod_stage_load { /* Both of the following functions return 0 on success, -1 on error. */ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage); int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl); -#endif struct rmodule { void *location; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e35116b..c3658d2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -74,17 +74,8 @@ ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -# The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. -ifeq ($(CONFIG_DYNAMIC_CBMEM),y) -ramstage-y += dynamic_cbmem.c -romstage-y += dynamic_cbmem.c -else -ramstage-y += cbmem.c -romstage-y += cbmem.c -endif # CONFIG_DYNAMIC_CBMEM - -romstage-y += cbmem_common.c -ramstage-y += cbmem_common.c +romstage-y += cbmem_common.c dynamic_cbmem.c +ramstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += hexdump.c romstage-y += hexdump.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c deleted file mode 100644 index 5ea8d88..0000000 --- a/src/lib/cbmem.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <bootmem.h> -#include <bootstate.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -#include <arch/acpi.h> -#endif - -// The CBMEM TOC reserves 512 bytes to keep -// the other entries somewhat aligned. -// Increase if MAX_CBMEM_ENTRIES exceeds 21 -#define CBMEM_TOC_RESERVED 512 -#define MAX_CBMEM_ENTRIES 16 -#define CBMEM_MAGIC 0x434f5245 - -struct cbmem_entry { - u32 magic; - u32 id; - u64 base; - u64 size; -} __attribute__((packed)); - -#ifndef __PRE_RAM__ -static uint64_t cbmem_base = 0; -static uint64_t cbmem_size = 0; -#endif - -static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) -{ - if (base && size && s) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", - base, base + size - 1, s); - } -} - -static void cbmem_locate_table(uint64_t *base, uint64_t *size) -{ -#ifdef __PRE_RAM__ - get_cbmem_table(base, size); -#else - if (!(cbmem_base && cbmem_size)) { - get_cbmem_table(&cbmem_base, &cbmem_size); - cbmem_trace_location(cbmem_base, cbmem_size, __FUNCTION__); - } - *base = cbmem_base; - *size = cbmem_size; -#endif -} - -struct cbmem_entry *get_cbmem_toc(void) -{ - uint64_t base, size; - cbmem_locate_table(&base, &size); - return (struct cbmem_entry *)(unsigned long)base; -} - -#if !defined(__PRE_RAM__) -void cbmem_late_set_table(uint64_t base, uint64_t size) -{ - cbmem_trace_location(base, size, __FUNCTION__); - cbmem_base = base; - cbmem_size = size; -} -#endif - -/** - * cbmem is a simple mechanism to do some kind of book keeping of the coreboot - * high tables memory. This is a small amount of memory which is "stolen" from - * the system memory for coreboot purposes. Usually this memory is used for - * - the coreboot table - * - legacy tables (PIRQ, MP table) - * - ACPI tables - * - suspend/resume backup memory - */ - -static void cbmem_initialize_empty(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - if (!(baseaddr && size)) { - printk(BIOS_CRIT, "Unable to set location for CBMEM.\n"); - return; - } - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); - - cbmem_toc[0] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = CBMEM_ID_FREESPACE, - .base = baseaddr + CBMEM_TOC_RESERVED, - .size = size - CBMEM_TOC_RESERVED - }; -} - -static int cbmem_check_toc(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - - return (cbmem_toc[0].magic == CBMEM_MAGIC); -} - -void *cbmem_add(u32 id, u64 size) -{ - struct cbmem_entry *cbmem_toc; - int i; - void *p; - - /* - * This could be a restart, check if the section is there already. It - * is remotely possible that the dram contents persisted over the - * bootloader upgrade AND the same section now needs more room, but - * this is quite a remote possibility and it is ignored here. - */ - p = cbmem_find(id); - if (p) { - printk(BIOS_NOTICE, - "CBMEM section %x: using existing location at %p.\n", - id, p); - return p; - } - - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) { - return NULL; - } - - if (cbmem_toc[0].magic != CBMEM_MAGIC) { - printk(BIOS_ERR, "ERROR: CBMEM was not initialized yet.\n"); - return NULL; - } - - /* Will the entry fit at all? */ - if (size > cbmem_toc[0].size) { - printk(BIOS_ERR, "ERROR: Not enough memory for table %x\n", id); - return NULL; - } - - /* Align size to 512 byte blocks */ - - size = ALIGN(size, 512) < cbmem_toc[0].size ? - ALIGN(size, 512) : cbmem_toc[0].size; - - /* Now look for the first free/usable TOC entry */ - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == CBMEM_ID_NONE) - break; - } - - if (i >= MAX_CBMEM_ENTRIES) { - printk(BIOS_ERR, "ERROR: No more CBMEM entries available.\n"); - return NULL; - } - - printk(BIOS_DEBUG, "Adding CBMEM entry as no. %d\n", i); - - cbmem_toc[i] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = id, - .base = cbmem_toc[0].base, - .size = size - }; - - cbmem_toc[0].base += size; - cbmem_toc[0].size -= size; - - return (void *)(uintptr_t)cbmem_toc[i].base; -} - -void *cbmem_find(u32 id) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return NULL; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == id) - return (void *)(unsigned long)cbmem_toc[i].base; - } - - return (void *)NULL; -} - -/* Returns True if it was not initialized before. */ -int cbmem_recovery(int is_wakeup) -{ - int found = cbmem_check_toc(); - int wipe = 0; - - /* CBMEM TOC is wiped clean when we are not waking up from S3 - * suspend. Boards with EARLY_CBMEM_INIT do this in romstage, - * boards without EARLY_CBMEM_INIT do this in ramstage. - */ -#if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif -#if !defined(__PRE_RAM__) && !CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif - - if (!is_wakeup && wipe) - cbmem_initialize_empty(); - - if (is_wakeup && !found) { - cbmem_initialize_empty(); - cbmem_fail_resume(); - } - - /* Complete migration to CBMEM. */ - cbmem_arch_init(); - - return !found; -} - -#ifndef __PRE_RAM__ -static void init_cbmem_post_device(void *unused) -{ -#if CONFIG_HAVE_ACPI_RESUME - cbmem_recovery(acpi_is_wakeup()); -#else - cbmem_recovery(0); -#endif -} - -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; - -void cbmem_add_bootmem(void) -{ - bootmem_add_range(cbmem_base, cbmem_size, LB_MEM_TABLE); -} - -void cbmem_list(void) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - - if (cbmem_toc[i].magic != CBMEM_MAGIC) - continue; - cbmem_print_entry(i, cbmem_toc[i].id, cbmem_toc[i].base, - cbmem_toc[i].size); - } -} -#endif diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 908297b..5c6df02 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <assert.h> +#include <cbmem.h> +#include <cbfs_core.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -249,10 +251,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, return region_alignment - sizeof(struct rmodule_header); } -#if CONFIG_DYNAMIC_CBMEM -#include <cbmem.h> -#include <cbfs_core.h> - int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) { struct rmodule rmod_stage; @@ -307,5 +305,3 @@ int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl) return rmodule_stage_load(rsl, stage); } - -#endif /* DYNAMIC_CBMEM */ diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 7e24a20..b275e88 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARM_ROMSTAGE_ARMV7 select ARM_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 - select DYNAMIC_CBMEM config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index b002c21..406612e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 4931523..08d563f 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -130,10 +130,6 @@ static void cpu_pci_domain_read_resources(struct device *dev) "debugcon"); } -#if !CONFIG_DYNAMIC_CBMEM - set_top_of_ram(tomk * 1024); -#endif - if (q35 && ((tomk * 1024) < 0xb0000000)) { /* * Reserve the region between top-of-ram and the diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3949937..fcc750c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index fa08acc..a804fd3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select DYNAMIC_CBMEM select INTEL_INT15 select VGA select INTEL_EDID diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fac7329..096c80f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_DEBUG_RAM_SETUP select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select IOMMU select VGA select INTEL_EDID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c578011..8a0cb5b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index b49f331..ca5ffa5 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select CPU_INTEL_MODEL_2065X select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 647b4fb..11370f5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select PER_DEVICE_ACPI_TABLES @@ -31,7 +30,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES @@ -41,7 +39,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select PER_DEVICE_ACPI_TABLES @@ -50,7 +47,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bcaa1ff..28dc7d7 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b93216e..2c5ebd3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b61fac3..081ea09 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,8 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select DYNAMIC_CBMEM - select BROKEN_CAR_MIGRATE select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 195261e..89d07c5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM select ARM_LPAE diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 8d7c867..9cbd37f 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -5,7 +5,6 @@ config CPU_SAMSUNG_EXYNOS5250 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 904091e..c9f2ec6 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -6,7 +6,6 @@ config CPU_SAMSUNG_EXYNOS5420 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select RELOCATABLE_MODULES - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index be4a675..d1e4ba7 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -3,7 +3,6 @@ config SOC_UCB_RISCV select ARCH_BOOTBLOCK_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select DYNAMIC_CBMEM bool default n

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Patch set updated for coreboot: 72c9b7d CBMEM: Tag chipsets with LATE_CBMEM_INIT
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7850 -gerrit commit 72c9b7df96c65265c29d9209941b5932a81e1f3c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 18 22:22:04 2014 +0200 CBMEM: Tag chipsets with LATE_CBMEM_INIT In preparation to remove the static CBMEM allocator, tag the chipsets that still do not implement get_top_of_ram() for romstage. LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE. Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 15 ++++++++------- src/arch/x86/boot/cbmem.c | 2 +- src/northbridge/amd/agesa/Kconfig | 1 + src/northbridge/amd/amdfam10/Kconfig | 1 + src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/amd/gx2/Kconfig | 1 + src/northbridge/amd/lx/Kconfig | 1 + src/northbridge/amd/pi/Kconfig | 1 + src/northbridge/dmp/vortex86ex/Kconfig | 1 + src/northbridge/intel/e7501/Kconfig | 1 + src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i440bx/Kconfig | 1 + src/northbridge/intel/i440lx/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 + src/northbridge/intel/i82810/Kconfig | 1 + src/northbridge/intel/i82830/Kconfig | 1 + src/northbridge/intel/i855/Kconfig | 1 + src/northbridge/intel/sch/Kconfig | 1 + src/northbridge/rdc/r8610/Kconfig | 1 + src/northbridge/via/cn700/Kconfig | 1 + src/northbridge/via/cx700/Kconfig | 1 + src/northbridge/via/vx800/Kconfig | 1 + src/northbridge/via/vx900/Kconfig | 1 + 24 files changed, 31 insertions(+), 8 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 30961a4..c9a04a4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -157,16 +157,17 @@ config INCLUDE_CONFIG_FILE (empty) 0x8e480 null 3610440 config EARLY_CBMEM_INIT - bool - default n + def_bool !LATE_CBMEM_INIT + +config LATE_CBMEM_INIT + def_bool n help - Make coreboot initialize the CBMEM structures while running in ROM - stage. This is useful when the ROM stage wants to communicate - some, for instance, execution timestamps. It needs support in - romstage.c and should be enabled by the board's Kconfig. + Enable this in chipset's Kconfig if northbridge does not implement + early get_top_of_ram() call for romstage. CBMEM tables will be + allocated late in ramstage, after PCI devices resources are known. config BROKEN_CAR_MIGRATE - def_bool !EARLY_CBMEM_INIT + def_bool LATE_CBMEM_INIT help Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and manage CAR migration on S3 resume path only. Couple boards use diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 84fdc97..79cf46c 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -56,7 +56,7 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if CONFIG_BROKEN_CAR_MIGRATE || !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); diff --git a/src/northbridge/amd/agesa/Kconfig b/src/northbridge/amd/agesa/Kconfig index 68551fb..8fd8bfd 100644 --- a/src/northbridge/amd/agesa/Kconfig +++ b/src/northbridge/amd/agesa/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_AGESA bool default CPU_AMD_AGESA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AGESA diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 0789ac3..13b912e 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HYPERTRANSPORT_PLUGIN_SUPPORT select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDFAM10 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index 8bee5ca..65dc173 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -24,6 +24,7 @@ config NORTHBRIDGE_AMD_AMDK8 select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_AMDK8 config AGP_APERTURE_SIZE diff --git a/src/northbridge/amd/gx2/Kconfig b/src/northbridge/amd/gx2/Kconfig index dc347c4..1fe33f8 100644 --- a/src/northbridge/amd/gx2/Kconfig +++ b/src/northbridge/amd/gx2/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_GX2 bool select GEODE_VSA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_GX2 diff --git a/src/northbridge/amd/lx/Kconfig b/src/northbridge/amd/lx/Kconfig index d74d715..abc3e4c 100644 --- a/src/northbridge/amd/lx/Kconfig +++ b/src/northbridge/amd/lx/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_AMD_LX bool select GEODE_VSA + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_LX diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index 8af4872..2b8e356 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_AMD_PI bool default CPU_AMD_PI + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI diff --git a/src/northbridge/dmp/vortex86ex/Kconfig b/src/northbridge/dmp/vortex86ex/Kconfig index 7bf5235..74239ad 100644 --- a/src/northbridge/dmp/vortex86ex/Kconfig +++ b/src/northbridge/dmp/vortex86ex/Kconfig @@ -19,3 +19,4 @@ config NORTHBRIDGE_DMP_VORTEX86EX bool + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/e7501/Kconfig b/src/northbridge/intel/e7501/Kconfig index 88c0b45..763b96e 100644 --- a/src/northbridge/intel/e7501/Kconfig +++ b/src/northbridge/intel/e7501/Kconfig @@ -2,4 +2,5 @@ config NORTHBRIDGE_INTEL_E7501 bool select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index ff7f5a5..e755852 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT config HW_SCRUBBER bool diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 079004b..cb0bd38 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_I3100 config DIMM_MAP_LOGICAL diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 902eb73..c5cc43e 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_I440BX bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT config SDRAMPWR_4DIMM bool diff --git a/src/northbridge/intel/i440lx/Kconfig b/src/northbridge/intel/i440lx/Kconfig index a88a7a1..1ccaac6 100644 --- a/src/northbridge/intel/i440lx/Kconfig +++ b/src/northbridge/intel/i440lx/Kconfig @@ -20,4 +20,5 @@ config NORTHBRIDGE_INTEL_I440LX bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index f7344ca..3bd685a 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -22,6 +22,7 @@ config NORTHBRIDGE_INTEL_I5000 select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_I5000 diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 79fe36a..723f751 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -20,6 +20,7 @@ config NORTHBRIDGE_INTEL_I82810 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 20b31a2..662840f 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I82830 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index f5c2890..44becf6 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_INTEL_I855 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT choice prompt "Onboard graphics" diff --git a/src/northbridge/intel/sch/Kconfig b/src/northbridge/intel/sch/Kconfig index b8dad72..f495e6a 100644 --- a/src/northbridge/intel/sch/Kconfig +++ b/src/northbridge/intel/sch/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_SCH bool select MMCONF_SUPPORT select PER_DEVICE_ACPI_TABLES + select LATE_CBMEM_INIT if NORTHBRIDGE_INTEL_SCH diff --git a/src/northbridge/rdc/r8610/Kconfig b/src/northbridge/rdc/r8610/Kconfig index 85461b7..e93a3e6 100644 --- a/src/northbridge/rdc/r8610/Kconfig +++ b/src/northbridge/rdc/r8610/Kconfig @@ -1,2 +1,3 @@ config NORTHBRIDGE_RDC_R8610 bool + select LATE_CBMEM_INIT diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 34c330e..15c86eb 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -1,6 +1,7 @@ config NORTHBRIDGE_VIA_CN700 bool select HAVE_DEBUG_RAM_SETUP + select LATE_CBMEM_INIT # TODO: Values are from the CX700 datasheet, not sure if this matches CN700. # TODO: What should be the per-chipset default value here? diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 8f6e337..03014eb 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -5,6 +5,7 @@ config NORTHBRIDGE_VIA_CX700 select HAVE_HARD_RESET select IOAPIC select SMP + select LATE_CBMEM_INIT # TODO: What should be the per-chipset default value here? choice diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 48ea456..a59fc41 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -2,4 +2,5 @@ config NORTHBRIDGE_VIA_VX800 bool select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS + select LATE_CBMEM_INIT diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 9fe5909..617074f 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT + select LATE_CBMEM_INIT if NORTHBRIDGE_VIA_VX900

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Patch set updated for coreboot: 27ee060 CBMEM console: Fix CAR migration step
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8032 -gerrit commit 27ee060fe27b1e2e1e1e640cc5ea7bfdbacd07c8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 18:34:59 2014 +0200 CBMEM console: Fix CAR migration step With the change it becomes irrelevant if memcpy() car.global_data or cbmemc_reinit() is done first. Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/x86/car.c | 3 ++- src/lib/cbmem_console.c | 8 +++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index c9cc6d6..ba1a49d 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -54,7 +54,8 @@ void *car_get_var_ptr(void *var) if (!car_migrated) return var; - if (var < _car_start || var >= _car_end) { + /* NOTE: preram_console_buffer at _car_end also counts as CAR region. */ + if (var < _car_start || var > _car_end) { printk(BIOS_ERR, "Requesting CAR variable outside of CAR region: %p\n", var); diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 997bb7d..630d9c9 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -65,7 +65,13 @@ static u8 static_console[STATIC_CONSOLE_SIZE]; static inline struct cbmem_console *current_console(void) { - return car_get_var(cbmem_console_p); + struct cbmem_console *cbm_cons_p = car_get_var(cbmem_console_p); +#ifdef __PRE_RAM__ + /* Must not call car_get_var_ptr() after buffer is in CBMEM. */ + if (cbm_cons_p != &preram_cbmem_console) + return cbm_cons_p; +#endif + return car_get_var_ptr(cbm_cons_p); } static inline void current_console_set(struct cbmem_console *new_console_p)

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Patch set updated for coreboot: 1708cc2 CBMEM: Add timestamp_reinit()
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8033 -gerrit commit 1708cc27e54b16143dd993e857536eea64ecf50a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 19 10:17:46 2014 +0200 CBMEM: Add timestamp_reinit() This avoids the need for separate timestamp_reinit() calls made via CAR_MIGRATE() that is not implemented for ARM. Change-Id: Ia683162f3cb5d3cb3d4b7983a4b7e13306b0cfc8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem_common.c | 4 ++++ src/lib/hardwaremain.c | 2 -- 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 389b382..84fdc97 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -23,6 +23,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <cpu/x86/gdt.h> #include <console/cbmem_console.h> +#include <timestamp.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -79,6 +80,9 @@ void cbmem_arch_init(void) /* Relocate CBMEM console. */ cbmemc_reinit(); + /* Relocate timestamps stash. */ + timestamp_reinit(); + move_gdt(); #endif } diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index de20adc..2d4c306 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -22,6 +22,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <console/cbmem_console.h> +#include <timestamp.h> #ifndef __PRE_RAM__ @@ -56,6 +57,9 @@ void __attribute__((weak)) cbmem_arch_init(void) { /* Relocate CBMEM console. */ cbmemc_reinit(); + + /* Relocate timestamps stash. */ + timestamp_reinit(); } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index be052b3..657fc07 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -181,8 +181,6 @@ static boot_state_t bs_post_device(void *arg) dev_finalize(); timestamp_add_now(TS_DEVICE_DONE); - timestamp_reinit(); - return BS_OS_RESUME_CHECK; }

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coreboot-gerrit January 2015