coreboot-gerrit January 2015

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Patch set updated for coreboot: db248bc cbmem: [NOTFORMERGE] CBMEM_INIT_HOOK() API
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7878 -gerrit commit db248bc842fcdba718d2654d1218611cb6b9a589 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Dec 1 18:08:03 2014 -0800 cbmem: [NOTFORMERGE] CBMEM_INIT_HOOK() API Squashed two changes from chromium.git. cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API There are several use cases for performing a certain task when CBMEM is first set up (usually to migrate some data into it that was previously kept in BSS/SRAM/hammerspace), and unfortunately we handle each of them differently: timestamp migration is called explicitly from cbmem_initialize(), certain x86-chipset-specific tasks use the CAR_MIGRATION() macro to register a hook, and the CBMEM console is migrated through a direct call from romstage (on non-x86 and SandyBridge boards). This patch decouples the CAR_MIGRATION() hook mechanism from cache-as-RAM and rechristens it to CBMEM_INIT_HOOK(), which is a clearer description of what it really does. All of the above use cases are ported to this new, consistent model, allowing us to have one less line of boilerplate in non-CAR romstages. BRANCH=None BUG=None TEST=Built and booted on Nyan_Blaze and Falco with and without CONFIG_CBMEM_CONSOLE. Confirmed that 'cbmem -c' shows the full log after boot (and the resume log after S3 resume on Falco). Compiled for Parrot, Stout and Lumpy. Original-Change-Id: I1681b372664f5a1f15c3733cbd32b9b11f55f8ea Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/232612 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> cbmem: Extend hooks to ramstage, fix timestamp synching Commit 7dd5bbd71 (cbmem: Unify random on-CBMEM-init tasks under common CBMEM_INIT_HOOK() API) inadvertently broke ramstage timestamps since timestamp_sync() was no longer called there. Oops. This patch fixes the issue by extending the CBMEM_INIT_HOOK() mechanism to the cbmem_initialize() call in ramstage. The macro is split into explicit ROMSTAGE_/RAMSTAGE_ versions to make the behavior as clear as possible and prevent surprises (although just using a single macro and relying on the Makefiles to link an object into all appropriate stages would also work). This allows us to get rid of the explicit cbmemc_reinit() in ramstage (which I somehow accounted for in the last patch without realizing that timestamps work exactly the same way...), and replace the older and less flexible cbmem_arch_init() mechanism. Also added a size assertion for the pre-RAM CBMEM console to memlayout that could prevent a very unlikely buffer overflow I just noticed. BRANCH=None BUG=None TEST=Booted on Pinky and Falco, confirmed that ramstage timestamps once again show up. Compile-tested for Rambi and Samus. Original-Change-Id: If907266c3f20dc3d599b5c968ea5b39fe5c00e9c Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233533 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I1be89bafacfe85cba63426e2d91f5d8d4caa1800 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 1 - src/arch/x86/boot/cbmem.c | 22 ----- src/arch/x86/boot/gdt.c | 3 +- src/arch/x86/include/arch/early_variables.h | 14 --- src/arch/x86/init/romstage.ld | 9 +- src/cpu/x86/car.c | 15 +--- src/drivers/usb/ehci_debug.c | 2 +- src/include/cbmem.h | 20 ++++- src/include/cpu/x86/gdt.h | 3 - src/include/timestamp.h | 2 - src/lib/cbmem_common.c | 20 ++--- src/lib/cbmem_console.c | 4 +- src/lib/dynamic_cbmem.c | 4 +- src/lib/ramstage.ld | 117 +++++++++++++++++++++++++ src/lib/rmodule.ld | 3 + src/lib/romstage.ld | 62 +++++++++++++ src/lib/timestamp.c | 7 +- src/soc/intel/baytrail/romstage/romstage.c | 2 +- src/soc/intel/broadwell/romstage/power_state.c | 2 +- 20 files changed, 228 insertions(+), 85 deletions(-) diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 539b572..6145703 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 539b572..6145703 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -22,7 +22,6 @@ #define CAR_GLOBAL -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 82bbe3f..414782a 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,12 +20,6 @@ #include <cbmem.h> #include <arch/acpi.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <arch/early_variables.h> -#include <cpu/x86/gdt.h> -#include <console/cbmem_console.h> -#include <timestamp.h> - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -55,22 +49,6 @@ void *cbmem_top(void) #endif /* LATE_CBMEM_INIT */ -void cbmem_arch_init(void) -{ - /* Migrate car.global_data. */ - car_migrate_variables(); - -#if !defined(__PRE_RAM__) - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); - - move_gdt(); -#endif -} - /* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { diff --git a/src/arch/x86/boot/gdt.c b/src/arch/x86/boot/gdt.c index 7b64af7..b4cfbee 100644 --- a/src/arch/x86/boot/gdt.c +++ b/src/arch/x86/boot/gdt.c @@ -32,7 +32,7 @@ struct gdtarg { /* Copy GDT to new location and reload it. * FIXME: We only do this for BSP CPU. */ -void move_gdt(void) +static void move_gdt(void) { void *newgdt; u16 num_gdt_bytes = (u32)&gdt_end - (u32)&gdt; @@ -55,3 +55,4 @@ void move_gdt(void) __asm__ __volatile__ ("lgdt %0\n\t" : : "m" (gdtarg)); printk(BIOS_DEBUG, "ok\n"); } +RAMSTAGE_CBMEM_INIT_HOOK(move_gdt) diff --git a/src/arch/x86/include/arch/early_variables.h b/src/arch/x86/include/arch/early_variables.h index f76c048..742d3c6 100644 --- a/src/arch/x86/include/arch/early_variables.h +++ b/src/arch/x86/include/arch/early_variables.h @@ -29,12 +29,6 @@ asm(".previous"); #endif #if defined(__PRE_RAM__) -#define CAR_MIGRATE_ATTR __attribute__ ((used,section (".car.migrate"))) - -/* Call migrate_fn_() when CAR globals are migrated. */ -#define CAR_MIGRATE(migrate_fn_) \ - static void (* const migrate_fn_ ## _ptr)(void) CAR_MIGRATE_ATTR = \ - migrate_fn_; /* Get the correct pointer for the CAR global variable. */ void *car_get_var_ptr(void *var); @@ -46,17 +40,9 @@ void *car_get_var_ptr(void *var); do { car_get_var(var) = (val); } while(0) #else -#define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) #endif -#if defined(__PRE_RAM__) && IS_ENABLED(CONFIG_CACHE_AS_RAM) -/* Migrate the CAR variables to memory. */ -void car_migrate_variables(void); -#else -static inline void car_migrate_variables(void) { } -#endif - #endif diff --git a/src/arch/x86/init/romstage.ld b/src/arch/x86/init/romstage.ld index 99bcc8e..3ade87f 100644 --- a/src/arch/x86/init/romstage.ld +++ b/src/arch/x86/init/romstage.ld @@ -31,15 +31,14 @@ SECTIONS _rom = .; *(.rom.text); *(.rom.data); + . = ALIGN(4); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; *(.rodata); *(.rodata.*); *(.rom.data.*); . = ALIGN(16); - _car_migrate_start = .; - *(.car.migrate); - LONG(0); - _car_migrate_end = .; - . = ALIGN(16); _erom = .; } diff --git a/src/cpu/x86/car.c b/src/cpu/x86/car.c index ba1a49d..ae4a486 100644 --- a/src/cpu/x86/car.c +++ b/src/cpu/x86/car.c @@ -23,10 +23,6 @@ #include <cbmem.h> #include <arch/early_variables.h> -typedef void (* const car_migration_func_t)(void); - -extern car_migration_func_t _car_migrate_start; - extern char _car_data_start[]; extern char _car_data_end[]; @@ -77,7 +73,6 @@ void *car_get_var_ptr(void *var) static void do_car_migrate_variables(void) { void *migrated_base; - car_migration_func_t *migrate_func; size_t car_data_size = &_car_data_end[0] - &_car_data_start[0]; /* Check if already migrated. */ @@ -95,17 +90,11 @@ static void do_car_migrate_variables(void) /* Mark that the data has been moved. */ car_migrated = ~0; - - /* Call all the migration functions. */ - migrate_func = &_car_migrate_start; - while (*migrate_func != NULL) { - (*migrate_func)(); - migrate_func++; - } } -void car_migrate_variables(void) +static void car_migrate_variables(void) { if (!IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) do_car_migrate_variables(); } +ROMSTAGE_CBMEM_INIT_HOOK(car_migrate_variables) diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 83c23a3..f89ea2f 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -683,7 +683,7 @@ static void migrate_ehci_debug(void) memcpy(dbg_info_cbmem, dbg_info, sizeof(*dbg_info)); car_set_var(glob_dbg_info_p, dbg_info_cbmem); } -CAR_MIGRATE(migrate_ehci_debug); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_ehci_debug); #endif int dbgp_ep_is_active(struct dbgp_pipe *pipe) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index ea81fd0..68a03ad 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -179,16 +179,32 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); -void cbmem_arch_init(void); void cbmem_fail_resume(void); +typedef void (* const cbmem_init_hook_t)(void); +void cbmem_run_init_hooks(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -#endif /* __PRE_RAM__ */ +#endif + +#ifndef __PRE_RAM__ +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#else /* __PRE_RAM__ */ +#define ROMSTAGE_CBMEM_INIT_HOOK(init_fn_) \ + static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used, \ + section(".rodata.cbmem_init_hooks"))) = init_fn_; +#define RAMSTAGE_CBMEM_INIT_HOOK(init_fn_) static cbmem_init_hook_t \ + init_fn_ ## _unused_ __attribute__((unused)) = init_fn_; +#endif /* !__PRE_RAM__ */ /* These are for compatibility with old boards only. Any new chipset and board * must implement cbmem_top() for both romstage and ramstage to support diff --git a/src/include/cpu/x86/gdt.h b/src/include/cpu/x86/gdt.h index 260b158..43a80fe 100644 --- a/src/include/cpu/x86/gdt.h +++ b/src/include/cpu/x86/gdt.h @@ -28,7 +28,4 @@ extern char _secondary_gdt_addr[]; extern char _secondary_start[]; extern char _secondary_start_end[]; -/* Defined in src/arch/x86/boot/gdt.c */ -void move_gdt(void); - #endif /* CPU_X86_GDT */ diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 66c1d9a..fb594d2 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -63,13 +63,11 @@ enum timestamp_id { void timestamp_init(tsc_t base); void timestamp_add(enum timestamp_id id, tsc_t ts_time); void timestamp_add_now(enum timestamp_id id); -void timestamp_reinit(void); tsc_t get_initial_timestamp(void); #else #define timestamp_init(base) #define timestamp_add(id, time) #define timestamp_add_now(id) -#define timestamp_reinit() #endif #endif diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index 2d4c306..6509c3f 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,10 +20,6 @@ #include <cbmem.h> #include <stdlib.h> -/* FIXME: Remove after CBMEM_INIT_HOOKS. */ -#include <console/cbmem_console.h> -#include <timestamp.h> - #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -52,14 +48,16 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) #endif /* !__PRE_RAM__ */ -/* FIXME: Replace with CBMEM_INIT_HOOKS. */ -void __attribute__((weak)) cbmem_arch_init(void) +extern cbmem_init_hook_t _cbmem_init_hooks; +extern cbmem_init_hook_t _ecbmem_init_hooks; + +void cbmem_run_init_hooks(void) { - /* Relocate CBMEM console. */ - cbmemc_reinit(); - - /* Relocate timestamps stash. */ - timestamp_reinit(); + cbmem_init_hook_t *init_hook_ptr = &_cbmem_init_hooks; + while (init_hook_ptr != &_ecbmem_init_hooks) { + (*init_hook_ptr)(); + init_hook_ptr++; + } } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index b1aeedd..ddc2873 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -232,5 +232,5 @@ void cbmemc_reinit(void) init_console_ptr(cbm_cons_p, CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } -/* Call cbmemc_reinit() at CAR migration time. */ -CAR_MIGRATE(cbmemc_reinit) +ROMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(cbmemc_reinit) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 5fa7211..1b2bcbc 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -177,7 +177,7 @@ void cbmem_initialize_empty(void) root, root->max_entries); /* Complete migration to CBMEM. */ - cbmem_arch_init(); + cbmem_run_init_hooks(); } static inline int cbmem_fail_recovery(void) @@ -251,7 +251,7 @@ int cbmem_initialize(void) #endif /* Complete migration to CBMEM. */ - cbmem_arch_init(); + cbmem_run_init_hooks(); /* Recovery successful. */ return 0; diff --git a/src/lib/ramstage.ld b/src/lib/ramstage.ld new file mode 100644 index 0000000..732c8e9 --- /dev/null +++ b/src/lib/ramstage.ld @@ -0,0 +1,117 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file is included inside a SECTIONS block */ + +/* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. + */ +.text : { + _program = .; + _ramstage = .; + _text = .; + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); + . = ALIGN(16); + _etext = .; +} : to_load + +#ifdef CONFIG_COVERAGE +.ctors : { + . = ALIGN(0x100); + __CTOR_LIST__ = .; + KEEP(*(.ctors)); + LONG(0); + LONG(0); + __CTOR_END__ = .; +} +#endif + +/* TODO: align data sections to cache lines? (is that really useful?) */ +.rodata : { + _rodata = .; + . = ALIGN(8); + + /* If any changes are made to the driver start/symbols or the + * section names the equivalent changes need to made to + * rmodule.ld. */ + console_drivers = .; + KEEP(*(.rodata.console_drivers)); + econsole_drivers = . ; + . = ALIGN(8); + pci_drivers = . ; + KEEP(*(.rodata.pci_driver)); + epci_drivers = . ; + cpu_drivers = . ; + KEEP(*(.rodata.cpu_driver)); + ecpu_drivers = . ; + _bs_init_begin = .; + KEEP(*(.bs_init)); + _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; + + *(.rodata) + *(.rodata.*) + /* kevinh/Ispiri - Added an align, because the objcopy tool + * incorrectly converts sections that are not long word aligned. + */ + . = ALIGN(8); + + _erodata = .; +} + +.data : { + /* Move to different cache line to avoid false sharing with .rodata. */ + . = ALIGN(64); /* May not be actual line size, not that important. */ + _data = .; + *(.data) + *(.data.*) + _edata = .; +} + +.bss . : { + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; +} + +.heap . : { + _heap = .; + /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ + . += CONFIG_HEAP_SIZE ; + . = ALIGN(4); + _eheap = .; + _eramstage = .; + _eprogram = .; +} + +/* Discard the sections we don't need/want */ + +/DISCARD/ : { + *(.comment) + *(.note) + *(.note.*) +} diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..ad2c852 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -48,6 +48,9 @@ SECTIONS _bs_init_begin = .; *(.bs_init) _bs_init_end = .; + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; . = ALIGN(8); diff --git a/src/lib/romstage.ld b/src/lib/romstage.ld new file mode 100644 index 0000000..bbad333 --- /dev/null +++ b/src/lib/romstage.ld @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file is included inside a SECTIONS block */ + +.text . : { + _program = .; + _romstage = .; + *(.text._start); + *(.text.stage_entry); + *(.text); + *(.text.*); +} : to_load + +.data . : { + . = ALIGN(8); + _cbmem_init_hooks = .; + KEEP(*(.rodata.cbmem_init_hooks)); + _ecbmem_init_hooks = .; + *(.rodata); + *(.rodata.*); + *(.data); + *(.data.*); + . = ALIGN(8); +} + +.bss . : { + . = ALIGN(8); + _bss = .; + *(.bss) + *(.bss.*) + *(.sbss) + *(.sbss.*) + _ebss = .; + _eromstage = .; + _eprogram = .; +} + +/* Discard the sections we don't need/want */ +/DISCARD/ : { + *(.comment) + *(.note) + *(.comment.*) + *(.note.*) + *(.eh_frame); +} diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index f0ee48d..6a42d43 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -148,7 +148,7 @@ void timestamp_init(tsc_t base) #endif } -void timestamp_reinit(void) +static void timestamp_reinit(void) { if (!boot_cpu()) return; @@ -163,5 +163,6 @@ void timestamp_reinit(void) timestamp_do_sync(); } -/* Call timestamp_reinit at CAR migration time. */ -CAR_MIGRATE(timestamp_reinit) +/* Call timestamp_reinit CBMEM init hooks. */ +ROMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) +RAMSTAGE_CBMEM_INIT_HOOK(timestamp_reinit) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index b69b532..63e7bf4 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -178,7 +178,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) static struct chipset_power_state *fill_power_state(void) { diff --git a/src/soc/intel/broadwell/romstage/power_state.c b/src/soc/intel/broadwell/romstage/power_state.c index 6e333c1..5871ad9 100644 --- a/src/soc/intel/broadwell/romstage/power_state.c +++ b/src/soc/intel/broadwell/romstage/power_state.c @@ -50,7 +50,7 @@ static void migrate_power_state(void) } memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); } -CAR_MIGRATE(migrate_power_state); +ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state) /* Return 0, 3, or 5 to indicate the previous sleep state. */ static int prev_sleep_state(struct chipset_power_state *ps)

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Patch set updated for coreboot: 78b54c5 CBMEM: Rename utility file
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8031 -gerrit commit 78b54c51ee9cda8204920cfde54ff090ea598a20 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 19:13:12 2014 +0200 CBMEM: Rename utility file This file will have CBMEM init hooks API one day. Change-Id: I0c31495d4217a5eb235b13e6d8e8c99a87a3b840 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/Makefile.inc | 4 +++- src/lib/cbmem_common.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++ src/lib/cbmem_info.c | 45 --------------------------------------------- 3 files changed, 52 insertions(+), 46 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 0501091..ec3c2f4 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -81,7 +81,9 @@ else ramstage-y += cbmem.c romstage-y += cbmem.c endif # CONFIG_DYNAMIC_CBMEM -ramstage-y += cbmem_info.c + +romstage-y += cbmem_common.c +ramstage-y += cbmem_common.c ramstage-y += hexdump.c romstage-y += hexdump.c diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c new file mode 100644 index 0000000..a800173 --- /dev/null +++ b/src/lib/cbmem_common.c @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <console/console.h> +#include <cbmem.h> +#include <stdlib.h> + +#ifndef __PRE_RAM__ + +static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; + +void cbmem_print_entry(int n, u32 id, u64 base, u64 size) +{ + int i; + const char *name; + + name = NULL; + for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { + if (cbmem_ids[i].id == id) { + name = cbmem_ids[i].name; + break; + } + } + + if (name == NULL) + printk(BIOS_DEBUG, "%08x ", id); + else + printk(BIOS_DEBUG, "%s", name); + printk(BIOS_DEBUG, "%2d. ", n); + printk(BIOS_DEBUG, "%08llx ", base); + printk(BIOS_DEBUG, "%08llx\n", size); +} + +#endif /* !__PRE_RAM__ */ diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c deleted file mode 100644 index 7b1168d..0000000 --- a/src/lib/cbmem_info.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ -#include <console/console.h> -#include <cbmem.h> -#include <stdlib.h> - -static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; - -void cbmem_print_entry(int n, u32 id, u64 base, u64 size) -{ - int i; - const char *name; - - name = NULL; - for (i = 0; i < ARRAY_SIZE(cbmem_ids); i++) { - if (cbmem_ids[i].id == id) { - name = cbmem_ids[i].name; - break; - } - } - - if (name == NULL) - printk(BIOS_DEBUG, "%08x ", id); - else - printk(BIOS_DEBUG, "%s", name); - printk(BIOS_DEBUG, "%2d. ", n); - printk(BIOS_DEBUG, "%08llx ", base); - printk(BIOS_DEBUG, "%08llx\n", size); -}

1 0

Patch set updated for coreboot: f07c9a8 ARMv7: Always has DYNAMIC_CBMEM
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8030 -gerrit commit f07c9a806e88c0b5c04c5ebe741d1435b9340e1a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Nov 10 15:08:47 2014 +0200 ARMv7: Always has DYNAMIC_CBMEM The static allocator only worked for x86 anyway. Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/tables.c | 9 --------- src/cpu/ti/am335x/Kconfig | 1 + src/cpu/ti/am335x/Makefile.inc | 2 ++ src/cpu/ti/am335x/cbmem.c | 24 ++++++++++++++++++++++++ src/mainboard/emulation/qemu-armv7/Kconfig | 1 + src/mainboard/emulation/qemu-armv7/Makefile.inc | 3 +++ src/mainboard/emulation/qemu-armv7/cbmem.c | 24 ++++++++++++++++++++++++ 7 files changed, 55 insertions(+), 9 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 20c5a9f..a2b7b9b 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -29,15 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -#if !CONFIG_DYNAMIC_CBMEM -void __attribute__((weak)) get_cbmem_table(uint64_t *base, uint64_t *size) -{ - printk(BIOS_WARNING, "WARNING: you need to define get_cbmem_table for your board\n"); - *base = 0; - *size = 0; -} -#endif - void cbmem_arch_init(void) { } diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index fae527d..eb60ad1 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,6 +6,7 @@ config CPU_TI_AM335X select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT + select DYNAMIC_CBMEM bool default n diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index 24d2594..45188ce 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -4,11 +4,13 @@ bootblock-y += dmtimer.c bootblock-y += pinmux.c romstage-y += nand.c +romstage-y += cbmem.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c ramstage-y += timer.c +ramstage-y += cbmem.c ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c diff --git a/src/cpu/ti/am335x/cbmem.c b/src/cpu/ti/am335x/cbmem.c new file mode 100644 index 0000000..84f88cf --- /dev/null +++ b/src/cpu/ti/am335x/cbmem.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20); +} diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index b275e88..7e24a20 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARM_ROMSTAGE_ARMV7 select ARM_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 + select DYNAMIC_CBMEM config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index e088da6..4119f93 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -14,6 +14,9 @@ romstage-y += romstage.c +romstage-y += cbmem.c +ramstage-y += cbmem.c + bootblock-y += media.c romstage-y += media.c ramstage-y += media.c diff --git a/src/mainboard/emulation/qemu-armv7/cbmem.c b/src/mainboard/emulation/qemu-armv7/cbmem.c new file mode 100644 index 0000000..84f88cf --- /dev/null +++ b/src/mainboard/emulation/qemu-armv7/cbmem.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stddef.h> +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20); +}

1 0

Patch set updated for coreboot: 4804ea4 CBMEM: Implement cbmem_arch_init() for romstage too
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7876 -gerrit commit 4804ea4fa0c3bed8c2af03935c6a90eb660d1c92 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 18 18:30:29 2014 +0200 CBMEM: Implement cbmem_arch_init() for romstage too Until we completely can unify early_variables, use this to handle CBMEM update hooks for both romstage and ramstage. Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/tables.c | 8 -------- src/arch/arm64/tables.c | 4 ---- src/arch/riscv/tables.c | 8 -------- src/arch/x86/boot/cbmem.c | 18 ++++++++++++------ src/arch/x86/boot/tables.c | 8 -------- src/include/cbmem.h | 8 +++----- src/lib/cbmem_common.c | 9 +++++++++ 7 files changed, 24 insertions(+), 39 deletions(-) diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index a2b7b9b..09385b6 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -29,14 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - -void cbmem_fail_resume(void) -{ -} - void write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/arm64/tables.c b/src/arch/arm64/tables.c index ce7ad5a..f71c215 100644 --- a/src/arch/arm64/tables.c +++ b/src/arch/arm64/tables.c @@ -29,10 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - struct lb_memory *write_tables(void) { unsigned long table_pointer, new_table_pointer; diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 6300f7b..124a659 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -29,10 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -void cbmem_arch_init(void) -{ -} - // WTF. this does not agre with the prototype! static struct lb_memory *wtf_write_tables(void) { @@ -70,7 +66,3 @@ void write_tables(void) { wtf_write_tables(); } - -void cbmem_fail_resume(void) -{ -} diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 8b2b6da..15f35c2 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <arch/acpi.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <cpu/x86/gdt.h> + #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) { @@ -69,16 +72,19 @@ void *cbmem_top(void) #endif /* DYNAMIC_CBMEM */ +void cbmem_arch_init(void) +{ #if !defined(__PRE_RAM__) + move_gdt(); +#endif +} -/* ACPI resume needs to be cleared in the fail-to-recover case, but that - * condition is only handled during ramstage. */ +/* Something went wrong, our high memory area got wiped */ void cbmem_fail_resume(void) { -#if CONFIG_HAVE_ACPI_RESUME - /* Something went wrong, our high memory area got wiped */ +#if !defined(__PRE_RAM__) && IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + /* ACPI resume needs to be cleared in the fail-to-recover case, but that + * condition is only handled during ramstage. */ acpi_fail_wakeup(); #endif } - -#endif /* !__PRE_RAM__ */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index 8685ed4..c2265ea 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -21,7 +21,6 @@ #include <console/console.h> #include <cpu/cpu.h> -#include <cpu/x86/gdt.h> #include <boot/tables.h> #include <boot/coreboot_tables.h> #include <arch/pirq_routing.h> @@ -31,13 +30,6 @@ #include <cbmem.h> #include <smbios.h> - -void cbmem_arch_init(void) -{ - /* defined in gdt.c */ - move_gdt(); -} - void write_tables(void) { unsigned long low_table_start, low_table_end; diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7de6e56..a7bd904 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -213,17 +213,15 @@ void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +void cbmem_arch_init(void); +void cbmem_fail_resume(void); + #ifndef __PRE_RAM__ /* Ramstage only functions. */ /* Add the cbmem memory used to the memory map at boot. */ void cbmem_add_bootmem(void); void cbmem_list(void); -void cbmem_arch_init(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); -void cbmem_fail_resume(void); -#else -static inline void cbmem_arch_init(void) {} -static inline void cbmem_fail_resume(void) {} #endif /* __PRE_RAM__ */ #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index a800173..a944dd3 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -47,3 +47,12 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) } #endif /* !__PRE_RAM__ */ + +/* FIXME: Replace with CBMEM_INIT_HOOKS. */ +void __attribute__((weak)) cbmem_arch_init(void) +{ +} + +void __attribute__((weak)) cbmem_fail_resume(void) +{ +}

1 0

Patch set updated for coreboot: 3a38ed6 CBMEM: Move cbmemc_reinit()
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7859 -gerrit commit 3a38ed689023200fd8632562840083666489f243 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 19:29:02 2014 +0200 CBMEM: Move cbmemc_reinit() This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem.c | 2 -- src/lib/cbmem_common.c | 5 +++++ src/lib/dynamic_cbmem.c | 2 -- src/mainboard/google/nyan/romstage.c | 5 ----- src/mainboard/google/nyan_big/romstage.c | 5 ----- src/mainboard/google/nyan_blaze/romstage.c | 5 ----- src/mainboard/via/epia-m850/romstage.c | 1 - src/soc/intel/fsp_baytrail/romstage/romstage.c | 1 - 9 files changed, 9 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 15f35c2..389b382 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -22,6 +22,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <cpu/x86/gdt.h> +#include <console/cbmem_console.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -75,6 +76,9 @@ void *cbmem_top(void) void cbmem_arch_init(void) { #if !defined(__PRE_RAM__) + /* Relocate CBMEM console. */ + cbmemc_reinit(); + move_gdt(); #endif } diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 0b24ad2..f8077b6 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> @@ -256,7 +255,6 @@ static void init_cbmem_post_device(void *unused) #else cbmem_recovery(0); #endif - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index a944dd3..de20adc 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <stdlib.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <console/cbmem_console.h> + #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -51,6 +54,8 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) /* FIXME: Replace with CBMEM_INIT_HOOKS. */ void __attribute__((weak)) cbmem_arch_init(void) { + /* Relocate CBMEM console. */ + cbmemc_reinit(); } void __attribute__((weak)) cbmem_fail_resume(void) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 5eddbca..dd3e9f2 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,7 +21,6 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> @@ -426,7 +425,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) static void init_cbmem_pre_device(void *unused) { cbmem_initialize(); - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 899c5a6..7eb8d60 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/bist.h> #include <string.h> #include <timestamp.h> -#include <console/cbmem_console.h> #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 2619c96..f4442ac 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -43,7 +43,6 @@ #include <version.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> -#include <console/cbmem_console.h> /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ uint32_t chipset_prev_sleep_state(uint32_t clear)

1 0

Patch set updated for coreboot: 6aec025 CBMEM: Tidy up CAR migration
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7860 -gerrit commit 6aec0251e4207da4bbb1c6bf55c896f90eb9cedc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 20:55:19 2014 +0200 CBMEM: Tidy up CAR migration Move the CAR migration call to arch -specific part of CBMEM init, it is truly a x86 specific thing. Change-Id: I715417e54f197b8745e0670d6b900a5660178141 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 14 -------------- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 5 ----- src/arch/riscv/include/arch/early_variables.h | 5 ----- src/arch/x86/Kconfig | 15 +++++++++++++++ src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem.c | 3 ++- src/lib/dynamic_cbmem.c | 10 ++-------- 8 files changed, 23 insertions(+), 34 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c9a04a4..cf66598 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,20 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config LATE_CBMEM_INIT - def_bool n - help - Enable this in chipset's Kconfig if northbridge does not implement - early get_top_of_ram() call for romstage. CBMEM tables will be - allocated late in ramstage, after PCI devices resources are known. - -config BROKEN_CAR_MIGRATE - def_bool LATE_CBMEM_INIT - help - Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and - manage CAR migration on S3 resume path only. Couple boards use - CAR_GLOBAL and never do CAR migration. - config DYNAMIC_CBMEM bool default n diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 5b58baa..539b572 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -26,6 +26,5 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..539b572 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -20,16 +20,11 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if CONFIG_CAR_MIGRATION - #error "This is ARM, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index 3a1f20d..539b572 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -20,16 +20,11 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if defined(CONFIG_CAR_MIGRATION) && CONFIG_CAR_MIGRATION - #error "This is RISCV, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 56d8f88..b6791ed 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -47,6 +47,21 @@ config ROMCC bool default n +config BROKEN_CAR_MIGRATE + def_bool n + help + Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and + manage CAR migration on S3 resume path only. Couple boards use + CAR_GLOBAL and never do CAR migration. + +config LATE_CBMEM_INIT + def_bool n + select BROKEN_CAR_MIGRATE + help + Enable this in chipset's Kconfig if northbridge does not implement + early get_top_of_ram() call for romstage. CBMEM tables will be + allocated late in ramstage, after PCI devices resources are known. + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 79cf46c..750e8b2 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -21,6 +21,7 @@ #include <arch/acpi.h> /* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <arch/early_variables.h> #include <cpu/x86/gdt.h> #include <console/cbmem_console.h> #include <timestamp.h> @@ -76,6 +77,9 @@ void *cbmem_top(void) void cbmem_arch_init(void) { + /* Migrate car.global_data. */ + car_migrate_variables(); + #if !defined(__PRE_RAM__) /* Relocate CBMEM console. */ cbmemc_reinit(); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f8077b6..5ea8d88 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -242,8 +242,9 @@ int cbmem_recovery(int is_wakeup) cbmem_fail_resume(); } + /* Complete migration to CBMEM. */ cbmem_arch_init(); - car_migrate_variables(); + return !found; } diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index dd3e9f2..fbd6148 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -170,18 +170,14 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", root, root->max_entries); + /* Complete migration to CBMEM. */ cbmem_arch_init(); - - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); } static inline int cbmem_fail_recovery(void) { cbmem_initialize_empty(); cbmem_fail_resume(); - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); return 1; } @@ -248,11 +244,9 @@ int cbmem_initialize(void) root->locked = 1; #endif + /* Complete migration to CBMEM. */ cbmem_arch_init(); - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); - /* Recovery successful. */ return 0; }

1 0

Patch set updated for coreboot: ba44274 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7861 -gerrit commit ba442749248f9207036dda428ea3c8a80de00bfc Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 19 08:20:45 2014 +0200 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT We can now create CBMEM with dynamic allocation even if CBMEM location is resolved late in ramstage. TODO: Handle case of get_top_of_ram() returning 0. Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 3 +-- src/arch/x86/boot/cbmem.c | 14 +++++++++----- src/include/cbmem.h | 19 +++++++++++++------ src/lib/cbmem_console.c | 2 +- src/lib/dynamic_cbmem.c | 32 ++++++++++++++++++++++++++++---- 5 files changed, 52 insertions(+), 18 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index cf66598..73cd803 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -162,7 +162,6 @@ config EARLY_CBMEM_INIT config DYNAMIC_CBMEM bool default n - select EARLY_CBMEM_INIT help Instead of reserving a static amount of CBMEM space the CBMEM area grows dynamically. CBMEM can be used both in romstage (after @@ -201,7 +200,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM) + depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index d75845d..7d7ec3d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -39,6 +39,9 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) *size = 0; } } +#endif /* !DYNAMIC_CBMEM */ + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) @@ -46,14 +49,14 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ } -/* This is for compatibility with old boards only. Any new chipset and board - * must implement get_top_of_ram() for both romstage and ramstage to support - * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. - */ void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); +#if !CONFIG_DYNAMIC_CBMEM cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); +#else + cbmem_set_top((void*)(uintptr_t)ramtop); +#endif } #endif /* !__PRE_RAM__ */ @@ -70,7 +73,8 @@ void *cbmem_top(void) return (void *)get_top_of_ram(); } #endif -#endif /* !DYNAMIC_CBMEM */ + +#endif /* LATE_CBMEM_INIT */ void cbmem_arch_init(void) { diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 1b7f307..b1f3b5e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -151,6 +151,9 @@ void cbmem_initialize_empty(void); * below 4GiB. */ void *cbmem_top(void); +/* Set the top address for dynamic cbmem. Not for new designs. */ +void cbmem_set_top(void *ramtop); + /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ @@ -168,7 +171,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); - #else /* !CONFIG_DYNAMIC_CBMEM */ /* Allocation with static CBMEM is resolved at build time. We start @@ -183,15 +185,10 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - #ifndef __PRE_RAM__ -void set_top_of_ram(uint64_t ramtop); -void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif -unsigned long get_top_of_ram(void); - void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -224,6 +221,16 @@ void cbmem_list(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); #endif /* __PRE_RAM__ */ +/* These are for compatibility with old boards only. Any new chipset and board + * must implement cbmem_top() for both romstage and ramstage to support + * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. + */ +#if IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +unsigned long get_top_of_ram(void); +void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); +#endif + #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 5f8ff0c..b1aeedd 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -58,7 +58,7 @@ extern struct cbmem_console preram_cbmem_console; * during the ROM stage, once CBMEM becomes available at RAM stage. */ -#if CONFIG_DYNAMIC_CBMEM +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #define STATIC_CONSOLE_SIZE 1024 #else #define STATIC_CONSOLE_SIZE CONFIG_CONSOLE_CBMEM_BUFFER_SIZE diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index fbd6148..5fa7211 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -24,10 +24,9 @@ #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> #endif - #ifndef UINT_MAX #define UINT_MAX 4294967295U #endif @@ -69,11 +68,18 @@ struct cbmem_root { } __attribute__((packed)); +#if !defined(__PRE_RAM__) +static void *cached_cbmem_top; + +void cbmem_set_top(void * ramtop) +{ + cached_cbmem_top = ramtop; +} +#endif + static inline void *cbmem_top_cached(void) { #if !defined(__PRE_RAM__) - static void *cached_cbmem_top; - if (cached_cbmem_top == NULL) cached_cbmem_top = cbmem_top(); @@ -413,6 +419,8 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) #if !defined(__PRE_RAM__) + +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) /* selected cbmem can be initialized early in ramstage. Additionally, that * means cbmem console can be reinitialized early as well. The post_device * function is empty since cbmem was initialized early in ramstage. */ @@ -426,6 +434,22 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_pre_device, NULL), }; +#else + +static void init_cbmem_post_device(void *unused) +{ + if (acpi_is_wakeup()) + cbmem_initialize(); + else + cbmem_initialize_empty(); +} + +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL), +}; +#endif + void cbmem_add_bootmem(void) { unsigned long base;

1 0

Patch set updated for coreboot: 8c5d948 CBMEM console: Fix and enhance pre-RAM support
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7862 -gerrit commit 8c5d94801eafb91f437cbe9afc33c21092f56fc6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 21 08:55:47 2014 +0200 CBMEM console: Fix and enhance pre-RAM support Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can do CBMEM console in bootblock and romstage. Kconfig forces it to zero if _BASE is unset or we cannot do CAR migration on x86. Add CBMEM console to bootblock, except for x86. Only one of bootblock and romstage clears the pre-RAM buffer. To start with empty console log on S3 wakeup, ramstage now clears previous contents of CBMEM buffer if there was no pre-RAM buffer. Unify Kconfig variable naming. TODO: ARM configurations do not define PRERAM_BUFFER_BASE values. Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/Kconfig | 4 -- src/arch/arm/bootblock.ld | 2 +- src/arch/arm/romstage.ld | 2 +- src/arch/arm64/bootblock.ld | 2 + src/arch/arm64/romstage.ld | 2 +- src/arch/riscv/romstage.ld | 2 +- src/console/Kconfig | 12 +++++- src/include/console/cbmem_console.h | 3 +- src/lib/Makefile.inc | 1 + src/lib/cbmem_console.c | 79 +++++++++++++++++++++---------------- 10 files changed, 63 insertions(+), 46 deletions(-) diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index e946f59..edc4b12 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -20,10 +20,6 @@ config ARM_BOOTBLOCK_CUSTOM bool default n -config CBMEM_CONSOLE_PRERAM_BASE - hex - depends on CONSOLE_CBMEM - config CPU_HAS_BOOTBLOCK_INIT bool default n diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index 150bf2d..c355348 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -49,7 +49,7 @@ SECTIONS *(.sbss.*); } : to_load = 0xff - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld index 8c32046..34e9eaa 100644 --- a/src/arch/arm/romstage.ld +++ b/src/arch/arm/romstage.ld @@ -69,7 +69,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld index acce1f1..907d009 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/bootblock.ld @@ -49,6 +49,8 @@ SECTIONS *(.sbss.*); } : to_load = 0xff + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; + /DISCARD/ : { *(.comment) *(.note) diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld index d05fdd1..a8d092c 100644 --- a/src/arch/arm64/romstage.ld +++ b/src/arch/arm64/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld index 839c285..a58aee3 100644 --- a/src/arch/riscv/romstage.ld +++ b/src/arch/riscv/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - /*preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;*/ + /*preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;*/ /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/console/Kconfig b/src/console/Kconfig index 0d32011..6d9bf1e 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -175,8 +175,9 @@ config CONSOLE_CBMEM Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space. +if CONSOLE_CBMEM + config CONSOLE_CBMEM_BUFFER_SIZE - depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" default 0x20000 help @@ -184,16 +185,23 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_PRERAM_BUFFER_BASE + hex + default 0xabadbeef if !CACHE_AS_RAM || BROKEN_CAR_MIGRATE + default 0x0 + config CONSOLE_PRERAM_BUFFER_SIZE - depends on CONSOLE_CBMEM hex "Room allocated for console output before RAM is initialized" default 0xc00 + depends on CONSOLE_PRERAM_BUFFER_BASE != 0xabadbeef help Console is used before RAM is initialized. This is the room reserved in the DCACHE based RAM, SRAM, etc. to keep console output before it can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. +endif + config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" depends on BOARD_EMULATION_QEMU_X86 diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 36d132c..81bc10f 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -32,7 +32,8 @@ static inline void cbmemc_reinit(void) {} #endif #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ - ((ENV_ROMSTAGE && !CONFIG_BROKEN_CAR_MIGRATE) || ENV_RAMSTAGE) + (ENV_RAMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE && \ + ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || ENV_ROMSTAGE))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ec3c2f4..e35116b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += loaders bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 630d9c9..5f8ff0c 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -37,6 +37,9 @@ struct cbmem_console { static struct cbmem_console *cbmem_console_p CAR_GLOBAL; +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p); + #ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -63,6 +66,10 @@ extern struct cbmem_console preram_cbmem_console; static u8 static_console[STATIC_CONSOLE_SIZE]; #endif +/* flags for init */ +#define CBMEMC_RESET (1<<0) +#define CBMEMC_APPEND (1<<1) + static inline struct cbmem_console *current_console(void) { struct cbmem_console *cbm_cons_p = car_get_var(cbmem_console_p); @@ -79,27 +86,45 @@ static inline void current_console_set(struct cbmem_console *new_console_p) car_set_var(cbmem_console_p, new_console_p); } -static inline void init_console_ptr(void *storage, u32 total_space) +static inline void init_console_ptr(void *storage, u32 total_space, int flags) { struct cbmem_console *cbm_cons_p = storage; - /* Initialize the cache-as-ram pointer and underlying structure. */ - car_set_var(cbmem_console_p, cbm_cons_p); - cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); - cbm_cons_p->buffer_cursor = 0; + if (!cbm_cons_p) { + current_console_set(NULL); + return; + } + + if (flags & CBMEMC_RESET) { + cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); + cbm_cons_p->buffer_cursor = 0; + } + if (flags & CBMEMC_APPEND) { + struct cbmem_console *tmp_cons_p = current_console(); + if (tmp_cons_p) + copy_console_buffer(tmp_cons_p, cbm_cons_p); + } + + current_console_set(cbm_cons_p); } void cbmemc_init(void) { #ifdef __PRE_RAM__ + int flags = CBMEMC_RESET; + + /* Do not clear output from bootblock. */ + if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + flags = 0; + init_console_ptr(&preram_cbmem_console, - CONFIG_CONSOLE_PRERAM_BUFFER_SIZE); + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE, flags); #else /* * Initializing before CBMEM is available, use static buffer to store * the log. */ - init_console_ptr(static_console, sizeof(static_console)); + init_console_ptr(static_console, sizeof(static_console), CBMEMC_RESET); #endif } @@ -125,13 +150,11 @@ void cbmemc_tx_byte(unsigned char data) * If there is overflow - add to the destination area a string, reporting the * overflow and the number of dropped characters. */ -static void copy_console_buffer(struct cbmem_console *new_cons_p) +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p) { u32 copy_size, dropped_chars; u32 cursor = new_cons_p->buffer_cursor; - struct cbmem_console *old_cons_p; - - old_cons_p = current_console(); if (old_cons_p->buffer_cursor < old_cons_p->buffer_size) copy_size = old_cons_p->buffer_cursor; @@ -193,35 +216,21 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p = NULL; + int flags = CBMEMC_APPEND; -#ifdef __PRE_RAM__ - if (IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + if (ENV_ROMSTAGE && (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) return; -#endif - -#ifndef __PRE_RAM__ - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (!cbm_cons_p) { - cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, - CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - - if (!cbm_cons_p) { - current_console_set(NULL); - return; - } - cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE - - sizeof(struct cbmem_console); + /* If CBMEM entry already existed, old contents is not altered. */ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - cbm_cons_p->buffer_cursor = 0; - } + /* Clear old contents of CBMEM buffer. */ + if (ENV_ROMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) + flags |= CBMEMC_RESET; - copy_console_buffer(cbm_cons_p); - - current_console_set(cbm_cons_p); + init_console_ptr(cbm_cons_p, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } - /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit)

1 0

Patch set updated for coreboot: b672e1b CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7888 -gerrit commit b672e1b6c4acf96fef796d8a39243ece990c6c53 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 22 12:28:07 2014 +0200 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 9 ++--- src/cpu/intel/haswell/romstage.c | 4 +- src/include/cbmem.h | 4 +- src/mainboard/emulation/qemu-i440fx/memory.c | 4 +- src/northbridge/intel/fsp_rangeley/raminit.c | 14 ++++--- src/northbridge/intel/fsp_sandybridge/Makefile.inc | 2 + .../intel/fsp_sandybridge/northbridge.c | 10 ----- src/northbridge/intel/fsp_sandybridge/ram_calc.c | 38 +++++++++++++++++ src/northbridge/intel/fsp_sandybridge/raminit.c | 8 ---- src/northbridge/intel/gm45/ram_calc.c | 7 +++- src/northbridge/intel/haswell/ram_calc.c | 11 +++-- src/northbridge/intel/i945/ram_calc.c | 11 +++-- src/northbridge/intel/nehalem/ram_calc.c | 11 +++-- src/northbridge/intel/sandybridge/ram_calc.c | 11 +++-- src/soc/intel/baytrail/baytrail/smm.h | 2 +- src/soc/intel/baytrail/memmap.c | 8 ++-- src/soc/intel/broadwell/memmap.c | 13 ++++-- src/soc/intel/fsp_baytrail/Makefile.inc | 2 - src/soc/intel/fsp_baytrail/baytrail/smm.h | 2 +- src/soc/intel/fsp_baytrail/memmap.c | 22 +++++++++- src/soc/intel/fsp_baytrail/raminit.c | 47 ---------------------- 21 files changed, 131 insertions(+), 109 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 750e8b2..d75845d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -57,23 +57,20 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } -#endif - -#else +#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } - -#endif /* DYNAMIC_CBMEM */ +#endif +#endif /* !DYNAMIC_CBMEM */ void cbmem_arch_init(void) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index bd2513f..1af5259 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; - top_of_ram = get_top_of_ram(); + top_of_ram = (uint32_t)cbmem_top(); /* Cache 8MiB below the top of ram. On haswell systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later @@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size) /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); + return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } void ramstage_cache_invalid(struct ramstage_cache *cache) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a7bd904..1b7f307 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -190,6 +190,8 @@ void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif +unsigned long get_top_of_ram(void); + void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -201,8 +203,6 @@ static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) /* Common API between cbmem and dynamic cbmem. */ -unsigned long get_top_of_ram(void); - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index a189d75..d43b4e9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,7 +40,7 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return qemu_get_memory_size() * 1024; + return (void *) (qemu_get_memory_size() * 1024); } diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..ea750e7 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -26,19 +26,23 @@ #include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Calculate the top of usable (low) DRAM. * The FSP's reserved memory sits just below the SMM region, * allowing calculation of the top of usable memory. */ - u32 tom = sideband_read(B_UNIT, BMBOUND); - u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; + uintptr_t tom = sideband_read(B_UNIT, BMBOUND); + uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; if (bsmmrrl) { tom = bsmmrrl; } - tom -= FSP_RESERVE_MEMORY_SIZE; - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index 080a7f4..ca6f345 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -20,11 +20,13 @@ subdirs-y += fsp ramstage-y += northbridge.c +ramstage-y += ram_calc.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += raminit.c +romstage-y += ram_calc.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..b39f4c9 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -245,16 +245,6 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -unsigned long get_top_of_ram(void) -{ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c new file mode 100644 index 0000000..bbfc874 --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <fsp_util.h> +#include "northbridge.h" + +static uintptr_t smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start() - FSP_RESERVE_MEMORY_SIZE; +} diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c index 19b48ca..8689274 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.c +++ b/src/northbridge/intel/fsp_sandybridge/raminit.c @@ -74,11 +74,3 @@ void report_memory_config(void) ((ch_conf >> 16) & 1) ? ", selected" : ""); } } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c8c15d3..d9d3357 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -86,7 +86,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -105,3 +105,8 @@ unsigned long get_top_of_ram(void) } return tor; } + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index 99e7d67..01ad50d 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -24,12 +24,17 @@ #include <cbmem.h> #include "haswell.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignement. */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); } diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index d09b2e1..4b7d895 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -24,9 +24,9 @@ #include <cbmem.h> #include "i945.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { - u32 tom; + uintptr_t tom; if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { /* IGD enabled, get top of Memory from BSM register */ @@ -53,5 +53,10 @@ unsigned long get_top_of_ram(void) /* TSEG either disabled or invalid */ break; } - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index db57a3d..d36684e 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "nehalem.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 3693a07..e147909 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "sandybridge.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h index 5ead89f..0d920fb 100644 --- a/src/soc/intel/baytrail/baytrail/smm.h +++ b/src/soc/intel/baytrail/baytrail/smm.h @@ -31,7 +31,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f383d82..f2e14b3 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -22,12 +22,12 @@ #include <baytrail/iosf.h> #include <baytrail/smm.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return (unsigned long)smm_region_start(); + return (void *) smm_region_start(); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 046cc1d..28f4062 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -23,19 +23,24 @@ #include <broadwell/pci_devs.h> #include <broadwell/systemagent.h> -unsigned long get_top_of_ram(void) +static uintptr_t dpr_region_start(void) { /* * Base of DPR is top of usable DRAM below 4GiB. The register has * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR); - u32 tom = dpr & ~((1 << 20) - 1); + uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t tom = dpr & ~((1 << 20) - 1); /* Subtract DMA Protected Range size if enabled */ if (dpr & DPR_EPM) tom -= (dpr & DPR_SIZE_MASK) << 16; - return (unsigned long)tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) dpr_region_start(); } diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index fcbe6e7..3896e85 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -44,8 +44,6 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c ramstage-y += pmutil.c -romstage-y += raminit.c -ramstage-y += raminit.c ramstage-y += southcluster.c romstage-y += reset.c ramstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h index 0208c9f..136c2ca 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/smm.h +++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h @@ -36,7 +36,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 83858b8..615916b 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,25 @@ #include <cbmem.h> #include <baytrail/iosf.h> #include <baytrail/smm.h> +#include <drivers/intel/fsp/fsp_util.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); +} + +/* + * Calculate the top of usable (low) DRAM. + * The FSP's reserved memory sits just below the SMM region, + * allowing calculation of the top of usable memory. + * + * The entire memory map is shown in northcluster.c + */ + +void *cbmem_top(void) +{ + uintptr_t tom = smm_region_start(); + if (!tom) + tom = iosf_bunit_read(BUNIT_BMBOUND); + return (void *) tom - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c deleted file mode 100644 index 55692d2..0000000 --- a/src/soc/intel/fsp_baytrail/raminit.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <cbmem.h> -#include <device/device.h> -#include <baytrail/baytrail.h> -#include <baytrail/iosf.h> -#include <cpu/x86/msr.h> -#include <drivers/intel/fsp/fsp_util.h> - -unsigned long get_top_of_ram(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - * - * The entire memory map is shown in northcluster.c - */ - u32 tom = iosf_bunit_read(BUNIT_BMBOUND); - u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - tom -= FSP_RESERVE_MEMORY_SIZE; - - return (unsigned long) tom; -}

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Patch set updated for coreboot: e0ebb58 CBMEM: Always use DYNAMIC_CBMEM
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7851 -gerrit commit e0ebb584e32895aeeb85d7a3231ed8246916ed8f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 28 11:24:19 2014 +0200 CBMEM: Always use DYNAMIC_CBMEM Drop the implementation of statically allocated high memory region for CBMEM. There is no longer the need to explicitly select DYNAMIC_CBMEM, it is the only remaining choice. Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 10 +- src/arch/x86/boot/cbmem.c | 21 -- src/arch/x86/boot/tables.c | 9 +- src/cpu/allwinner/a10/Kconfig | 1 - src/cpu/intel/fsp_model_206ax/Kconfig | 1 - src/cpu/intel/fsp_model_406dx/Kconfig | 1 - src/cpu/intel/haswell/Kconfig | 1 - src/cpu/intel/haswell/romstage.c | 5 +- src/cpu/ti/am335x/Kconfig | 1 - src/include/cbmem.h | 31 --- src/include/rmodule.h | 2 - src/lib/Makefile.inc | 13 +- src/lib/cbmem.c | 288 ---------------------- src/lib/rmodule.c | 8 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/Kconfig | 1 - src/mainboard/emulation/qemu-i440fx/northbridge.c | 4 - src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 1 - src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 4 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 2 - src/soc/nvidia/tegra124/Kconfig | 1 - src/soc/samsung/exynos5250/Kconfig | 1 - src/soc/samsung/exynos5420/Kconfig | 1 - src/soc/ucb/riscv/Kconfig | 1 - 30 files changed, 7 insertions(+), 408 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 73cd803..fd9ceca 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,14 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config DYNAMIC_CBMEM - bool - default n - help - Instead of reserving a static amount of CBMEM space the CBMEM - area grows dynamically. CBMEM can be used both in romstage (after - memory initialization) and ramstage. - config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" default n @@ -200,7 +192,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) + depends on (RELOCATABLE_MODULES && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 7d7ec3d..82bbe3f 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -26,21 +26,6 @@ #include <console/cbmem_console.h> #include <timestamp.h> -#if !CONFIG_DYNAMIC_CBMEM -void get_cbmem_table(uint64_t *base, uint64_t *size) -{ - uint64_t top_of_ram = get_top_of_ram(); - - if (top_of_ram >= HIGH_MEMORY_SIZE) { - *base = top_of_ram - HIGH_MEMORY_SIZE; - *size = HIGH_MEMORY_SIZE; - } else { - *base = 0; - *size = 0; - } -} -#endif /* !DYNAMIC_CBMEM */ - #if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) @@ -52,11 +37,7 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); -#if !CONFIG_DYNAMIC_CBMEM - cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); -#else cbmem_set_top((void*)(uintptr_t)ramtop); -#endif } #endif /* !__PRE_RAM__ */ @@ -66,13 +47,11 @@ unsigned long __attribute__((weak)) get_top_of_ram(void) return 0; } -#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } -#endif #endif /* LATE_CBMEM_INIT */ diff --git a/src/arch/x86/boot/tables.c b/src/arch/x86/boot/tables.c index c2265ea..712f66f 100644 --- a/src/arch/x86/boot/tables.c +++ b/src/arch/x86/boot/tables.c @@ -101,11 +101,8 @@ void write_tables(void) #endif /* CONFIG_GENERATE_MP_TABLE */ #if CONFIG_HAVE_ACPI_TABLES -#if CONFIG_DYNAMIC_CBMEM #define MAX_ACPI_SIZE (144 * 1024) -#else -#define MAX_ACPI_SIZE (45 * 1024) -#endif + post_code(0x9c); /* Write ACPI tables to F segment and high tables area */ @@ -199,11 +196,7 @@ void write_tables(void) /* FIXME: The high_table_base parameter is not reference when tables are high, * or high_table_pointer >1 MB. */ -#if CONFIG_DYNAMIC_CBMEM u64 fixme_high_tables_base = 0; -#else - u64 fixme_high_tables_base = (u32)get_cbmem_toc(); -#endif /* Also put a forwarder entry into 0-4K */ new_high_table_pointer = write_coreboot_table(low_table_start, low_table_end, diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index b7b435f..2bf32ec 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM # The "eGON.BT0" header takes 32 bytes config BOOTBLOCK_BASE diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 9b0edfc..e9cbe43 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -41,7 +41,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM config BOOTBLOCK_CPU_INIT string diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 2f891ad..5cd4c65 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -36,7 +36,6 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select LAPIC_MONOTONIC_TIMER select BROKEN_CAR_MIGRATE - select DYNAMIC_CBMEM choice prompt "Rangeley CPU Stepping" diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 0597363..37ae5b3 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SMM_MODULES select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE - select DYNAMIC_CBMEM select SUPPORT_CPU_UCODE_IN_CBFS #select AP_IN_SIPI_WAIT select TSC_SYNC_MFENCE diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 1af5259..50150cf 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -75,14 +75,11 @@ static inline u32 *stack_push(u32 *stack, u32 value) static unsigned long choose_top_of_stack(void) { unsigned long stack_top; -#if CONFIG_DYNAMIC_CBMEM + /* cbmem_add() does a find() before add(). */ stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; -#else - stack_top = CONFIG_RAMTOP; -#endif return stack_top; } diff --git a/src/cpu/ti/am335x/Kconfig b/src/cpu/ti/am335x/Kconfig index eb60ad1..fae527d 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/cpu/ti/am335x/Kconfig @@ -6,7 +6,6 @@ config CPU_TI_AM335X select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE select CPU_HAS_BOOTBLOCK_INIT - select DYNAMIC_CBMEM bool default n diff --git a/src/include/cbmem.h b/src/include/cbmem.h index b1f3b5e..ea81fd0 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -118,8 +118,6 @@ struct cbmem_id_to_name { struct cbmem_entry; -#if CONFIG_DYNAMIC_CBMEM - /* * The dynamic cbmem infrastructure allows for growing cbmem dynamically as * things are added. It requires an external function, cbmem_top(), to be @@ -171,35 +169,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); -#else /* !CONFIG_DYNAMIC_CBMEM */ - -/* Allocation with static CBMEM is resolved at build time. We start - * with 128kB and conditionally add some of the most greedy CBMEM - * table entries. - */ -#define _CBMEM_SZ_MINIMAL ( 128 * 1024 ) - -#define _CBMEM_SZ_TOTAL \ - (_CBMEM_SZ_MINIMAL + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE + \ - HIGH_MEMORY_SAVE + HIGH_MEMORY_SCRATCH) - -#define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - -#ifndef __PRE_RAM__ -void cbmem_late_set_table(uint64_t base, uint64_t size); -#endif - -void get_cbmem_table(uint64_t *base, uint64_t *size); -struct cbmem_entry *get_cbmem_toc(void); - -static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) -{ - return NULL; -} -#endif /* CONFIG_DYNAMIC_CBMEM */ - -/* Common API between cbmem and dynamic cbmem. */ - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/include/rmodule.h b/src/include/rmodule.h index d229cf8..76b855a 100644 --- a/src/include/rmodule.h +++ b/src/include/rmodule.h @@ -54,7 +54,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, /* Support for loading rmodule stages. This API is only available when * using dynamic cbmem because it uses the dynamic cbmem API to obtain * the backing store region for the stage. */ -#if CONFIG_DYNAMIC_CBMEM struct cbfs_stage; struct cbmem_entry; @@ -70,7 +69,6 @@ struct rmod_stage_load { /* Both of the following functions return 0 on success, -1 on error. */ int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage); int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl); -#endif struct rmodule { void *location; diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index e35116b..c3658d2 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -74,17 +74,8 @@ ramstage-y += memrange.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_TIMER_QUEUE) += timer_queue.c -# The CBMEM implementations are chosen based on CONFIG_DYNAMIC_CBMEM. -ifeq ($(CONFIG_DYNAMIC_CBMEM),y) -ramstage-y += dynamic_cbmem.c -romstage-y += dynamic_cbmem.c -else -ramstage-y += cbmem.c -romstage-y += cbmem.c -endif # CONFIG_DYNAMIC_CBMEM - -romstage-y += cbmem_common.c -ramstage-y += cbmem_common.c +romstage-y += cbmem_common.c dynamic_cbmem.c +ramstage-y += cbmem_common.c dynamic_cbmem.c ramstage-y += hexdump.c romstage-y += hexdump.c diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c deleted file mode 100644 index 5ea8d88..0000000 --- a/src/lib/cbmem.c +++ /dev/null @@ -1,288 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA - */ - -#include <types.h> -#include <string.h> -#include <bootmem.h> -#include <bootstate.h> -#include <cbmem.h> -#include <console/console.h> -#include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) -#include <arch/acpi.h> -#endif - -// The CBMEM TOC reserves 512 bytes to keep -// the other entries somewhat aligned. -// Increase if MAX_CBMEM_ENTRIES exceeds 21 -#define CBMEM_TOC_RESERVED 512 -#define MAX_CBMEM_ENTRIES 16 -#define CBMEM_MAGIC 0x434f5245 - -struct cbmem_entry { - u32 magic; - u32 id; - u64 base; - u64 size; -} __attribute__((packed)); - -#ifndef __PRE_RAM__ -static uint64_t cbmem_base = 0; -static uint64_t cbmem_size = 0; -#endif - -static void cbmem_trace_location(uint64_t base, uint64_t size, const char *s) -{ - if (base && size && s) { - printk(BIOS_DEBUG, "CBMEM region %llx-%llx (%s)\n", - base, base + size - 1, s); - } -} - -static void cbmem_locate_table(uint64_t *base, uint64_t *size) -{ -#ifdef __PRE_RAM__ - get_cbmem_table(base, size); -#else - if (!(cbmem_base && cbmem_size)) { - get_cbmem_table(&cbmem_base, &cbmem_size); - cbmem_trace_location(cbmem_base, cbmem_size, __FUNCTION__); - } - *base = cbmem_base; - *size = cbmem_size; -#endif -} - -struct cbmem_entry *get_cbmem_toc(void) -{ - uint64_t base, size; - cbmem_locate_table(&base, &size); - return (struct cbmem_entry *)(unsigned long)base; -} - -#if !defined(__PRE_RAM__) -void cbmem_late_set_table(uint64_t base, uint64_t size) -{ - cbmem_trace_location(base, size, __FUNCTION__); - cbmem_base = base; - cbmem_size = size; -} -#endif - -/** - * cbmem is a simple mechanism to do some kind of book keeping of the coreboot - * high tables memory. This is a small amount of memory which is "stolen" from - * the system memory for coreboot purposes. Usually this memory is used for - * - the coreboot table - * - legacy tables (PIRQ, MP table) - * - ACPI tables - * - suspend/resume backup memory - */ - -static void cbmem_initialize_empty(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - if (!(baseaddr && size)) { - printk(BIOS_CRIT, "Unable to set location for CBMEM.\n"); - return; - } - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); - - cbmem_toc[0] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = CBMEM_ID_FREESPACE, - .base = baseaddr + CBMEM_TOC_RESERVED, - .size = size - CBMEM_TOC_RESERVED - }; -} - -static int cbmem_check_toc(void) -{ - uint64_t baseaddr, size; - struct cbmem_entry *cbmem_toc; - - cbmem_locate_table(&baseaddr, &size); - cbmem_trace_location(baseaddr, size, __FUNCTION__); - - cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - - return (cbmem_toc[0].magic == CBMEM_MAGIC); -} - -void *cbmem_add(u32 id, u64 size) -{ - struct cbmem_entry *cbmem_toc; - int i; - void *p; - - /* - * This could be a restart, check if the section is there already. It - * is remotely possible that the dram contents persisted over the - * bootloader upgrade AND the same section now needs more room, but - * this is quite a remote possibility and it is ignored here. - */ - p = cbmem_find(id); - if (p) { - printk(BIOS_NOTICE, - "CBMEM section %x: using existing location at %p.\n", - id, p); - return p; - } - - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) { - return NULL; - } - - if (cbmem_toc[0].magic != CBMEM_MAGIC) { - printk(BIOS_ERR, "ERROR: CBMEM was not initialized yet.\n"); - return NULL; - } - - /* Will the entry fit at all? */ - if (size > cbmem_toc[0].size) { - printk(BIOS_ERR, "ERROR: Not enough memory for table %x\n", id); - return NULL; - } - - /* Align size to 512 byte blocks */ - - size = ALIGN(size, 512) < cbmem_toc[0].size ? - ALIGN(size, 512) : cbmem_toc[0].size; - - /* Now look for the first free/usable TOC entry */ - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == CBMEM_ID_NONE) - break; - } - - if (i >= MAX_CBMEM_ENTRIES) { - printk(BIOS_ERR, "ERROR: No more CBMEM entries available.\n"); - return NULL; - } - - printk(BIOS_DEBUG, "Adding CBMEM entry as no. %d\n", i); - - cbmem_toc[i] = (struct cbmem_entry) { - .magic = CBMEM_MAGIC, - .id = id, - .base = cbmem_toc[0].base, - .size = size - }; - - cbmem_toc[0].base += size; - cbmem_toc[0].size -= size; - - return (void *)(uintptr_t)cbmem_toc[i].base; -} - -void *cbmem_find(u32 id) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return NULL; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - if (cbmem_toc[i].id == id) - return (void *)(unsigned long)cbmem_toc[i].base; - } - - return (void *)NULL; -} - -/* Returns True if it was not initialized before. */ -int cbmem_recovery(int is_wakeup) -{ - int found = cbmem_check_toc(); - int wipe = 0; - - /* CBMEM TOC is wiped clean when we are not waking up from S3 - * suspend. Boards with EARLY_CBMEM_INIT do this in romstage, - * boards without EARLY_CBMEM_INIT do this in ramstage. - */ -#if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif -#if !defined(__PRE_RAM__) && !CONFIG_EARLY_CBMEM_INIT - wipe = 1; -#endif - - if (!is_wakeup && wipe) - cbmem_initialize_empty(); - - if (is_wakeup && !found) { - cbmem_initialize_empty(); - cbmem_fail_resume(); - } - - /* Complete migration to CBMEM. */ - cbmem_arch_init(); - - return !found; -} - -#ifndef __PRE_RAM__ -static void init_cbmem_post_device(void *unused) -{ -#if CONFIG_HAVE_ACPI_RESUME - cbmem_recovery(acpi_is_wakeup()); -#else - cbmem_recovery(0); -#endif -} - -BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { - BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, - init_cbmem_post_device, NULL), -}; - -void cbmem_add_bootmem(void) -{ - bootmem_add_range(cbmem_base, cbmem_size, LB_MEM_TABLE); -} - -void cbmem_list(void) -{ - struct cbmem_entry *cbmem_toc; - int i; - cbmem_toc = get_cbmem_toc(); - - if (cbmem_toc == NULL) - return; - - for (i = 0; i < MAX_CBMEM_ENTRIES; i++) { - - if (cbmem_toc[i].magic != CBMEM_MAGIC) - continue; - cbmem_print_entry(i, cbmem_toc[i].id, cbmem_toc[i].base, - cbmem_toc[i].size); - } -} -#endif diff --git a/src/lib/rmodule.c b/src/lib/rmodule.c index 908297b..5c6df02 100644 --- a/src/lib/rmodule.c +++ b/src/lib/rmodule.c @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ #include <assert.h> +#include <cbmem.h> +#include <cbfs_core.h> #include <stdint.h> #include <stdlib.h> #include <string.h> @@ -249,10 +251,6 @@ int rmodule_calc_region(unsigned int region_alignment, size_t rmodule_size, return region_alignment - sizeof(struct rmodule_header); } -#if CONFIG_DYNAMIC_CBMEM -#include <cbmem.h> -#include <cbfs_core.h> - int rmodule_stage_load(struct rmod_stage_load *rsl, struct cbfs_stage *stage) { struct rmodule rmod_stage; @@ -307,5 +305,3 @@ int rmodule_stage_load_from_cbfs(struct rmod_stage_load *rsl) return rmodule_stage_load(rsl, stage); } - -#endif /* DYNAMIC_CBMEM */ diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 7e24a20..b275e88 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARM_ROMSTAGE_ARMV7 select ARM_RAMSTAGE_ARMV7 select BOARD_ROMSIZE_KB_4096 - select DYNAMIC_CBMEM config MAINBOARD_DIR string diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index b002c21..406612e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -8,7 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c index 4931523..08d563f 100644 --- a/src/mainboard/emulation/qemu-i440fx/northbridge.c +++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c @@ -130,10 +130,6 @@ static void cpu_pci_domain_read_resources(struct device *dev) "debugcon"); } -#if !CONFIG_DYNAMIC_CBMEM - set_top_of_ram(tomk * 1024); -#endif - if (q35 && ((tomk * 1024) < 0xb0000000)) { /* * Reserve the region between top-of-ram and the diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 3949937..fcc750c 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 - select DYNAMIC_CBMEM select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index fa08acc..a804fd3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select DYNAMIC_CBMEM select INTEL_INT15 select VGA select INTEL_EDID diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index fac7329..096c80f 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -27,7 +27,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select HAVE_DEBUG_RAM_SETUP select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select IOMMU select VGA select INTEL_EDID diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index c578011..8a0cb5b 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index b49f331..ca5ffa5 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_NEHALEM select CPU_INTEL_MODEL_2065X select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 647b4fb..11370f5 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -22,7 +22,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select PER_DEVICE_ACPI_TABLES @@ -31,7 +30,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES @@ -41,7 +39,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select PER_DEVICE_ACPI_TABLES @@ -50,7 +47,6 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE select CACHE_MRC_BIN select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select DYNAMIC_CBMEM select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select PER_DEVICE_ACPI_TABLES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index bcaa1ff..28dc7d7 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -16,7 +16,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index b93216e..2c5ebd3 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select COLLECT_TIMESTAMPS select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select SUPPORT_CPU_UCODE_IN_CBFS - select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index b61fac3..081ea09 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,8 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_BOOTBLOCK_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 - select DYNAMIC_CBMEM - select BROKEN_CAR_MIGRATE select HAVE_SMI_HANDLER select HAVE_HARD_RESET select MMCONF_SUPPORT diff --git a/src/soc/nvidia/tegra124/Kconfig b/src/soc/nvidia/tegra124/Kconfig index 195261e..89d07c5 100644 --- a/src/soc/nvidia/tegra124/Kconfig +++ b/src/soc/nvidia/tegra124/Kconfig @@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA124 select ARCH_RAMSTAGE_ARMV7 select HAVE_UART_SPECIAL select BOOTBLOCK_CONSOLE - select DYNAMIC_CBMEM select ARM_BOOTBLOCK_CUSTOM select ARM_LPAE diff --git a/src/soc/samsung/exynos5250/Kconfig b/src/soc/samsung/exynos5250/Kconfig index 8d7c867..9cbd37f 100644 --- a/src/soc/samsung/exynos5250/Kconfig +++ b/src/soc/samsung/exynos5250/Kconfig @@ -5,7 +5,6 @@ config CPU_SAMSUNG_EXYNOS5250 select CPU_HAS_BOOTBLOCK_INIT select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/samsung/exynos5420/Kconfig b/src/soc/samsung/exynos5420/Kconfig index 904091e..c9f2ec6 100644 --- a/src/soc/samsung/exynos5420/Kconfig +++ b/src/soc/samsung/exynos5420/Kconfig @@ -6,7 +6,6 @@ config CPU_SAMSUNG_EXYNOS5420 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL select RELOCATABLE_MODULES - select DYNAMIC_CBMEM bool default n diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index be4a675..d1e4ba7 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -3,7 +3,6 @@ config SOC_UCB_RISCV select ARCH_BOOTBLOCK_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV - select DYNAMIC_CBMEM bool default n

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coreboot-gerrit January 2015