coreboot-gerrit January 2015

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Patch set updated for coreboot: 45b3ba5 CBMEM: Move cbmemc_reinit()
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7859 -gerrit commit 45b3ba59e9947cd3ce29fcd81fb469964d98fb02 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 19:29:02 2014 +0200 CBMEM: Move cbmemc_reinit() This replaces need for separate cbmemc_reinit() calls made via CAR_MIGRATE() and in ramstage. Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem.c | 2 -- src/lib/cbmem_common.c | 5 +++++ src/lib/dynamic_cbmem.c | 2 -- src/mainboard/google/nyan/romstage.c | 5 ----- src/mainboard/google/nyan_big/romstage.c | 5 ----- src/mainboard/google/nyan_blaze/romstage.c | 5 ----- src/mainboard/via/epia-m850/romstage.c | 1 - src/soc/intel/fsp_baytrail/romstage/romstage.c | 1 - 9 files changed, 9 insertions(+), 21 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 15f35c2..389b382 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -22,6 +22,7 @@ /* FIXME: Remove after CBMEM_INIT_HOOKS. */ #include <cpu/x86/gdt.h> +#include <console/cbmem_console.h> #if !CONFIG_DYNAMIC_CBMEM void get_cbmem_table(uint64_t *base, uint64_t *size) @@ -75,6 +76,9 @@ void *cbmem_top(void) void cbmem_arch_init(void) { #if !defined(__PRE_RAM__) + /* Relocate CBMEM console. */ + cbmemc_reinit(); + move_gdt(); #endif } diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 0b24ad2..f8077b6 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -23,7 +23,6 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> -#include <console/cbmem_console.h> #include <arch/early_variables.h> #if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) #include <arch/acpi.h> @@ -256,7 +255,6 @@ static void init_cbmem_post_device(void *unused) #else cbmem_recovery(0); #endif - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index a07916a..17ca7cb 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -20,6 +20,9 @@ #include <cbmem.h> #include <stdlib.h> +/* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <console/cbmem_console.h> + #ifndef __PRE_RAM__ static const struct cbmem_id_to_name cbmem_ids[] = { CBMEM_ID_TO_NAME_TABLE }; @@ -51,6 +54,8 @@ void cbmem_print_entry(int n, u32 id, u64 base, u64 size) /* FIXME: Replace with CBMEM_INIT_HOOKS. */ void attribute((__weak__)) cbmem_arch_init(void) { + /* Relocate CBMEM console. */ + cbmemc_reinit(); } void attribute((__weak__)) cbmem_fail_resume(void) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 5eddbca..dd3e9f2 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,7 +21,6 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> @@ -426,7 +425,6 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) static void init_cbmem_pre_device(void *unused) { cbmem_initialize(); - cbmemc_reinit(); } BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..749b87d 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -25,7 +25,6 @@ #include <device/device.h> #include <cbfs.h> #include <cbmem.h> -#include <console/cbmem_console.h> #include <console/console.h> #include <mainboard/google/nyan/reset.h> #include <romstage_handoff.h> @@ -224,10 +223,6 @@ static void __attribute__((noinline)) romstage(void) configure_ec_spi_bus(); configure_tpm_i2c_bus(); -#if CONFIG_CONSOLE_CBMEM - cbmemc_reinit(); -#endif - vboot_verify_firmware(romstage_handoff_find_or_add()); timestamp_add(TS_START_COPYRAM, timestamp_get()); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 899c5a6..7eb8d60 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/bist.h> #include <string.h> #include <timestamp.h> -#include <console/cbmem_console.h> #include "northbridge/via/vx900/early_vx900.h" #include "northbridge/via/vx900/raminit.h" diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 2619c96..f4442ac 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -43,7 +43,6 @@ #include <version.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> -#include <console/cbmem_console.h> /* Return 0, 3, 4 or 5 to indicate the previous sleep state. */ uint32_t chipset_prev_sleep_state(uint32_t clear)

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Patch set updated for coreboot: 4f44707 CBMEM: Tidy up CAR migration
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7860 -gerrit commit 4f44707196d177cd720f913115093abbb697b977 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 20:55:19 2014 +0200 CBMEM: Tidy up CAR migration Move the CAR migration call to arch -specific part of CBMEM init, it is truly a x86 specific thing. Change-Id: I715417e54f197b8745e0670d6b900a5660178141 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 14 -------------- src/arch/arm/include/arch/early_variables.h | 1 - src/arch/arm64/include/arch/early_variables.h | 5 ----- src/arch/riscv/include/arch/early_variables.h | 5 ----- src/arch/x86/Kconfig | 15 +++++++++++++++ src/arch/x86/boot/cbmem.c | 4 ++++ src/lib/cbmem.c | 3 ++- src/lib/dynamic_cbmem.c | 10 ++-------- 8 files changed, 23 insertions(+), 34 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index c9a04a4..cf66598 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -159,20 +159,6 @@ config INCLUDE_CONFIG_FILE config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT -config LATE_CBMEM_INIT - def_bool n - help - Enable this in chipset's Kconfig if northbridge does not implement - early get_top_of_ram() call for romstage. CBMEM tables will be - allocated late in ramstage, after PCI devices resources are known. - -config BROKEN_CAR_MIGRATE - def_bool LATE_CBMEM_INIT - help - Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and - manage CAR migration on S3 resume path only. Couple boards use - CAR_GLOBAL and never do CAR migration. - config DYNAMIC_CBMEM bool default n diff --git a/src/arch/arm/include/arch/early_variables.h b/src/arch/arm/include/arch/early_variables.h index 5b58baa..539b572 100644 --- a/src/arch/arm/include/arch/early_variables.h +++ b/src/arch/arm/include/arch/early_variables.h @@ -26,6 +26,5 @@ static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/arm64/include/arch/early_variables.h b/src/arch/arm64/include/arch/early_variables.h index 3d9fa26..539b572 100644 --- a/src/arch/arm64/include/arch/early_variables.h +++ b/src/arch/arm64/include/arch/early_variables.h @@ -20,16 +20,11 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if CONFIG_CAR_MIGRATION - #error "This is ARM, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/riscv/include/arch/early_variables.h b/src/arch/riscv/include/arch/early_variables.h index 3a1f20d..539b572 100644 --- a/src/arch/riscv/include/arch/early_variables.h +++ b/src/arch/riscv/include/arch/early_variables.h @@ -20,16 +20,11 @@ #ifndef ARCH_EARLY_VARIABLES_H #define ARCH_EARLY_VARIABLES_H -#if defined(CONFIG_CAR_MIGRATION) && CONFIG_CAR_MIGRATION - #error "This is RISCV, silly... we don't have CAR here." -#endif - #define CAR_GLOBAL #define CAR_MIGRATE(migrate_fn_) static inline void *car_get_var_ptr(void *var) { return var; } #define car_get_var(var) (var) #define car_set_var(var, val) do { (var) = (val); } while (0) -static inline void car_migrate_variables(void) { } #endif diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index 56d8f88..b6791ed 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -47,6 +47,21 @@ config ROMCC bool default n +config BROKEN_CAR_MIGRATE + def_bool n + help + Many boards use CAR_GLOBAL but have no EARLY_CBMEM_INIT and + manage CAR migration on S3 resume path only. Couple boards use + CAR_GLOBAL and never do CAR migration. + +config LATE_CBMEM_INIT + def_bool n + select BROKEN_CAR_MIGRATE + help + Enable this in chipset's Kconfig if northbridge does not implement + early get_top_of_ram() call for romstage. CBMEM tables will be + allocated late in ramstage, after PCI devices resources are known. + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 79cf46c..750e8b2 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -21,6 +21,7 @@ #include <arch/acpi.h> /* FIXME: Remove after CBMEM_INIT_HOOKS. */ +#include <arch/early_variables.h> #include <cpu/x86/gdt.h> #include <console/cbmem_console.h> #include <timestamp.h> @@ -76,6 +77,9 @@ void *cbmem_top(void) void cbmem_arch_init(void) { + /* Migrate car.global_data. */ + car_migrate_variables(); + #if !defined(__PRE_RAM__) /* Relocate CBMEM console. */ cbmemc_reinit(); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index f8077b6..5ea8d88 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -242,8 +242,9 @@ int cbmem_recovery(int is_wakeup) cbmem_fail_resume(); } + /* Complete migration to CBMEM. */ cbmem_arch_init(); - car_migrate_variables(); + return !found; } diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index dd3e9f2..fbd6148 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -170,18 +170,14 @@ void cbmem_initialize_empty(void) printk(BIOS_DEBUG, "CBMEM: root @ %p %d entries.\n", root, root->max_entries); + /* Complete migration to CBMEM. */ cbmem_arch_init(); - - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); } static inline int cbmem_fail_recovery(void) { cbmem_initialize_empty(); cbmem_fail_resume(); - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); return 1; } @@ -248,11 +244,9 @@ int cbmem_initialize(void) root->locked = 1; #endif + /* Complete migration to CBMEM. */ cbmem_arch_init(); - /* Migrate cache-as-ram variables. */ - car_migrate_variables(); - /* Recovery successful. */ return 0; }

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Patch set updated for coreboot: 6aba439 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7861 -gerrit commit 6aba4396e56dfc4b7173dd54ac813429c3e47837 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 19 08:20:45 2014 +0200 CBMEM: Support DYNAMIC_CBMEM with LATE_CBMEM_INIT We can now create CBMEM with dynamic allocation even if CBMEM location is resolved late in ramstage. TODO: Handle case of get_top_of_ram() returning 0. Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 3 +-- src/arch/x86/boot/cbmem.c | 14 +++++++++----- src/include/cbmem.h | 19 +++++++++++++------ src/lib/cbmem_console.c | 2 +- src/lib/dynamic_cbmem.c | 32 ++++++++++++++++++++++++++++---- 5 files changed, 52 insertions(+), 18 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index cf66598..73cd803 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -162,7 +162,6 @@ config EARLY_CBMEM_INIT config DYNAMIC_CBMEM bool default n - select EARLY_CBMEM_INIT help Instead of reserving a static amount of CBMEM space the CBMEM area grows dynamically. CBMEM can be used both in romstage (after @@ -201,7 +200,7 @@ config RELOCATABLE_MODULES loaded anywhere and all the relocations are handled automatically. config RELOCATABLE_RAMSTAGE - depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM) + depends on (RELOCATABLE_MODULES && DYNAMIC_CBMEM && EARLY_CBMEM_INIT) bool "Build the ramstage to be relocatable in 32-bit address space." default n help diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index d75845d..7d7ec3d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -39,6 +39,9 @@ void get_cbmem_table(uint64_t *base, uint64_t *size) *size = 0; } } +#endif /* !DYNAMIC_CBMEM */ + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if !defined(__PRE_RAM__) void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) @@ -46,14 +49,14 @@ void __attribute__((weak)) backup_top_of_ram(uint64_t ramtop) /* Do nothing. Chipset may have implementation to save ramtop in NVRAM. */ } -/* This is for compatibility with old boards only. Any new chipset and board - * must implement get_top_of_ram() for both romstage and ramstage to support - * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. - */ void set_top_of_ram(uint64_t ramtop) { backup_top_of_ram(ramtop); +#if !CONFIG_DYNAMIC_CBMEM cbmem_late_set_table(ramtop - HIGH_MEMORY_SIZE, HIGH_MEMORY_SIZE); +#else + cbmem_set_top((void*)(uintptr_t)ramtop); +#endif } #endif /* !__PRE_RAM__ */ @@ -70,7 +73,8 @@ void *cbmem_top(void) return (void *)get_top_of_ram(); } #endif -#endif /* !DYNAMIC_CBMEM */ + +#endif /* LATE_CBMEM_INIT */ void cbmem_arch_init(void) { diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 1b7f307..b1f3b5e 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -151,6 +151,9 @@ void cbmem_initialize_empty(void); * below 4GiB. */ void *cbmem_top(void); +/* Set the top address for dynamic cbmem. Not for new designs. */ +void cbmem_set_top(void *ramtop); + /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ @@ -168,7 +171,6 @@ int cbmem_entry_remove(const struct cbmem_entry *entry); void *cbmem_entry_start(const struct cbmem_entry *entry); u64 cbmem_entry_size(const struct cbmem_entry *entry); - #else /* !CONFIG_DYNAMIC_CBMEM */ /* Allocation with static CBMEM is resolved at build time. We start @@ -183,15 +185,10 @@ u64 cbmem_entry_size(const struct cbmem_entry *entry); #define HIGH_MEMORY_SIZE ALIGN_UP(_CBMEM_SZ_TOTAL, 0x10000) - #ifndef __PRE_RAM__ -void set_top_of_ram(uint64_t ramtop); -void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif -unsigned long get_top_of_ram(void); - void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -224,6 +221,16 @@ void cbmem_list(void); void cbmem_print_entry(int n, u32 id, u64 start, u64 size); #endif /* __PRE_RAM__ */ +/* These are for compatibility with old boards only. Any new chipset and board + * must implement cbmem_top() for both romstage and ramstage to support + * early features like COLLECT_TIMESTAMPS and CBMEM_CONSOLE. + */ +#if IS_ENABLED(CONFIG_ARCH_X86) && IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +unsigned long get_top_of_ram(void); +void set_top_of_ram(uint64_t ramtop); +void backup_top_of_ram(uint64_t ramtop); +#endif + #endif /* __ASSEMBLER__ */ diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 5f8ff0c..b1aeedd 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -58,7 +58,7 @@ extern struct cbmem_console preram_cbmem_console; * during the ROM stage, once CBMEM becomes available at RAM stage. */ -#if CONFIG_DYNAMIC_CBMEM +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #define STATIC_CONSOLE_SIZE 1024 #else #define STATIC_CONSOLE_SIZE CONFIG_CONSOLE_CBMEM_BUFFER_SIZE diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index fbd6148..5fa7211 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -24,10 +24,9 @@ #include <string.h> #include <stdlib.h> #include <arch/early_variables.h> -#if CONFIG_HAVE_ACPI_RESUME && !defined(__PRE_RAM__) +#if IS_ENABLED(CONFIG_ARCH_X86) && !IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) #include <arch/acpi.h> #endif - #ifndef UINT_MAX #define UINT_MAX 4294967295U #endif @@ -69,11 +68,18 @@ struct cbmem_root { } __attribute__((packed)); +#if !defined(__PRE_RAM__) +static void *cached_cbmem_top; + +void cbmem_set_top(void * ramtop) +{ + cached_cbmem_top = ramtop; +} +#endif + static inline void *cbmem_top_cached(void) { #if !defined(__PRE_RAM__) - static void *cached_cbmem_top; - if (cached_cbmem_top == NULL) cached_cbmem_top = cbmem_top(); @@ -413,6 +419,8 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) #if !defined(__PRE_RAM__) + +#if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) /* selected cbmem can be initialized early in ramstage. Additionally, that * means cbmem console can be reinitialized early as well. The post_device * function is empty since cbmem was initialized early in ramstage. */ @@ -426,6 +434,22 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { init_cbmem_pre_device, NULL), }; +#else + +static void init_cbmem_post_device(void *unused) +{ + if (acpi_is_wakeup()) + cbmem_initialize(); + else + cbmem_initialize_empty(); +} + +BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, + init_cbmem_post_device, NULL), +}; +#endif + void cbmem_add_bootmem(void) { unsigned long base;

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Patch set updated for coreboot: c22bf3b CBMEM console: Fix and enhance pre-RAM support
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7862 -gerrit commit c22bf3b40bdffe03bce262cf1669af8d68dae69c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 21 08:55:47 2014 +0200 CBMEM console: Fix and enhance pre-RAM support Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can do CBMEM console in bootblock and romstage. Kconfig forces it to zero if _BASE is unset or we cannot do CAR migration on x86. Add CBMEM console to bootblock, except for x86. Only one of bootblock and romstage clears the pre-RAM buffer. To start with empty console log on S3 wakeup, ramstage now clears previous contents of CBMEM buffer if there was no pre-RAM buffer. Unify Kconfig variable naming. TODO: ARM configurations do not define PRERAM_BUFFER_BASE values. Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/Kconfig | 4 -- src/arch/arm/bootblock.ld | 2 +- src/arch/arm/romstage.ld | 2 +- src/arch/arm64/bootblock.ld | 2 + src/arch/arm64/romstage.ld | 2 +- src/arch/riscv/romstage.ld | 2 +- src/console/Kconfig | 12 +++++- src/include/console/cbmem_console.h | 3 +- src/lib/Makefile.inc | 1 + src/lib/cbmem_console.c | 79 +++++++++++++++++++++---------------- 10 files changed, 63 insertions(+), 46 deletions(-) diff --git a/src/arch/arm/Kconfig b/src/arch/arm/Kconfig index e946f59..edc4b12 100644 --- a/src/arch/arm/Kconfig +++ b/src/arch/arm/Kconfig @@ -20,10 +20,6 @@ config ARM_BOOTBLOCK_CUSTOM bool default n -config CBMEM_CONSOLE_PRERAM_BASE - hex - depends on CONSOLE_CBMEM - config CPU_HAS_BOOTBLOCK_INIT bool default n diff --git a/src/arch/arm/bootblock.ld b/src/arch/arm/bootblock.ld index 150bf2d..c355348 100644 --- a/src/arch/arm/bootblock.ld +++ b/src/arch/arm/bootblock.ld @@ -49,7 +49,7 @@ SECTIONS *(.sbss.*); } : to_load = 0xff - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /DISCARD/ : { *(.comment) diff --git a/src/arch/arm/romstage.ld b/src/arch/arm/romstage.ld index 8c32046..34e9eaa 100644 --- a/src/arch/arm/romstage.ld +++ b/src/arch/arm/romstage.ld @@ -69,7 +69,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/arm64/bootblock.ld b/src/arch/arm64/bootblock.ld index acce1f1..907d009 100644 --- a/src/arch/arm64/bootblock.ld +++ b/src/arch/arm64/bootblock.ld @@ -49,6 +49,8 @@ SECTIONS *(.sbss.*); } : to_load = 0xff + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; + /DISCARD/ : { *(.comment) *(.note) diff --git a/src/arch/arm64/romstage.ld b/src/arch/arm64/romstage.ld index d05fdd1..a8d092c 100644 --- a/src/arch/arm64/romstage.ld +++ b/src/arch/arm64/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE; + preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE; /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/arch/riscv/romstage.ld b/src/arch/riscv/romstage.ld index 839c285..a58aee3 100644 --- a/src/arch/riscv/romstage.ld +++ b/src/arch/riscv/romstage.ld @@ -76,7 +76,7 @@ SECTIONS _end = .; - /*preram_cbmem_console = CONFIG_CBMEM_CONSOLE_PRERAM_BASE;*/ + /*preram_cbmem_console = CONFIG_CONSOLE_PRERAM_BUFFER_BASE;*/ /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/console/Kconfig b/src/console/Kconfig index 0d32011..6d9bf1e 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -175,8 +175,9 @@ config CONSOLE_CBMEM Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space. +if CONSOLE_CBMEM + config CONSOLE_CBMEM_BUFFER_SIZE - depends on CONSOLE_CBMEM hex "Room allocated for console output in CBMEM" default 0x20000 help @@ -184,16 +185,23 @@ config CONSOLE_CBMEM_BUFFER_SIZE value (128K or 0x20000 bytes) is large enough to accommodate even the BIOS_SPEW level. +config CONSOLE_PRERAM_BUFFER_BASE + hex + default 0xabadbeef if !CACHE_AS_RAM || BROKEN_CAR_MIGRATE + default 0x0 + config CONSOLE_PRERAM_BUFFER_SIZE - depends on CONSOLE_CBMEM hex "Room allocated for console output before RAM is initialized" default 0xc00 + depends on CONSOLE_PRERAM_BUFFER_BASE != 0xabadbeef help Console is used before RAM is initialized. This is the room reserved in the DCACHE based RAM, SRAM, etc. to keep console output before it can be saved in a CBMEM buffer. 3K bytes should be enough even for the BIOS_SPEW level. +endif + config CONSOLE_QEMU_DEBUGCON bool "QEMU debug console output" depends on BOARD_EMULATION_QEMU_X86 diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 36d132c..81bc10f 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -32,7 +32,8 @@ static inline void cbmemc_reinit(void) {} #endif #define __CBMEM_CONSOLE_ENABLE__ CONFIG_CONSOLE_CBMEM && \ - ((ENV_ROMSTAGE && !CONFIG_BROKEN_CAR_MIGRATE) || ENV_RAMSTAGE) + (ENV_RAMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE && \ + ((ENV_BOOTBLOCK && CONFIG_BOOTBLOCK_CONSOLE) || ENV_ROMSTAGE))) #if __CBMEM_CONSOLE_ENABLE__ static inline void __cbmemc_init(void) { cbmemc_init(); } diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index ec3c2f4..e35116b 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += loaders bootblock-y += cbfs.c cbfs_core.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c +bootblock-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c bootblock-y += memchr.c bootblock-y += memcmp.c diff --git a/src/lib/cbmem_console.c b/src/lib/cbmem_console.c index 630d9c9..5f8ff0c 100644 --- a/src/lib/cbmem_console.c +++ b/src/lib/cbmem_console.c @@ -37,6 +37,9 @@ struct cbmem_console { static struct cbmem_console *cbmem_console_p CAR_GLOBAL; +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p); + #ifdef __PRE_RAM__ /* * While running from ROM, before DRAM is initialized, some area in cache as @@ -63,6 +66,10 @@ extern struct cbmem_console preram_cbmem_console; static u8 static_console[STATIC_CONSOLE_SIZE]; #endif +/* flags for init */ +#define CBMEMC_RESET (1<<0) +#define CBMEMC_APPEND (1<<1) + static inline struct cbmem_console *current_console(void) { struct cbmem_console *cbm_cons_p = car_get_var(cbmem_console_p); @@ -79,27 +86,45 @@ static inline void current_console_set(struct cbmem_console *new_console_p) car_set_var(cbmem_console_p, new_console_p); } -static inline void init_console_ptr(void *storage, u32 total_space) +static inline void init_console_ptr(void *storage, u32 total_space, int flags) { struct cbmem_console *cbm_cons_p = storage; - /* Initialize the cache-as-ram pointer and underlying structure. */ - car_set_var(cbmem_console_p, cbm_cons_p); - cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); - cbm_cons_p->buffer_cursor = 0; + if (!cbm_cons_p) { + current_console_set(NULL); + return; + } + + if (flags & CBMEMC_RESET) { + cbm_cons_p->buffer_size = total_space - sizeof(struct cbmem_console); + cbm_cons_p->buffer_cursor = 0; + } + if (flags & CBMEMC_APPEND) { + struct cbmem_console *tmp_cons_p = current_console(); + if (tmp_cons_p) + copy_console_buffer(tmp_cons_p, cbm_cons_p); + } + + current_console_set(cbm_cons_p); } void cbmemc_init(void) { #ifdef __PRE_RAM__ + int flags = CBMEMC_RESET; + + /* Do not clear output from bootblock. */ + if (ENV_ROMSTAGE && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) + flags = 0; + init_console_ptr(&preram_cbmem_console, - CONFIG_CONSOLE_PRERAM_BUFFER_SIZE); + CONFIG_CONSOLE_PRERAM_BUFFER_SIZE, flags); #else /* * Initializing before CBMEM is available, use static buffer to store * the log. */ - init_console_ptr(static_console, sizeof(static_console)); + init_console_ptr(static_console, sizeof(static_console), CBMEMC_RESET); #endif } @@ -125,13 +150,11 @@ void cbmemc_tx_byte(unsigned char data) * If there is overflow - add to the destination area a string, reporting the * overflow and the number of dropped characters. */ -static void copy_console_buffer(struct cbmem_console *new_cons_p) +static void copy_console_buffer(struct cbmem_console *old_cons_p, + struct cbmem_console *new_cons_p) { u32 copy_size, dropped_chars; u32 cursor = new_cons_p->buffer_cursor; - struct cbmem_console *old_cons_p; - - old_cons_p = current_console(); if (old_cons_p->buffer_cursor < old_cons_p->buffer_size) copy_size = old_cons_p->buffer_cursor; @@ -193,35 +216,21 @@ static void copy_console_buffer(struct cbmem_console *new_cons_p) void cbmemc_reinit(void) { struct cbmem_console *cbm_cons_p = NULL; + int flags = CBMEMC_APPEND; -#ifdef __PRE_RAM__ - if (IS_ENABLED(CONFIG_BROKEN_CAR_MIGRATE)) + if (ENV_ROMSTAGE && (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) return; -#endif - -#ifndef __PRE_RAM__ - cbm_cons_p = cbmem_find(CBMEM_ID_CONSOLE); -#endif - - if (!cbm_cons_p) { - cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, - CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - - if (!cbm_cons_p) { - current_console_set(NULL); - return; - } - cbm_cons_p->buffer_size = CONFIG_CONSOLE_CBMEM_BUFFER_SIZE - - sizeof(struct cbmem_console); + /* If CBMEM entry already existed, old contents is not altered. */ + cbm_cons_p = cbmem_add(CBMEM_ID_CONSOLE, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE); - cbm_cons_p->buffer_cursor = 0; - } + /* Clear old contents of CBMEM buffer. */ + if (ENV_ROMSTAGE || (CONFIG_CONSOLE_PRERAM_BUFFER_SIZE == 0)) + flags |= CBMEMC_RESET; - copy_console_buffer(cbm_cons_p); - - current_console_set(cbm_cons_p); + init_console_ptr(cbm_cons_p, + CONFIG_CONSOLE_CBMEM_BUFFER_SIZE, flags); } - /* Call cbmemc_reinit() at CAR migration time. */ CAR_MIGRATE(cbmemc_reinit)

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Patch set updated for coreboot: 0ad4bcb CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7888 -gerrit commit 0ad4bcb123b6f59ac3b54cf35b243b82e97068f8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 22 12:28:07 2014 +0200 CBMEM: Do not use get_top_of_ram() with DYNAMIC_CBMEM The name was always obscure and confusing. Instead define cbmem_top() directly in the chipset code for x86 like on ARMs. TODO: Check TSEG alignment, it used for MTRR programming. Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/boot/cbmem.c | 9 ++--- src/cpu/intel/haswell/romstage.c | 4 +- src/include/cbmem.h | 4 +- src/mainboard/emulation/qemu-i440fx/memory.c | 4 +- src/northbridge/intel/fsp_rangeley/raminit.c | 14 ++++--- src/northbridge/intel/fsp_sandybridge/Makefile.inc | 2 + .../intel/fsp_sandybridge/northbridge.c | 10 ----- src/northbridge/intel/fsp_sandybridge/ram_calc.c | 38 +++++++++++++++++ src/northbridge/intel/fsp_sandybridge/raminit.c | 8 ---- src/northbridge/intel/gm45/ram_calc.c | 7 +++- src/northbridge/intel/haswell/ram_calc.c | 11 +++-- src/northbridge/intel/i945/ram_calc.c | 11 +++-- src/northbridge/intel/nehalem/ram_calc.c | 11 +++-- src/northbridge/intel/sandybridge/ram_calc.c | 11 +++-- src/soc/intel/baytrail/baytrail/smm.h | 2 +- src/soc/intel/baytrail/memmap.c | 8 ++-- src/soc/intel/broadwell/memmap.c | 13 ++++-- src/soc/intel/fsp_baytrail/Makefile.inc | 2 - src/soc/intel/fsp_baytrail/baytrail/smm.h | 2 +- src/soc/intel/fsp_baytrail/memmap.c | 22 +++++++++- src/soc/intel/fsp_baytrail/raminit.c | 47 ---------------------- 21 files changed, 131 insertions(+), 109 deletions(-) diff --git a/src/arch/x86/boot/cbmem.c b/src/arch/x86/boot/cbmem.c index 750e8b2..d75845d 100644 --- a/src/arch/x86/boot/cbmem.c +++ b/src/arch/x86/boot/cbmem.c @@ -57,23 +57,20 @@ void set_top_of_ram(uint64_t ramtop) } #endif /* !__PRE_RAM__ */ -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) unsigned long __attribute__((weak)) get_top_of_ram(void) { printk(BIOS_WARNING, "WARNING: you need to define get_top_of_ram() for your chipset\n"); return 0; } -#endif - -#else +#if IS_ENABLED(CONFIG_DYNAMIC_CBMEM) void *cbmem_top(void) { /* Top of cbmem is at lowest usable DRAM address below 4GiB. */ return (void *)get_top_of_ram(); } - -#endif /* DYNAMIC_CBMEM */ +#endif +#endif /* !DYNAMIC_CBMEM */ void cbmem_arch_init(void) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index bd2513f..1af5259 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -133,7 +133,7 @@ static void *setup_romstage_stack_after_car(void) slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); num_mtrrs++; - top_of_ram = get_top_of_ram(); + top_of_ram = (uint32_t)cbmem_top(); /* Cache 8MiB below the top of ram. On haswell systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later @@ -318,7 +318,7 @@ struct ramstage_cache *ramstage_cache_location(long *size) /* The ramstage cache lives in the TSEG region at RESERVED_SMM_OFFSET. * The top of ram is defined to be the TSEG base address. */ *size = RESERVED_SMM_SIZE; - return (void *)(get_top_of_ram() + RESERVED_SMM_OFFSET); + return (void *)((uint32_t)cbmem_top() + RESERVED_SMM_OFFSET); } void ramstage_cache_invalid(struct ramstage_cache *cache) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index a7bd904..1b7f307 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -190,6 +190,8 @@ void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif +unsigned long get_top_of_ram(void); + void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); @@ -201,8 +203,6 @@ static inline const struct cbmem_entry *cbmem_entry_find(uint32_t id) /* Common API between cbmem and dynamic cbmem. */ -unsigned long get_top_of_ram(void); - /* Returns 0 if old cbmem was recovered. Recovery is only attempted if * s3resume is non-zero. */ int cbmem_recovery(int s3resume); diff --git a/src/mainboard/emulation/qemu-i440fx/memory.c b/src/mainboard/emulation/qemu-i440fx/memory.c index a189d75..d43b4e9 100644 --- a/src/mainboard/emulation/qemu-i440fx/memory.c +++ b/src/mainboard/emulation/qemu-i440fx/memory.c @@ -40,7 +40,7 @@ static unsigned long qemu_get_memory_size(void) return tomk; } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return qemu_get_memory_size() * 1024; + return (void *) (qemu_get_memory_size() * 1024); } diff --git a/src/northbridge/intel/fsp_rangeley/raminit.c b/src/northbridge/intel/fsp_rangeley/raminit.c index 3513c0f..ea750e7 100644 --- a/src/northbridge/intel/fsp_rangeley/raminit.c +++ b/src/northbridge/intel/fsp_rangeley/raminit.c @@ -26,19 +26,23 @@ #include "northbridge.h" #include <drivers/intel/fsp/fsp_util.h> -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Calculate the top of usable (low) DRAM. * The FSP's reserved memory sits just below the SMM region, * allowing calculation of the top of usable memory. */ - u32 tom = sideband_read(B_UNIT, BMBOUND); - u32 bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; + uintptr_t tom = sideband_read(B_UNIT, BMBOUND); + uintptr_t bsmmrrl = sideband_read(B_UNIT, BSMMRRL) << 20; if (bsmmrrl) { tom = bsmmrrl; } - tom -= FSP_RESERVE_MEMORY_SIZE; - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start() - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/northbridge/intel/fsp_sandybridge/Makefile.inc b/src/northbridge/intel/fsp_sandybridge/Makefile.inc index 080a7f4..ca6f345 100644 --- a/src/northbridge/intel/fsp_sandybridge/Makefile.inc +++ b/src/northbridge/intel/fsp_sandybridge/Makefile.inc @@ -20,11 +20,13 @@ subdirs-y += fsp ramstage-y += northbridge.c +ramstage-y += ram_calc.c ramstage-y += gma.c ramstage-y += acpi.c romstage-y += raminit.c +romstage-y += ram_calc.c romstage-y += early_init.c romstage-y += report_platform.c romstage-y += ../../../arch/x86/lib/walkcbfs.S diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index a95d736..b39f4c9 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -245,16 +245,6 @@ static void pci_domain_set_resources(device_t dev) assign_resources(dev->link_list); } -unsigned long get_top_of_ram(void) -{ - struct device *dev = dev_find_slot(0, PCI_DEVFN(0, 0)); - - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev, TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} - /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. diff --git a/src/northbridge/intel/fsp_sandybridge/ram_calc.c b/src/northbridge/intel/fsp_sandybridge/ram_calc.c new file mode 100644 index 0000000..bbfc874 --- /dev/null +++ b/src/northbridge/intel/fsp_sandybridge/ram_calc.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include <fsp_util.h> +#include "northbridge.h" + +static uintptr_t smm_region_start(void) +{ + /* Base of TSEG is top of usable DRAM */ + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start() - FSP_RESERVE_MEMORY_SIZE; +} diff --git a/src/northbridge/intel/fsp_sandybridge/raminit.c b/src/northbridge/intel/fsp_sandybridge/raminit.c index 19b48ca..8689274 100644 --- a/src/northbridge/intel/fsp_sandybridge/raminit.c +++ b/src/northbridge/intel/fsp_sandybridge/raminit.c @@ -74,11 +74,3 @@ void report_memory_config(void) ((ch_conf >> 16) & 1) ? ", selected" : ""); } } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG) & ~(1UL << 0); - tom -= 0x200000; /* 2MB for FSP HOB */ - return (unsigned long) tom; -} diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index c8c15d3..d9d3357 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -86,7 +86,7 @@ u32 decode_igd_gtt_size(const u32 gsm) } } -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); @@ -105,3 +105,8 @@ unsigned long get_top_of_ram(void) } return tor; } + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); +} diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c index 99e7d67..01ad50d 100644 --- a/src/northbridge/intel/haswell/ram_calc.c +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -24,12 +24,17 @@ #include <cbmem.h> #include "haswell.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* * Base of TSEG is top of usable DRAM below 4GiB. The register has * 1 MiB alignement. */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom & ~((1 << 20) - 1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); } diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index d09b2e1..4b7d895 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -24,9 +24,9 @@ #include <cbmem.h> #include "i945.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { - u32 tom; + uintptr_t tom; if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & (DEVEN_D2F0 | DEVEN_D2F1)) { /* IGD enabled, get top of Memory from BSM register */ @@ -53,5 +53,10 @@ unsigned long get_top_of_ram(void) /* TSEG either disabled or invalid */ break; } - return (unsigned long) tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index db57a3d..d36684e 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "nehalem.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 3693a07..e147909 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -23,9 +23,14 @@ #include <cbmem.h> #include "sandybridge.h" -unsigned long get_top_of_ram(void) +static uintptr_t smm_region_start(void) { /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; + uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return tom; +} + +void *cbmem_top(void) +{ + return (void *) smm_region_start(); } diff --git a/src/soc/intel/baytrail/baytrail/smm.h b/src/soc/intel/baytrail/baytrail/smm.h index 5ead89f..0d920fb 100644 --- a/src/soc/intel/baytrail/baytrail/smm.h +++ b/src/soc/intel/baytrail/baytrail/smm.h @@ -31,7 +31,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/baytrail/memmap.c b/src/soc/intel/baytrail/memmap.c index f383d82..f2e14b3 100644 --- a/src/soc/intel/baytrail/memmap.c +++ b/src/soc/intel/baytrail/memmap.c @@ -22,12 +22,12 @@ #include <baytrail/iosf.h> #include <baytrail/smm.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); } -unsigned long get_top_of_ram(void) +void *cbmem_top(void) { - return (unsigned long)smm_region_start(); + return (void *) smm_region_start(); } diff --git a/src/soc/intel/broadwell/memmap.c b/src/soc/intel/broadwell/memmap.c index 046cc1d..28f4062 100644 --- a/src/soc/intel/broadwell/memmap.c +++ b/src/soc/intel/broadwell/memmap.c @@ -23,19 +23,24 @@ #include <broadwell/pci_devs.h> #include <broadwell/systemagent.h> -unsigned long get_top_of_ram(void) +static uintptr_t dpr_region_start(void) { /* * Base of DPR is top of usable DRAM below 4GiB. The register has * 1 MiB alignment and reports the TOP of the range, the base * must be calculated from the size in MiB in bits 11:4. */ - u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR); - u32 tom = dpr & ~((1 << 20) - 1); + uintptr_t dpr = pci_read_config32(SA_DEV_ROOT, DPR); + uintptr_t tom = dpr & ~((1 << 20) - 1); /* Subtract DMA Protected Range size if enabled */ if (dpr & DPR_EPM) tom -= (dpr & DPR_SIZE_MASK) << 16; - return (unsigned long)tom; + return tom; +} + +void *cbmem_top(void) +{ + return (void *) dpr_region_start(); } diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index fcbe6e7..3896e85 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -44,8 +44,6 @@ ramstage-y += ramstage.c ramstage-y += gpio.c romstage-y += gpio.c ramstage-y += pmutil.c -romstage-y += raminit.c -ramstage-y += raminit.c ramstage-y += southcluster.c romstage-y += reset.c ramstage-y += reset.c diff --git a/src/soc/intel/fsp_baytrail/baytrail/smm.h b/src/soc/intel/fsp_baytrail/baytrail/smm.h index 0208c9f..136c2ca 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/smm.h +++ b/src/soc/intel/fsp_baytrail/baytrail/smm.h @@ -36,7 +36,7 @@ static inline int smm_region_size(void) return CONFIG_SMM_TSEG_SIZE; } -void *smm_region_start(void); +uintptr_t smm_region_start(void); #if !defined(__PRE_RAM__) && !defined(__SMM___) #include <stdint.h> diff --git a/src/soc/intel/fsp_baytrail/memmap.c b/src/soc/intel/fsp_baytrail/memmap.c index 83858b8..615916b 100644 --- a/src/soc/intel/fsp_baytrail/memmap.c +++ b/src/soc/intel/fsp_baytrail/memmap.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,8 +22,25 @@ #include <cbmem.h> #include <baytrail/iosf.h> #include <baytrail/smm.h> +#include <drivers/intel/fsp/fsp_util.h> -void *smm_region_start(void) +uintptr_t smm_region_start(void) { - return (void *)(iosf_bunit_read(BUNIT_SMRRL) << 20); + return (iosf_bunit_read(BUNIT_SMRRL) << 20); +} + +/* + * Calculate the top of usable (low) DRAM. + * The FSP's reserved memory sits just below the SMM region, + * allowing calculation of the top of usable memory. + * + * The entire memory map is shown in northcluster.c + */ + +void *cbmem_top(void) +{ + uintptr_t tom = smm_region_start(); + if (!tom) + tom = iosf_bunit_read(BUNIT_BMBOUND); + return (void *) tom - FSP_RESERVE_MEMORY_SIZE; } diff --git a/src/soc/intel/fsp_baytrail/raminit.c b/src/soc/intel/fsp_baytrail/raminit.c deleted file mode 100644 index 55692d2..0000000 --- a/src/soc/intel/fsp_baytrail/raminit.c +++ /dev/null @@ -1,47 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc. - * Copyright (C) 2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <console/console.h> -#include <arch/io.h> -#include <cbmem.h> -#include <device/device.h> -#include <baytrail/baytrail.h> -#include <baytrail/iosf.h> -#include <cpu/x86/msr.h> -#include <drivers/intel/fsp/fsp_util.h> - -unsigned long get_top_of_ram(void) -{ - /* - * Calculate the top of usable (low) DRAM. - * The FSP's reserved memory sits just below the SMM region, - * allowing calculation of the top of usable memory. - * - * The entire memory map is shown in northcluster.c - */ - u32 tom = iosf_bunit_read(BUNIT_BMBOUND); - u32 bsmmrrl = iosf_bunit_read(BUNIT_SMRRL) << 20; - if (bsmmrrl) { - tom = bsmmrrl; - } - tom -= FSP_RESERVE_MEMORY_SIZE; - - return (unsigned long) tom; -}

1 0

Patch set updated for coreboot: 33fc5e0 ARM romstages: Support and fix COLLECT_TIMESTAMPS
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8021 -gerrit commit 33fc5e08174e93ead17837868fc6eb79c1e0857d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 08:50:36 2014 +0200 ARM romstages: Support and fix COLLECT_TIMESTAMPS Change-Id: I53959eb937c1db3c4211e23a6476340383a33c5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/daisy/romstage.c | 12 ++++++++++++ src/mainboard/google/nyan/romstage.c | 12 ++++-------- src/mainboard/google/nyan_big/romstage.c | 12 ++++-------- src/mainboard/google/nyan_blaze/romstage.c | 12 ++++-------- src/mainboard/google/peach_pit/romstage.c | 11 +++++++++++ 5 files changed, 35 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/daisy/romstage.c b/src/mainboard/google/daisy/romstage.c index 9b35c4a..46c6593 100644 --- a/src/mainboard/google/daisy/romstage.c +++ b/src/mainboard/google/daisy/romstage.c @@ -22,6 +22,7 @@ #include <armv7.h> #include <cbfs.h> #include <cbmem.h> +#include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> @@ -147,6 +148,9 @@ void main(void) void *entry; int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP); + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ mem = setup_clock(); @@ -155,8 +159,13 @@ void main(void) exception_init(); setup_power(is_resume); + + timestamp_add_now(TS_BEFORE_INITRAM); + setup_memory(mem, is_resume); + timestamp_add_now(TS_AFTER_INITRAM); + /* This needs to happen on normal boots and on resume. */ trustzone_init(); @@ -174,5 +183,8 @@ void main(void) cbmem_initialize_empty(); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); + + timestamp_add_now(TS_END_ROMSTAGE); + stage_exit(entry); } diff --git a/src/mainboard/google/nyan/romstage.c b/src/mainboard/google/nyan/romstage.c index 4e02365..ba72c51 100644 --- a/src/mainboard/google/nyan/romstage.c +++ b/src/mainboard/google/nyan/romstage.c @@ -150,9 +150,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -213,9 +212,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -230,10 +226,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/nyan_big/romstage.c b/src/mainboard/google/nyan_big/romstage.c index 4e02365..ba72c51 100644 --- a/src/mainboard/google/nyan_big/romstage.c +++ b/src/mainboard/google/nyan_big/romstage.c @@ -150,9 +150,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -213,9 +212,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -230,10 +226,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/nyan_blaze/romstage.c b/src/mainboard/google/nyan_blaze/romstage.c index 4e02365..ba72c51 100644 --- a/src/mainboard/google/nyan_blaze/romstage.c +++ b/src/mainboard/google/nyan_blaze/romstage.c @@ -150,9 +150,8 @@ static void configure_tpm_i2c_bus(void) static void __attribute__((noinline)) romstage(void) { -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t romstage_start_time = timestamp_get(); -#endif + timestamp_init(0); + timestamp_add_now(TS_START_ROMSTAGE); configure_l2ctlr(); configure_l2actlr(); @@ -213,9 +212,6 @@ static void __attribute__((noinline)) romstage(void) cbmem_initialize_empty(); - timestamp_init(0); - timestamp_add(TS_START_ROMSTAGE, romstage_start_time); - // Enable additional peripherals we need for ROM stage. clock_enable_clear_reset(0, CLK_H_SBC1, CLK_U_I2C3, 0, 0, 0); @@ -230,10 +226,10 @@ static void __attribute__((noinline)) romstage(void) vboot_verify_firmware(romstage_handoff_find_or_add()); - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); void *entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); stage_exit(entry); } diff --git a/src/mainboard/google/peach_pit/romstage.c b/src/mainboard/google/peach_pit/romstage.c index 248809d..ce4e399 100644 --- a/src/mainboard/google/peach_pit/romstage.c +++ b/src/mainboard/google/peach_pit/romstage.c @@ -23,6 +23,7 @@ #include <armv7.h> #include <cbfs.h> #include <cbmem.h> +#include <timestamp.h> #include <arch/cache.h> #include <arch/exception.h> @@ -234,6 +235,9 @@ void main(void) exynos5420_config_smp(); power_init_failed = setup_power(is_resume); + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Clock must be initialized before console_init, otherwise you may need * to re-initialize serial console drivers again. */ system_clock_init(); @@ -248,8 +252,12 @@ void main(void) /* re-initialize PMIC I2C channel after (re-)setting system clocks */ i2c_init(PMIC_I2C_BUS, 1000000, 0x00); /* 1MHz */ + timestamp_add_now(TS_BEFORE_INITRAM); + setup_memory(&mem_timings, is_resume); + timestamp_add_now(TS_AFTER_INITRAM); + primitive_mem_test(); trustzone_init(); @@ -272,5 +280,8 @@ void main(void) entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/ramstage"); simple_spi_test(); + + timestamp_add_now(TS_END_ROMSTAGE); + stage_exit(entry); }

1 0

Patch set updated for coreboot: d7565bd timestamps: Switch from tsc_t to uint64_t
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8020 -gerrit commit d7565bd112059bcaefb94a8adfbd7d346aa43cc9 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Aug 1 13:31:44 2013 -0700 timestamps: Switch from tsc_t to uint64_t Cherry-pick from chromium and adjusted for added boards and changed directory layout for arch/arm. Timestamp implementation for ARMv7 Abstract the use of rdtsc() and make the timestamps uint64_t in the generic code. The ARM implementation uses the monotonic timer. Original-Signed-off-by: Stefan Reinauer <reinauer(a)google.com> BRANCH=none BUG=chrome-os-partner:18637 TEST=See cbmem print timestamps Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62 Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793 (cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c) Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/arm/armv7/Makefile.inc | 2 ++ src/arch/arm/armv7/timestamp.c | 29 ++++++++++++++++++ src/arch/x86/lib/Makefile.inc | 5 +++- src/arch/x86/lib/timestamp.c | 27 +++++++++++++++++ src/include/cpu/x86/tsc.h | 5 ++++ src/include/timestamp.h | 12 +++++--- src/lib/hardwaremain.c | 2 +- src/lib/timestamp.c | 25 +++++++--------- src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 41 ++++++++------------------ src/mainboard/lenovo/x201/romstage.c | 2 +- src/mainboard/packardbell/ms2290/romstage.c | 2 +- src/mainboard/via/epia-m850/romstage.c | 2 +- src/soc/intel/baytrail/romstage/romstage.c | 22 +++----------- src/soc/intel/broadwell/romstage/romstage.c | 22 +++----------- src/soc/intel/fsp_baytrail/romstage/romstage.c | 19 +++++------- src/southbridge/intel/bd82x6x/early_pch.c | 8 ++--- src/southbridge/intel/fsp_bd82x6x/bootblock.c | 2 +- src/southbridge/intel/fsp_rangeley/romstage.c | 16 +++++----- src/southbridge/intel/i82801gx/early_lpc.c | 7 ++--- src/southbridge/intel/lynxpoint/early_pch.c | 7 ++--- 22 files changed, 137 insertions(+), 124 deletions(-) diff --git a/src/arch/arm/armv7/Makefile.inc b/src/arch/arm/armv7/Makefile.inc index 62d5434..7e67178 100644 --- a/src/arch/arm/armv7/Makefile.inc +++ b/src/arch/arm/armv7/Makefile.inc @@ -57,6 +57,7 @@ romstage-y += cpu.S romstage-y += exception.c romstage-y += exception_asm.S romstage-y += mmu.c +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c romstage-c-ccopts += $(armv7_flags) romstage-S-ccopts += $(armv7_asm_flags) @@ -74,6 +75,7 @@ ramstage-y += cpu.S ramstage-y += exception.c ramstage-y += exception_asm.S ramstage-y += mmu.c +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c ramstage-c-ccopts += $(armv7_flags) ramstage-S-ccopts += $(armv7_asm_flags) diff --git a/src/arch/arm/armv7/timestamp.c b/src/arch/arm/armv7/timestamp.c new file mode 100644 index 0000000..07a209c --- /dev/null +++ b/src/arch/arm/armv7/timestamp.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <timestamp.h> +#include <timer.h> + +uint64_t timestamp_get(void) +{ + struct mono_time timestamp; + timer_monotonic_get(&timestamp); + return (uint64_t)timestamp.microseconds; +} + diff --git a/src/arch/x86/lib/Makefile.inc b/src/arch/x86/lib/Makefile.inc index 22306f1..c7e8b62 100644 --- a/src/arch/x86/lib/Makefile.inc +++ b/src/arch/x86/lib/Makefile.inc @@ -24,6 +24,9 @@ ramstage-y += ebda.c ramstage-y += rom_media.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c ramstage-$(CONFIG_COOP_MULTITASKING) += thread_switch.S +ramstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c + +romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c smm-y += memset.c smm-y += memcpy.c @@ -34,4 +37,4 @@ rmodules_x86_32-y += memset.c rmodules_x86_32-y += memcpy.c rmodules_x86_32-y += memmove.c -endif # CONFIG_ARCH_RAMSTAGE_X86_32 \ No newline at end of file +endif # CONFIG_ARCH_RAMSTAGE_X86_32 diff --git a/src/arch/x86/lib/timestamp.c b/src/arch/x86/lib/timestamp.c new file mode 100644 index 0000000..02582a5 --- /dev/null +++ b/src/arch/x86/lib/timestamp.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA + */ + +#include <cpu/x86/tsc.h> +#include <timestamp.h> + +uint64_t timestamp_get(void) +{ + return rdtscll(); +} + diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 7323599..71d253b 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -53,6 +53,11 @@ static inline unsigned long long rdtscll(void) ); return val; } + +static inline uint64_t tsc_to_uint64(tsc_t tstamp) +{ + return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; +} #endif #if CONFIG_TSC_CONSTANT_RATE diff --git a/src/include/timestamp.h b/src/include/timestamp.h index 66c1d9a..ba73135 100644 --- a/src/include/timestamp.h +++ b/src/include/timestamp.h @@ -20,6 +20,8 @@ #ifndef __TIMESTAMP_H__ #define __TIMESTAMP_H__ +#include <stdint.h> + struct timestamp_entry { uint32_t entry_id; uint64_t entry_stamp; @@ -59,12 +61,10 @@ enum timestamp_id { }; #if CONFIG_COLLECT_TIMESTAMPS && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) -#include <cpu/x86/tsc.h> -void timestamp_init(tsc_t base); -void timestamp_add(enum timestamp_id id, tsc_t ts_time); +void timestamp_init(uint64_t base); +void timestamp_add(enum timestamp_id id, uint64_t ts_time); void timestamp_add_now(enum timestamp_id id); void timestamp_reinit(void); -tsc_t get_initial_timestamp(void); #else #define timestamp_init(base) #define timestamp_add(id, time) @@ -72,4 +72,8 @@ tsc_t get_initial_timestamp(void); #define timestamp_reinit() #endif +/* Implemented by the architecture code */ +uint64_t timestamp_get(void); +uint64_t get_initial_timestamp(void); + #endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index be052b3..e01247b 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -452,7 +452,7 @@ static void boot_state_schedule_static_entries(void) void main(void) { /* Record current time, try to locate timestamps in CBMEM. */ - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_RAMSTAGE); post_code(POST_ENTRY_RAMSTAGE); diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index f0ee48d..67635f8 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -28,16 +28,11 @@ #define MAX_TIMESTAMPS 30 static struct timestamp_table* ts_table_p CAR_GLOBAL = NULL; -static tsc_t ts_basetime CAR_GLOBAL = { .lo = 0, .hi =0 }; +static uint64_t ts_basetime CAR_GLOBAL = 0; -static void timestamp_stash(enum timestamp_id id, tsc_t ts_time); +static void timestamp_stash(enum timestamp_id id, uint64_t ts_time); -static uint64_t tsc_to_uint64(tsc_t tstamp) -{ - return (((uint64_t)tstamp.hi) << 32) + tstamp.lo; -} - -static void timestamp_real_init(tsc_t base) +static void timestamp_real_init(uint64_t base) { struct timestamp_table* tst; @@ -50,14 +45,14 @@ static void timestamp_real_init(tsc_t base) return; } - tst->base_time = tsc_to_uint64(base); + tst->base_time = base; tst->max_entries = MAX_TIMESTAMPS; tst->num_entries = 0; car_set_var(ts_table_p, tst); } -void timestamp_add(enum timestamp_id id, tsc_t ts_time) +void timestamp_add(enum timestamp_id id, uint64_t ts_time) { struct timestamp_entry *tse; struct timestamp_table *ts_table = NULL; @@ -75,18 +70,18 @@ void timestamp_add(enum timestamp_id id, tsc_t ts_time) tse = &ts_table->entries[ts_table->num_entries++]; tse->entry_id = id; - tse->entry_stamp = tsc_to_uint64(ts_time) - ts_table->base_time; + tse->entry_stamp = ts_time - ts_table->base_time; } void timestamp_add_now(enum timestamp_id id) { - timestamp_add(id, rdtsc()); + timestamp_add(id, timestamp_get()); } #define MAX_TIMESTAMP_CACHE 8 struct timestamp_cache { enum timestamp_id id; - tsc_t time; + uint64_t time; } timestamp_cache[MAX_TIMESTAMP_CACHE] CAR_GLOBAL; static int timestamp_entries CAR_GLOBAL = 0; @@ -99,7 +94,7 @@ static int timestamp_entries CAR_GLOBAL = 0; * part of CAR migration for romstage, and in ramstage main(). */ -static void timestamp_stash(enum timestamp_id id, tsc_t ts_time) +static void timestamp_stash(enum timestamp_id id, uint64_t ts_time) { struct timestamp_cache *ts_cache = car_get_var(timestamp_cache); int ts_entries = car_get_var(timestamp_entries); @@ -124,7 +119,7 @@ static void timestamp_do_sync(void) car_set_var(timestamp_entries, 0); } -void timestamp_init(tsc_t base) +void timestamp_init(uint64_t base) { if (!boot_cpu()) return; diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index c617a0a..8992a57 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -50,7 +50,7 @@ void main(unsigned long bist) cbmem_was_initted = !cbmem_recovery(0); - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); } diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index 658051c..6f08b6a 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -52,7 +52,7 @@ void main(unsigned long bist) cbmem_was_initted = !cbmem_recovery(0); - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); } diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 6580ab9..0823ae2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -183,14 +183,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); #if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t before_initram_time; - - start_romstage_time = rdtsc(); - + uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4); /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time.lo >> 4 | - start_romstage_time.lo << 28); + pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time); #endif pch_enable_lpc(); @@ -240,11 +235,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); #if CONFIG_COLLECT_TIMESTAMPS - before_initram_time= rdtsc(); + uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4); /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time.lo >> 4 | - before_initram_time.lo << 28); - + pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time); #endif /* @@ -267,20 +260,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { void *cbmem_hob_ptr; #if CONFIG_COLLECT_TIMESTAMPS - tsc_t start_romstage_time; - tsc_t base_time; - tsc_t before_initram_time; - tsc_t after_initram_time = rdtsc(); - u32 timebase = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0); - u32 time_romstage_start = pci_read_config32(PCI_DEV(0, 27, 0), 0x2c); - u32 time_before_initram = pci_read_config32(PCI_DEV(0, 27, 0), 0x14); - - base_time.lo = timebase << 4; - base_time.hi = timebase >> 28; - start_romstage_time.lo = time_romstage_start << 4; - start_romstage_time.hi = time_romstage_start >> 28; - before_initram_time.lo = time_before_initram << 4; - before_initram_time.hi = time_before_initram >> 28; + uint64_t after_initram_time = timestamp_get(); + uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4; + uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4; #endif /* @@ -335,13 +317,11 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); timestamp_add(TS_BEFORE_INITRAM, before_initram_time ); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif /* Load the ramstage. */ copy_and_run(); @@ -353,3 +333,8 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) /* No overrides needed */ return; } + +uint64_t get_initial_timestamp(void) +{ + return (uint64_t) pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) << 4; +} diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index e58f5f6..be49067 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -190,7 +190,7 @@ void main(unsigned long bist) int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x51, 0 }; - timestamp_init(rdtsc ()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index ca96c87..fbbd4b5 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -175,7 +175,7 @@ void main(unsigned long bist) int s3resume = 0; const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - timestamp_init(rdtsc ()); + timestamp_init(timestamp_get()); /* SERR pin is confused on reset. Clear NMI. */ outb(4, 0x61); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 899c5a6..01d955a 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -46,7 +46,7 @@ void main(unsigned long bist) { u32 tolm; - timestamp_init(rdtsc()); + timestamp_init(timestamp_get()); timestamp_add_now(TS_START_ROMSTAGE); /* First thing we need to do on the VX900, before anything else */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index b69b532..ac5afab 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -44,20 +44,6 @@ #include <baytrail/smm.h> #include <baytrail/spi.h> -static inline uint64_t timestamp_get(void) -{ - return rdtscll(); -} - -static inline tsc_t ts64_to_tsc(uint64_t ts) -{ - tsc_t tsc = { - .lo = ts, - .hi = ts >> 32, - }; - return tsc; -} - /* The cache-as-ram assembly file calls romstage_main() after setting up * cache-as-ram. romstage_main() will then call the mainboards's * mainboard_romstage_entry() function. That function then calls @@ -274,10 +260,10 @@ void romstage_common(struct romstage_params *params) chromeos_init(prev_sleep_state); /* Save timestamp information. */ - timestamp_init(ts64_to_tsc(params->ts.times[0])); - timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1])); - timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2])); - timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); + timestamp_init(params->ts.times[0]); + timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); + timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); + timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 4a5a47c..f234fda 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,20 +38,6 @@ #include <broadwell/romstage.h> #include <broadwell/spi.h> -static inline uint64_t timestamp_get(void) -{ - return rdtscll(); -} - -static inline tsc_t ts64_to_tsc(uint64_t ts) -{ - tsc_t tsc = { - .lo = ts, - .hi = ts >> 32, - }; - return tsc; -} - static inline void mark_ts(struct romstage_params *rp, uint64_t ts) { struct romstage_timestamps *rt = &rp->ts; @@ -142,10 +128,10 @@ void romstage_common(struct romstage_params *params) chromeos_init(params->power_state->prev_sleep_state); /* Save timestamp information. */ - timestamp_init(ts64_to_tsc(params->ts.times[0])); - timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1])); - timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2])); - timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3])); + timestamp_init(params->ts.times[0]); + timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); + timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); + timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index 2619c96..ad42e73 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -221,10 +221,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { struct romstage_handoff *handoff; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - tsc_t after_initram_time = rdtsc(); - tsc_t base_time; - base_time.hi = 0; - base_time.lo = 0; + uint64_t after_initram_time = timestamp_get(); #endif post_code(0x4a); @@ -244,9 +241,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { report_platform_info(); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - after_initram_time = rdtsc(); -#endif post_code(0x4b); late_mainboard_romstage_entry(); @@ -271,13 +265,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - timestamp_init(base_time); - timestamp_reinit(); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif post_code(0x4f); @@ -285,3 +275,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { copy_and_run(); while (1); } + +uint64_t get_initial_timestamp(void) +{ + return 0; +} diff --git a/src/southbridge/intel/bd82x6x/early_pch.c b/src/southbridge/intel/bd82x6x/early_pch.c index 3438a0a..95182ce 100644 --- a/src/southbridge/intel/bd82x6x/early_pch.c +++ b/src/southbridge/intel/bd82x6x/early_pch.c @@ -20,21 +20,19 @@ #include <arch/io.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include "pch.h" #include <arch/acpi.h> #include <console/console.h> -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif - int southbridge_detect_s3_resume(void) { diff --git a/src/southbridge/intel/fsp_bd82x6x/bootblock.c b/src/southbridge/intel/fsp_bd82x6x/bootblock.c index 61ff301..9b3e97a 100644 --- a/src/southbridge/intel/fsp_bd82x6x/bootblock.c +++ b/src/southbridge/intel/fsp_bd82x6x/bootblock.c @@ -34,7 +34,7 @@ static void store_initial_timestamp(void) * only storing the low nibble of the high dword of the tsc. Even this * is probably 0 by the time we get here, so storing 64 bits is overkill.S */ - pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.lo >> 4 | tsc.hi << 28); } /* diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index 6c5751e..fba9eb6 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -95,11 +95,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { void *cbmem_hob_ptr; #if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - tsc_t after_initram_time = rdtsc(); - tsc_t base_time; - base_time.hi = 0; - base_time.lo = 0; + uint64_t after_initram_time = timestamp_get(); #endif + post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", __func__, (u32) status, (u32) hob_list_ptr); @@ -129,12 +127,9 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - timestamp_init(base_time); - timestamp_reinit(); + timestamp_init(get_initial_timestamp()); timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); -#endif post_code(0x4f); @@ -142,3 +137,8 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { copy_and_run(); while (1); } + +uint64_t get_initial_timestamp(void) +{ + return 0; +} diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 69bbfb2..b08a964 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -20,20 +20,19 @@ #include <arch/io.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801gx.h" -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif int southbridge_detect_s3_resume(void) { diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index fdbb2a3..5378428 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -23,6 +23,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <timestamp.h> +#include <cpu/x86/tsc.h> #include <elog.h> #include "pch.h" #include "chip.h" @@ -71,16 +72,14 @@ static void pch_generic_setup(void) printk(BIOS_DEBUG, " done.\n"); } -#if CONFIG_COLLECT_TIMESTAMPS -tsc_t get_initial_timestamp(void) +uint64_t get_initial_timestamp(void) { tsc_t base_time = { .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) }; - return base_time; + return tsc_to_uint64(base_time); } -#endif static int sleep_type_s3(void) {

1 0

Patch set updated for coreboot: df59234 [NOTFORMERGE]: Enable COLLECT_TIMESTAMPS by default
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8023 -gerrit commit df592348395e582d9b37d893c1e77d95bc9b2992 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 22:12:56 2014 +0200 [NOTFORMERGE]: Enable COLLECT_TIMESTAMPS by default Change-Id: I71b494ec52eb8de601321285b63be87f03f3ac0b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/Kconfig b/src/Kconfig index 30961a4..9deeac4 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -183,7 +183,7 @@ config DYNAMIC_CBMEM config COLLECT_TIMESTAMPS bool "Create a table of timestamps collected during boot" - default n + default y help Make coreboot create a table of timer-ID/timer-value pairs to allow measuring time spent at different phases of the boot process.

1 0

Patch set updated for coreboot: 8e98f35 baytrail broadwell: Use timestamps internal stash
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8022 -gerrit commit 8e98f353cf4d2601b2f29f17b944e85d36f91ca5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 21:11:51 2014 +0200 baytrail broadwell: Use timestamps internal stash No reason to carry timestamps on CAR stack, as implementation of timestamps internally stashes on CAR_GLOBAL table and migrates those to CBMEM. Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/baytrail/baytrail/romstage.h | 7 ------- src/soc/intel/baytrail/romstage/romstage.c | 23 +++++------------------ src/soc/intel/broadwell/broadwell/romstage.h | 7 ------- src/soc/intel/broadwell/romstage/romstage.c | 23 +++++------------------ 4 files changed, 10 insertions(+), 50 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/romstage.h b/src/soc/intel/baytrail/baytrail/romstage.h index 9ea3564..5fbda37 100644 --- a/src/soc/intel/baytrail/baytrail/romstage.h +++ b/src/soc/intel/baytrail/baytrail/romstage.h @@ -28,14 +28,7 @@ #include <arch/cpu.h> #include <baytrail/mrc_wrapper.h> -#define NUM_ROMSTAGE_TS 4 -struct romstage_timestamps { - uint64_t times[NUM_ROMSTAGE_TS]; - int count; -}; - struct romstage_params { - struct romstage_timestamps ts; unsigned long bist; struct mrc_params *mrc_params; }; diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index ac5afab..a989a99 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -99,14 +99,6 @@ static void spi_init(void) write32(bcr, reg); } -static inline void mark_ts(struct romstage_params *rp, uint64_t ts) -{ - struct romstage_timestamps *rt = &rp->ts; - - rt->times[rt->count] = ts; - rt->count++; -} - /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) @@ -117,9 +109,10 @@ void * asmlinkage romstage_main(unsigned long bist, }; /* Save initial timestamp from bootblock. */ - mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + /* Save romstage begin */ - mark_ts(&rp, timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); program_base_addresses(); @@ -233,7 +226,7 @@ void romstage_common(struct romstage_params *params) struct chipset_power_state *ps; int prev_sleep_state; - mark_ts(params, timestamp_get()); + timestamp_add_now(TS_BEFORE_INITRAM); ps = fill_power_state(); prev_sleep_state = chipset_prev_sleep_state(ps); @@ -249,7 +242,7 @@ void romstage_common(struct romstage_params *params) /* Initialize RAM */ raminit(params->mrc_params, prev_sleep_state); - mark_ts(params, timestamp_get()); + timestamp_add_now(TS_AFTER_INITRAM); handoff = romstage_handoff_find_or_add(); if (handoff != NULL) @@ -258,12 +251,6 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); chromeos_init(prev_sleep_state); - - /* Save timestamp information. */ - timestamp_init(params->ts.times[0]); - timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); - timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); - timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void) diff --git a/src/soc/intel/broadwell/broadwell/romstage.h b/src/soc/intel/broadwell/broadwell/romstage.h index d3702c7..946d1d0 100644 --- a/src/soc/intel/broadwell/broadwell/romstage.h +++ b/src/soc/intel/broadwell/broadwell/romstage.h @@ -23,16 +23,9 @@ #include <stdint.h> #include <arch/cpu.h> -#define NUM_ROMSTAGE_TS 4 -struct romstage_timestamps { - uint64_t times[NUM_ROMSTAGE_TS]; - int count; -}; - struct chipset_power_state; struct pei_data; struct romstage_params { - struct romstage_timestamps ts; unsigned long bist; struct chipset_power_state *power_state; struct pei_data *pei_data; diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index f234fda..5ca57d0 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -38,14 +38,6 @@ #include <broadwell/romstage.h> #include <broadwell/spi.h> -static inline void mark_ts(struct romstage_params *rp, uint64_t ts) -{ - struct romstage_timestamps *rt = &rp->ts; - - rt->times[rt->count] = ts; - rt->count++; -} - /* Entry from cache-as-ram.inc. */ void * asmlinkage romstage_main(unsigned long bist, uint32_t tsc_low, uint32_t tsc_hi) @@ -58,10 +50,10 @@ void * asmlinkage romstage_main(unsigned long bist, post_code(0x30); /* Save initial timestamp from bootblock. */ - mark_ts(&rp, (((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); + timestamp_init((((uint64_t)tsc_hi) << 32) | (uint64_t)tsc_low); /* Save romstage begin */ - mark_ts(&rp, timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); /* System Agent Early Initialization */ systemagent_early_init(); @@ -102,7 +94,7 @@ void romstage_common(struct romstage_params *params) post_code(0x32); - mark_ts(params, timestamp_get()); + timestamp_add_now(TS_BEFORE_INITRAM); params->pei_data->boot_mode = params->power_state->prev_sleep_state; @@ -116,7 +108,8 @@ void romstage_common(struct romstage_params *params) /* Initialize RAM */ raminit(params->pei_data); - mark_ts(params, timestamp_get()); + + timestamp_add_now(TS_AFTER_INITRAM); handoff = romstage_handoff_find_or_add(); if (handoff != NULL) @@ -126,12 +119,6 @@ void romstage_common(struct romstage_params *params) printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); chromeos_init(params->power_state->prev_sleep_state); - - /* Save timestamp information. */ - timestamp_init(params->ts.times[0]); - timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]); - timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]); - timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]); } void asmlinkage romstage_after_car(void)

1 0

Patch set updated for coreboot: be15366 [NOTFORMERGE] Intel FSP: Timestamps
by Kyösti Mälkki 01 Jan '15

01 Jan '15

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8024 -gerrit commit be15366a3997bbdffefa002792e8cb366e078c00 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 31 21:48:48 2014 +0200 [NOTFORMERGE] Intel FSP: Timestamps Only after BROKEN_CAR_MIGRATE is fixed. Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/cougar_canyon2/romstage.c | 23 ++++------------------- src/soc/intel/fsp_baytrail/romstage/romstage.c | 11 ++++++----- src/southbridge/intel/fsp_rangeley/romstage.c | 11 ++++++----- 3 files changed, 16 insertions(+), 29 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 0823ae2..02a00eb 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -182,11 +182,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); -#if CONFIG_COLLECT_TIMESTAMPS - uint32_t start_romstage_time = (uint32_t) (timestamp_get() >> 4); - /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x2c, start_romstage_time); -#endif + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); pch_enable_lpc(); @@ -234,11 +231,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x48); -#if CONFIG_COLLECT_TIMESTAMPS - uint32_t before_initram_time = (uint32_t) (timestamp_get() >> 4); - /* since this mainboard doesn't use audio, we can stuff the TSC values in there */ - pci_write_config32(PCI_DEV(0, 27, 0), 0x14, before_initram_time); -#endif + timestamp_add_now(TS_BEFORE_INITRAM); /* * Call early init to initialize memory and chipset. This function returns @@ -259,11 +252,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { u32 reg32; void *cbmem_hob_ptr; -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t after_initram_time = timestamp_get(); - uint64_t start_romstage_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x2c) << 4; - uint64_t before_initram_time = (uint64_t) pci_read_config32(PCI_DEV(0, 27, 0), 0x14) << 4; -#endif + timestamp_add_now(TS_AFTER_INITRAM); /* * HD AUDIO is not used on this system, so we're using some registers @@ -317,10 +306,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { *(u32*)cbmem_hob_ptr = (u32)HobListPtr; post_code(0x4f); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time ); - timestamp_add(TS_BEFORE_INITRAM, before_initram_time ); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); /* Load the ramstage. */ diff --git a/src/soc/intel/fsp_baytrail/romstage/romstage.c b/src/soc/intel/fsp_baytrail/romstage/romstage.c index ad42e73..f18daef 100644 --- a/src/soc/intel/fsp_baytrail/romstage/romstage.c +++ b/src/soc/intel/fsp_baytrail/romstage/romstage.c @@ -161,6 +161,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x40); + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + program_base_addresses(); post_code(0x41); @@ -199,6 +202,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) post_code(0x47); + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -220,9 +225,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { uint32_t prev_sleep_state; struct romstage_handoff *handoff; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x4a); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -265,8 +268,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f); diff --git a/src/southbridge/intel/fsp_rangeley/romstage.c b/src/southbridge/intel/fsp_rangeley/romstage.c index fba9eb6..a668815 100644 --- a/src/southbridge/intel/fsp_rangeley/romstage.c +++ b/src/southbridge/intel/fsp_rangeley/romstage.c @@ -53,6 +53,9 @@ void main(FSP_INFO_HEADER *fsp_info_header) */ outb(0x40, 0x80); + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Rangeley UART POR state is enabled */ console_init(); post_code(0x41); @@ -75,6 +78,8 @@ void main(FSP_INFO_HEADER *fsp_info_header) read32(func_dis); } + timestamp_add_now(TS_BEFORE_INITRAM); + /* * Call early init to initialize memory and chipset. This function returns * to the romstage_main_continue function with a pointer to the HOB @@ -94,9 +99,7 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { int cbmem_was_initted; void *cbmem_hob_ptr; -#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) - uint64_t after_initram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); post_code(0x48); printk(BIOS_DEBUG, "%s status: %x hob_list_ptr: %x\n", @@ -127,8 +130,6 @@ void romstage_main_continue(EFI_STATUS status, void *hob_list_ptr) { *(u32*)cbmem_hob_ptr = (u32)hob_list_ptr; post_code(0x4e); - timestamp_init(get_initial_timestamp()); - timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); post_code(0x4f);

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coreboot-gerrit January 2015