coreboot-gerrit July 2014

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Patch set updated for coreboot: cc145df device/pci_early.c: Mixes up variants of a typedefs to 'u32'
by Edward O'Callaghan 10 Jul '14

10 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6225 -gerrit commit cc145df33888fe24fe6f808f587bbac13bcf124d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 04:55:16 2014 +1000 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Unfortantly coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer time exclusively. Change-Id: I948801f5be968a934798f1bad7722649758cd4d3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/pci_early.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index e31287e..e690211 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -25,8 +25,7 @@ #include <delay.h> #ifdef __PRE_RAM__ - -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) +unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; u16 status; @@ -69,11 +68,11 @@ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) return 0; } -unsigned pci_find_capability(device_t dev, unsigned cap) +unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } -#endif +#endif /* __PRE_RAM__ */ #if CONFIG_EARLY_PCI_BRIDGE

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Patch set updated for coreboot: 954c27c AMD SPI: Optimise for longer writes
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6164 -gerrit commit 954c27cdfb6cd0851ebb57c03a5e3b87b94569e6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jun 30 07:34:36 2014 +0300 AMD SPI: Optimise for longer writes Leave it to the implementation of flash->write() to split the writes to match SPI controller and SPI flash part restrictions. This allows for some optimisation for auto-address-increment (AAI) commands. Kconfig AMD_SB_SPI_TX_LEN can be kept as local. Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/spi.c | 7 +------ src/southbridge/amd/Kconfig | 9 --------- src/southbridge/amd/agesa/hudson/spi.c | 15 +++++++++++++++ src/southbridge/amd/cimx/sb800/spi.c | 14 ++++++++++++++ 4 files changed, 30 insertions(+), 15 deletions(-) diff --git a/src/cpu/amd/agesa/spi.c b/src/cpu/amd/agesa/spi.c index 5631053..1c652fd 100644 --- a/src/cpu/amd/agesa/spi.c +++ b/src/cpu/amd/agesa/spi.c @@ -40,12 +40,7 @@ void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len) flash->erase(flash, pos, size); flash->write(flash, pos, sizeof(len), &len); - - u32 nvram_pos; - for (nvram_pos = 0; nvram_pos < len - CONFIG_AMD_SB_SPI_TX_LEN; nvram_pos += CONFIG_AMD_SB_SPI_TX_LEN) { - flash->write(flash, nvram_pos + pos + 4, CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); - } - flash->write(flash, nvram_pos + pos + 4, len % CONFIG_AMD_SB_SPI_TX_LEN, (u8 *)(buf + nvram_pos)); + flash->write(flash, pos + sizeof(len), len, buf); flash->spi->rw = SPI_WRITE_FLAG; spi_release_bus(flash->spi); diff --git a/src/southbridge/amd/Kconfig b/src/southbridge/amd/Kconfig index 39aeb09..867afca 100644 --- a/src/southbridge/amd/Kconfig +++ b/src/southbridge/amd/Kconfig @@ -14,12 +14,3 @@ source src/southbridge/amd/sb800/Kconfig source src/southbridge/amd/cimx/Kconfig source src/southbridge/amd/agesa/Kconfig source src/southbridge/amd/sr5650/Kconfig - -if CPU_AMD_AGESA - -config AMD_SB_SPI_TX_LEN - int - default 4 - depends on SPI_FLASH - -endif diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index f050a63..2aeb2c0 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> @@ -101,6 +102,20 @@ int spi_xfer(struct spi_slave *slave, const void *dout, u8 count; bytesout--; + + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + readoffby1 = bytesout ? 0 : 1; #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index e5b2407..f38e691 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -20,6 +20,7 @@ #include <stdlib.h> #include <string.h> #include <arch/io.h> +#include <console/console.h> #include <spi-generic.h> #include <device/device.h> #include <device/pci.h> @@ -74,6 +75,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout, bytesout--; + /* + * Check if this is a write command attempting to transfer more bytes + * than the controller can handle. Iterations for writes are not + * supported here because each SPI write command needs to be preceded + * and followed by other SPI commands, and this sequence is controlled + * by the SPI chip driver. + */ + if (bytesout > AMD_SB_SPI_TX_LEN) { + printk(BIOS_DEBUG, "FCH SPI: Too much to write. Does your SPI chip driver use" + " spi_crop_chunk()?\n"); + return -1; + } + readoffby1 = bytesout ? 0 : 1; readwrite = (bytesin + readoffby1) << 4 | bytesout;

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Patch set updated for coreboot: 415ea03 SPI: Split writes using spi_crop_chunk()
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6163 -gerrit commit 415ea03dbb6f7a686fc0ff385e0c648eb8bd61b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 29 16:17:33 2014 +0300 SPI: Split writes using spi_crop_chunk() SPI controllers in Intel and AMD bridges have a slightly different restriction on how long transactions they can handle. Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/spi/adesto.c | 4 ++-- src/drivers/spi/amic.c | 4 ++-- src/drivers/spi/gigadevice.c | 4 ++-- src/drivers/spi/macronix.c | 5 ++--- src/drivers/spi/stmicro.c | 4 ++-- src/drivers/spi/winbond.c | 4 ++-- src/include/spi-generic.h | 2 ++ src/include/spi_flash.h | 8 -------- src/soc/intel/baytrail/spi.c | 7 ++++++- src/soc/intel/fsp_baytrail/spi.c | 7 ++++++- src/southbridge/amd/agesa/hudson/spi.c | 6 ++++++ src/southbridge/amd/cimx/sb800/spi.c | 7 +++++++ src/southbridge/intel/common/spi.c | 7 ++++++- 13 files changed, 45 insertions(+), 24 deletions(-) diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 9dc8e14..50e5883 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -100,7 +100,7 @@ static int adesto_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); - chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); cmd[0] = CMD_AT25DF_PP; cmd[1] = (offset >> 16) & 0xff; @@ -118,7 +118,7 @@ static int adesto_write(struct spi_flash *flash, goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: adesto Page Program failed\n"); diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index 4cccc71..63a68a5 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -82,7 +82,7 @@ static int amic_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); - chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); cmd[0] = CMD_A25_PP; cmd[1] = (offset >> 16) & 0xff; @@ -100,7 +100,7 @@ static int amic_write(struct spi_flash *flash, goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: AMIC Page Program failed\n"); diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 3fb89c7..783d321 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -141,7 +141,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); - chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); ret = spi_flash_cmd(flash->spi, CMD_GD25_WREN, NULL, 0); if (ret < 0) { @@ -161,7 +161,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); #endif - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 3611599..6e910f6 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -144,13 +144,12 @@ static int macronix_write(struct spi_flash *flash, ret = 0; for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); - chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); cmd[0] = CMD_MX25XX_PP; cmd[1] = (offset >> 16) & 0xff; cmd[2] = (offset >> 8) & 0xff; cmd[3] = offset & 0xff; - #if CONFIG_DEBUG_SPI_FLASH printk(BIOS_SPEW, "PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x }" " chunk_len = %zu\n", @@ -163,7 +162,7 @@ static int macronix_write(struct spi_flash *flash, break; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Macronix Page Program failed\n"); diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index c825bd0..bc7969d 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -155,7 +155,7 @@ static int stmicro_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); - chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); cmd[0] = CMD_M25PXX_PP; cmd[1] = (offset >> 16) & 0xff; @@ -173,7 +173,7 @@ static int stmicro_write(struct spi_flash *flash, goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: STMicro Page Program failed\n"); diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index eb0868e..7ddd312 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -134,7 +134,7 @@ static int winbond_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); - chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); + chunk_len = spi_crop_chunk(sizeof(cmd), chunk_len); cmd[0] = CMD_W25_PP; cmd[1] = (offset >> 16) & 0xff; @@ -152,7 +152,7 @@ static int winbond_write(struct spi_flash *flash, goto out; } - ret = spi_flash_cmd_write(flash->spi, cmd, 4, + ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf + actual, chunk_len); if (ret < 0) { printk(BIOS_WARNING, "SF: Winbond Page Program failed\n"); diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 6c62de6..3b10ae9 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -168,6 +168,8 @@ void spi_cs_deactivate(struct spi_slave *slave); */ void spi_set_speed(struct spi_slave *slave, uint32_t hz); +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len); + /*----------------------------------------------------------------------- * Write 8 bits, then read 8 bits. * slave: The SPI slave we're communicating with diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 61c931e..70ca784 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -39,14 +39,6 @@ const typeof( ((type *)0)->member ) *__mptr = (ptr); \ (type *)( (char *)__mptr - offsetof(type,member) );}) -#define CONFIG_ICH_SPI -#ifdef CONFIG_ICH_SPI -#define CONTROLLER_PAGE_LIMIT 64 -#else -/* any number larger than 4K would do, actually */ -#define CONTROLLER_PAGE_LIMIT ((int)(~0U>>1)) -#endif - struct spi_flash { struct spi_slave *spi; diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index b649f53..0dc980f 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -499,6 +499,11 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) return -1; } +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(cntlr.databytes, buf_len); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { @@ -588,7 +593,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, */ if (trans.bytesout > cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); + " spi_crop_chunk()?\n"); return -1; } diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 50f1123..4feb502 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -497,6 +497,11 @@ static int ich_status_poll(u16 bitmask, int wait_til_set) return -1; } +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(cntlr.databytes, buf_len); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { @@ -585,7 +590,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, */ if (trans.bytesout > cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); + " spi_crop_chunk()?\n"); return -1; } diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 720b26f..f050a63 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -42,6 +42,7 @@ static int bus_claimed = 0; #define SPI_REG_CNTRL11 0xd #define CNTRL11_FIFOPTR_MASK 0x07 +#define AMD_SB_SPI_TX_LEN 64 static u32 spibar; @@ -86,6 +87,11 @@ void spi_init(void) spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index a46349e..e5b2407 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -32,6 +32,8 @@ static int bus_claimed = 0; #endif +#define AMD_SB_SPI_TX_LEN 8 + static u32 spibar; static void reset_internal_fifo_pointer(void) @@ -56,6 +58,11 @@ void spi_init() spibar = pci_read_config32(dev, 0xA0) & ~0x1F; } +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 76fd226..8e7192b 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -550,6 +550,11 @@ static int spi_is_multichip (void) return !!((cntlr.flmap0 >> 8) & 3); } +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return min(cntlr.databytes, buf_len); +} + int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bytesout, void *din, unsigned int bytesin) { @@ -639,7 +644,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, */ if (trans.bytesout > cntlr.databytes) { printk(BIOS_DEBUG, "ICH SPI: Too much to write. Does your SPI chip driver use" - " CONTROLLER_PAGE_LIMIT?\n"); + " spi_crop_chunk()?\n"); return -1; }

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Patch set updated for coreboot: e3d387d SPI flash: Fix alignment checks in Page Program commands
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6162 -gerrit commit e3d387d42fa622093a61ccbf72382d95e36c58c8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jun 29 16:15:39 2014 +0300 SPI flash: Fix alignment checks in Page Program commands There are two separate restrictions to take into account: Page Program command must not cross address boundaries defined by the flash part's page size. Total number of bytes for any command sent to flash part is restricted by the SPI controller capabilities. Consider CONTROLLER_PAGE_LIMIT=64, page_size=256, offset=62, len=4. This write would be split at offset 64 for no reason. Consider CONTROLLER_PAGE_LIMIT=40, page_size=256, offset=254, len=4. This write would not be split at page boundary as required. We do not really hit the second case. Nevertheless, CONTROLLER_PAGE_LIMIT is a misnomer for the maximum payload length supported by the SPI controller and is removed in a followup. Change-Id: I727f2e7de86a91b6a509460ff1f374acd006a0bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/spi/adesto.c | 3 ++- src/drivers/spi/amic.c | 3 ++- src/drivers/spi/gigadevice.c | 3 ++- src/drivers/spi/macronix.c | 3 ++- src/drivers/spi/stmicro.c | 3 ++- src/drivers/spi/winbond.c | 3 ++- 6 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/drivers/spi/adesto.c b/src/drivers/spi/adesto.c index 83be8b8..9dc8e14 100644 --- a/src/drivers/spi/adesto.c +++ b/src/drivers/spi/adesto.c @@ -88,7 +88,7 @@ static int adesto_write(struct spi_flash *flash, int ret; u8 cmd[4]; - page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + page_size = 1 << stm->params->l2_page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; @@ -100,6 +100,7 @@ static int adesto_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); cmd[0] = CMD_AT25DF_PP; cmd[1] = (offset >> 16) & 0xff; diff --git a/src/drivers/spi/amic.c b/src/drivers/spi/amic.c index fa17036..4cccc71 100644 --- a/src/drivers/spi/amic.c +++ b/src/drivers/spi/amic.c @@ -70,7 +70,7 @@ static int amic_write(struct spi_flash *flash, int ret; u8 cmd[4]; - page_size = min(1 << amic->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + page_size = 1 << amic->params->l2_page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; @@ -82,6 +82,7 @@ static int amic_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); cmd[0] = CMD_A25_PP; cmd[1] = (offset >> 16) & 0xff; diff --git a/src/drivers/spi/gigadevice.c b/src/drivers/spi/gigadevice.c index 5a8f82f..3fb89c7 100644 --- a/src/drivers/spi/gigadevice.c +++ b/src/drivers/spi/gigadevice.c @@ -128,7 +128,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, int ret; u8 cmd[4]; - page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + page_size = 1 << stm->params->l2_page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; @@ -141,6 +141,7 @@ static int gigadevice_write(struct spi_flash *flash, u32 offset, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); ret = spi_flash_cmd(flash->spi, CMD_GD25_WREN, NULL, 0); if (ret < 0) { diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index bbc3704..3611599 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -131,7 +131,7 @@ static int macronix_write(struct spi_flash *flash, int ret; u8 cmd[4]; - page_size = min(mcx->params->page_size, CONTROLLER_PAGE_LIMIT); + page_size = mcx->params->page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; @@ -144,6 +144,7 @@ static int macronix_write(struct spi_flash *flash, ret = 0; for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); cmd[0] = CMD_MX25XX_PP; cmd[1] = (offset >> 16) & 0xff; diff --git a/src/drivers/spi/stmicro.c b/src/drivers/spi/stmicro.c index af23853..c825bd0 100644 --- a/src/drivers/spi/stmicro.c +++ b/src/drivers/spi/stmicro.c @@ -143,7 +143,7 @@ static int stmicro_write(struct spi_flash *flash, int ret; u8 cmd[4]; - page_size = min(stm->params->page_size, CONTROLLER_PAGE_LIMIT); + page_size = stm->params->page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; @@ -155,6 +155,7 @@ static int stmicro_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); cmd[0] = CMD_M25PXX_PP; cmd[1] = (offset >> 16) & 0xff; diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index 52c7b61..eb0868e 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -122,7 +122,7 @@ static int winbond_write(struct spi_flash *flash, int ret; u8 cmd[4]; - page_size = min(1 << stm->params->l2_page_size, CONTROLLER_PAGE_LIMIT); + page_size = 1 << stm->params->l2_page_size; byte_addr = offset % page_size; flash->spi->rw = SPI_WRITE_FLAG; @@ -134,6 +134,7 @@ static int winbond_write(struct spi_flash *flash, for (actual = 0; actual < len; actual += chunk_len) { chunk_len = min(len - actual, page_size - byte_addr); + chunk_len = min(chunk_len, CONTROLLER_PAGE_LIMIT); cmd[0] = CMD_W25_PP; cmd[1] = (offset >> 16) & 0xff;

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Patch set updated for coreboot: d67dfba AGESA f15tn f16kb: Handle XHCI enable in Fch_Oem_config()
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6241 -gerrit commit d67dfba64312d2077d3b64b0bed1e2b22318cf41 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 6 22:40:15 2014 +0300 AGESA f15tn f16kb: Handle XHCI enable in Fch_Oem_config() Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper while AMD_INIT_ENV was already handled as part of BiosCallouts. OEM configuration is supposed to be implemented as part of BiosCallouts, leaving agesawrapper agnostic of platform details. Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 10 ++++------ src/mainboard/amd/olivehill/agesawrapper.c | 4 ---- src/mainboard/amd/parmer/BiosCallOuts.c | 10 ++++------ src/mainboard/amd/parmer/agesawrapper.c | 4 ---- src/mainboard/amd/thatcher/agesawrapper.c | 2 -- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 10 ++++------ src/mainboard/asrock/imb-a180/agesawrapper.c | 4 ---- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 13 +++++-------- src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ---- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 10 ++++------ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 4 ---- 11 files changed, 21 insertions(+), 54 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 76c0c52..942115c 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -194,9 +194,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -209,11 +211,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index b7b56ac..e3c6d8f 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -165,10 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index f09e27c..6b75b21 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -194,10 +194,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -210,11 +212,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 42fb3e6..d9b23de 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -165,10 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 7f6a703..e6b60f9 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -165,8 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; - AmdResetParams.FchInterface.Xhci0Enable = FALSE; - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index f348fec..c99f9d7 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -307,9 +307,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -322,11 +324,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) //oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 093bb14..8b2074c 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -194,10 +194,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index b671f8c..e1bfabd 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -83,9 +83,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -98,13 +100,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; - FchParams_env->Usb.Xhci1Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index a964238..a6deacc 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -178,10 +178,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; - AmdResetParams.FchInterface.Xhci1Enable = FALSE; -#endif status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 736811e..457c64e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -190,10 +190,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -206,11 +208,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 76d3209..9c34230 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -179,10 +179,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);

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New patch to review for coreboot: eeafdf8 AGESA f15tn f16kb: Handle XCHI enable in Fch_Oem_config()
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6241 -gerrit commit eeafdf8628171af16589627ddd7235f3ceda6be6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 6 22:40:15 2014 +0300 AGESA f15tn f16kb: Handle XCHI enable in Fch_Oem_config() Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper while AMD_INIT_ENV was already handled as part of BiosCallouts. OEM configuration is supposed to be implemented as part of BiosCallouts, leaving agesawrapper agnostic of platform details. Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 10 ++++------ src/mainboard/amd/olivehill/agesawrapper.c | 4 ---- src/mainboard/amd/parmer/BiosCallOuts.c | 10 ++++------ src/mainboard/amd/parmer/agesawrapper.c | 4 ---- src/mainboard/amd/thatcher/agesawrapper.c | 2 -- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 10 ++++------ src/mainboard/asrock/imb-a180/agesawrapper.c | 4 ---- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 13 +++++-------- src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ---- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 10 ++++------ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 4 ---- 11 files changed, 21 insertions(+), 54 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 76c0c52..942115c 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -194,9 +194,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -209,11 +211,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index b7b56ac..e3c6d8f 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -165,10 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index f09e27c..6b75b21 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -194,10 +194,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -210,11 +212,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 42fb3e6..d9b23de 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -165,10 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 7f6a703..e6b60f9 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -165,8 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; - AmdResetParams.FchInterface.Xhci0Enable = FALSE; - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index f348fec..c99f9d7 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -307,9 +307,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -322,11 +324,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) //oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 093bb14..8b2074c 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -194,10 +194,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index b671f8c..e1bfabd 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -83,9 +83,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -98,13 +100,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; - FchParams_env->Usb.Xhci1Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index a964238..a6deacc 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -178,10 +178,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; - AmdResetParams.FchInterface.Xhci1Enable = FALSE; -#endif status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 736811e..457c64e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -190,10 +190,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -206,11 +208,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 76d3209..9c34230 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -179,10 +179,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus);

1 0

New patch to review for coreboot: ea82a8c AGESA Hudson: Fix typecasts in Fch_Oem_config()
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6240 -gerrit commit ea82a8c3043fafa8132e989ee6457add7694fd30 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 10 06:32:36 2014 +0300 AGESA Hudson: Fix typecasts in Fch_Oem_config() Like many other (but not all) BiosCallouts, StdHeader is also passed as ConfigPtr argument. Use that instead to make no assumptions of the real type of FchData as it changes depending of the StdHeader. Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 6 +++--- src/mainboard/amd/parmer/BiosCallOuts.c | 6 +++--- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 6 +++--- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 6 +++--- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 6 +++--- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index bf9a345..76c0c52 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -191,13 +191,13 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 308acd2..f09e27c 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -191,14 +191,14 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index 9b1d489..f348fec 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -304,13 +304,13 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 933b754..b671f8c 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -80,13 +80,13 @@ static const CODEC_TBL_LIST CodecTableList[] = */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 645f334..736811e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -187,14 +187,14 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

1 0

New patch to review for coreboot: cb5f5be AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREE
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6239 -gerrit commit cb5f5be64c06b74d32695bae8b07c846aa48a807 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 10 06:43:44 2014 +0300 AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREE Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 4 +--- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 4 +--- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 4 +--- 3 files changed, 3 insertions(+), 9 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 2945c6d..308acd2 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -197,9 +197,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ -#if CONFIG_HUDSON_LEGACY_FREE - FchParams_reset->LegacyFree = 1; -#endif + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 539f4bd..933b754 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -83,11 +83,9 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; if (FchParams->StdHeader->Func == AMD_INIT_RESET) { -#if CONFIG_HUDSON_LEGACY_FREE FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; - FchParams_reset->LegacyFree = 1; -#endif printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index cef364c..645f334 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -193,9 +193,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ -#if CONFIG_HUDSON_LEGACY_FREE - FchParams_reset->LegacyFree = 1; -#endif + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

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New patch to review for coreboot: 4af65ea AGESA fam15: Fix entry to cimx/sb900
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6238 -gerrit commit 4af65ea91d84b747138e2655f5add005a93b1ba4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 7 18:16:55 2014 +0300 AGESA fam15: Fix entry to cimx/sb900 Move SB900 call to match comments and changes already made for family14 et al. Change-Id: I22aa0bbeeabf9cff929c49c23014005bc3d53ccb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 3 --- src/northbridge/amd/agesa/family15/northbridge.c | 5 +++++ src/southbridge/amd/cimx/sb700/sb_cimx.h | 1 - 3 files changed, 5 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 83e9ed8..0453006 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -40,9 +40,6 @@ static void agesawrapper_post_device(void *unused) /* Preparation for write_tables(). */ get_bus_conf(); -#if CONFIG_AMD_SB_CIMX && CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15 - sb_After_Pci_Init(); -#endif #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 34f58d3..34d7ea3 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -42,6 +42,7 @@ #include "agesawrapper.h" #include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge.h" +#include "sb_cimx.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -591,6 +592,10 @@ static void domain_enable_resources(device_t dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam15 - %s: AmdInitMid.\n", __func__); + +#if CONFIG_AMD_SB_CIMX + sb_After_Pci_Init(); +#endif AGESAWRAPPER(amdinitmid); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); } diff --git a/src/southbridge/amd/cimx/sb700/sb_cimx.h b/src/southbridge/amd/cimx/sb700/sb_cimx.h index ebfaca8..b123c51 100644 --- a/src/southbridge/amd/cimx/sb700/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb700/sb_cimx.h @@ -34,7 +34,6 @@ void sb_Poweron_Init(void); void sb_Before_Pci_Init(void); void sb_After_Pci_Init(void); -void sb_Mid_Post_Init(void); void sb_Late_Post(void); void sb7xx_51xx_enable_wideio(u8 wio_index, u16 base);

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New patch to review for coreboot: 21a2b73 AGESA CIMx: Move late init out of get_bus_conf()
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6237 -gerrit commit 21a2b73c2b2dbb386021fc963756b2c7f2c70bee Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 7 15:06:00 2014 +0300 AGESA CIMx: Move late init out of get_bus_conf() Followup deals further with Fam15 case. For unknown reasons calls were commented out for amd/dinar and they remain that way. Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 10 ++++++++++ src/mainboard/amd/dinar/get_bus_conf.c | 7 ------- src/mainboard/amd/inagua/get_bus_conf.c | 6 ------ src/mainboard/amd/persimmon/get_bus_conf.c | 6 ------ src/mainboard/amd/south_station/get_bus_conf.c | 6 ------ src/mainboard/amd/torpedo/get_bus_conf.c | 2 -- src/mainboard/amd/union_station/get_bus_conf.c | 6 ------ src/mainboard/asrock/e350m1/get_bus_conf.c | 6 ------ src/mainboard/asus/m5a88-v/get_bus_conf.c | 6 ------ src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 6 ------ src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 6 ------ src/mainboard/lippert/frontrunner-af/get_bus_conf.c | 6 ------ src/mainboard/lippert/toucan-af/get_bus_conf.c | 6 ------ src/mainboard/supermicro/h8qgi/get_bus_conf.c | 7 ------- src/mainboard/supermicro/h8scm/get_bus_conf.c | 7 ------- src/mainboard/tyan/s8226/get_bus_conf.c | 7 ------- src/southbridge/amd/cimx/sb900/early.c | 4 ++++ 17 files changed, 14 insertions(+), 90 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index cf1caf1..83e9ed8 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -24,6 +24,10 @@ #include "agesawrapper.h" #include <northbridge/amd/agesa/agesawrapper_call.h> +#if CONFIG_AMD_SB_CIMX +#include <sb_cimx.h> +#endif + void get_bus_conf(void); static void agesawrapper_post_device(void *unused) @@ -36,6 +40,12 @@ static void agesawrapper_post_device(void *unused) /* Preparation for write_tables(). */ get_bus_conf(); +#if CONFIG_AMD_SB_CIMX && CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15 + sb_After_Pci_Init(); +#endif +#if CONFIG_AMD_SB_CIMX + sb_Late_Post(); +#endif if (!acpi_s3_resume_allowed()) return; diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index e93ca84..d62e111 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam15.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -116,9 +113,5 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_AMD_SB_CIMX -// sb_After_Pci_Init(); -// sb_Late_Post(); -#endif printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); } diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index ac72b48..be113b3 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -99,7 +96,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index c8369e1..b31f687 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -26,9 +26,6 @@ #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" #include <arch/ioapic.h> -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -109,7 +106,4 @@ void get_bus_conf(void) apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index 7eedcba8..99b3880 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -102,7 +99,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 36613f7..b7895e4 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -24,7 +24,6 @@ #include <stdint.h> #include <stdlib.h> #include <cpu/amd/amdfam12.h> -#include "sb_cimx.h" #include "agesawrapper.h" /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -100,6 +99,5 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; - sb_Late_Post(); printk(BIOS_DEBUG, "Mainboard - %s - %s - End.\n", __FILE__, __func__); } diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index 7eedcba8..99b3880 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -102,7 +99,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 7eedcba8..99b3880 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -102,7 +99,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/asus/m5a88-v/get_bus_conf.c b/src/mainboard/asus/m5a88-v/get_bus_conf.c index 9bb26e6..b312ec1 100644 --- a/src/mainboard/asus/m5a88-v/get_bus_conf.c +++ b/src/mainboard/asus/m5a88-v/get_bus_conf.c @@ -27,9 +27,6 @@ #include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable * and acpi_tables busnum is default. @@ -147,7 +144,4 @@ void get_bus_conf(void) #endif apicid_sb800 = apicid_base + 0; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c index ca20a0c..44d0b0f 100755 --- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c +++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c @@ -26,9 +26,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -101,7 +98,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 43aa984..3992cb7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -28,9 +28,6 @@ #include <stdlib.h> #include <string.h> -#include <southbridge/amd/cimx/sb800/sb_cimx.h> - - /** * Global variables for mainboard layouts. These are shared by irqtable, * mptable and acpi_tables where busnum is default. @@ -110,7 +107,4 @@ void get_bus_conf(void) apicid_sb800 = (io_apic_read(IO_APIC_ADDR, 0x00) >> 24); apicver_sb800 = (io_apic_read(IO_APIC_ADDR, 0x01) & 0xFF); -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif /* CONFIG_AMD_SB_CIMX */ } diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index bddcee1..c1a3fc2 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -100,7 +97,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index f0de0e5..c49fff1 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include <cpu/amd/amdfam14.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -99,7 +96,4 @@ void get_bus_conf(void) apicid_base = CONFIG_MAX_CPUS; apicid_sb800 = apicid_base; -#if CONFIG_AMD_SB_CIMX - sb_Late_Post(); -#endif } diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 7a69a7c..bce9737 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include "agesawrapper.h" #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -108,8 +105,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); - sb_Late_Post(); -#endif } diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 932e2de..9a70fca 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -25,9 +25,6 @@ #include <stdlib.h> #include "agesawrapper.h" #include <cpu/amd/amdfam10_sysconf.h> -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -108,8 +105,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); - sb_Late_Post(); -#endif } diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index 508f379..e7529c3 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -24,9 +24,6 @@ #include <stdint.h> #include <stdlib.h> #include "agesawrapper.h" -#if CONFIG_AMD_SB_CIMX -#include <sb_cimx.h> -#endif /* Global variables for MB layouts and these will be shared by irqtable mptable @@ -109,8 +106,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ bus_isa = 10; -#if CONFIG_AMD_SB_CIMX - sb_After_Pci_Init(); - sb_Late_Post(); -#endif } diff --git a/src/southbridge/amd/cimx/sb900/early.c b/src/southbridge/amd/cimx/sb900/early.c index 237137f..6e4e44e 100644 --- a/src/southbridge/amd/cimx/sb900/early.c +++ b/src/southbridge/amd/cimx/sb900/early.c @@ -100,6 +100,7 @@ void sb_before_pci_init(void) void sb_After_Pci_Init(void) { +#if !CONFIG_BOARD_AMD_DINAR AMDSBCFG sb_early_cfg; printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - Start.\n"); @@ -111,6 +112,7 @@ void sb_After_Pci_Init(void) // VerifyImage() will fail, LocateImage() take minitues to find the image. sbAfterPciInit(&sb_early_cfg); printk(BIOS_SPEW, "SB900 - Early.c - sb_After_Pci_Init - End.\n"); +#endif } void sb_Mid_Post_Init(void) @@ -130,6 +132,7 @@ void sb_Mid_Post_Init(void) void sb_Late_Post(void) { +#if !CONFIG_BOARD_AMD_DINAR AMDSBCFG sb_early_cfg; u8 data; @@ -160,4 +163,5 @@ void sb_Late_Post(void) } printk(BIOS_SPEW, "SB900 - Early.c - sb_Late_Post - End.\n"); +#endif }

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coreboot-gerrit July 2014