coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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861 discussions

New patch to review for coreboot: b9f47cc include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs
by Edward O'Callaghan 09 Jul '14

09 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6230 -gerrit commit b9f47cc1821457576d867a0e82e298be6c924f7d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 18:41:12 2014 +1000 include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs 'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/device/device.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index ec17adf..132e4ef 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -18,8 +18,6 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations;

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Patch set updated for coreboot: 3a5ecde intel/haswell: add vmx support w/Kconfig option
by Matt DeVillier 09 Jul '14

09 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6223 -gerrit commit 3a5ecde26f0c2986e5a7e9bd33a36546a7dd67b4 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jul 7 18:48:16 2014 -0500 intel/haswell: add vmx support w/Kconfig option patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx tested/verified working on google/panther Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 4 ++++ src/cpu/intel/haswell/haswell_init.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9cda140..9e62ae5 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,6 +34,10 @@ config SMM_TSEG_SIZE hex default 0x800000 +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9fa9b48..043ba3a 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,6 +150,47 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -703,6 +744,9 @@ static void haswell_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); + /* Enable virtualization if Kconfig option is set */ + enable_vmx(); + /* Configure C States */ configure_c_states();

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New patch to review for coreboot: 6480353 cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct comment
by Paul Menzel 08 Jul '14

08 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6228 -gerrit commit 64803535e2004c5726aa81cb73597a4143821373 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 8 23:15:20 2014 +0200 cpu/intel/fsp_model_206ax/model_206ax_init.c: Correct comment Currently there is no way to enable or disable VMX during runtime using CMOS/NVRAM. It is only possible to configure it during build time by setting the Kconfig option `CONFIG_ENABLE_VMX`. So update the comment accordingly. Change-Id: I4e3294cb39a40cf30d294fd566bc97420592262f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index d0b2d3d..938b811 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -372,7 +372,7 @@ static void model_206ax_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); - /* Enable virtualization if enabled in CMOS */ + /* Enable virtualization if Kconfig option is set */ enable_vmx(); /* Configure Enhanced SpeedStep and Thermal Sensors */

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New patch to review for coreboot: b604ab7 cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`
by Paul Menzel 08 Jul '14

08 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6227 -gerrit commit b604ab7cb25d44d875d27661cf8bec2e8e0bbba2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Jul 8 23:13:05 2014 +0200 cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()` Change-Id: I91cd84d155a2cb1200cb82c31256cfa743e8ea9b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/fsp_model_206ax/model_206ax_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c index e242e40..d0b2d3d 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax_init.c +++ b/src/cpu/intel/fsp_model_206ax/model_206ax_init.c @@ -40,7 +40,7 @@ static void enable_vmx(void) { struct cpuid_result regs; msr_t msr; - int enable = CONFIG_ENABLE_VMX; + int enable = IS_ENABLED(CONFIG_ENABLE_VMX); regs = cpuid(1); /* Check that the VMX is supported before reading or writing the MSR. */

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New patch to review for coreboot: 8095dbf Fix romstage dev type, 'device_t' -> 'pci_devfn_t' in get_sbdn()
by Edward O'Callaghan 08 Jul '14

08 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6226 -gerrit commit 8095dbfa14fb04126f009397b66a22595e40835f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 05:22:32 2014 +1000 Fix romstage dev type, 'device_t' -> 'pci_devfn_t' in get_sbdn() Unfortantly coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer time exclusively. Change-Id: Ied3940d9b2ec119ca4b75b955305add59edbbb18 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 2 +- src/mainboard/asus/m2v/romstage.c | 2 +- src/southbridge/amd/cimx/sb700/early.c | 2 +- src/southbridge/amd/cimx/sb800/early.c | 2 +- src/southbridge/amd/sb600/early_setup.c | 2 +- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/broadcom/bcm5785/early_setup.c | 2 +- src/southbridge/nvidia/mcp55/early_ctrl.c | 2 +- src/southbridge/sis/sis966/early_ctrl.c | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 1dea57b..9604816 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index abe5f84..1261293 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -90,7 +90,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4d6bd60..e4b9c6b 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -88,7 +88,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index d374828..6e113c0 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -107,7 +107,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index a2c6a03..94b1251 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -91,7 +91,7 @@ void soft_reset(void) unsigned int get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); diff --git a/src/southbridge/amd/cimx/sb700/early.c b/src/southbridge/amd/cimx/sb700/early.c index 6dc4ff4..fd9d26b 100644 --- a/src/southbridge/amd/cimx/sb700/early.c +++ b/src/southbridge/amd/cimx/sb700/early.c @@ -34,7 +34,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_SPEW, "SB700 - Early.c - %s - Start.\n", __func__); dev = pci_locate_device_on_bus( diff --git a/src/southbridge/amd/cimx/sb800/early.c b/src/southbridge/amd/cimx/sb800/early.c index 40648ed..0341567 100644 --- a/src/southbridge/amd/cimx/sb800/early.c +++ b/src/southbridge/amd/cimx/sb800/early.c @@ -33,7 +33,7 @@ */ u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; printk(BIOS_DEBUG, "SB800 - %s - %s - Start.\n", __FILE__, __func__); //dev = PCI_DEV(bus, 0x14, 0); diff --git a/src/southbridge/amd/sb600/early_setup.c b/src/southbridge/amd/sb600/early_setup.c index b6611f6..6797399 100644 --- a/src/southbridge/amd/sb600/early_setup.c +++ b/src/southbridge/amd/sb600/early_setup.c @@ -106,7 +106,7 @@ static void sb600_lpc_init(void) /* what is its usage? */ static u32 get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index b7a5e77..7208146 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -221,7 +221,7 @@ void sb7xx_51xx_disable_wideio(u8 wio_index) /* what is its usage? */ u32 __attribute__ ((weak)) get_sbdn(u32 bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(0x1002, 0x4385), bus); diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 9dee295..0a69e5e 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -69,7 +69,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. diff --git a/src/southbridge/nvidia/mcp55/early_ctrl.c b/src/southbridge/nvidia/mcp55/early_ctrl.c index 92f9d03..865c023 100644 --- a/src/southbridge/nvidia/mcp55/early_ctrl.c +++ b/src/southbridge/nvidia/mcp55/early_ctrl.c @@ -24,7 +24,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_NVIDIA, diff --git a/src/southbridge/sis/sis966/early_ctrl.c b/src/southbridge/sis/sis966/early_ctrl.c index 3695023..4b3a228 100644 --- a/src/southbridge/sis/sis966/early_ctrl.c +++ b/src/southbridge/sis/sis966/early_ctrl.c @@ -23,7 +23,7 @@ static unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. */ dev = pci_locate_device_on_bus(

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New patch to review for coreboot: 4123a62 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
by Edward O'Callaghan 08 Jul '14

08 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6225 -gerrit commit 4123a620600d2d73115659bc86ad83319b08a94f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 04:55:16 2014 +1000 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Unfortantly coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer time exclusively. Change-Id: I948801f5be968a934798f1bad7722649758cd4d3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/pci_early.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index e31287e..e690211 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -25,8 +25,7 @@ #include <delay.h> #ifdef __PRE_RAM__ - -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) +unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; u16 status; @@ -69,11 +68,11 @@ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) return 0; } -unsigned pci_find_capability(device_t dev, unsigned cap) +unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } -#endif +#endif /* __PRE_RAM__ */ #if CONFIG_EARLY_PCI_BRIDGE

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New patch to review for coreboot: b61c917 superio/fintek/f71869ad: config struct should be const qualified
by Edward O'Callaghan 08 Jul '14

08 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6224 -gerrit commit b61c917a90a21708e60ab0b0dfef50cbdd84e9be Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 04:12:42 2014 +1000 superio/fintek/f71869ad: config struct should be const qualified The 'superio_fintek_f71869ad_config' struct packed by devicetree.cb should have its type declared with the 'const' qualifier. Change-Id: Ieb86861ee821e77680cc4d0de202dbd7535b844d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71869ad/f71869ad_hwm.c | 2 +- src/superio/fintek/f71869ad/f71869ad_multifunc.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/superio/fintek/f71869ad/f71869ad_hwm.c b/src/superio/fintek/f71869ad/f71869ad_hwm.c index f048299..0475081 100644 --- a/src/superio/fintek/f71869ad/f71869ad_hwm.c +++ b/src/superio/fintek/f71869ad/f71869ad_hwm.c @@ -64,7 +64,7 @@ static void pnp_write_index(u16 port, u8 reg, u8 value) /* note: multifunc registers need to be tweaked before here */ void f71869ad_hwm_init(device_t dev) { - struct superio_fintek_f71869ad_config *conf = dev->chip_info; + const struct superio_fintek_f71869ad_config *conf = dev->chip_info; struct resource *res = find_resource(dev, PNP_IDX_IO0); if (!res) { diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c index 46c4d2c..e0182ed 100644 --- a/src/superio/fintek/f71869ad/f71869ad_multifunc.c +++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c @@ -32,7 +32,7 @@ void f71869ad_multifunc_init(device_t dev) { - struct superio_fintek_f71869ad_config *conf = dev->chip_info; + const struct superio_fintek_f71869ad_config *conf = dev->chip_info; pnp_enter_conf_mode(dev);

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Patch set updated for coreboot: 7d5c412 intel/haswell: add vmx support w/Kconfig option
by Matt DeVillier 08 Jul '14

08 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6223 -gerrit commit 7d5c412639ad2e144038144a49fc19a10946fe06 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jul 7 18:48:16 2014 -0500 intel/haswell: add vmx support w/Kconfig option patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx tested/verified working on google/panther Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 4 ++++ src/cpu/intel/haswell/haswell_init.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9cda140..9e62ae5 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,6 +34,10 @@ config SMM_TSEG_SIZE hex default 0x800000 +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9fa9b48..0fa7dc6 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,6 +150,47 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = IS_ENABLED(CONFIG_ENABLE_VMX); + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -703,6 +744,9 @@ static void haswell_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); + /* Enable virtualization if Kconfig option set */ + enable_vmx(); + /* Configure C States */ configure_c_states();

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Patch set updated for coreboot: 70cc0fc intel/haswell: add vmx support w/Kconfig option
by Matt DeVillier 08 Jul '14

08 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6223 -gerrit commit 70cc0fc961555c715207b077d1cee630eba12c49 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jul 7 18:48:16 2014 -0500 intel/haswell: add vmx support w/Kconfig option patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 4 ++++ src/cpu/intel/haswell/haswell_init.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9cda140..9e62ae5 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,6 +34,10 @@ config SMM_TSEG_SIZE hex default 0x800000 +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9fa9b48..3a99c61 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,6 +150,47 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = CONFIG_ENABLE_VMX; + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -703,6 +744,9 @@ static void haswell_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); + /* Enable virtualization if Kconfig option set */ + enable_vmx(); + /* Configure C States */ configure_c_states();

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Patch set updated for coreboot: e783b41 intel/haswell: add vmx support w/Kconfig option
by Matt DeVillier 08 Jul '14

08 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6223 -gerrit commit e783b4106a014071dd1017e155f53455f522421c Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jul 7 18:48:16 2014 -0500 intel/haswell: add vmx support w/Kconfig option patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/cpu/intel/haswell/Kconfig | 4 ++++ src/cpu/intel/haswell/haswell_init.c | 44 ++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 9cda140..9e62ae5 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -34,6 +34,10 @@ config SMM_TSEG_SIZE hex default 0x800000 +config ENABLE_VMX + bool "Enable VMX for virtualization" + default n + config IED_REGION_SIZE hex default 0x400000 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 9fa9b48..328791f 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -150,6 +150,47 @@ static acpi_cstate_t cstate_map[NUM_C_STATES] = { }, }; +static void enable_vmx(void) +{ + struct cpuid_result regs; + msr_t msr; + int enable = CONFIG_ENABLE_VMX; + + regs = cpuid(1); + /* Check that the VMX is supported before reading or writing the MSR. */ + if (!((regs.ecx & CPUID_VMX) || (regs.ecx & CPUID_SMX))) + return; + + msr = rdmsr(IA32_FEATURE_CONTROL); + + if (msr.lo & (1 << 0)) { + printk(BIOS_ERR, "VMX is locked, so %s will do nothing\n", __func__); + /* VMX locked. If we set it again we get an illegal + * instruction + */ + return; + } + + /* The IA32_FEATURE_CONTROL MSR may initialize with random values. + * It must be cleared regardless of VMX config setting. + */ + msr.hi = msr.lo = 0; + + printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); + + if (enable) { + msr.lo |= (1 << 2); + if (regs.ecx & CPUID_SMX) + msr.lo |= (1 << 1); + } + + wrmsr(IA32_FEATURE_CONTROL, msr); + + msr.lo |= (1 << 0); /* Set lock bit */ + + wrmsr(IA32_FEATURE_CONTROL, msr); +} + /* Convert time in seconds to POWER_LIMIT_1_TIME MSR value */ static const u8 power_limit_time_sec_to_msr[] = { [0] = 0x00, @@ -703,6 +744,9 @@ static void haswell_init(device_t cpu) enable_lapic_tpr(); setup_lapic(); + /* Enable virtualization if enabled in CMOS */ + enable_vmx(); + /* Configure C States */ configure_c_states();

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coreboot-gerrit July 2014