coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 3534433 AGESA Hudson: Fix build without HAVE_ACPI_RESUME
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6253 -gerrit commit 35344333e2a3fff605e432e895836d9e3c8fb265 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 10 20:27:27 2014 +0300 AGESA Hudson: Fix build without HAVE_ACPI_RESUME If one commented out HAVE_ACPI_RESUME in Kconfig file for a board using agesa/hudson the build failed. Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/southbridge/amd/agesa/hudson/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index b0437d9..492f9f3 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -17,7 +17,7 @@ ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c romstage-y += early_setup.c ramstage-$(CONFIG_SPI_FLASH) += spi.c -ramstage-$(CONFIG_HAVE_ACPI_RESUME) += resume.c +ramstage-y += resume.c romstage-y += imc.c ramstage-y += imc.c

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Patch set updated for coreboot: 293b6f5 AGESA Hudson: Fix typecasts in Fch_Oem_config()
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6240 -gerrit commit 293b6f50ca4358763b63ff9befd37afc0ff7bcff Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 10 06:32:36 2014 +0300 AGESA Hudson: Fix typecasts in Fch_Oem_config() Like many other (but not all) BiosCallouts, StdHeader is also passed as ConfigPtr argument. Use that instead to make no assumptions of the real type of FchData as it changes depending of the StdHeader. Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 6 +++--- src/mainboard/amd/parmer/BiosCallOuts.c | 6 +++--- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 6 +++--- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 6 +++--- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 6 +++--- 5 files changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index bf9a345..76c0c52 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -191,13 +191,13 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 308acd2..f09e27c 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -191,14 +191,14 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index 9b1d489..f348fec 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -304,13 +304,13 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 933b754..b671f8c 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -80,13 +80,13 @@ static const CODEC_TBL_LIST CodecTableList[] = */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 645f334..736811e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -187,14 +187,14 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) */ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) { - FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; + AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - if (FchParams->StdHeader->Func == AMD_INIT_RESET) { + if (StdHeader->Func == AMD_INIT_RESET) { FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); - } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { + } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

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Patch set updated for coreboot: 2578c7a AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLE
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6241 -gerrit commit 2578c7a17b9576993d76abe38013a487f6462de8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jul 6 22:40:15 2014 +0300 AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLE Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper while AMD_INIT_ENV was already handled as part of BiosCallouts. OEM configuration is supposed to be implemented as part of BiosCallouts, leaving agesawrapper agnostic of platform details. TODO: S3 resume for XHCI1. Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/BiosCallOuts.c | 10 ++++------ src/mainboard/amd/olivehill/agesawrapper.c | 4 ---- src/mainboard/amd/parmer/BiosCallOuts.c | 10 ++++------ src/mainboard/amd/parmer/agesawrapper.c | 4 ---- src/mainboard/amd/thatcher/agesawrapper.c | 2 -- src/mainboard/asrock/imb-a180/BiosCallOuts.c | 10 ++++------ src/mainboard/asrock/imb-a180/agesawrapper.c | 4 ---- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 13 +++++-------- src/mainboard/asus/f2a85-m/agesawrapper.c | 4 ---- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 10 ++++------ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 4 ---- src/southbridge/amd/agesa/hudson/resume.c | 6 ++---- 12 files changed, 23 insertions(+), 58 deletions(-) diff --git a/src/mainboard/amd/olivehill/BiosCallOuts.c b/src/mainboard/amd/olivehill/BiosCallOuts.c index 76c0c52..942115c 100644 --- a/src/mainboard/amd/olivehill/BiosCallOuts.c +++ b/src/mainboard/amd/olivehill/BiosCallOuts.c @@ -194,9 +194,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -209,11 +211,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index b7b56ac..e3c6d8f 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -165,10 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index f09e27c..6b75b21 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -194,10 +194,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -210,11 +212,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index 42fb3e6..d9b23de 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -165,10 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 7f6a703..e6b60f9 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -165,8 +165,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; - AmdResetParams.FchInterface.Xhci0Enable = FALSE; - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asrock/imb-a180/BiosCallOuts.c b/src/mainboard/asrock/imb-a180/BiosCallOuts.c index f348fec..c99f9d7 100644 --- a/src/mainboard/asrock/imb-a180/BiosCallOuts.c +++ b/src/mainboard/asrock/imb-a180/BiosCallOuts.c @@ -307,9 +307,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - //FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -322,11 +324,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) //oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 093bb14..8b2074c 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -194,10 +194,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index b671f8c..e1bfabd 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -83,9 +83,11 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -98,13 +100,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Hwm.HwmFchtsiAutoPoll = FALSE;/* 1 enable, 0 disable TSI Auto Polling */ /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; - FchParams_env->Usb.Xhci1Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; - FchParams_env->Usb.Xhci1Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_env->Usb.Xhci1Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); } printk(BIOS_DEBUG, "Done\n"); diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c index a964238..a6deacc 100644 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ b/src/mainboard/asus/f2a85-m/agesawrapper.c @@ -178,10 +178,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; - AmdResetParams.FchInterface.Xhci1Enable = FALSE; -#endif status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index 736811e..457c64e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -190,10 +190,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); + FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams_reset->FchReset.Xhci1Enable = FALSE; } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); @@ -206,11 +208,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) oem_fan_control(FchParams_env); /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE - FchParams_env->Usb.Xhci0Enable = TRUE; -#else - FchParams_env->Usb.Xhci0Enable = FALSE; -#endif + FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); FchParams_env->Usb.Xhci1Enable = FALSE; /* sata configuration */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 76d3209..9c34230 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -179,10 +179,6 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct (&AmdParamStruct); AmdResetParams.HtConfig.Depth = 0; -#if !CONFIG_HUDSON_XHCI_ENABLE - AmdResetParams.FchInterface.Xhci0Enable = FALSE; -#endif - AmdResetParams.FchInterface.Xhci1Enable = FALSE; status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); diff --git a/src/southbridge/amd/agesa/hudson/resume.c b/src/southbridge/amd/agesa/hudson/resume.c index ecf06a0..0e986ff 100644 --- a/src/southbridge/amd/agesa/hudson/resume.c +++ b/src/southbridge/amd/agesa/hudson/resume.c @@ -111,10 +111,8 @@ void s3_resume_init_data(void *data) FchParams->Usb.Ohci4Enable = FchInterfaceDefault.Ohci4Enable; FchParams->HwAcpi.PwrFailShadow = FchInterfaceDefault.FchPowerFail; -#if !CONFIG_HUDSON_XHCI_ENABLE - FchParams->Usb.Xhci0Enable = FALSE; -#endif - FchParams->Usb.Xhci1Enable = FALSE; + FchParams->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchParams->Usb.Xhci1Enable = FALSE; #if DUMP_FCH_SETTING int i;

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Patch merged into coreboot/master: 7e5494c northbridge/amd: Fix the family15tn option rom mapping
by gerrit＠coreboot.org 10 Jul '14

10 Jul '14

the following patch was just integrated into master: commit 7e5494c549f1642cc9a98a8e59e87007572c8f88 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jul 9 15:40:15 2014 -0600 northbridge/amd: Fix the family15tn option rom mapping Family15tn video bioses internal have a PCI ID of 1002/9901. The vendor/device mapping in the family15tn/northbridge.c file needs to map to 1002/9901 and not to 1002/9900. This was tested on the amd/parmer mainboard. Change-Id: I0153e9b522e847099c6054d91bf73b50966ed838 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6252 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/6252 for details. -gerrit

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Patch set updated for coreboot: cd9a67e AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREE
by Kyösti Mälkki 10 Jul '14

10 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6239 -gerrit commit cd9a67ead9dc49a3f9b0ef6503188d8d598cdfbb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Jul 10 06:43:44 2014 +0300 AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREE Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/parmer/BiosCallOuts.c | 4 +--- src/mainboard/amd/thatcher/BiosCallOuts.c | 6 ++---- src/mainboard/asus/f2a85-m/BiosCallOuts.c | 4 +--- src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c | 4 +--- 4 files changed, 5 insertions(+), 13 deletions(-) diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c b/src/mainboard/amd/parmer/BiosCallOuts.c index 2945c6d..308acd2 100644 --- a/src/mainboard/amd/parmer/BiosCallOuts.c +++ b/src/mainboard/amd/parmer/BiosCallOuts.c @@ -197,9 +197,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ -#if CONFIG_HUDSON_LEGACY_FREE - FchParams_reset->LegacyFree = 1; -#endif + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/amd/thatcher/BiosCallOuts.c b/src/mainboard/amd/thatcher/BiosCallOuts.c index 1106421..ffb5f7c 100644 --- a/src/mainboard/amd/thatcher/BiosCallOuts.c +++ b/src/mainboard/amd/thatcher/BiosCallOuts.c @@ -194,12 +194,10 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; if (FchParams->StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; + FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ -#if CONFIG_HUDSON_LEGACY_FREE - FchParams_reset->LegacyFree = 1; -#endif + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/asus/f2a85-m/BiosCallOuts.c b/src/mainboard/asus/f2a85-m/BiosCallOuts.c index 539f4bd..933b754 100644 --- a/src/mainboard/asus/f2a85-m/BiosCallOuts.c +++ b/src/mainboard/asus/f2a85-m/BiosCallOuts.c @@ -83,11 +83,9 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams = (FCH_RESET_DATA_BLOCK *)FchData; if (FchParams->StdHeader->Func == AMD_INIT_RESET) { -#if CONFIG_HUDSON_LEGACY_FREE FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; - FchParams_reset->LegacyFree = 1; -#endif printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c index cef364c..645f334 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/BiosCallOuts.c @@ -193,9 +193,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *) FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ -#if CONFIG_HUDSON_LEGACY_FREE - FchParams_reset->LegacyFree = 1; -#endif + FchParams_reset->LegacyFree = IS_ENABLED(CONFIG_HUDSON_LEGACY_FREE); } else if (FchParams->StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV ");

1 0

Patch merged into coreboot/master: b2a14fb intel/haswell: add vmx support w/Kconfig option
by gerrit＠coreboot.org 10 Jul '14

10 Jul '14

the following patch was just integrated into master: commit b2a14fb4f1656c9811f158140040f1157ccb5960 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Mon Jul 7 18:48:16 2014 -0500 intel/haswell: add vmx support w/Kconfig option patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx tested/verified working on google/panther Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: http://review.coreboot.org/6223 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6223 for details. -gerrit

1 0

Patch set updated for coreboot: db71a5f southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes
by Edward O'Callaghan 10 Jul '14

10 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6155 -gerrit commit db71a5fbd82c467d8d229c91d930eea059e53cdf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Jun 28 22:47:22 2014 +1000 southbridge/amd/rsXY0/cmn.c: Trivial - Style fixes Remove some ASCII art past 80 columns. Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/rs690/cmn.c | 40 ++++++++++++++++++---------------------- src/southbridge/amd/rs780/cmn.c | 40 ++++++++++++++++++---------------------- 2 files changed, 36 insertions(+), 44 deletions(-) diff --git a/src/southbridge/amd/rs690/cmn.c b/src/southbridge/amd/rs690/cmn.c index c5523a1..05a47b3 100644 --- a/src/southbridge/amd/rs690/cmn.c +++ b/src/southbridge/amd/rs690/cmn.c @@ -47,7 +47,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -60,7 +60,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -191,12 +191,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -245,11 +245,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -278,17 +278,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -309,9 +305,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs690_set_tom(device_t nb_dev) { /* set TOM */ diff --git a/src/southbridge/amd/rs780/cmn.c b/src/southbridge/amd/rs780/cmn.c index cf09b9a..497d1af 100644 --- a/src/southbridge/amd/rs780/cmn.c +++ b/src/southbridge/amd/rs780/cmn.c @@ -46,7 +46,7 @@ static void nb_write_index(device_t dev, u32 index_reg, u32 index, u32 data) /* extension registers */ u32 pci_ext_read_config32(device_t nb_dev, device_t dev, u32 reg) { - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; printk(BIOS_DEBUG, "addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn); @@ -59,7 +59,7 @@ void pci_ext_write_config32(device_t nb_dev, device_t dev, u32 reg_pos, u32 mask { u32 reg_old, reg; - /*get BAR3 base address for nbcfg0x1c */ + /* get BAR3 base address for nbcfg0x1c */ u32 addr = pci_read_config32(nb_dev, 0x1c) & ~0xF; /*printk(BIOS_DEBUG, "write: addr=%x,bus=%x,devfn=%x\n", addr, dev->bus->secondary, dev->path.pci.devfn);*/ @@ -190,12 +190,12 @@ void set_pcie_enable_bits(device_t dev, u32 reg_pos, u32 mask, u32 val) } } -/*********************************************************** -* To access bar3 we need to program PCI MMIO 7 in K8. -* in_out: -* 1: enable/enter k8 temp mmio base -* 0: disable/restore -***********************************************************/ +/* + * To access bar3 we need to program PCI MMIO 7 in K8. + * in_out: + * 1: enable/enter k8 temp mmio base + * 0: disable/restore + */ void ProgK8TempMmioBase(u8 in_out, u32 pcie_base_add, u32 mmio_base_add) { /* K8 Function1 is address map */ @@ -249,11 +249,11 @@ void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) } } -/******************************************************************************************************** -* Output: -* 0: no device is present. -* 1: device is present and is trained. -********************************************************************************************************/ +/* + * Output: + * 0: no device is present. + * 1: device is present and is trained. + */ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) { u16 count = 5000; @@ -319,17 +319,13 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) count = 0; break; case 0x10: - reg = - pci_ext_read_config32(nb_dev, dev, - PCIE_VC0_RESOURCE_STATUS); + reg = pci_ext_read_config32(nb_dev, dev, PCIE_VC0_RESOURCE_STATUS); printk(BIOS_DEBUG, "PcieTrainPort reg=0x%x\n", reg); /* check bit1 */ if (reg & VC_NEGOTIATION_PENDING) { /* bit1=1 means the link needs to be re-trained. */ /* set bit8=1, bit0-2=bit4-6 */ u32 tmp; - reg = - nbpcie_p_read_index(dev, - PCIE_LC_LINK_WIDTH); + reg = nbpcie_p_read_index(dev, PCIE_LC_LINK_WIDTH); tmp = (reg >> 4) && 0x3; /* get bit4-6 */ reg &= 0xfff8; /* clear bit0-2 */ reg += tmp; /* merge */ @@ -350,9 +346,9 @@ u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port) } /* -* Compliant with CIM_33's ATINB_SetToms. -* Set Top Of Memory below and above 4G. -*/ + * Compliant with CIM_33's ATINB_SetToms. + * Set Top Of Memory below and above 4G. + */ void rs780_set_tom(device_t nb_dev) { /* set TOM */

1 0

New patch to review for coreboot: 8ff4aa3 northbridge/amd: Fix the family15tn option rom mapping
by Dave Frodin 10 Jul '14

10 Jul '14

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6252 -gerrit commit 8ff4aa3a8993c553578a2f605ebef734bb657239 Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Wed Jul 9 15:40:15 2014 -0600 northbridge/amd: Fix the family15tn option rom mapping Family15tn video bioses internal have a PCI ID of 1002/9901. The vendor/device mapping in the family15tn/northbridge.c file needs to map to 1002/9901 and not to 1002/9900. This was tested on the amd/parmer mainboard. Change-Id: I0153e9b522e847099c6054d91bf73b50966ed838 Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/northbridge/amd/agesa/family15tn/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 49f3610..8241f54 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -1148,7 +1148,7 @@ u32 map_oprom_vendev(u32 vendev) case 0x100299A0: /* AMD Radeon HD 7520G (Trinity) */ case 0x100299A2: /* AMD Radeon HD 7420G (Trinity) */ case 0x100299A4: /* AMD Radeon HD 7400G (Trinity) */ - new_vendev=0x10029900; + new_vendev=0x10029901; break; }

1 0

New patch to review for coreboot: eaefc72 libpayload: Drop obsolete setting of reg_base in [oex]hci
by Nico Huber 10 Jul '14

10 Jul '14

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6251 -gerrit commit eaefc7223a20f655ebed4b3809dd5dd6135b2638 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Jul 10 12:56:34 2014 +0200 libpayload: Drop obsolete setting of reg_base in [oex]hci Setting of `controller->reg_base` is of no use here, as it is never read (in another function) later. Looks like this pattern originated from uhci.c where it makes sense. By removing the indirection through `reg_base` we also fix a possible truncation to u32. Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- payloads/libpayload/drivers/usb/ehci.c | 5 ++--- payloads/libpayload/drivers/usb/ohci.c | 3 +-- payloads/libpayload/drivers/usb/xhci.c | 6 ++---- 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 03d0aef..82802a7 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -751,14 +751,13 @@ ehci_init (unsigned long physical_bar) controller->create_intr_queue = ehci_create_intr_queue; controller->destroy_intr_queue = ehci_destroy_intr_queue; controller->poll_intr_queue = ehci_poll_intr_queue; - controller->reg_base = (u32)physical_bar; for (i = 0; i < 128; i++) { controller->devices[i] = 0; } init_device_entry (controller, 0); - EHCI_INST(controller)->capabilities = phys_to_virt(controller->reg_base); - EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(controller->reg_base) + EHCI_INST(controller)->capabilities->caplength); + EHCI_INST(controller)->capabilities = phys_to_virt(physical_bar); + EHCI_INST(controller)->operation = (hc_op_t *)(phys_to_virt(physical_bar) + EHCI_INST(controller)->capabilities->caplength); /* Set the high address word (aka segment) if controller is 64-bit */ if (EHCI_INST(controller)->capabilities->hccparams & 1) diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index 84547e6..9f15dd0 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -201,8 +201,7 @@ ohci_init (unsigned long physical_bar) init_device_entry (controller, 0); OHCI_INST (controller)->roothub = controller->devices[0]; - controller->reg_base = (u32)physical_bar; - OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(controller->reg_base); + OHCI_INST (controller)->opreg = (opreg_t*)phys_to_virt(physical_bar); usb_debug("OHCI Version %x.%x\n", (OHCI_INST (controller)->opreg->HcRevision >> 4) & 0xf, OHCI_INST (controller)->opreg->HcRevision & 0xf); if ((OHCI_INST (controller)->opreg->HcControl & HostControllerFunctionalStateMask) == USBReset) { diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 69ddab7..0bd54c7 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -193,13 +193,11 @@ xhci_init (unsigned long physical_bar) goto _free_xhci; } - controller->reg_base = (u32)physical_bar; - - xhci->capreg = phys_to_virt(controller->reg_base); + xhci->capreg = phys_to_virt(physical_bar); xhci->opreg = ((void *)xhci->capreg) + xhci->capreg->caplength; xhci->hcrreg = ((void *)xhci->capreg) + xhci->capreg->rtsoff; xhci->dbreg = ((void *)xhci->capreg) + xhci->capreg->dboff; - xhci_debug("regbase: 0x%"PRIx32"\n", controller->reg_base); + xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar); xhci_debug("caplen: 0x%"PRIx32"\n", xhci->capreg->caplength); xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff); xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff);

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Patch set updated for coreboot: d7a314b Remove unnecessary mappings in cbfs_media
by Naman Govil 10 Jul '14

10 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6169 -gerrit commit d7a314b743ab7568bc4df487070d18b198a662ec Author: Naman Govil <namangov(a)gmail.com> Date: Mon Jun 30 22:57:11 2014 +0530 Remove unnecessary mappings in cbfs_media Reducing the sram usage while booting by removing unwanted map()s by creating a structure to replace it with appropriate read()s Change-Id: If503368553308a2fdd3ecc1a312a11f14c7a707f Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/arch/x86/boot/smbios.c | 8 +-- src/include/cbfs_core.h | 27 +++++-- src/lib/cbfs.c | 81 +++++++++++++++------ src/lib/cbfs_core.c | 176 +++++++++++++++++++++++++-------------------- 4 files changed, 185 insertions(+), 107 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index ce47a8b..951f264 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -152,11 +152,11 @@ static int smbios_write_type0(unsigned long *current, int handle) #endif { - const struct cbfs_header *header; + struct cbfs_header header; u32 romsize = CONFIG_ROM_SIZE; - header = cbfs_get_header(CBFS_DEFAULT_MEDIA); - if (header != CBFS_HEADER_INVALID_ADDRESS) - romsize = ntohl(header->romsize); + if (!cbfs_get_header(CBFS_DEFAULT_MEDIA, &header)) { + romsize = ntohl(header.romsize); + } t->bios_rom_size = (romsize / 65535) - 1; } diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index a1d8127..7c94be0 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -4,6 +4,7 @@ * Copyright (C) 2008 Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2012 Google, Inc. * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This file is dual-licensed. You can choose between: * - The GNU GPL, version 2, as published by the Free Software Foundation @@ -189,6 +190,12 @@ struct cbfs_optionrom { #define CBFS_MEDIA_INVALID_MAP_ADDRESS ((void*)(0xffffffff)) #define CBFS_DEFAULT_MEDIA ((void*)(0x0)) +struct cbfs_file_handle { + uint32_t data_offset; + uint32_t data_len; + struct cbfs_file file; +}; + /* Media for CBFS to load files. */ struct cbfs_media { @@ -220,16 +227,24 @@ struct cbfs_media { /* returns pointer to a file entry inside CBFS or NULL */ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); -/* returns pointer to file content inside CBFS after if type is correct */ -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media); +/* finds the CBFS master header and fills it in a cbfs_header structure, + return 0 on success and <0 if header not found */ +int cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header); + +/* Returns success (0) on finding the file requested by verifying name/type; + -1 if file not found + The absolute data_offset to the file is stored */ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handle *f, + const char *name, int type); + + +/* returns pointer to file content inside CBFS after verifying if type is correct */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, + int type, size_t *sz); #endif /* __ROMCC__ */ diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index dc08937..e6c9afa 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,7 +3,7 @@ * * Copyright (C) 2008, Jordan Crouse <jordan(a)cosmicpenguin.net> * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. - * + * Copyright (C) 2014, Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -119,38 +119,79 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, void * cbfs_load_stage(struct cbfs_media *media, const char *name) { - struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); + struct cbfs_file_handle f; + struct cbfs_stage stage; + int c; + ssize_t value_read; + void * data; + ssize_t v_read; + struct cbfs_media default_media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return (void *)-1; + } + } + + c = cbfs_find_file(media, &f, name, CBFS_TYPE_STAGE); + + if (c < 0) { + ERROR("Stage not loaded\n"); + return (void *)-1; + } + + value_read = media->read(media, &stage, f.data_offset, sizeof(stage)); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ + if (value_read != sizeof(stage)) + return (void *)-1; + uint32_t entry; uint32_t final_size; - if (stage == NULL) - return (void *) -1; + DEBUG("Read Complete @offset = 0x%x and length = %d\n", + f.data_offset, value_read); LOG("loading stage %s @ 0x%x (%d bytes), entry @ 0x%llx\n", name, - (uint32_t) stage->load, stage->memlen, - stage->entry); + (uint32_t) stage.load, stage.memlen, + stage.entry); - final_size = cbfs_decompress(stage->compression, - ((unsigned char *) stage) + - sizeof(struct cbfs_stage), - (void *) (uint32_t) stage->load, - stage->len); - if (!final_size) - return (void *) -1; - /* Stages rely the below clearing so that the bss is initialized. */ - memset((void *)((uintptr_t)stage->load + final_size), 0, - stage->memlen - final_size); + if(stage.compression == CBFS_COMPRESS_NONE) { + //No compression; hence we can directly read + DEBUG("Read Done\n"); + v_read = media->read(media, (void *) (uintptr_t) stage.load, + f.data_offset + sizeof(stage), f.data_len); + if (v_read != f.data_len) + return (void *)-1; - DEBUG("stage loaded.\n"); + final_size = f.data_len; + } + else { + data = media->map(media, f.data_offset + sizeof(stage), f.data_len); + if (data == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ERROR("Map not successful"); + return (void *) -1; + } + + DEBUG("Map Done\n"); + final_size = cbfs_decompress(stage.compression, data, + (void *) (uint32_t) stage.load, + stage.len); + + if (!final_size) + return (void *) -1; + } - entry = stage->entry; - // entry = ntohll(stage->entry); + /* Stages rely the below clearing so that the bss is initialized. */ + memset((void *)((uintptr_t)stage.load + final_size), 0, + stage.memlen - final_size); + DEBUG("stage loaded.\n"); + entry = stage.entry; return (void *) entry; } diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 50c037e..be80b0a 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -3,6 +3,7 @@ * * Copyright (C) 2011 secunet Security Networks AG * Copyright (C) 2013 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -52,150 +53,171 @@ #include <cbfs.h> #include <string.h> -/* returns a pointer to CBFS master header, or CBFS_HEADER_INVALID_ADDRESS - * on failure */ -const struct cbfs_header *cbfs_get_header(struct cbfs_media *media) +/* fills in the header structure with a pointer to CBFS master header, + returns 0 on success and <0 if header not found */ +int cbfs_get_header(struct cbfs_media *media, struct cbfs_header *header) { - const struct cbfs_header *header; struct cbfs_media default_media; + ssize_t header_size; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return CBFS_HEADER_INVALID_ADDRESS; + return -1; } } media->open(media); DEBUG("CBFS_HEADER_ROM_ADDRESS: 0x%x/0x%x\n", CBFS_HEADER_ROM_ADDRESS, CONFIG_ROM_SIZE); - header = media->map(media, CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); + header_size = media->read(media, (void *)header , + CBFS_HEADER_ROM_ADDRESS, sizeof(*header)); media->close(media); - if (header == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + header->offset = ntohl(header->offset); + header->align = ntohl(header->align); + header->romsize = ntohl(header->romsize); + header->magic = ntohl(header->magic); + header->version = ntohl(header->version); + header->architecture = ntohl(header->architecture); + header->bootblocksize = ntohl(header->bootblocksize); + header->pad[1] = ntohl(header->pad[1]); + + if (header_size != sizeof(*header)) { ERROR("Failed to load CBFS header from 0x%x\n", CBFS_HEADER_ROM_ADDRESS); - return CBFS_HEADER_INVALID_ADDRESS; + return -1; } - - if (CBFS_HEADER_MAGIC != ntohl(header->magic)) { + else if (CBFS_HEADER_MAGIC != header->magic) { ERROR("Could not find valid CBFS master header at %x: " "%x vs %x.\n", CBFS_HEADER_ROM_ADDRESS, CBFS_HEADER_MAGIC, - ntohl(header->magic)); + header->magic); if (header->magic == 0xffffffff) { ERROR("Maybe ROM is not mapped properly?\n"); } - return CBFS_HEADER_INVALID_ADDRESS; + return -1; } - return header; + return 0; } /* public API starts here*/ -struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) +/* This functions finds the absolute data_offset of a file searched for by name/type + Returns 0 on success and -1 on failure + */ +int cbfs_find_file(struct cbfs_media *media, struct cbfs_file_handle *f, + const char *name, int type) { - const char *file_name; - uint32_t offset, align, romsize, name_len; - const struct cbfs_header *header; - struct cbfs_file file, *file_ptr; + uint32_t offset, align, romsize,name_len; struct cbfs_media default_media; + ssize_t value_read; + const char *file_name; + struct cbfs_header header; if (media == CBFS_DEFAULT_MEDIA) { media = &default_media; if (init_default_cbfs_media(media) != 0) { ERROR("Failed to initialize default media.\n"); - return NULL; + return -1; } } - if (CBFS_HEADER_INVALID_ADDRESS == (header = cbfs_get_header(media))) - return NULL; + if (cbfs_get_header(media, &header)) + return -1; // error - // Logical offset (for source media) of first file. - offset = ntohl(header->offset); - align = ntohl(header->align); - romsize = ntohl(header->romsize); + // Offset (for source media) of first file. + offset = header.offset; + align = header.align; + romsize = header.romsize; - // TODO Add a "size" in CBFS header for a platform independent way to - // determine the end of CBFS data. #if defined(CONFIG_ARCH_X86) && CONFIG_ARCH_X86 - romsize -= htonl(header->bootblocksize); + romsize -= htonl(header.bootblocksize); #endif DEBUG("CBFS location: 0x%x~0x%x, align: %d\n", offset, romsize, align); - DEBUG("Looking for '%s' starting from 0x%x.\n", name, offset); media->open(media); - while (offset < romsize && - media->read(media, &file, offset, sizeof(file)) == sizeof(file)) { - if (memcmp(CBFS_FILE_MAGIC, file.magic, - sizeof(file.magic)) != 0) { + while (offset < romsize) + { + value_read = media->read(media, &f->file, offset, sizeof(f->file)); + if(value_read != sizeof(f->file)){ + return -1; //error: since read not successful + } + //make all ntohl() at once place to avoid any gibberish later + f->file.len = ntohl(f->file.len); + f->file.offset = ntohl(f->file.offset); + f->file.type = ntohl(f->file.type); + + if (memcmp(CBFS_FILE_MAGIC, f->file.magic, + sizeof(f->file.magic)) != 0) { uint32_t new_align = align; if (offset % align) new_align += align - (offset % align); - ERROR("ERROR: No file header found at 0x%x - " - "try next aligned address: 0x%x.\n", offset, - offset + new_align); + ERROR("ERROR: No file header found at 0x%x - try next aligned address: 0x%x.\n", offset,offset+new_align); offset += new_align; continue; } - name_len = ntohl(file.offset) - sizeof(file); - DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset, - name_len); - - // load file name (arbitrary length). - file_name = (const char *)media->map( - media, offset + sizeof(file), name_len); - if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { - ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); - } else if (strcmp(file_name, name) == 0) { - int file_offset = ntohl(file.offset), - file_len = ntohl(file.len); - DEBUG("Found file (offset=0x%x, len=%d).\n", - offset + file_offset, file_len); - media->unmap(media, file_name); - file_ptr = media->map(media, offset, - file_offset + file_len); - media->close(media); - return file_ptr; - } else { - DEBUG(" (unmatched file @0x%x: %s)\n", offset, - file_name); - media->unmap(media, file_name); - } + if (f->file.type == type) { + + name_len = f->file.offset - sizeof(f->file); + DEBUG(" - load entry 0x%x file name (%d bytes)...\n", offset,name_len); + // load file name (arbitrary length). + file_name = (const char *)media->map(media, offset + sizeof(f->file), name_len); + //this mapping done to verify name of file + if (file_name == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + ERROR("ERROR: Failed to get filename: 0x%x.\n", offset); + } else if (strcmp(file_name, name) == 0) { + f->data_offset = offset + f->file.offset; + f->data_len = f->file.len; + media->unmap(media, file_name); + DEBUG("Found file:offset = 0x%x, len=%d\n", f->data_offset, f->data_len); + return 0; + } else { + DEBUG("unmatched file offset = 0x%x : %s\n", offset, file_name); + media->unmap(media,file_name); + } + } // Move to next file. - offset += ntohl(file.len) + ntohl(file.offset); + offset += f->file.len + f->file.offset; if (offset % align) offset += align - (offset % align); + DEBUG("Going for next offset\n"); } media->close(media); - LOG("WARNING: '%s' not found.\n", name); - return NULL; + LOG("Warning: '%s' not found\n",name); + return -1; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type, size_t *sz) -{ - struct cbfs_file *file = cbfs_get_file(media, name); - if (sz) - *sz = 0; +/*Returns pointer to file content inside CBFS after verifying type + */ +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type, size_t *sz) +{ + struct cbfs_file_handle f; + int c; + struct cbfs_media default_media; - if (file == NULL) { - ERROR("Could not find file '%s'.\n", name); - return NULL; + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + ERROR("Failed to initialize default media.\n"); + return NULL; + } } + c = cbfs_find_file(media, &f, name, type); - if (ntohl(file->type) != type) { - ERROR("File '%s' is of type %x, but we requested %x.\n", name, - ntohl(file->type), type); + if (c < 0) { + ERROR("File not found\n"); return NULL; } + DEBUG("Found file. Will be mapping it now!\n"); if (sz) - *sz = ntohl(file->len); + *sz = 0; - return (void *)CBFS_SUBHEADER(file); + if (sz) + *sz = f.data_len; + return media->map(media, f.data_offset, f.data_len); } int cbfs_decompress(int algo, void *src, void *dst, int len)

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coreboot-gerrit July 2014