coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 48f9302 board_status.sh allow cmd() to not save output
by Martin Roth 10 Jul '14

10 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6258 -gerrit commit 48f9302ec5bab7afdaf77134ef87a582e236d13f Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jul 10 14:57:34 2014 -0600 board_status.sh allow cmd() to not save output - allow for cmd() to be run, but not pipe to a file. Change-Id: I3e1650e421a49a06218e082ceb5a60b7b4808ce8 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- util/board_status/board_status.sh | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 7c321b3..20ba48f 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -60,10 +60,16 @@ _cmd() return $EXIT_FAILURE fi + if [ -n "$3" ]; then + pipe_location="${3}" + else + pipe_location="/dev/null" + fi + if [ "$1" -eq "$REMOTE" ] && [ -n "$REMOTE_HOST" ]; then - ssh root@${REMOTE_HOST} "$2" > "${3}" 2>&1 + ssh root@${REMOTE_HOST} "$2" > "$pipe_location" 2>&1 else - $2 > "${3}" 2>&1 + $2 > "$pipe_location" 2>&1 fi return $?

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New patch to review for coreboot: af580b4 board_status.sh add non-fatal test_cmd
by Martin Roth 10 Jul '14

10 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6257 -gerrit commit af580b43b2a8b5e8d338a50e4af1f7ba351cb649 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jun 22 21:46:24 2014 -0600 board_status.sh add non-fatal test_cmd - add a non-fatal option to test_cmd. Change-Id: If74693ea7ec8ea24104d5836e4c24bfb135ef0e1 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- util/board_status/board_status.sh | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 65576f4..7c321b3 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -17,11 +17,15 @@ UPLOAD_RESULTS=0 # if command should be run remoteley when a remote host is specified. LOCAL=0 REMOTE=1 +FATAL=0 +NONFATAL=1 # test a command # # $1: test command on remote host (0=no, 1=yes) # $2: command to test +# $3: 0 ($FATAL) Exit with an error if the command fails +# 1 ($NONFATAL) Don't exit on command test failure test_cmd() { local rc @@ -39,7 +43,11 @@ test_cmd() fi if [ $rc -eq 0 ]; then - return + return 0 + fi + + if [ $3 -eq 1 ]; then + return 1 fi echo "$2 not found"

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New patch to review for coreboot: 4449761 src: Remove 'CONFIG_CHROMEOS' guard around header inclusion
by Edward O'Callaghan 10 Jul '14

10 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6256 -gerrit commit 44497617f9d4733a0c84b858e697e91819fa4395 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Jul 11 05:49:52 2014 +1000 src: Remove 'CONFIG_CHROMEOS' guard around header inclusion No need to guard the pre-processor with the pre-processor. Change-Id: I3eab8b55dc104927a0c6bbe6e09ff9083bccf8d2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/boot/smbios.c | 3 +-- src/cpu/intel/haswell/romstage.c | 4 ---- src/lib/bootmode.c | 2 -- src/lib/coreboot_table.c | 2 -- src/northbridge/intel/haswell/mrccache.c | 2 -- src/northbridge/intel/sandybridge/mrccache.c | 2 -- src/soc/intel/baytrail/mrc_cache.c | 2 -- src/soc/intel/baytrail/romstage/romstage.c | 2 -- src/southbridge/intel/bd82x6x/me.c | 2 -- src/southbridge/intel/fsp_bd82x6x/me.c | 2 -- src/southbridge/intel/fsp_bd82x6x/me_8.x.c | 2 -- src/southbridge/intel/ibexpeak/me.c | 2 -- src/southbridge/intel/lynxpoint/me_9.x.c | 2 -- 13 files changed, 1 insertion(+), 28 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index ce47a8b..c8ca11c 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -30,9 +30,8 @@ #include <cbfs_core.h> #include <arch/byteorder.h> #include <elog.h> -#if CONFIG_CHROMEOS + #include <vendorcode/google/chromeos/gnvs.h> -#endif static u8 smbios_checksum(u8 *p, u32 length) { diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9e27668..541b903 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -36,12 +36,8 @@ #include <ramstage_cache.h> #include <romstage_handoff.h> #include <reset.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> -#endif -#if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> -#endif #include "haswell.h" #include "northbridge/intel/haswell/haswell.h" #include "northbridge/intel/haswell/raminit.h" diff --git a/src/lib/bootmode.c b/src/lib/bootmode.c index 9818490..3d4d871 100644 --- a/src/lib/bootmode.c +++ b/src/lib/bootmode.c @@ -19,9 +19,7 @@ #include <rules.h> #include <bootmode.h> -#if CONFIG_CHROMEOS || CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> -#endif #if CONFIG_BOOTMODE_STRAPS int developer_mode_enabled(void) diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 1e1ad82..0745f4d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -31,13 +31,11 @@ #include <cbfs.h> #include <cbmem.h> #include <bootmem.h> -#if CONFIG_CHROMEOS #if CONFIG_GENERATE_ACPI_TABLES #include <arch/acpi.h> #endif #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> -#endif #if CONFIG_ARCH_X86 #include <cpu/x86/mtrr.h> #endif diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index a921e04..3374b98 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -29,9 +29,7 @@ #include "haswell.h" #include <spi-generic.h> #include <spi_flash.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#endif /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..7951aa9 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -29,9 +29,7 @@ #include "sandybridge.h" #include <spi-generic.h> #include <spi_flash.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#endif /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { diff --git a/src/soc/intel/baytrail/mrc_cache.c b/src/soc/intel/baytrail/mrc_cache.c index ae0afe7..28a8955 100644 --- a/src/soc/intel/baytrail/mrc_cache.c +++ b/src/soc/intel/baytrail/mrc_cache.c @@ -21,9 +21,7 @@ #include <console/console.h> #include <cbmem.h> #include <ip_checksum.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#endif #include <baytrail/mrc_cache.h> #define MRC_DATA_ALIGN 0x1000 diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 3a1d65d..d9f29b1 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -26,9 +26,7 @@ #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> -#if CONFIG_EC_GOOGLE_CHROMEEC #include <ec/google/chromeec/ec.h> -#endif #include <elog.h> #include <ramstage_cache.h> #include <romstage_handoff.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 44c7273..f38063b 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -47,9 +47,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> -#endif #ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index 2282378..deafbc2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -46,9 +46,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> -#endif #ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 1c2ab34..65b9f6d 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -45,10 +45,8 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> -#endif #ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 99920f5..6b8da5b 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -47,9 +47,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/gnvs.h> -#endif #ifndef __SMM__ /* Path that the BIOS should take based on ME state */ diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index c8ff913..ed39636 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -42,10 +42,8 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> -#endif #ifndef __SMM__ /* Path that the BIOS should take based on ME state */

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Patch set updated for coreboot: d59bcd9 src: Make use of 'CEIL_DIV(a, b)' macro across tree
by Edward O'Callaghan 10 Jul '14

10 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6215 -gerrit commit d59bcd953b6acd194cc1b6ffa71095a1cf9cd20d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Jul 8 01:53:24 2014 +1000 src: Make use of 'CEIL_DIV(a, b)' macro across tree The objective here is to tighten coreboot up a bit by not repeating common helpers. This makes the code base more consistent and unified/tight. Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/cpu/allwinner/a10/clock.c | 9 ++------- src/cpu/samsung/exynos5250/cpu.c | 2 +- src/cpu/samsung/exynos5420/clock.c | 7 +------ src/cpu/samsung/exynos5420/cpu.c | 4 ++-- src/cpu/x86/tsc/delay_tsc.c | 2 +- src/northbridge/amd/amdk8/raminit.c | 12 ++++++------ src/northbridge/amd/amdk8/raminit_f.c | 6 +++--- src/northbridge/intel/gm45/raminit.c | 2 +- src/northbridge/intel/i3100/raminit_ep80579.c | 10 +++++----- src/northbridge/intel/nehalem/raminit.c | 4 ++-- src/northbridge/via/vx800/timing_setting.c | 19 ++++++++----------- src/northbridge/via/vx900/raminit_ddr3.c | 22 +++++++++++----------- 12 files changed, 43 insertions(+), 56 deletions(-) diff --git a/src/cpu/allwinner/a10/clock.c b/src/cpu/allwinner/a10/clock.c index 945dfd7..f189aea 100644 --- a/src/cpu/allwinner/a10/clock.c +++ b/src/cpu/allwinner/a10/clock.c @@ -159,11 +159,6 @@ static const struct { { PLL1_CFG(20, 4, 1, 0), 1944 }, }; -static inline u32 div_ceil(u32 a, u32 b) -{ - return (a + b - 1) / b; -} - static void cpu_clk_src_switch(u32 clksel_bits) { u32 reg32; @@ -241,8 +236,8 @@ void a1x_set_cpu_clock(u16 cpu_clk_mhz) * will always be in spec, as long as AHB is in spec, although the max * AHB0 clock we can get is 125 MHz */ - axi = div_ceil(actual_mhz, 450); /* Max 450 MHz */ - ahb = div_ceil(actual_mhz/axi, 250); /* Max 250 MHz */ + axi = CEIL_DIV(actual_mhz, 450); /* Max 450 MHz */ + ahb = CEIL_DIV(actual_mhz/axi, 250); /* Max 250 MHz */ apb0 = 2; /* Max 150 MHz */ ahb_exp = log2_ceil(ahb); diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 2354be1..9a44409 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -140,7 +140,7 @@ static void cpu_enable(device_t dev) u32 lcdbase = get_fb_base_kb() * KiB; ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); + mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); exynos_displayport_init(dev, lcdbase, fb_size); diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 34d3fb5..7ecb717 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -40,11 +40,6 @@ static struct st_epll_con_val epll_div[] = { { 180633600, 0, 45, 3, 1, 10381 } }; -static inline unsigned long div_round_up(unsigned int n, unsigned int d) -{ - return (n + d - 1) / d; -} - /* exynos5: return pll clock frequency */ unsigned long get_pll_clk(int pllreg) { @@ -346,7 +341,7 @@ int clock_set_dwmci(enum periph_id peripheral) if (!sclk) { return -1; } - div = div_round_up(sclk, freq); + div = CEIL_DIV(sclk, freq); set_mmc_clk(device_index, div); return 0; } diff --git a/src/cpu/samsung/exynos5420/cpu.c b/src/cpu/samsung/exynos5420/cpu.c index 5ff345e..176a3f2 100644 --- a/src/cpu/samsung/exynos5420/cpu.c +++ b/src/cpu/samsung/exynos5420/cpu.c @@ -140,7 +140,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, dcache_clean_invalidate_by_mva(lower, upper - lower); mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF); - mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); + mmio_resource(dev, 1, lcdbase/KiB, CEIL_DIV(fb_size, KiB)); } static void tps65090_thru_ec_fet_disable(int index) @@ -160,7 +160,7 @@ static void cpu_enable(device_t dev) u32 lcdbase = get_fb_base_kb() * KiB; ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB - FB_SIZE_KB); - mmio_resource(dev, 1, lcdbase / KiB, (fb_size + KiB - 1) / KiB); + mmio_resource(dev, 1, lcdbase / KiB, CEIL_DIV(fb_size, KiB)); /* * Disable LCD FETs before we do anything with the display. diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index b8f2503..07a4053 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -78,7 +78,7 @@ static unsigned long long calibrate_tsc(void) if (end.lo <= CALIBRATE_DIVISOR) goto bad_ctc; - return (end.lo + CALIBRATE_DIVISOR -1)/CALIBRATE_DIVISOR; + return CEIL_DIV(end.lo, CALIBRATE_DIVISOR); } /* diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 7e42e94..f319450 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -1712,7 +1712,7 @@ static int update_dimm_Trc(const struct mem_controller *ctrl, const struct mem_p if ((value == 0) || (value == 0xff)) { value = param->tRC; } - clocks = ((value << 1) + param->divisor - 1)/param->divisor; + clocks = CEIL_DIV((value << 1), param->divisor); if (clocks < DTL_TRC_MIN) { clocks = DTL_TRC_MIN; } @@ -1741,7 +1741,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_ if ((value == 0) || (value == 0xff)) { value = param->tRFC; } - clocks = ((value << 1) + param->divisor - 1)/param->divisor; + clocks = CEIL_DIV((value << 1), param->divisor); if (clocks < DTL_TRFC_MIN) { clocks = DTL_TRFC_MIN; } @@ -1767,7 +1767,7 @@ static int update_dimm_Trcd(const struct mem_controller *ctrl, const struct mem_ int value; value = spd_read_byte(ctrl->channel0[i], 29); if (value < 0) return -1; - clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1); + clocks = CEIL_DIV(value, (param->divisor << 1)); if (clocks < DTL_TRCD_MIN) { clocks = DTL_TRCD_MIN; } @@ -1792,7 +1792,7 @@ static int update_dimm_Trrd(const struct mem_controller *ctrl, const struct mem_ int value; value = spd_read_byte(ctrl->channel0[i], 28); if (value < 0) return -1; - clocks = (value + (param->divisor << 1) -1)/(param->divisor << 1); + clocks = CEIL_DIV(value, (param->divisor << 1)); if (clocks < DTL_TRRD_MIN) { clocks = DTL_TRRD_MIN; } @@ -1817,7 +1817,7 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_ int value; value = spd_read_byte(ctrl->channel0[i], 30); if (value < 0) return -1; - clocks = ((value << 1) + param->divisor - 1)/param->divisor; + clocks = CEIL_DIV((value << 1), param->divisor); if (clocks < DTL_TRAS_MIN) { clocks = DTL_TRAS_MIN; } @@ -1842,7 +1842,7 @@ static int update_dimm_Trp(const struct mem_controller *ctrl, const struct mem_p int value; value = spd_read_byte(ctrl->channel0[i], 27); if (value < 0) return -1; - clocks = (value + (param->divisor << 1) - 1)/(param->divisor << 1); + clocks = CEIL_DIV(value, (param->divisor << 1)); if (clocks < DTL_TRP_MIN) { clocks = DTL_TRP_MIN; } diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 36e0527..b8417a6 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -1973,7 +1973,7 @@ static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param) value *= 10; printk_raminit("update_dimm_Trc: tRC final value = %i\n", value); - clocks = (value + param->divisor - 1)/param->divisor; + clocks = CEIL_DIV(value, param->divisor); printk_raminit("update_dimm_Trc: clocks = %i\n", clocks); if (clocks < DTL_TRC_MIN) { @@ -2069,7 +2069,7 @@ static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct me value = spd_read_byte(spd_device, SPD_TT); //already in 1/4 ns if (value < 0) return -1; value *=10; - clocks = (value + param->divisor -1)/param->divisor; + clocks = CEIL_DIV(value, param->divisor); if (clocks < TT_MIN) { clocks = TT_MIN; } @@ -2123,7 +2123,7 @@ static int update_dimm_Tras(const struct mem_controller *ctrl, const struct mem_ value *= 10; printk_raminit("update_dimm_Tras: 1 value= %08x\n", value); - clocks = (value + param->divisor - 1)/param->divisor; + clocks = CEIL_DIV(value, param->divisor); printk_raminit("update_dimm_Tras: divisor= %08x\n", param->divisor); printk_raminit("update_dimm_Tras: clocks= %08x\n", clocks); if (clocks < DTL_TRAS_MIN) { diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c index 0636d9f..1f66760 100644 --- a/src/northbridge/intel/gm45/raminit.c +++ b/src/northbridge/intel/gm45/raminit.c @@ -362,7 +362,7 @@ static void collect_ddr3(spdinfo_t *const config) } } -#define ROUNDUP_DIV(val, by) (((val) + (by) - 1) / (by)) +#define ROUNDUP_DIV(val, by) CEIL_DIV(val, by) #define ROUNDUP_DIV_THIS(val, by) val = ROUNDUP_DIV(val, by) static fsb_clock_t read_fsb_clock(void) { diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 90c1005..962b7aa 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -335,7 +335,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACT_TO_ACT_AUTO_REFRESH); val <<= 2; /* convert to 1/4 ns */ val += byte40rem[(val1 >> 4) & 0x7]; - val = (val + ci - 1) / ci + 1; /* convert to cycles */ + val = CEIL_DIV(val, ci) + 1; /* convert to cycles */ if (trc < val) trc = val; val = spd_read_byte(ctrl->channel0[i], SPD_MIN_AUTO_REFRESH_TO_ACT); @@ -343,7 +343,7 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, if (val1 & 0x01) val += 1024; val += byte40rem[(val1 >> 1) & 0x7]; - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (trfc < val) trfc = val; } @@ -360,15 +360,15 @@ static u32 spd_set_drt_attributes(const struct mem_controller *ctrl, continue; val = spd_read_byte(ctrl->channel0[i], SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); val <<= 2; /* convert to 1/4 ns */ - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (tras < val) tras = val; val = spd_read_byte(ctrl->channel0[i], SPD_INT_READ_TO_PRECHARGE_DELAY); - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (trtp < val) trtp = val; val = spd_read_byte(ctrl->channel0[i], SPD_INT_WRITE_TO_READ_DELAY); - val = (val + ci - 1) / ci; /* convert to cycles */ + val = CEIL_DIV(val, ci); /* convert to cycles */ if (twtr < val) twtr = val; } diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 761dc52..6673b5a 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -647,7 +647,7 @@ static void calculate_timings(struct raminfo *info) break; } } - min_cas_latency = (cas_latency_time + cycletime - 1) / cycletime; + min_cas_latency = CEIL_DIV(cas_latency_time, cycletime); cas_latency = 0; while (supported_cas_latencies) { cas_latency = find_highest_bit_set(supported_cas_latencies) + 3; @@ -3337,7 +3337,7 @@ static unsigned gcd(unsigned a, unsigned b) static inline int div_roundup(int a, int b) { - return (a + b - 1) / b; + return CEIL_DIV(a, b); } static unsigned lcm(unsigned a, unsigned b) diff --git a/src/northbridge/via/vx800/timing_setting.c b/src/northbridge/via/vx800/timing_setting.c index df90304..3bd45e4 100644 --- a/src/northbridge/via/vx800/timing_setting.c +++ b/src/northbridge/via/vx800/timing_setting.c @@ -117,8 +117,7 @@ void SetTrp(DRAM_SYS_ATTR * DramAttr) /*Calculate clock,this value should be 2T,3T,4T,5T */ } Tmp = - (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - - 1) / ((DramAttr->DramCyc) << 2)); + (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trp = "); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -168,8 +167,7 @@ void SetTrcd(DRAM_SYS_ATTR * DramAttr) } /*Calculate clock,this value should be 2T,3T,4T,5T */ Tmp = - (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - - 1) / ((DramAttr->DramCyc) << 2)); + (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trcd ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -213,7 +211,7 @@ void SetTras(DRAM_SYS_ATTR * DramAttr) } /*Calculate clock,value range 5T-20T */ - Tmp = (u16) ((Max * 100 + DramAttr->DramCyc - 1) / (DramAttr->DramCyc)); + Tmp = (u16) CEIL_DIV((Max * 100), DramAttr->DramCyc); PRINT_DEBUG_MEM("Tras ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -288,7 +286,7 @@ void SetTrfc(DRAM_SYS_ATTR * DramAttr) } /*Calculate clock,value range 8T-71T */ - Tmp = (u16) ((Max + DramAttr->DramCyc - 1) / (DramAttr->DramCyc)); + Tmp = (u16) CEIL_DIV(Max, DramAttr->DramCyc); PRINT_DEBUG_MEM("Trfc = "); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -334,8 +332,7 @@ void SetTrrd(DRAM_SYS_ATTR * DramAttr) /*Calculate clock,this value should be 2T,3T,4T,5T */ Tmp = - (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - - 1) / ((DramAttr->DramCyc) << 2)); + (u16) CEIL_DIV(Max * 100, (DramAttr->DramCyc) << 2); PRINT_DEBUG_MEM("Trrd ="); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -378,7 +375,7 @@ void SetTwr(DRAM_SYS_ATTR * DramAttr) } } /*Calculate clock */ - Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T + Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T,3T,4T,5T PRINT_DEBUG_MEM("Twr = "); PRINT_DEBUG_MEM_HEX16(Tmp); PRINT_DEBUG_MEM("\r"); @@ -421,7 +418,7 @@ void SetTwtr(DRAM_SYS_ATTR * DramAttr) } } /*Calculate clock */ - Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T + Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T PRINT_DEBUG_MEM("Twtr ="); PRINT_DEBUG_MEM_HEX16(Tmp); @@ -463,7 +460,7 @@ void SetTrtp(DRAM_SYS_ATTR * DramAttr) } } /*Calculate clock */ - Tmp = (u16) ((Max * 100 + ((DramAttr->DramCyc) << 2) - 1) / ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T + Tmp = (u16) CEIL_DIV((Max * 100), ((DramAttr->DramCyc) << 2)); //this value should be 2T or 3T PRINT_DEBUG_MEM("Trtp ="); PRINT_DEBUG_MEM_HEX16(Tmp); diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index a69d699..3979466 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -575,7 +575,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl) printram("Selected DRAM frequency: %u MHz\n", val32); /* Find CAS and CWL latencies */ - val = (ctrl->tAA + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tAA, ctrl->tCK); printram("Minimum CAS latency : %uT\n", val); /* Find lowest supported CAS latency that satisfies the minimum value */ while (!((ctrl->cas_supported >> (val - 4)) & 1) @@ -594,30 +594,30 @@ static void vx900_dram_timing(ramctr_timing * ctrl) pci_write_config8(MCU, 0xc0, reg8); /* Find tRCD */ - val = (ctrl->tRCD + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tRCD, ctrl->tCK); printram("Selected tRCD : %uT\n", val); reg8 = ((val - 4) & 0x7) << 4; /* Find tRP */ - val = (ctrl->tRP + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tRP, ctrl->tCK); printram("Selected tRP : %uT\n", val); reg8 |= ((val - 4) & 0x7); pci_write_config8(MCU, 0xc1, reg8); /* Find tRAS */ - val = (ctrl->tRAS + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tRAS, ctrl->tCK); printram("Selected tRAS : %uT\n", val); reg8 = ((val - 15) & 0x7) << 4; /* Find tWR */ - ctrl->WR = (ctrl->tWR + ctrl->tCK - 1) / ctrl->tCK; + ctrl->WR = CEIL_DIV(ctrl->tWR, ctrl->tCK); printram("Selected tWR : %uT\n", ctrl->WR); reg8 |= ((ctrl->WR - 4) & 0x7); pci_write_config8(MCU, 0xc2, reg8); /* Find tFAW */ - tFAW = (ctrl->tFAW + ctrl->tCK - 1) / ctrl->tCK; + tFAW = CEIL_DIV(ctrl->tFAW, ctrl->tCK); printram("Selected tFAW : %uT\n", tFAW); /* Find tRRD */ - tRRD = (ctrl->tRRD + ctrl->tCK - 1) / ctrl->tCK; + tRRD = CEIL_DIV(ctrl->tRRD, ctrl->tCK); printram("Selected tRRD : %uT\n", tRRD); val = tFAW - 4 * tRRD; /* number of cycles above 4*tRRD */ reg8 = ((val - 0) & 0x7) << 4; @@ -625,11 +625,11 @@ static void vx900_dram_timing(ramctr_timing * ctrl) pci_write_config8(MCU, 0xc3, reg8); /* Find tRTP */ - val = (ctrl->tRTP + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tRTP, ctrl->tCK); printram("Selected tRTP : %uT\n", val); reg8 = ((val & 0x3) << 4); /* Find tWTR */ - val = (ctrl->tWTR + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tWTR, ctrl->tCK); printram("Selected tWTR : %uT\n", val); reg8 |= ((val - 2) & 0x7); pci_mod_config8(MCU, 0xc4, 0x3f, reg8); @@ -642,7 +642,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl) * Since we previously set RxC4[7] */ reg8 = pci_read_config8(MCU, 0xc5); - val = (ctrl->tRFC + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tRFC, ctrl->tCK); printram("Minimum tRFC : %uT\n", val); if (val < 30) { val = 0; @@ -655,7 +655,7 @@ static void vx900_dram_timing(ramctr_timing * ctrl) pci_write_config8(MCU, 0xc5, reg8); /* Where does this go??? */ - val = (ctrl->tRC + ctrl->tCK - 1) / ctrl->tCK; + val = CEIL_DIV(ctrl->tRC, ctrl->tCK); printram("Required tRC : %uT\n", val); }

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New patch to review for coreboot: 76acae8 build system: create .xcompile dependency
by Patrick Georgi 10 Jul '14

10 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6255 -gerrit commit 76acae8b86a40b9c96ad9a17bbc4269bd3a37012 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 21:06:04 2014 +0200 build system: create .xcompile dependency It's probably safe to say that .xcompile needs an update if util/xcompile/xcompile changed, so tell make about this dependency. Updates are honored immediately due to GNU make's feature of reinterpreting everything when an included file changes. See "How Makefiles Are Remade" in the GNU make documentation for details. Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c8cad4f..9422728 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,9 @@ ## SUCH DAMAGE. ## -$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile $(XGCCPATH) > .xcompile))) +.xcompile: util/xcompile/xcompile + bash $< $(XGCCPATH) > $@ + include .xcompile export top := $(CURDIR)

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Patch set updated for coreboot: f5abfd7 build system: remove duplicate architecture list
by Patrick Georgi 10 Jul '14

10 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6254 -gerrit commit f5abfd773d9310b65676a29c71f5673582759482 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 20:38:21 2014 +0200 build system: remove duplicate architecture list Let xcompile pass the list of architectures, given that it already has it. This potentially requires removing $(src)/.xcompile so it gets updated. Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- toolchain.inc | 2 -- util/xcompile/xcompile | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index b5b4fe0..842473b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -17,8 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ARCH_SUPPORTED := armv7 x86_32 - # ccache integration ifeq ($(CONFIG_CCACHE),y) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index d133bd2..b42da7b 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -147,6 +147,7 @@ detect_special_flags() { report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) +ARCH_SUPPORTED+=${TARCH} CC_${TARCH}:=${GCCPREFIX}gcc CFLAGS_${TARCH}:=${CFLAGS} CPP_${TARCH}:=${GCCPREFIX}cpp

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New patch to review for coreboot: 08cf241 build system: remove duplicate architecture list
by Patrick Georgi 10 Jul '14

10 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6254 -gerrit commit 08cf241880ed6fb911b03040a73b270ff200a3f0 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 20:38:21 2014 +0200 build system: remove duplicate architecture list Let xcompile pass the list of architectures, given that it already has it. This potentially requires removing $(src)/.xcompile so it gets updated. Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- toolchain.inc | 2 -- util/xcompile/xcompile | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index b5b4fe0..842473b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -17,8 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ARCH_SUPPORTED := armv7 x86_32 - # ccache integration ifeq ($(CONFIG_CCACHE),y) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index d133bd2..b42da7b 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -147,6 +147,7 @@ detect_special_flags() { report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) +ARCH_SUPPORTED+=${TARCH} CC_${TARCH}:=${GCCPREFIX}gcc CFLAGS_${TARCH}:=${CFLAGS} CPP_${TARCH}:=${GCCPREFIX}cpp

1 0

Patch merged into coreboot/master: 533c119 build system: avoid more race conditions
by gerrit＠coreboot.org 10 Jul '14

10 Jul '14

the following patch was just integrated into master: commit 533c119f5b4fd7725ab3f09a0f3af7b623cc501d Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Thu Jul 10 09:42:03 2014 +0200 build system: avoid more race conditions In an abuild run, cbfstool is built in a shared directory using "make tools". Unfortunately the build system doesn't actually use that binary directly but creates a per-board copy (for convenience purposes when editing the image later) and uses that. With this change the build system uses the original file but still creates the copy for the user, avoiding the race while ensuring convenience. Change-Id: I38c603a7eca5ef859875ad3031bf7a850189645f Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> Reviewed-on: http://review.coreboot.org/6242 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/6242 for details. -gerrit

1 0

Patch merged into coreboot/master: 5b9e6f1 libpayload: Drop obsolete setting of reg_base in [oex]hci
by gerrit＠coreboot.org 10 Jul '14

10 Jul '14

the following patch was just integrated into master: commit 5b9e6f175f7778b16ac988e2de4e271751ecc019 Author: Nico Huber <nico.huber(a)secunet.com> Date: Thu Jul 10 12:56:34 2014 +0200 libpayload: Drop obsolete setting of reg_base in [oex]hci Setting of `controller->reg_base` is of no use here, as it is never read (in another function) later. Looks like this pattern originated from uhci.c where it makes sense. By removing the indirection through `reg_base` we also fix a possible truncation to u32. Change-Id: I5c99c5bf1f5b1d6c04bd84d87fd3e275fd7d0411 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/6251 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6251 for details. -gerrit

1 0

Patch merged into coreboot/master: f4316f8 libpayload: Catch null-pointer dereference in xHCI
by gerrit＠coreboot.org 10 Jul '14

10 Jul '14

the following patch was just integrated into master: commit f4316f8c101b956af624b0c046c418b4489f6558 Author: Nico Huber <nico.huber(a)secunet.com> Date: Mon Jul 7 17:11:53 2014 +0200 libpayload: Catch null-pointer dereference in xHCI Fix a possible null-pointer dereference (hopefully) before anyone runs into this. Also don't switch ports to xHCI if initialization failed. Change-Id: I5dbaeb435a98ead0b50d27fde13c9f1433ea3e81 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: http://review.coreboot.org/6245 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/6245 for details. -gerrit

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coreboot-gerrit July 2014