coreboot-gerrit July 2014

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Patch set updated for coreboot: 78f9994 device/pci_early.c: Mixes up variants of a typedefs to 'u32'
by Edward O'Callaghan 12 Jul '14

12 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6225 -gerrit commit 78f9994b8349410105c7260bf2ac0d362d426183 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 04:55:16 2014 +1000 device/pci_early.c: Mixes up variants of a typedefs to 'u32' Unfortantly coreboot has to deal with ROMCC's short comings which has lead to a little bit of confusion due to typedefs. Essentially, coreboot defines four typedefs: * 'typedef struct device * device_t' in ramstage not in SIMPLE_DEVICE mode * 'typedef u32 device_t' in romstage or when SIMPLE_DEVICE is defined * 'typedef u32 pnp_devfn_t' * 'typedef u32 pci_devfn_t' Some early functions make use of 'device_t' over 'pci_devfn_t' and since the C type-checker does not enforce typedefs to the same type 'u32' these are never noticed. Fix these so that 'device_t' does not conflict in romstage for later work. We later plan to have 'pnp_devfn_t' and 'pci_devfn_t' as the only variants of 'u32' and 'device_t' to be a struct pointer time exclusively. Change-Id: I948801f5be968a934798f1bad7722649758cd4d3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/pci_early.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/device/pci_early.c b/src/device/pci_early.c index e31287e..b9e5c47 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -25,8 +25,7 @@ #include <delay.h> #ifdef __PRE_RAM__ - -unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) +static unsigned pci_find_next_capability(pci_devfn_t dev, unsigned cap, unsigned last) { unsigned pos = 0; u16 status; @@ -69,11 +68,11 @@ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) return 0; } -unsigned pci_find_capability(device_t dev, unsigned cap) +unsigned pci_find_capability(pci_devfn_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } -#endif +#endif /* __PRE_RAM__ */ #if CONFIG_EARLY_PCI_BRIDGE

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Patch set updated for coreboot: 74f63ed superio: Use 'pnp_devfn_t' over 'device_t' in romstage component
by Edward O'Callaghan 12 Jul '14

12 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6231 -gerrit commit 74f63edee2cfa7ecfa105fec57f30a6b305f3c36 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 20:26:25 2014 +1000 superio: Use 'pnp_devfn_t' over 'device_t' in romstage component The romstage component of Super I/O support is in fact written around passing a lower and upper half packed integer. We currently have two typedef's for this, 'device_t' and 'pnp_devfn_t'. We wish to make use of 'pnp_devfn_t' over 'device_t' as 'device_t' changes it's typedef in the ramstage context and so is really a conflicting definition. This helps solve problems down the road to having the 'real' 'device_t' definition usable in romstage later. Change-Id: Ia9f238ebb944f9fe7b274621ee0c09a6de288a76 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/common/early_serial.c | 6 +++--- src/superio/fintek/common/fintek.h | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++---- src/superio/ite/common/early_serial.c | 16 ++++++++-------- src/superio/ite/common/ite.h | 10 +++++----- src/superio/ite/it8661f/early_serial.c | 10 +++++----- src/superio/ite/it8661f/it8661f.h | 2 +- src/superio/ite/it8671f/early_serial.c | 2 +- src/superio/ite/it8671f/it8671f.h | 2 +- src/superio/ite/it8718f/early_serial.c | 2 +- src/superio/ite/it8718f/it8718f.h | 2 +- src/superio/nsc/pc8374/early_init.c | 2 +- src/superio/nsc/pc87309/early_serial.c | 2 +- src/superio/nsc/pc87309/pc87309.h | 2 +- src/superio/nsc/pc87351/early_serial.c | 2 +- src/superio/nsc/pc87360/early_serial.c | 2 +- src/superio/nsc/pc87366/early_serial.c | 2 +- src/superio/nsc/pc87392/early_serial.c | 2 +- src/superio/nsc/pc87417/early_init.c | 6 +++--- src/superio/nsc/pc87417/early_serial.c | 4 ++-- src/superio/nsc/pc87417/pc87417.h | 4 ++-- src/superio/nsc/pc87427/early_init.c | 6 +++--- src/superio/nsc/pc97317/early_serial.c | 2 +- src/superio/nuvoton/common/early_serial.c | 6 +++--- src/superio/nuvoton/common/nuvoton.h | 2 +- src/superio/nuvoton/nct5104d/early_init.c | 6 +++--- src/superio/nuvoton/nct5104d/nct5104d.h | 2 +- src/superio/serverengines/pilot/early_init.c | 2 +- src/superio/serverengines/pilot/early_serial.c | 8 ++++---- src/superio/serverengines/pilot/pilot.h | 10 +++++----- src/superio/smsc/fdc37m60x/early_serial.c | 2 +- src/superio/smsc/kbc1100/early_init.c | 8 ++++---- src/superio/smsc/kbc1100/kbc1100.h | 2 +- src/superio/smsc/lpc47b272/early_serial.c | 6 +++--- src/superio/smsc/lpc47b397/early_serial.c | 6 +++--- src/superio/smsc/lpc47m10x/early_serial.c | 6 +++--- src/superio/smsc/lpc47m15x/early_serial.c | 6 +++--- src/superio/smsc/lpc47n217/early_serial.c | 10 +++++----- src/superio/smsc/lpc47n227/early_serial.c | 10 +++++----- src/superio/smsc/sch4037/sch4037_early_init.c | 6 +++--- src/superio/smsc/sio1036/sio1036_early_init.c | 8 ++++---- src/superio/smsc/smscsuperio/early_serial.c | 6 +++--- src/superio/smsc/smscsuperio/smscsuperio.h | 2 +- src/superio/winbond/common/early_serial.c | 6 +++--- src/superio/winbond/common/winbond.h | 2 +- src/superio/winbond/w83627dhg/early_serial.c | 8 ++++---- src/superio/winbond/w83627dhg/w83627dhg.h | 8 ++++---- src/superio/winbond/w83627ehg/early_serial.c | 4 ++-- src/superio/winbond/w83627ehg/w83627ehg.h | 4 ++-- src/superio/winbond/w83627hf/early_init.c | 6 +++--- src/superio/winbond/w83627hf/early_serial.c | 8 ++++---- src/superio/winbond/w83627hf/w83627hf.h | 4 ++-- src/superio/winbond/w83627thg/w83627thg.h | 6 +++--- src/superio/winbond/w83697hf/early_serial.c | 8 ++++---- src/superio/winbond/w83697hf/w83697hf.h | 4 ++-- src/superio/winbond/w83977f/early_serial.c | 6 +++--- src/superio/winbond/w83977tf/early_serial.c | 6 +++--- 57 files changed, 146 insertions(+), 146 deletions(-) diff --git a/src/superio/fintek/common/early_serial.c b/src/superio/fintek/common/early_serial.c index d74b786..4433d11 100644 --- a/src/superio/fintek/common/early_serial.c +++ b/src/superio/fintek/common/early_serial.c @@ -46,7 +46,7 @@ #define FINTEK_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(FINTEK_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void fintek_enable_serial(device_t dev, u16 iobase) +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/fintek/common/fintek.h b/src/superio/fintek/common/fintek.h index a08cf92..1bc308b 100644 --- a/src/superio/fintek/common/fintek.h +++ b/src/superio/fintek/common/fintek.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void fintek_enable_serial(device_t dev, u16 iobase); +void fintek_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_FINTEK_COMMON_ROMSTAGE_H */ diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..96bb550 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "i3100.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -29,7 +29,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(0x86, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -38,14 +38,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +static void i3100_configure_uart_clk(pnp_devfn_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +static void i3100_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c index 73354d4..a57c047 100644 --- a/src/superio/ite/common/early_serial.c +++ b/src/superio/ite/common/early_serial.c @@ -33,14 +33,14 @@ #define ITE_CONFIG_REG_WATCHDOG 0x72 /* watchdog config */ /* Helper procedure */ -static void ite_sio_write(device_t dev, u8 reg, u8 value) +static void ite_sio_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_set_logical_device(dev); pnp_write_config(dev, reg, value); } /* Enable configuration */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; @@ -51,12 +51,12 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); } -void ite_reg_write(device_t dev, u8 reg, u8 value) +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value) { pnp_enter_conf_state(dev); ite_sio_write(dev, reg, value); @@ -71,13 +71,13 @@ void ite_reg_write(device_t dev, u8 reg, u8 value) * ITE_UART_CLK_PREDIVIDE_24 * ITE_UART_CLK_PREDIVIDE_48 (default) */ -void ite_conf_clkin(device_t dev, u8 predivide) +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide) { ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); } /* Bring up early serial debugging output before the RAM is initialized. */ -void ite_enable_serial(device_t dev, u16 iobase) +void ite_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -101,7 +101,7 @@ void ite_enable_serial(device_t dev, u16 iobase) * and pass: GPIO_DEV */ -void ite_enable_3vsbsw(device_t dev) +void ite_enable_3vsbsw(pnp_devfn_t dev) { u8 tmp; pnp_enter_conf_state(dev); @@ -118,7 +118,7 @@ void ite_enable_3vsbsw(device_t dev) * and pass: GPIO_DEV */ -void ite_kill_watchdog(device_t dev) +void ite_kill_watchdog(pnp_devfn_t dev) { pnp_enter_conf_state(dev); ite_sio_write(dev, ITE_CONFIG_REG_WATCHDOG, 0x00); diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h index 5389f14..c732664 100644 --- a/src/superio/ite/common/ite.h +++ b/src/superio/ite/common/ite.h @@ -27,12 +27,12 @@ #define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ #define ITE_UART_CLK_PREDIVIDE_24 0x01 -void ite_conf_clkin(device_t dev, u8 predivide); -void ite_enable_serial(device_t dev, u16 iobase); +void ite_conf_clkin(pnp_devfn_t dev, u8 predivide); +void ite_enable_serial(pnp_devfn_t dev, u16 iobase); /* Some boards need to init wdt+gpio's very early */ -void ite_reg_write(device_t dev, u8 reg, u8 value); -void ite_enable_3vsbsw(device_t dev); -void ite_kill_watchdog(device_t dev); +void ite_reg_write(pnp_devfn_t dev, u8 reg, u8 value); +void ite_enable_3vsbsw(pnp_devfn_t dev); +void ite_kill_watchdog(pnp_devfn_t dev); #endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8661f/early_serial.c b/src/superio/ite/it8661f/early_serial.c index 7373f71..19d60b1 100644 --- a/src/superio/ite/it8661f/early_serial.c +++ b/src/superio/ite/it8661f/early_serial.c @@ -26,7 +26,7 @@ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { int i; u16 port = dev >> 8; @@ -42,7 +42,7 @@ static void pnp_enter_ext_func_mode(device_t dev) outb(init_values[i], port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); } @@ -55,21 +55,21 @@ static void pnp_exit_ext_func_mode(device_t dev) * * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. */ -static void it8661f_enable_logical_devices(device_t dev) +static void it8661f_enable_logical_devices(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); pnp_exit_ext_func_mode(dev); } -static void it8661f_set_clkin(device_t dev, u8 clkin) +static void it8661f_set_clkin(pnp_devfn_t dev, u8 clkin) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); pnp_exit_ext_func_mode(dev); } -void it8661f_enable_serial(device_t dev, u16 iobase) +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/ite/it8661f/it8661f.h b/src/superio/ite/it8661f/it8661f.h index 045a54c..297dea3 100644 --- a/src/superio/ite/it8661f/it8661f.h +++ b/src/superio/ite/it8661f/it8661f.h @@ -52,6 +52,6 @@ static const u8 init_values[] = { 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -void it8661f_enable_serial(device_t dev, u16 iobase); +void it8661f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8661F_H */ diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index 9f35b8a..89feb5f 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -89,7 +89,7 @@ void it8671f_48mhz_clkin(void) } /* Enable the serial port(s). */ -void it8671f_enable_serial(device_t dev, u16 iobase) +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase) { it8671f_enter_conf(); diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index c3865ff..90f1481 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -34,6 +34,6 @@ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ void it8671f_48mhz_clkin(void); -void it8671f_enable_serial(device_t dev, u16 iobase); +void it8671f_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_ITE_IT8671F__H */ diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 166c856..563132a 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -27,7 +27,7 @@ * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(device_t dev) +void it8718f_disable_reboot(pnp_devfn_t dev) { ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 61c75cf..c0a79c2 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -35,6 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -void it8718f_disable_reboot(device_t dev); +void it8718f_disable_reboot(pnp_devfn_t dev); #endif /* SUPERIO_ITE_IT8718F_H */ diff --git a/src/superio/nsc/pc8374/early_init.c b/src/superio/nsc/pc8374/early_init.c index d3f601d..a5e9b95 100644 --- a/src/superio/nsc/pc8374/early_init.c +++ b/src/superio/nsc/pc8374/early_init.c @@ -46,7 +46,7 @@ static void pc8374_enable(u16 iobase, u8 *init) } } -static void pc8374_enable_dev(device_t dev, u16 iobase) +static void pc8374_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/early_serial.c b/src/superio/nsc/pc87309/early_serial.c index 6e48e0c..da0d5d7 100644 --- a/src/superio/nsc/pc87309/early_serial.c +++ b/src/superio/nsc/pc87309/early_serial.c @@ -22,7 +22,7 @@ #include <device/pnp_def.h> #include "pc87309.h" -void pc87309_enable_serial(device_t dev, u16 iobase) +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87309/pc87309.h b/src/superio/nsc/pc87309/pc87309.h index 5f39b6e..513576e 100644 --- a/src/superio/nsc/pc87309/pc87309.h +++ b/src/superio/nsc/pc87309/pc87309.h @@ -34,6 +34,6 @@ #include <arch/io.h> #include <stdint.h> -void pc87309_enable_serial(device_t dev, u16 iobase); +void pc87309_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NSC_PC87309_H */ diff --git a/src/superio/nsc/pc87351/early_serial.c b/src/superio/nsc/pc87351/early_serial.c index c34538f..a31f79c 100644 --- a/src/superio/nsc/pc87351/early_serial.c +++ b/src/superio/nsc/pc87351/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87351.h" -static void pc87351_enable_serial(device_t dev, u16 iobase) +static void pc87351_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87360/early_serial.c b/src/superio/nsc/pc87360/early_serial.c index da4abdb..3deac3b 100644 --- a/src/superio/nsc/pc87360/early_serial.c +++ b/src/superio/nsc/pc87360/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87360.h" -static void pc87360_enable_serial(device_t dev, u16 iobase) +static void pc87360_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87366/early_serial.c b/src/superio/nsc/pc87366/early_serial.c index e173afd..e663df6 100644 --- a/src/superio/nsc/pc87366/early_serial.c +++ b/src/superio/nsc/pc87366/early_serial.c @@ -22,7 +22,7 @@ #include <arch/io.h> #include "pc87366.h" -static void pc87366_enable_serial(device_t dev, u16 iobase) +static void pc87366_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87392/early_serial.c b/src/superio/nsc/pc87392/early_serial.c index 6e85fb9..f1e5716 100644 --- a/src/superio/nsc/pc87392/early_serial.c +++ b/src/superio/nsc/pc87392/early_serial.c @@ -21,7 +21,7 @@ #include <arch/io.h> #include "pc87392.h" -static void pc87392_enable_serial(device_t dev, u16 iobase) +static void pc87392_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); diff --git a/src/superio/nsc/pc87417/early_init.c b/src/superio/nsc/pc87417/early_init.c index d1870f9..42f8cd1 100644 --- a/src/superio/nsc/pc87417/early_init.c +++ b/src/superio/nsc/pc87417/early_init.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "pc87417.h" -static void pc87417_disable_dev(device_t dev) +static void pc87417_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(device_t dev, u16 iobase) +static void pc87417_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -37,7 +37,7 @@ static void pc87417_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc87417/early_serial.c b/src/superio/nsc/pc87417/early_serial.c index 33bae7e..42ba941 100644 --- a/src/superio/nsc/pc87417/early_serial.c +++ b/src/superio/nsc/pc87417/early_serial.c @@ -23,7 +23,7 @@ #include <arch/io.h> #include "pc87417.h" -void pc87417_enable_serial(device_t dev, u16 iobase) +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -31,7 +31,7 @@ void pc87417_enable_serial(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -void pc87417_enable_dev(device_t dev) +void pc87417_enable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 1); diff --git a/src/superio/nsc/pc87417/pc87417.h b/src/superio/nsc/pc87417/pc87417.h index 73c1fbc..e7d5413 100644 --- a/src/superio/nsc/pc87417/pc87417.h +++ b/src/superio/nsc/pc87417/pc87417.h @@ -115,8 +115,8 @@ #define PC87417_XWBCNF 0x16 #if defined(__PRE_RAM__) -void pc87417_enable_serial(device_t dev, u16 iobase); -void pc87417_enable_dev(device_t dev); +void pc87417_enable_serial(pnp_devfn_t dev, u16 iobase); +void pc87417_enable_dev(pnp_devfn_t dev); #endif #endif diff --git a/src/superio/nsc/pc87427/early_init.c b/src/superio/nsc/pc87427/early_init.c index 6df1b9f..adaa868 100644 --- a/src/superio/nsc/pc87427/early_init.c +++ b/src/superio/nsc/pc87427/early_init.c @@ -22,13 +22,13 @@ #include <arch/io.h> #include "pc87427.h" -static void pc87427_disable_dev(device_t dev) +static void pc87427_disable_dev(pnp_devfn_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87427_enable_dev(device_t dev, u16 iobase) +static void pc87427_enable_dev(pnp_devfn_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -36,7 +36,7 @@ static void pc87427_enable_dev(device_t dev, u16 iobase) pnp_set_enable(dev, 1); } -static void xbus_cfg(device_t dev) +static void xbus_cfg(pnp_devfn_t dev) { u8 i, data; u16 xbus_index; diff --git a/src/superio/nsc/pc97317/early_serial.c b/src/superio/nsc/pc97317/early_serial.c index 0c21561..ad43010 100644 --- a/src/superio/nsc/pc97317/early_serial.c +++ b/src/superio/nsc/pc97317/early_serial.c @@ -25,7 +25,7 @@ #define PM_BASE 0xe8 /* The PC97317 needs clocks to be set up before the serial port will operate. */ -static void pc97317_enable_serial(device_t dev, u16 iobase) +static void pc97317_enable_serial(pnp_devfn_t dev, u16 iobase) { /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); diff --git a/src/superio/nuvoton/common/early_serial.c b/src/superio/nuvoton/common/early_serial.c index 1cbcee8..dbb0d13 100644 --- a/src/superio/nuvoton/common/early_serial.c +++ b/src/superio/nuvoton/common/early_serial.c @@ -49,7 +49,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -57,14 +57,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void nuvoton_enable_serial(device_t dev, u16 iobase) +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/nuvoton/common/nuvoton.h b/src/superio/nuvoton/common/nuvoton.h index e9e8d4b..43d80a9 100644 --- a/src/superio/nuvoton/common/nuvoton.h +++ b/src/superio/nuvoton/common/nuvoton.h @@ -25,6 +25,6 @@ #include <arch/io.h> #include <stdint.h> -void nuvoton_enable_serial(device_t dev, u16 iobase); +void nuvoton_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_NUVOTON_COMMON_ROMSTAGE_H */ diff --git a/src/superio/nuvoton/nct5104d/early_init.c b/src/superio/nuvoton/nct5104d/early_init.c index c9a408e..96fac19 100644 --- a/src/superio/nuvoton/nct5104d/early_init.c +++ b/src/superio/nuvoton/nct5104d/early_init.c @@ -28,7 +28,7 @@ /* Enable configuration: pass entry key '0x87' into index port dev * two times. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_ENTRY_KEY, port); @@ -36,14 +36,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(NUVOTON_EXIT_KEY, port); } /* Route UARTD to pins 41-48 */ -void nct5104d_enable_uartd(device_t dev) +void nct5104d_enable_uartd(pnp_devfn_t dev) { u8 tmp; u16 port = dev >> 8; diff --git a/src/superio/nuvoton/nct5104d/nct5104d.h b/src/superio/nuvoton/nct5104d/nct5104d.h index e4dcf38..5b12cc5 100644 --- a/src/superio/nuvoton/nct5104d/nct5104d.h +++ b/src/superio/nuvoton/nct5104d/nct5104d.h @@ -48,6 +48,6 @@ #define NCT5104D_GPIO1 ((1 << 8) | NCT5104D_GPIO_V) #define NCT5104D_GPIO6 ((6 << 8) | NCT5104D_GPIO_V) -void nct5104d_enable_uartd(device_t dev); +void nct5104d_enable_uartd(pnp_devfn_t dev); #endif /* SUPERIO_NUVOTON_NCT5104D_H */ diff --git a/src/superio/serverengines/pilot/early_init.c b/src/superio/serverengines/pilot/early_init.c index 002210f..6635645 100644 --- a/src/superio/serverengines/pilot/early_init.c +++ b/src/superio/serverengines/pilot/early_init.c @@ -32,7 +32,7 @@ * Logical device 4, 5 and 7 are being deactivated. Logical Device 1 seems to * be another serial (?), it is also deactivated on the HP machine. */ -void pilot_early_init(device_t dev) +void pilot_early_init(pnp_devfn_t dev) { u16 port = dev >> 8; diff --git a/src/superio/serverengines/pilot/early_serial.c b/src/superio/serverengines/pilot/early_serial.c index 82e124c..3e99ef4 100644 --- a/src/superio/serverengines/pilot/early_serial.c +++ b/src/superio/serverengines/pilot/early_serial.c @@ -26,20 +26,20 @@ #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x5A, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xA5, port); } /* Serial config is a fairly standard procedure. */ -void pilot_enable_serial(device_t dev, u16 iobase) +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -48,7 +48,7 @@ void pilot_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void pilot_disable_serial(device_t dev) +void pilot_disable_serial(pnp_devfn_t dev) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/serverengines/pilot/pilot.h b/src/superio/serverengines/pilot/pilot.h index e19cf37..cffa258 100644 --- a/src/superio/serverengines/pilot/pilot.h +++ b/src/superio/serverengines/pilot/pilot.h @@ -31,12 +31,12 @@ #define PILOT_LD7 0x07 /* Logical device 7 */ /* should not expose these however early_init needs love */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void pilot_early_init(device_t dev); +void pilot_early_init(pnp_devfn_t dev); -void pilot_enable_serial(device_t dev, u16 iobase); -void pilot_disable_serial(device_t dev); +void pilot_enable_serial(pnp_devfn_t dev, u16 iobase); +void pilot_disable_serial(pnp_devfn_t dev); #endif /* SUPERIO_SERVERENGINES_PILOT_PILOT_H */ diff --git a/src/superio/smsc/fdc37m60x/early_serial.c b/src/superio/smsc/fdc37m60x/early_serial.c index 38cb0f8..80258a9 100644 --- a/src/superio/smsc/fdc37m60x/early_serial.c +++ b/src/superio/smsc/fdc37m60x/early_serial.c @@ -46,7 +46,7 @@ static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) } /* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, u16 iobase) +static void fdc37m60x_enable_serial(pnp_devfn_t dev, u16 iobase) { /* (1) Enter the configuration state. */ outb(0x55, FDC37M60X_CONFIGURATION_PORT); diff --git a/src/superio/smsc/kbc1100/early_init.c b/src/superio/smsc/kbc1100/early_init.c index d075f9c..bd42288 100644 --- a/src/superio/smsc/kbc1100/early_init.c +++ b/src/superio/smsc/kbc1100/early_init.c @@ -26,19 +26,19 @@ #include "kbc1100.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void kbc1100_early_serial(device_t dev, u16 iobase) +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); @@ -50,7 +50,7 @@ void kbc1100_early_serial(device_t dev, u16 iobase) void kbc1100_early_init(u16 port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, KBC1100_KBC); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/kbc1100/kbc1100.h b/src/superio/smsc/kbc1100/kbc1100.h index 2b588f9..ec24dd3 100644 --- a/src/superio/smsc/kbc1100/kbc1100.h +++ b/src/superio/smsc/kbc1100/kbc1100.h @@ -36,7 +36,7 @@ #define KBC1100_EC1 0x0D /* EC Channel 1 */ #define KBC1100_EC2 0x0E /* EC Channel 2 */ -void kbc1100_early_serial(device_t dev, u16 iobase); +void kbc1100_early_serial(pnp_devfn_t dev, u16 iobase); void kbc1100_early_init(u16 port); #endif /* SUPERIO_SMSC_KBC1100_H */ diff --git a/src/superio/smsc/lpc47b272/early_serial.c b/src/superio/smsc/lpc47b272/early_serial.c index b2f0d1b..3624df2 100644 --- a/src/superio/smsc/lpc47b272/early_serial.c +++ b/src/superio/smsc/lpc47b272/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47b272.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47b272_enable_serial(device_t dev, u16 iobase) +static void lpc47b272_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47b397/early_serial.c b/src/superio/smsc/lpc47b397/early_serial.c index 31d515b..953cd4b 100644 --- a/src/superio/smsc/lpc47b397/early_serial.c +++ b/src/superio/smsc/lpc47b397/early_serial.c @@ -23,19 +23,19 @@ #include <arch/io.h> #include "lpc47b397.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void lpc47b397_enable_serial(device_t dev, u16 iobase) +static void lpc47b397_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m10x/early_serial.c b/src/superio/smsc/lpc47m10x/early_serial.c index fc6efb9..1174120 100644 --- a/src/superio/smsc/lpc47m10x/early_serial.c +++ b/src/superio/smsc/lpc47m10x/early_serial.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "lpc47m10x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -40,7 +40,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(device_t dev, u16 iobase) +static void lpc47m10x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47m15x/early_serial.c b/src/superio/smsc/lpc47m15x/early_serial.c index 7d75bae..5a16c25 100644 --- a/src/superio/smsc/lpc47m15x/early_serial.c +++ b/src/superio/smsc/lpc47m15x/early_serial.c @@ -22,19 +22,19 @@ #include <arch/io.h> #include "lpc47m15x.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) +static inline void lpc47m15x_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/lpc47n217/early_serial.c b/src/superio/smsc/lpc47n217/early_serial.c index 451628a..7405f32 100644 --- a/src/superio/smsc/lpc47n217/early_serial.c +++ b/src/superio/smsc/lpc47n217/early_serial.c @@ -24,13 +24,13 @@ #include <assert.h> #include "lpc47n217.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n217_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); @@ -74,7 +74,7 @@ static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n217_pnp_set_enable(device_t dev, int enable) +static void lpc47n217_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -109,7 +109,7 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(device_t dev, u16 iobase) +static void lpc47n217_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/lpc47n227/early_serial.c b/src/superio/smsc/lpc47n227/early_serial.c index 4aea7c5..64a6d84 100644 --- a/src/superio/smsc/lpc47n227/early_serial.c +++ b/src/superio/smsc/lpc47n227/early_serial.c @@ -23,13 +23,13 @@ #include <arch/io.h> #include "lpc47n227.h" -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -41,7 +41,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) +static void lpc47n227_pnp_set_iobase(pnp_devfn_t dev, u16 iobase) { /* LPC47N227 requires base ports to be a multiple of 4. */ /* it's not very useful to do an ASSERT here: if it trips, @@ -76,7 +76,7 @@ static void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param enable 0 to disable, anythig else to enable. */ -static void lpc47n227_pnp_set_enable(device_t dev, int enable) +static void lpc47n227_pnp_set_enable(pnp_devfn_t dev, int enable) { u8 power_register = 0, power_mask = 0, current_power, new_power; @@ -111,7 +111,7 @@ static void lpc47n227_pnp_set_enable(device_t dev, int enable) * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n227_enable_serial(device_t dev, u16 iobase) +static void lpc47n227_enable_serial(pnp_devfn_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip diff --git a/src/superio/smsc/sch4037/sch4037_early_init.c b/src/superio/smsc/sch4037/sch4037_early_init.c index 29517ed..5be8fa8 100644 --- a/src/superio/smsc/sch4037/sch4037_early_init.c +++ b/src/superio/smsc/sch4037/sch4037_early_init.c @@ -21,13 +21,13 @@ #include <arch/io.h> #include "sch4037.h" -static inline void pnp_enter_conf_state(device_t dev) +static inline void pnp_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0x55, port); } -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0xaa, port); @@ -35,7 +35,7 @@ static void pnp_exit_conf_state(device_t dev) static inline void sch4037_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV(port, SMSCSUPERIO_SP1); pnp_enter_conf_state(dev); diff --git a/src/superio/smsc/sio1036/sio1036_early_init.c b/src/superio/smsc/sio1036/sio1036_early_init.c index 52232a5..9b1be52 100644 --- a/src/superio/smsc/sio1036/sio1036_early_init.c +++ b/src/superio/smsc/sio1036/sio1036_early_init.c @@ -25,13 +25,13 @@ #ifndef CONFIG_TTYS0_BASE #define CONFIG_TTYS0_BASE 0x3F8 #endif -static inline void sio1036_enter_conf_state(device_t dev) +static inline void sio1036_enter_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0x55, port); } -static inline void sio1036_exit_conf_state(device_t dev) +static inline void sio1036_exit_conf_state(pnp_devfn_t dev) { unsigned port = dev>>8; outb(0xaa, port); @@ -39,7 +39,7 @@ static inline void sio1036_exit_conf_state(device_t dev) static u8 detect_sio1036_chip(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, SIO1036_SP1); unsigned data; sio1036_enter_conf_state (dev); @@ -57,7 +57,7 @@ static u8 detect_sio1036_chip(unsigned port) static inline void sio1036_early_init(unsigned port) { - device_t dev; + pnp_devfn_t dev; dev = PNP_DEV (port, SIO1036_SP1); if (detect_sio1036_chip(port) != 0) { diff --git a/src/superio/smsc/smscsuperio/early_serial.c b/src/superio/smsc/smscsuperio/early_serial.c index e2eea6d..c058ef5 100644 --- a/src/superio/smsc/smscsuperio/early_serial.c +++ b/src/superio/smsc/smscsuperio/early_serial.c @@ -29,14 +29,14 @@ #define SMSC_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_ENTRY_KEY, port); } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(SMSC_EXIT_KEY, port); @@ -49,7 +49,7 @@ static void pnp_exit_conf_state(device_t dev) * @param dev The device to use. * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ -void smscsuperio_enable_serial(device_t dev, u16 iobase) +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/smsc/smscsuperio/smscsuperio.h b/src/superio/smsc/smscsuperio/smscsuperio.h index 60a58e6..8a761ba 100644 --- a/src/superio/smsc/smscsuperio/smscsuperio.h +++ b/src/superio/smsc/smscsuperio/smscsuperio.h @@ -30,6 +30,6 @@ #define SMSCSUPERIO_SP1 4 /* Com1 */ #define SMSCSUPERIO_SP2 5 /* Com2 */ -void smscsuperio_enable_serial(device_t dev, u16 iobase); +void smscsuperio_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_SMSC_SMSCSUPERIO_H */ diff --git a/src/superio/winbond/common/early_serial.c b/src/superio/winbond/common/early_serial.c index 747cc45..fd51cd5 100644 --- a/src/superio/winbond/common/early_serial.c +++ b/src/superio/winbond/common/early_serial.c @@ -46,7 +46,7 @@ #define WINBOND_EXIT_KEY 0xAA /* Enable configuration: pass entry key '0x87' into index port dev. */ -static void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_ENTRY_KEY, port); @@ -54,14 +54,14 @@ static void pnp_enter_conf_state(device_t dev) } /* Disable configuration: pass exit key '0xAA' into index port dev. */ -static void pnp_exit_conf_state(device_t dev) +static void pnp_exit_conf_state(pnp_devfn_t dev) { u16 port = dev >> 8; outb(WINBOND_EXIT_KEY, port); } /* Bring up early serial debugging output before the RAM is initialized. */ -void winbond_enable_serial(device_t dev, u16 iobase) +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/common/winbond.h b/src/superio/winbond/common/winbond.h index 20eefc8..0f937c1 100644 --- a/src/superio/winbond/common/winbond.h +++ b/src/superio/winbond/common/winbond.h @@ -24,6 +24,6 @@ #include <arch/io.h> #include <stdint.h> -void winbond_enable_serial(device_t dev, u16 iobase); +void winbond_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_COMMON_ROMSTAGE_H */ diff --git a/src/superio/winbond/w83627dhg/early_serial.c b/src/superio/winbond/w83627dhg/early_serial.c index 67aaa93..83f8e34 100644 --- a/src/superio/winbond/w83627dhg/early_serial.c +++ b/src/superio/winbond/w83627dhg/early_serial.c @@ -24,14 +24,14 @@ #include <stdint.h> #include "w83627dhg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -42,7 +42,7 @@ void pnp_exit_ext_func_mode(device_t dev) * {Pin 89, Pin 90} function can be selected as {GP33, GP32}, or * {RSTOUT3#, RSTOUT2#} or {SDA, SCL} */ -void w83627dhg_enable_i2c(device_t dev) +void w83627dhg_enable_i2c(pnp_devfn_t dev) { u8 val; @@ -56,7 +56,7 @@ void w83627dhg_enable_i2c(device_t dev) pnp_exit_ext_func_mode(dev); } -void w83627dhg_set_clksel_48(device_t dev) +void w83627dhg_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627dhg/w83627dhg.h b/src/superio/winbond/w83627dhg/w83627dhg.h index 08ea04f..c4ead34 100644 --- a/src/superio/winbond/w83627dhg/w83627dhg.h +++ b/src/superio/winbond/w83627dhg/w83627dhg.h @@ -52,9 +52,9 @@ /* Note: There is no GPIO1 on the W83627DHG as per datasheet. */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); -void w83627dhg_enable_i2c(device_t dev); -void w83627dhg_set_clksel_48(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); +void w83627dhg_enable_i2c(pnp_devfn_t dev); +void w83627dhg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627DHG_H */ diff --git a/src/superio/winbond/w83627ehg/early_serial.c b/src/superio/winbond/w83627ehg/early_serial.c index 346d6cf..e052863 100644 --- a/src/superio/winbond/w83627ehg/early_serial.c +++ b/src/superio/winbond/w83627ehg/early_serial.c @@ -23,14 +23,14 @@ #include <device/pnp.h> #include "w83627ehg.h" -void pnp_enter_ext_func_mode(device_t dev) +void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -void pnp_exit_ext_func_mode(device_t dev) +void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); diff --git a/src/superio/winbond/w83627ehg/w83627ehg.h b/src/superio/winbond/w83627ehg/w83627ehg.h index 221de7b..3d6f56f 100644 --- a/src/superio/winbond/w83627ehg/w83627ehg.h +++ b/src/superio/winbond/w83627ehg/w83627ehg.h @@ -54,7 +54,7 @@ #define W83627EHG_GPIO4 ((2 << 8) | W83627EHG_GPIO_SUSLED_V) #define W83627EHG_GPIO5 ((3 << 8) | W83627EHG_GPIO_SUSLED_V) -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627EHG_H */ diff --git a/src/superio/winbond/w83627hf/early_init.c b/src/superio/winbond/w83627hf/early_init.c index db616ae..2e275e6 100644 --- a/src/superio/winbond/w83627hf/early_init.c +++ b/src/superio/winbond/w83627hf/early_init.c @@ -25,14 +25,14 @@ #include <device/pnp.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -43,7 +43,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * work around a limitation of ROMCC where we can no make early_serial.c into * link-time symbols and #include early_serial.c. */ -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/early_serial.c b/src/superio/winbond/w83627hf/early_serial.c index bc251a6..694a3fe 100644 --- a/src/superio/winbond/w83627hf/early_serial.c +++ b/src/superio/winbond/w83627hf/early_serial.c @@ -24,14 +24,14 @@ #include <arch/io.h> #include "w83627hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); @@ -49,7 +49,7 @@ static void pnp_exit_ext_func_mode(device_t dev) * XXX: ROMCC - everything is inlined, no forwarding function prototypes * declarations are accepted. */ -void w83627hf_enable_serial(device_t dev, u16 iobase) +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -59,7 +59,7 @@ void w83627hf_enable_serial(device_t dev, u16 iobase) pnp_exit_ext_func_mode(dev); } -void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; diff --git a/src/superio/winbond/w83627hf/w83627hf.h b/src/superio/winbond/w83627hf/w83627hf.h index bf7186e..6eeb62b 100644 --- a/src/superio/winbond/w83627hf/w83627hf.h +++ b/src/superio/winbond/w83627hf/w83627hf.h @@ -115,7 +115,7 @@ #include <arch/io.h> -void w83627hf_set_clksel_48(device_t dev); -void w83627hf_enable_serial(device_t dev, u16 iobase); +void w83627hf_set_clksel_48(pnp_devfn_t dev); +void w83627hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83627HF_H */ diff --git a/src/superio/winbond/w83627thg/w83627thg.h b/src/superio/winbond/w83627thg/w83627thg.h index ec857d3..8d85379 100644 --- a/src/superio/winbond/w83627thg/w83627thg.h +++ b/src/superio/winbond/w83627thg/w83627thg.h @@ -34,9 +34,9 @@ #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware monitor */ -void pnp_enter_ext_func_mode(device_t dev); -void pnp_exit_ext_func_mode(device_t dev); +void pnp_enter_ext_func_mode(pnp_devfn_t dev); +void pnp_exit_ext_func_mode(pnp_devfn_t dev); -void w83627thg_set_clksel_48(device_t dev); +void w83627thg_set_clksel_48(pnp_devfn_t dev); #endif /* SUPERIO_WINBOND_W83627THG_W83627THG_H */ diff --git a/src/superio/winbond/w83697hf/early_serial.c b/src/superio/winbond/w83697hf/early_serial.c index 6c00b27..515fee9 100644 --- a/src/superio/winbond/w83697hf/early_serial.c +++ b/src/superio/winbond/w83697hf/early_serial.c @@ -22,20 +22,20 @@ #include <device/pnp_def.h> #include "w83697hf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -void w83697hf_set_clksel_48(device_t dev) +void w83697hf_set_clksel_48(pnp_devfn_t dev) { u8 reg8; @@ -47,7 +47,7 @@ void w83697hf_set_clksel_48(device_t dev) } /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase) +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83697hf/w83697hf.h b/src/superio/winbond/w83697hf/w83697hf.h index f711786..3bd1f44 100644 --- a/src/superio/winbond/w83697hf/w83697hf.h +++ b/src/superio/winbond/w83697hf/w83697hf.h @@ -34,9 +34,9 @@ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware monitor */ -void w83697hf_set_clksel_48(device_t); +void w83697hf_set_clksel_48(pnp_devfn_t); /* Depreciated, use winbond_enable_serial() */ -void w83697hf_enable_serial(device_t dev, u16 iobase); +void w83697hf_enable_serial(pnp_devfn_t dev, u16 iobase); #endif /* SUPERIO_WINBOND_W83697HF_H */ diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index c572dcb..9b5785d 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -21,20 +21,20 @@ #include <arch/io.h> #include "w83977f.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977f_enable_serial(device_t dev, u16 iobase) +static void w83977f_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83977tf/early_serial.c b/src/superio/winbond/w83977tf/early_serial.c index c016515..866d9f2 100644 --- a/src/superio/winbond/w83977tf/early_serial.c +++ b/src/superio/winbond/w83977tf/early_serial.c @@ -23,20 +23,20 @@ #include <arch/io.h> #include "w83977tf.h" -static void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0x87, port); outb(0x87, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void pnp_exit_ext_func_mode(pnp_devfn_t dev) { u16 port = dev >> 8; outb(0xaa, port); } -static void w83977tf_enable_serial(device_t dev, u16 iobase) +static void w83977tf_enable_serial(pnp_devfn_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev);

1 0

Patch set updated for coreboot: 54535fc include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs
by Edward O'Callaghan 12 Jul '14

12 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6230 -gerrit commit 54535fc11663472fc07638dbc6119cb36c0bec8e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Jul 9 18:41:12 2014 +1000 include/device/device.h: Duplicate '*_pnp_devfn_t' typedefs 'pci_devfn_t' and 'pnp_devfn_t' are already defined in arch/io.h Change-Id: I006182bf6933fae21fe6671659b76e7031e74b71 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/arch/x86/include/arch/io.h | 9 ++++++--- src/include/device/device.h | 2 -- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index b6d82f9..d5cdf35 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -4,6 +4,11 @@ #include <stdint.h> #include <rules.h> +/* FIXME: Sources for romstage still use device_t. */ +/* Use pci_devfn_t or pnp_devfn_t instead */ +typedef u32 pci_devfn_t; +typedef u32 pnp_devfn_t; + /* * This file contains the definitions for the x86 IO instructions * inb/inw/inl/outb/outw/outl and the "string versions" of the same @@ -218,11 +223,9 @@ static inline int log2f(int value) #define PNP_DEV(PORT, FUNC) (((PORT) << 8) | (FUNC)) /* FIXME: Sources for romstage still use device_t. */ +/* Use pci_devfn_t or pnp_devfn_t instead */ typedef u32 device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; - /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access diff --git a/src/include/device/device.h b/src/include/device/device.h index ec17adf..132e4ef 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -18,8 +18,6 @@ struct device; #ifndef __SIMPLE_DEVICE__ typedef struct device * device_t; -typedef u32 pci_devfn_t; -typedef u32 pnp_devfn_t; struct pci_operations; struct pci_bus_operations; struct smbus_bus_operations;

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Patch set updated for coreboot: b300623 intel/i945: Add PCI ID of IGD on Intel 945G/945GZ/945GC
by HAOUAS Elyes 12 Jul '14

12 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6192 -gerrit commit b3006237e9fd5353f8858a28ec9b246751fc2f73 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Jul 11 21:29:28 2014 +0200 intel/i945: Add PCI ID of IGD on Intel 945G/945GZ/945GC Change-Id: I263eeba8fcfdfe9253449913bb46956c796ac825 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/Kconfig | 3 ++- src/northbridge/intel/i945/gma.c | 12 ++++++++++++ 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..99ea1fd 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -41,7 +41,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config VGA_BIOS_ID string - default "8086,27a2" + default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM + default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index c04483e..061770a 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -142,13 +142,25 @@ static struct device_operations gma_func1_ops = { }; static const struct pci_driver i945_gma_func0_driver __pci_driver = { +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x27a2, +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2772, +#endif }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x27a6, +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + .ops = &gma_func1_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2776, +#endif };

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Patch set updated for coreboot: 39dc186 Add IGD "8086, 2772" string for 945G/945GZ/945GC
by HAOUAS Elyes 11 Jul '14

11 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6192 -gerrit commit 39dc186314b3d3cef1595e062a9d7c3046f2bad8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Fri Jul 11 21:29:28 2014 +0200 Add IGD "8086,2772" string for 945G/945GZ/945GC Change-Id: I263eeba8fcfdfe9253449913bb46956c796ac825 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/Kconfig | 3 ++- src/northbridge/intel/i945/gma.c | 13 +++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 360b2ab..99ea1fd 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -41,7 +41,8 @@ config BOOTBLOCK_NORTHBRIDGE_INIT config VGA_BIOS_ID string - default "8086,27a2" + default "8086,27a2" if NORTHBRIDGE_INTEL_SUBTYPE_I945GM + default "8086,2772" if NORTHBRIDGE_INTEL_SUBTYPE_I945GC config CHANNEL_XOR_RANDOMIZATION bool diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index c04483e..2803aec 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -142,13 +142,26 @@ static struct device_operations gma_func1_ops = { }; static const struct pci_driver i945_gma_func0_driver __pci_driver = { +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM .ops = &gma_func0_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x27a2, +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + .ops = &gma_func0_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2772, +#endif + }; static const struct pci_driver i945_gma_func1_driver __pci_driver = { +#if CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM .ops = &gma_func1_ops, .vendor = PCI_VENDOR_ID_INTEL, .device = 0x27a6, +#elif CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC + .ops = &gma_func1_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = 0x2776, +#endif };

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Patch set updated for coreboot: 8ebf567 mainboard/asrock/e350m1: Fix style in PlatformGnbPcie bits
by Edward O'Callaghan 11 Jul '14

11 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5613 -gerrit commit 8ebf5672c1a70aea116fc30711644dade012968c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 20:13:22 2014 +1000 mainboard/asrock/e350m1: Fix style in PlatformGnbPcie bits Cleanup style in PlatformGnbPcie bits to reflect similar changes found in: e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA feebd86 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics This mainly sanitises header includes, fixes up indentation and various comment styles. Change-Id: I801053e7ff5da2885aa282f84143c0399d766e26 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 248 ++++++++++++--------- .../asrock/e350m1/PlatformGnbPcieComplex.h | 98 ++++---- 2 files changed, 200 insertions(+), 146 deletions(-) diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index eefd27f..3d28e8e 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,136 +18,177 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" +#include "BiosCallOuts.h" + +#include <string.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <string.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE -/*---------------------------------------------------------------------------------------*/ /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly * **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + void *BrazosPcieComplexListPtr; + void *BrazosPciePortPtr; + void *BrazosPcieDdiPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams; +/** + * @brief Initialize Port descriptors + */ PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) - }, - #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) - }, - #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) + }, + /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ + { + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) + } }; +/** + * @brief Initialize Ddi descriptors + */ PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} - } + /* (DDI interface Lanes 8:11, DdA, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ + {ConnectorTypeLvds, Aux1, Hdp1} + }, + /* (DDI interface Lanes 12:15, DdB, ...) */ + { + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ + {ConnectorTypeDP, Aux2, Hdp2} + } }; PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] }; - // GNB PCIe topology Porting - - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); - - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; - } - - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + /** + * @brief GNB PCIe topology Porting + * + * Allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + AllocHeapParams.RequestedBufferSize = + sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + + /** + * Could not allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + if (Status!= AGESA_SUCCESS) { + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..dd6f7d7 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,53 +21,64 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/** + * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) + * + * GNB_GPP_PORT?_PORT_PRESENT + * 0:Disable 1:Enable + * + * GNB_GPP_PORT?_SPEED_MODE + * 0:Auto 1:GEN1 2:GEN2 + * + * GNB_GPP_PORT?_LINK_ASPM + * 0:Disable 1:L0s 2:L1 3:L0s+L1 + * + * GNB_GPP_PORT?_CHANNEL_TYPE - + * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) + * + * GNB_GPP_PORT?_HOTPLUG_SUPPORT + * 0:Disable 1:Basic 3:Enhanced + */ + +/* GNB GPP 4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */

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Patch set updated for coreboot: 2ec22b6 mainboard/asrock/e350m1: Use std memset/memcpy func over AGESA
by Edward O'Callaghan 11 Jul '14

11 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5613 -gerrit commit 2ec22b6e60c957a013f198891fed478ff600e7ab Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Apr 29 20:13:22 2014 +1000 mainboard/asrock/e350m1: Use std memset/memcpy func over AGESA Following the combined reasoning in: e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA feebd86 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics Change-Id: I801053e7ff5da2885aa282f84143c0399d766e26 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 248 ++++++++++++--------- .../asrock/e350m1/PlatformGnbPcieComplex.h | 98 ++++---- 2 files changed, 200 insertions(+), 146 deletions(-) diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index eefd27f..3d28e8e 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -17,136 +18,177 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "AGESA.h" -#include "amdlib.h" -#include "Ids.h" -#include "heapManager.h" #include "PlatformGnbPcieComplex.h" -#include "Filecode.h" +#include "BiosCallOuts.h" + +#include <string.h> +#include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #include <string.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE -/*---------------------------------------------------------------------------------------*/ /** - * OemCustomizeInitEarly + * OemCustomizeInitEarly * - * Description: - * This stub function will call the host environment through the binary block - * interface (call-out port) to provide a user hook opportunity + * Description: + * This stub function will call the host environment through the binary block + * interface (call-out port) to provide a user hook opportunity * - * Parameters: - * @param[in] **PeiServices - * @param[in] *InitEarly - * - * @retval VOID + * Parameters: + * @param[in] **PeiServices + * @param[in] *InitEarly * **/ -/*---------------------------------------------------------------------------------------*/ -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ) +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly) { - AGESA_STATUS Status; - VOID *BrazosPcieComplexListPtr; - VOID *BrazosPciePortPtr; - VOID *BrazosPcieDdiPtr; + AGESA_STATUS Status; + void *BrazosPcieComplexListPtr; + void *BrazosPciePortPtr; + void *BrazosPcieDdiPtr; - ALLOCATE_HEAP_PARAMS AllocHeapParams; + ALLOCATE_HEAP_PARAMS AllocHeapParams; +/** + * @brief Initialize Port descriptors + */ PCIe_PORT_DESCRIPTOR PortList [] = { - // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 0) - }, - #if 1 - // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) - { - 0, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 0) - }, - // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) - { - 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) - }, - #endif - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) - } + /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 4), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT4_PORT_PRESENT, + GNB_GPP_PORT4_CHANNEL_TYPE, + 4, + GNB_GPP_PORT4_HOTPLUG_SUPPORT, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_SPEED_MODE, + GNB_GPP_PORT4_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 5, 5), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT5_PORT_PRESENT, + GNB_GPP_PORT5_CHANNEL_TYPE, + 5, + GNB_GPP_PORT5_HOTPLUG_SUPPORT, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_SPEED_MODE, + GNB_GPP_PORT5_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 6, 6), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT6_PORT_PRESENT, + GNB_GPP_PORT6_CHANNEL_TYPE, + 6, + GNB_GPP_PORT6_HOTPLUG_SUPPORT, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_SPEED_MODE, + GNB_GPP_PORT6_LINK_ASPM, + 46) + }, + /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT7_PORT_PRESENT, + GNB_GPP_PORT7_CHANNEL_TYPE, + 7, + GNB_GPP_PORT7_HOTPLUG_SUPPORT, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_SPEED_MODE, + GNB_GPP_PORT7_LINK_ASPM, + 0) + }, + /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ + { + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER (GNB_GPP_PORT8_PORT_PRESENT, + GNB_GPP_PORT8_CHANNEL_TYPE, + 8, + GNB_GPP_PORT8_HOTPLUG_SUPPORT, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_SPEED_MODE, + GNB_GPP_PORT8_LINK_ASPM, + 0) + } }; +/** + * @brief Initialize Ddi descriptors + */ PCIe_DDI_DESCRIPTOR DdiList [] = { - // Initialize Ddi descriptor (DDI interface Lanes 8:11, DdA, ...) - { - 0, //Descriptor flags - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) - {ConnectorTypeDP, Aux1, Hdp1} - }, - // Initialize Ddi descriptor (DDI interface Lanes 12:15, DdB, ...) - { - DESCRIPTOR_TERMINATE_LIST, //Descriptor flags !!!IMPORTANT!!! Terminate last element of array - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), - //PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) - {ConnectorTypeDP, Aux2, Hdp2} - } + /* (DDI interface Lanes 8:11, DdA, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11), + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1) */ + {ConnectorTypeLvds, Aux1, Hdp1} + }, + /* (DDI interface Lanes 12:15, DdB, ...) */ + { + /* Descriptor flags. IMPORTANT! Terminate last element of array */ + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15), + /* PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux2, Hdp2) */ + {ConnectorTypeDP, Aux2, Hdp2} + } }; PCIe_COMPLEX_DESCRIPTOR Brazos = { - DESCRIPTOR_TERMINATE_LIST, - 0, - &PortList[0], - &DdiList[0] + DESCRIPTOR_TERMINATE_LIST, + 0, + &PortList[0], + &DdiList[0] }; - // GNB PCIe topology Porting - - // - // Allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - // - AllocHeapParams.RequestedBufferSize = sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); - - AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; - AllocHeapParams.Persist = HEAP_LOCAL_CACHE; - Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); - if ( Status!= AGESA_SUCCESS) { - // Could not allocate buffer for PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR - ASSERT(FALSE); - return; - } - - BrazosPcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(Brazos); - BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *)AllocHeapParams.BufferPtr; - - AllocHeapParams.BufferPtr += sizeof(PortList); - BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; + /** + * @brief GNB PCIe topology Porting + * + * Allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR, PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + AllocHeapParams.RequestedBufferSize = + sizeof(Brazos) + sizeof(PortList) + sizeof(DdiList); + + AllocHeapParams.BufferHandle = AMD_MEM_MISC_HANDLES_START; + AllocHeapParams.Persist = HEAP_LOCAL_CACHE; + Status = HeapAllocateBuffer (&AllocHeapParams, &InitEarly->StdHeader); + + /** + * Could not allocate buffer for + * PCIe_COMPLEX_DESCRIPTOR , PCIe_PORT_DESCRIPTOR and PCIe_DDI_DESCRIPTOR + */ + if (Status!= AGESA_SUCCESS) { + ASSERT(FALSE); + return; + } + + BrazosPcieComplexListPtr = + (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(Brazos); + BrazosPciePortPtr = (PCIe_PORT_DESCRIPTOR *) AllocHeapParams.BufferPtr; + + AllocHeapParams.BufferPtr += sizeof(PortList); + BrazosPcieDdiPtr = (PCIe_DDI_DESCRIPTOR *) AllocHeapParams.BufferPtr; memcpy(BrazosPcieComplexListPtr, &Brazos, sizeof(Brazos)); memcpy(BrazosPciePortPtr, &PortList[0], sizeof(PortList)); memcpy(BrazosPcieDdiPtr, &DdiList[0], sizeof(DdiList)); + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->PciePortList = + (PCIe_PORT_DESCRIPTOR *) BrazosPciePortPtr; + ((PCIe_COMPLEX_DESCRIPTOR *) BrazosPcieComplexListPtr)->DdiLinkList = + (PCIe_DDI_DESCRIPTOR *) BrazosPcieDdiPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->PciePortList = (PCIe_PORT_DESCRIPTOR*)BrazosPciePortPtr; - ((PCIe_COMPLEX_DESCRIPTOR*)BrazosPcieComplexListPtr)->DdiLinkList = (PCIe_DDI_DESCRIPTOR*)BrazosPcieDdiPtr; - - InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; - InitEarly->GnbConfig.PsppPolicy = 0; + InitEarly->GnbConfig.PcieComplexList = BrazosPcieComplexListPtr; + InitEarly->GnbConfig.PsppPolicy = 0; } diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..dd6f7d7 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,53 +21,64 @@ #ifndef _PLATFORM_GNB_PCIE_COMPLEX_H #define _PLATFORM_GNB_PCIE_COMPLEX_H -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" +#include <vendorcode/amd/agesa/f14/AGESA.h> +#include <vendorcode/amd/agesa/f14/Lib/amdlib.h> -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/** + * @brief Graphic NorthBridge (GNB) General Purpose Port (GPP) + * + * GNB_GPP_PORT?_PORT_PRESENT + * 0:Disable 1:Enable + * + * GNB_GPP_PORT?_SPEED_MODE + * 0:Auto 1:GEN1 2:GEN2 + * + * GNB_GPP_PORT?_LINK_ASPM + * 0:Disable 1:L0s 2:L1 3:L0s+L1 + * + * GNB_GPP_PORT?_CHANNEL_TYPE - + * 0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) + * 3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) + * + * GNB_GPP_PORT?_HOTPLUG_SUPPORT + * 0:Disable 1:Basic 3:Enhanced + */ + +/* GNB GPP 4 */ +#define GNB_GPP_PORT4_PORT_PRESENT 1 +#define GNB_GPP_PORT4_SPEED_MODE 2 +#define GNB_GPP_PORT4_LINK_ASPM 3 +#define GNB_GPP_PORT4_CHANNEL_TYPE 4 +#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 5 */ +#define GNB_GPP_PORT5_PORT_PRESENT 1 +#define GNB_GPP_PORT5_SPEED_MODE 2 +#define GNB_GPP_PORT5_LINK_ASPM 3 +#define GNB_GPP_PORT5_CHANNEL_TYPE 4 +#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 6 */ +#define GNB_GPP_PORT6_PORT_PRESENT 1 +#define GNB_GPP_PORT6_SPEED_MODE 2 +#define GNB_GPP_PORT6_LINK_ASPM 3 +#define GNB_GPP_PORT6_CHANNEL_TYPE 4 +#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 7 */ +#define GNB_GPP_PORT7_PORT_PRESENT 0 +#define GNB_GPP_PORT7_SPEED_MODE 2 +#define GNB_GPP_PORT7_LINK_ASPM 3 +#define GNB_GPP_PORT7_CHANNEL_TYPE 4 +#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced +/* GNB GPP 8 */ +#define GNB_GPP_PORT8_PORT_PRESENT 1 +#define GNB_GPP_PORT8_SPEED_MODE 2 +#define GNB_GPP_PORT8_LINK_ASPM 3 +#define GNB_GPP_PORT8_CHANNEL_TYPE 4 +#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); +void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H +#endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */

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Patch merged into coreboot/master: d13059a asus/f2a85-m: Switch off automatic fan control for fan2
by gerrit＠coreboot.org 11 Jul '14

11 Jul '14

the following patch was just integrated into master: commit d13059a5a2acfbd2e55484b5c6a161286d4e956c Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon Jul 7 22:40:12 2014 +0200 asus/f2a85-m: Switch off automatic fan control for fan2 The fan2 (chasis fan) was set to automatic mode, but the registers for smart guardian have still default value which will stop it. Run it in manual mode for now. Change-Id: Ic2c2414ac88abba77a9e7a129788f9777e7e5ad5 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/6217 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6217 for details. -gerrit

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Patch set updated for coreboot: 9f49674 build system: remove duplicate architecture list
by Patrick Georgi 11 Jul '14

11 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6254 -gerrit commit 9f496744c1411f87a56491c43ef08d74a6a16437 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 20:38:21 2014 +0200 build system: remove duplicate architecture list Let xcompile pass the list of architectures, given that it already has it. This potentially requires removing $(src)/.xcompile so it gets updated. Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- toolchain.inc | 2 -- util/xcompile/xcompile | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index b5b4fe0..842473b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -17,8 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ARCH_SUPPORTED := armv7 x86_32 - # ccache integration ifeq ($(CONFIG_CCACHE),y) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index d133bd2..b42da7b 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -147,6 +147,7 @@ detect_special_flags() { report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) +ARCH_SUPPORTED+=${TARCH} CC_${TARCH}:=${GCCPREFIX}gcc CFLAGS_${TARCH}:=${CFLAGS} CPP_${TARCH}:=${GCCPREFIX}cpp

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Patch set updated for coreboot: 1d4bf09 build system: create .xcompile dependency
by Patrick Georgi 11 Jul '14

11 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6255 -gerrit commit 1d4bf098d85a3a27c464610d3639d5d777406e52 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 21:06:04 2014 +0200 build system: create .xcompile dependency It's probably safe to say that .xcompile needs an update if util/xcompile/xcompile changed, so tell make about this dependency. Updates are honored immediately due to GNU make's feature of reinterpreting everything when an included file changes. See "How Makefiles Are Remade" in the GNU make documentation for details. Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 4 +++- util/xcompile/xcompile | 0 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c8cad4f..2ee6a96 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,9 @@ ## SUCH DAMAGE. ## -$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile $(XGCCPATH) > .xcompile))) +.xcompile: util/xcompile/xcompile + -A=`mktemp $@.XXXXXX`; $< $(XGCCPATH) > $$A && cmp $$A $@ > /dev/null 2> /dev/null || mv $$A $@ 2> /dev/null ; rm -f $$A + include .xcompile export top := $(CURDIR) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile old mode 100644 new mode 100755

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coreboot-gerrit July 2014