coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ac98d19 superio/ite/it8772f/Makefile.inc: Build romstage symbols
by Matt DeVillier 14 Jul '14

14 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6271 -gerrit commit ac98d1918aa1ced895e61efa5a9574f40b5959d7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 14 16:31:25 2014 +1000 superio/ite/it8772f/Makefile.inc: Build romstage symbols Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/panther/romstage.c | 1 - src/superio/ite/it8772f/Makefile.inc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968..df7d174 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -30,7 +30,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/it8772f/early_serial.c" #include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index 7b6be2c..b654102 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c

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Patch set updated for coreboot: 9b21f6c google/panther: general cleanup, file organization (non-functional)
by Matt DeVillier 14 Jul '14

14 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6270 -gerrit commit 9b21f6cf8a3788cf26d07c48d26c3e47e5347559 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sun Jul 13 18:51:28 2014 -0500 google/panther: general cleanup, file organization (non-functional) acpi_tables.c: consolidate/organize headers chromeos.c: consolidate/organize headers; move header, #defines outside of #ifdef fadt.c: organize headers gpio.h: rename include guard; add comment to trailing #endif had_verb.h: add include guard; replace manual array size calculation with std header macro lan.c: remove conditional header inclusion; organize headers; remove pre-processor directive indentations mainboard.c: remove conditional header inclusion; organize headers; replace spaced indentations with tab(s); add comment to trailing #endif onboard.h: move fn prototype after #defines; add comment to trailing #endif romstage.c: consolidate/organize headers smihandler.c: organize headers; remove commented-out/dead code; add comment to trailing #endif thermal.h: add comment to trailing #endif Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/panther/acpi_tables.c | 21 ++++--- src/mainboard/google/panther/chromeos.c | 7 +-- src/mainboard/google/panther/fadt.c | 2 +- src/mainboard/google/panther/gpio.h | 6 +- src/mainboard/google/panther/hda_verb.h | 9 ++- src/mainboard/google/panther/lan.c | 13 ++--- src/mainboard/google/panther/mainboard.c | 30 +++++----- src/mainboard/google/panther/onboard.h | 8 +-- src/mainboard/google/panther/romstage.c | 8 +-- src/mainboard/google/panther/smihandler.c | 91 ++---------------------------- src/mainboard/google/panther/thermal.h | 2 +- 11 files changed, 57 insertions(+), 140 deletions(-) diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c index de67c22..1a9e1e6 100644 --- a/src/mainboard/google/panther/acpi_tables.c +++ b/src/mainboard/google/panther/acpi_tables.c @@ -17,31 +17,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> #include <cbmem.h> -#include <console/console.h> +#include <string.h> +#include <types.h> #include <arch/acpi.h> -#include <arch/ioapic.h> #include <arch/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <ec/google/chromeec/ec.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include "thermal.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include "thermal.h" - static void acpi_update_thermal_table(global_nvs_t *gnvs) { gnvs->f4of = FAN4_THRESHOLD_OFF; diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 074f648..62165da 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -18,11 +18,12 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 58 #define GPIO_REC_MODE 12 @@ -31,13 +32,11 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - #define GPIO_COUNT 6 #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 +#ifndef __PRE_RAM__ static void fill_lb_gpio(struct lb_gpio *gpio, int num, int polarity, const char *name, int force) { diff --git a/src/mainboard/google/panther/fadt.c b/src/mainboard/google/panther/fadt.c index 7afbbfa..7289712 100644 --- a/src/mainboard/google/panther/fadt.c +++ b/src/mainboard/google/panther/fadt.c @@ -18,9 +18,9 @@ */ #include <string.h> -#include <device/pci.h> #include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h index 9951984..a83b47b 100644 --- a/src/mainboard/google/panther/gpio.h +++ b/src/mainboard/google/panther/gpio.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H +#ifndef PANTHER_GPIO_H +#define PANTHER_GPIO_H struct pch_lp_gpio_map; @@ -121,4 +121,4 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_END }; -#endif +#endif /* PANTHER_GPIO_H */ diff --git a/src/mainboard/google/panther/hda_verb.h b/src/mainboard/google/panther/hda_verb.h index cec56eb..456561b 100644 --- a/src/mainboard/google/panther/hda_verb.h +++ b/src/mainboard/google/panther/hda_verb.h @@ -17,6 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <stdlib.h> + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -109,4 +114,6 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = - sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); + ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* HDA_VERB_H */ diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 9e941d5..2d7eed0 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -17,18 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> +#include <cbfs.h> #include <string.h> +#include <types.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#else -#include <cbfs.h> -#endif #include "onboard.h" static unsigned int search(char *p, char *a, unsigned int lengthp, @@ -142,11 +139,11 @@ void lan_init(void) u16 io_base = 0; struct device *ethernet_dev = NULL; - #if CONFIG_CHROMEOS +#if CONFIG_CHROMEOS char **vpd_region_ptr = NULL; search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); search_address = (unsigned long)(*vpd_region_ptr); - #else +#else void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin", CBFS_TYPE_RAW, &search_length); if (vpd_file) { @@ -155,7 +152,7 @@ void lan_init(void) search_length = -1; search_address = 0; } - #endif +#endif /* Get NIC's IO base address */ ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID, diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index afa6526..0c59ded 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -18,25 +18,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> #include <smbios.h> +#include <string.h> +#include <types.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> #include <device/device.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif #include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <x86emu/x86emu.h> #include "hda_verb.h" #include "onboard.h" -#include <southbridge/intel/lynxpoint/pch.h> + void mainboard_suspend_resume(void) { @@ -50,7 +49,7 @@ static int int15_handler(void) int res = 0; printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX); switch (X86_AX) { case 0x5f34: @@ -116,19 +115,19 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } -#endif +#endif /* CONFIG_VGA_ROM_RUN */ /* Audio Setup */ @@ -167,4 +166,3 @@ static void mainboard_enable(device_t dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h index 0b67017..4d05dc7 100644 --- a/src/mainboard/google/panther/onboard.h +++ b/src/mainboard/google/panther/onboard.h @@ -1,10 +1,6 @@ #ifndef __MAINBOARD_ONBOARD_H #define __MAINBOARD_ONBOARD_H -#ifndef __ACPI__ -void lan_init(void); -#endif - /* defines for programming the MAC address */ #define PANTHER_NIC_VENDOR_ID 0x10EC #define PANTHER_NIC_DEVICE_ID 0x8168 @@ -18,4 +14,8 @@ void lan_init(void); /* WLAN wake is GPIO 10 */ #define PANTHER_WLAN_WAKE_GPIO 10 +#ifndef __ACPI__ +void lan_init(void); #endif + +#endif /* __MAINBOARD_ONBOARD_H */ diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index df7d174..90c397e 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -18,19 +18,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbfs.h> #include <stdint.h> #include <stdlib.h> #include <string.h> -#include <cbfs.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> #include "gpio.h" -#include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) diff --git a/src/mainboard/google/panther/smihandler.c b/src/mainboard/google/panther/smihandler.c index 2ad2498..3448648 100644 --- a/src/mainboard/google/panther/smihandler.c +++ b/src/mainboard/google/panther/smihandler.c @@ -20,12 +20,12 @@ #include <arch/io.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <cpu/x86/smm.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/me.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> #include <elog.h> /* GPIO46 controls the WLAN_DISABLE_L signal. */ @@ -49,82 +49,9 @@ int mainboard_io_trap_handler(int smif) * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //gnvs->smif = 0; return 1; } -#if 0 -static u8 mainboard_smi_ec(void) -{ - u8 cmd = 0;// google_chromeec_get_event(); - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - return cmd; -} -#endif - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -#if 0 - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -#endif -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - //if (smm_get_gnvs()->s3u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s3u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S3. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case 5: - //if (smm_get_gnvs()->s5u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s5u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S5. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - //google_chromeec_set_smi_mask(0); - //google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - //while (google_chromeec_get_event() != 0); -} - #define APMC_FINALIZE 0xcb static int mainboard_finalized = 0; @@ -144,17 +71,7 @@ int mainboard_smi_apmc(u8 apmc) mainboard_finalized = 1; break; - case APM_CNT_ACPI_ENABLE: - //google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - //google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + default: break; } return 0; diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h index 7a96561..1ed7ce7 100644 --- a/src/mainboard/google/panther/thermal.h +++ b/src/mainboard/google/panther/thermal.h @@ -54,4 +54,4 @@ /* Tj_max value for calculating PECI CPU temperature */ #define MAX_TEMPERATURE 100 -#endif +#endif /* THERMAL_H */

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Patch set updated for coreboot: 9825f0e superio/ite/it8772f/Makefile.inc: Build romstage symbols
by Edward O'Callaghan 14 Jul '14

14 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6271 -gerrit commit 9825f0efa5cc4a2ebd22b22988af23fe4ed13c01 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 14 16:31:25 2014 +1000 superio/ite/it8772f/Makefile.inc: Build romstage symbols Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/panther/romstage.c | 1 - src/superio/ite/it8772f/Makefile.inc | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968..df7d174 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -30,7 +30,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/it8772f/early_serial.c" #include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index 7b6be2c..b654102 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c

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New patch to review for coreboot: a2d07d2 superio/ite/it8772f/Makefile.inc: Build romstage symbols
by Edward O'Callaghan 14 Jul '14

14 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6271 -gerrit commit a2d07d2b70c94f5588d6ea7443a5e38330089a68 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 14 16:31:25 2014 +1000 superio/ite/it8772f/Makefile.inc: Build romstage symbols Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8772f/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index 7b6be2c..b654102 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c

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New patch to review for coreboot: e417f10 google/panther: general cleanup, file organization (non-functional)
by Matt DeVillier 13 Jul '14

13 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6270 -gerrit commit e417f101656f3131a64fd2d4cad49614b89a247d Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sun Jul 13 18:51:28 2014 -0500 google/panther: general cleanup, file organization (non-functional) acpi_tables.c: consolidate/organize headers chromeos.c: consolidate/organize headers; move header, #defines outside of #ifdef fadt.c: organize headers gpio.h: rename include guard; add comment to trailing #endif had_verb.h: add include guard; replace manual array size calculation with std header macro lan.c: remove conditional header inclusion; organize headers; remove pre-processor directive indentations mainboard.c: remove conditional header inclusion; organize headers; replace spaced indentations with tab(s); add comment to trailing #endif onboard.h: move fn prototype after #defines; add comment to trailing #endif romstage.c: consolidate/organize headers smihandler.c: organize headers; remove commented-out/dead code; add comment to trailing #endif thermal.h: add comment to trailing #endif Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/panther/acpi_tables.c | 21 ++++--- src/mainboard/google/panther/chromeos.c | 7 +-- src/mainboard/google/panther/fadt.c | 2 +- src/mainboard/google/panther/gpio.h | 6 +- src/mainboard/google/panther/hda_verb.h | 9 ++- src/mainboard/google/panther/lan.c | 13 ++--- src/mainboard/google/panther/mainboard.c | 30 +++++----- src/mainboard/google/panther/onboard.h | 8 +-- src/mainboard/google/panther/romstage.c | 10 ++-- src/mainboard/google/panther/smihandler.c | 91 ++---------------------------- src/mainboard/google/panther/thermal.h | 2 +- 11 files changed, 58 insertions(+), 141 deletions(-) diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c index de67c22..1a9e1e6 100644 --- a/src/mainboard/google/panther/acpi_tables.c +++ b/src/mainboard/google/panther/acpi_tables.c @@ -17,31 +17,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> #include <cbmem.h> -#include <console/console.h> +#include <string.h> +#include <types.h> #include <arch/acpi.h> -#include <arch/ioapic.h> #include <arch/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <ec/google/chromeec/ec.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include "thermal.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include "thermal.h" - static void acpi_update_thermal_table(global_nvs_t *gnvs) { gnvs->f4of = FAN4_THRESHOLD_OFF; diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 074f648..62165da 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -18,11 +18,12 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 58 #define GPIO_REC_MODE 12 @@ -31,13 +32,11 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - #define GPIO_COUNT 6 #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 +#ifndef __PRE_RAM__ static void fill_lb_gpio(struct lb_gpio *gpio, int num, int polarity, const char *name, int force) { diff --git a/src/mainboard/google/panther/fadt.c b/src/mainboard/google/panther/fadt.c index 7afbbfa..7289712 100644 --- a/src/mainboard/google/panther/fadt.c +++ b/src/mainboard/google/panther/fadt.c @@ -18,9 +18,9 @@ */ #include <string.h> -#include <device/pci.h> #include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h index 9951984..a83b47b 100644 --- a/src/mainboard/google/panther/gpio.h +++ b/src/mainboard/google/panther/gpio.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H +#ifndef PANTHER_GPIO_H +#define PANTHER_GPIO_H struct pch_lp_gpio_map; @@ -121,4 +121,4 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_END }; -#endif +#endif /* PANTHER_GPIO_H */ diff --git a/src/mainboard/google/panther/hda_verb.h b/src/mainboard/google/panther/hda_verb.h index cec56eb..456561b 100644 --- a/src/mainboard/google/panther/hda_verb.h +++ b/src/mainboard/google/panther/hda_verb.h @@ -17,6 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <stdlib.h> + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -109,4 +114,6 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = - sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); + ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* HDA_VERB_H */ diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 9e941d5..2d7eed0 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -17,18 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> +#include <cbfs.h> #include <string.h> +#include <types.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#else -#include <cbfs.h> -#endif #include "onboard.h" static unsigned int search(char *p, char *a, unsigned int lengthp, @@ -142,11 +139,11 @@ void lan_init(void) u16 io_base = 0; struct device *ethernet_dev = NULL; - #if CONFIG_CHROMEOS +#if CONFIG_CHROMEOS char **vpd_region_ptr = NULL; search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); search_address = (unsigned long)(*vpd_region_ptr); - #else +#else void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin", CBFS_TYPE_RAW, &search_length); if (vpd_file) { @@ -155,7 +152,7 @@ void lan_init(void) search_length = -1; search_address = 0; } - #endif +#endif /* Get NIC's IO base address */ ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID, diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index afa6526..0c59ded 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -18,25 +18,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> #include <smbios.h> +#include <string.h> +#include <types.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> #include <device/device.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif #include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <x86emu/x86emu.h> #include "hda_verb.h" #include "onboard.h" -#include <southbridge/intel/lynxpoint/pch.h> + void mainboard_suspend_resume(void) { @@ -50,7 +49,7 @@ static int int15_handler(void) int res = 0; printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX); switch (X86_AX) { case 0x5f34: @@ -116,19 +115,19 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } -#endif +#endif /* CONFIG_VGA_ROM_RUN */ /* Audio Setup */ @@ -167,4 +166,3 @@ static void mainboard_enable(device_t dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h index 0b67017..4d05dc7 100644 --- a/src/mainboard/google/panther/onboard.h +++ b/src/mainboard/google/panther/onboard.h @@ -1,10 +1,6 @@ #ifndef __MAINBOARD_ONBOARD_H #define __MAINBOARD_ONBOARD_H -#ifndef __ACPI__ -void lan_init(void); -#endif - /* defines for programming the MAC address */ #define PANTHER_NIC_VENDOR_ID 0x10EC #define PANTHER_NIC_DEVICE_ID 0x8168 @@ -18,4 +14,8 @@ void lan_init(void); /* WLAN wake is GPIO 10 */ #define PANTHER_WLAN_WAKE_GPIO 10 +#ifndef __ACPI__ +void lan_init(void); #endif + +#endif /* __MAINBOARD_ONBOARD_H */ diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968..1c89170 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -18,20 +18,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbfs.h> #include <stdint.h> #include <stdlib.h> #include <string.h> -#include <cbfs.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include "gpio.h" -#include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/it8772f/early_serial.c" +#include <southbridge/intel/lynxpoint/pch.h> #include "superio/ite/common/ite.h" +#include "superio/ite/it8772f/early_serial.c" +#include "superio/ite/it8772f/it8772f.h" +#include "gpio.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) diff --git a/src/mainboard/google/panther/smihandler.c b/src/mainboard/google/panther/smihandler.c index 2ad2498..3448648 100644 --- a/src/mainboard/google/panther/smihandler.c +++ b/src/mainboard/google/panther/smihandler.c @@ -20,12 +20,12 @@ #include <arch/io.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <cpu/x86/smm.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/me.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> #include <elog.h> /* GPIO46 controls the WLAN_DISABLE_L signal. */ @@ -49,82 +49,9 @@ int mainboard_io_trap_handler(int smif) * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //gnvs->smif = 0; return 1; } -#if 0 -static u8 mainboard_smi_ec(void) -{ - u8 cmd = 0;// google_chromeec_get_event(); - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - return cmd; -} -#endif - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -#if 0 - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -#endif -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - //if (smm_get_gnvs()->s3u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s3u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S3. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case 5: - //if (smm_get_gnvs()->s5u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s5u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S5. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - //google_chromeec_set_smi_mask(0); - //google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - //while (google_chromeec_get_event() != 0); -} - #define APMC_FINALIZE 0xcb static int mainboard_finalized = 0; @@ -144,17 +71,7 @@ int mainboard_smi_apmc(u8 apmc) mainboard_finalized = 1; break; - case APM_CNT_ACPI_ENABLE: - //google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - //google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + default: break; } return 0; diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h index 7a96561..1ed7ce7 100644 --- a/src/mainboard/google/panther/thermal.h +++ b/src/mainboard/google/panther/thermal.h @@ -54,4 +54,4 @@ /* Tj_max value for calculating PECI CPU temperature */ #define MAX_TEMPERATURE 100 -#endif +#endif /* THERMAL_H */

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Patch set updated for coreboot: c7e0367 intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH`
by Matt DeVillier 13 Jul '14

13 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6269 -gerrit commit c7e0367dc8674a9a38a544759b2460cb1e2d7f7e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jul 12 22:11:24 2014 +0200 intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH` Currently `IFD_BIN_PATH` is shown twice. Commit 5218e616 (intel/lynxpoint: Allow building without IFD (descripter.bin)) [1] accidentally added the option another time. So fix up the commit and remove one of the two options `IFD_BIN_PATH`. Keep the one which depends on `!HAVE_IFD_BIN` and is around the IFD options. [1] http://review.coreboot.org/6046 Change-Id: Id46f01ab8ee2e752e337e687a2ef0dfa374f44a5 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 0ba61bc..0f52011 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -116,10 +116,6 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" - config ME_MBP_CLEAR_LATE bool "Defer wait for ME MBP Cleared" default y

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Patch set updated for coreboot: e934c86 asrock/e350m1/mainboard.c: Power unused GPP PCIe clock pins off
by Paul Menzel 13 Jul '14

13 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5397 -gerrit commit e934c86a1162f9f04196760820a4ecc1c9ef7655 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 22 23:22:29 2014 +0100 asrock/e350m1/mainboard.c: Power unused GPP PCIe clock pins off According to the SB800 Register Reference Guide [1] the clock pins are powered on (0xFF) by default. On the ASRock E350M1 not all GPP PCIe devices are used, so power their clock pins off as there is no point in leaving them enabled and, according to Felix Held, it saves around 150 to 200 mW of power. The same was done for the board AMD Persimmon in commit 73be43a1 [2]. Persimmon: Disable the unused GPP PCIe clocks Note that the board AMD Persimmon has a normal PCI slot, where the ASRock E350M1 has a PCIe 2.0 x16 slot (electrical x4), for example usable for an external graphics cards. Felix Held measured directly on the board (ASRock E350M1/USB3) that only the clock pins GPP0 PCIE, GPP1 PCIE, GPP2 PCIE and Gfx PCIE are connected to the PCB. GPP_CLK1 clock pins are connected to the Ethernet chip, the GPP_CLK2 clock pins are connected to the USB 3.0 controller and the SLT_GFX_CLK clock pins are connected to the PCIe x16 (electrical x4) slot. GPP_CLK0 clock pins are connected to the unpopulated Mini PCIe slot. It is left enabled in case TODO: Add a configuration option to disable GPP_CLK2 clock pins on the ASRock E350M1, which does not have an USB 3.0 controller. The same for GPP_CLK0 pins as most users will solder on a Mini PCIe slot. Edward O’Callaghan first suggested to look into this to solve the problem of the disappearing Ethernet device. It did not fix the problem (the Super I/O support is incomplete), but thanks to Felix Held it turned out to be useful anyway. [1] AMD SB800-Series Southbridges Register Reference Guide Publication: #45482 Revision: 3.04 [2] http://review.coreboot.org/1876 Change-Id: Ibd839bb469f06cbbb8a50d6a0bc58ad967a1a5e1 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mainboard.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/asrock/e350m1/mainboard.c b/src/mainboard/asrock/e350m1/mainboard.c index a98a179..38bf457 100644 --- a/src/mainboard/asrock/e350m1/mainboard.c +++ b/src/mainboard/asrock/e350m1/mainboard.c @@ -25,6 +25,8 @@ #include <cpu/amd/mtrr.h> #include <device/pci_def.h> #include <southbridge/amd/cimx/cimx_util.h> +#include <agesawrapper.h> +#include "SBPLATFORM.h" //#define SMBUS_IO_BASE 0x6000 void set_pcie_reset(void); @@ -55,6 +57,24 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); /* + * Power off unused clock pins of GPP PCIe devices + * (Registers are interleaved.) + */ + u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); + + /* + * GPP CLK0 connected to unpopulated Mini PCIe slot (power off if nothing is soldered on) + * GPP CLK1 connected to Ethernet device + */ + *(misc_mem_clk_cntrl + 0) = 0xFF; + /* GPP CLK2 connected to USB controller */ + *(misc_mem_clk_cntrl + 1) = 0x0F; + *(misc_mem_clk_cntrl + 2) = 0x00; + *(misc_mem_clk_cntrl + 3) = 0x00; + /* SLT_GFX_CLK connected to PCIe slot */ + *(misc_mem_clk_cntrl + 4) = 0xF0; + + /* * Initialize ASF registers to an arbitrary address because someone * long ago set things up this way inside the SPD read code. The * SPD read code has been made generic and moved out of the board

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Patch set updated for coreboot: de7cbf2 southbridge/intel/bd82x6x/me_8.x.c: Trivial - space to tab fix
by Edward O'Callaghan 13 Jul '14

13 Jul '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6268 -gerrit commit de7cbf27e8716b827bd876ee9967ae6b3fe96f0e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Jul 13 00:28:05 2014 +1000 southbridge/intel/bd82x6x/me_8.x.c: Trivial - space to tab fix Change-Id: I5b6d0a1f5f96a8d6cfc5a14baaa0f9267339b072 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/intel/bd82x6x/me_8.x.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 356d9a5..2dc83f7 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -392,11 +392,10 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap) }; /* Send request and wait for response */ - if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) - < 0) { + if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) { printk(BIOS_ERR, "ME: GET FWCAPS message failed\n"); return -1; - } + } *cap = cap_msg.caps_sku; return 0; } @@ -420,7 +419,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) print_cap("IntelR Capability Licensing Service (CLS)", cap->intel_cls); print_cap("IntelR Power Sharing Technology (MPC)", cap->intel_mpc); print_cap("ICC Over Clocking", cap->icc_over_clocking); - print_cap("Protected Audio Video Path (PAVP)", cap->pavp); + print_cap("Protected Audio Video Path (PAVP)", cap->pavp); print_cap("IPV6", cap->ipv6); print_cap("KVM Remote Control (KVM)", cap->kvm); print_cap("Outbreak Containment Heuristic (OCH)", cap->och);

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Patch set updated for coreboot: a17c7b0 board_status.sh: name temp dir and print the name
by David Hendricks 12 Jul '14

12 Jul '14

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6259 -gerrit commit a17c7b0579b19589cee41dbd66c23af2d21c2603 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jul 10 14:59:11 2014 -0600 board_status.sh: name temp dir and print the name - give a template to the temp dir so they're recognizable. - show the location of the temp files again at the end of the script. Change-Id: Ieb031ee249043697f6a75e42284c23d0b9bad1b3 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- util/board_status/board_status.sh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 20ba48f..889419e 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -152,7 +152,7 @@ fi # Results will be placed in a temporary location until we're ready to upload. # If the user does not wish to upload, results will remain in /tmp. -tmpdir=$(mktemp -d) +tmpdir=$(mktemp -d --tmpdir coreboot_board_status.XXXXXXXX) # Obtain board and revision info to form the directory structure: # <vendor>/<board>/<revision>/<timestamp> @@ -229,6 +229,9 @@ cd "$coreboot_dir" if [ $CLOBBER_OUTPUT -eq 1 ]; then rm -rf ${tmpdir} +else + echo + echo "output files are in ${tmpdir}/${results}" fi exit $EXIT_SUCCESS

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New patch to review for coreboot: 289dd15 intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH`
by Paul Menzel 12 Jul '14

12 Jul '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6269 -gerrit commit 289dd15451701aed06e9d0879b57341776ed76e6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jul 12 22:11:24 2014 +0200 intel/lynxpoint/Kconfig: Remove duplicate option `IFD_BIN_PATH` Currently `IFD_BIN_PATH` is shown twice. Commit 5218e616 (intel/lynxpoint: Allow building without IFD (descripter.bin)) [1] accidentally added the option another time. So fix up the commit and remove one of the two options `IFD_BIN_PATH`. Keep the one which depends on `!HAVE_IFD_BIN` and is around the IFD options. [1] http://review.coreboot.org/6046 Change-Id: Id46f01ab8ee2e752e337e687a2ef0dfa374f44a5 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/southbridge/intel/lynxpoint/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 0ba61bc..0f52011 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -116,10 +116,6 @@ config ME_BIN_PATH depends on HAVE_ME_BIN default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin" -config IFD_BIN_PATH - string "Path to intel firmware descriptor" - default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin" - config ME_MBP_CLEAR_LATE bool "Defer wait for ME MBP Cleared" default y

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coreboot-gerrit July 2014