coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 18ff4f1 build system: create .xcompile dependency
by gerrit＠coreboot.org 15 Jul '14

15 Jul '14

the following patch was just integrated into master: commit 18ff4f166beef62175a81e9ffc7390d4a0ae5b64 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 21:06:04 2014 +0200 build system: create .xcompile dependency It's probably safe to say that .xcompile needs an update if util/xcompile/xcompile changed, so tell make about this dependency. Updates are honored immediately due to GNU make's feature of reinterpreting everything when an included file changes. See "How Makefiles Are Remade" in the GNU make documentation for details. Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/6255 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6255 for details. -gerrit

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Patch set updated for coreboot: a974f9c build system: remove duplicate architecture list
by Patrick Georgi 15 Jul '14

15 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6254 -gerrit commit a974f9c66f2af979230db574ea8e792e90b8de54 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 20:38:21 2014 +0200 build system: remove duplicate architecture list Let xcompile pass the list of architectures, given that it already has it. This potentially requires removing $(src)/.xcompile so it gets updated. Change-Id: I565512d3bef987c9a4e48a39bfd88bacf0b65de9 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- toolchain.inc | 2 -- util/xcompile/xcompile | 1 + 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/toolchain.inc b/toolchain.inc index b5b4fe0..842473b 100644 --- a/toolchain.inc +++ b/toolchain.inc @@ -17,8 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ARCH_SUPPORTED := armv7 x86_32 - # ccache integration ifeq ($(CONFIG_CCACHE),y) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 8239243..01d75bf 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -145,6 +145,7 @@ detect_special_flags() { report_arch_toolchain() { cat <<EOF # elf${TWIDTH}-${TBFDARCH} toolchain (${GCCPREFIX}gcc) +ARCH_SUPPORTED+=${TARCH} CC_${TARCH}:=${GCCPREFIX}gcc CFLAGS_${TARCH}:=${CFLAGS} CPP_${TARCH}:=${GCCPREFIX}cpp

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Patch set updated for coreboot: a5cc61e build system: create .xcompile dependency
by Patrick Georgi 15 Jul '14

15 Jul '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6255 -gerrit commit a5cc61e0a8d84846a48ac6613121bc948d2ec1ab Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Jul 10 21:06:04 2014 +0200 build system: create .xcompile dependency It's probably safe to say that .xcompile needs an update if util/xcompile/xcompile changed, so tell make about this dependency. Updates are honored immediately due to GNU make's feature of reinterpreting everything when an included file changes. See "How Makefiles Are Remade" in the GNU make documentation for details. Change-Id: Ide2f028eaddcee66028c6403688cc83e1622fa6b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile | 6 ++++-- util/xcompile/xcompile | 0 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/Makefile b/Makefile index c8cad4f..fad8103 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,9 @@ ## SUCH DAMAGE. ## -$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile $(XGCCPATH) > .xcompile))) +.xcompile: util/xcompile/xcompile + A=`mktemp $@.XXXXXX`; $< $(XGCCPATH) > $$A && mv $$A $@ 2> /dev/null + include .xcompile export top := $(CURDIR) @@ -271,4 +273,4 @@ clean-cscope: distclean: clean rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig* .ccwrap .xcompile -.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy .xcompile +.PHONY: $(PHONY) clean clean-for-update clean-cscope cscope distclean doxygen doxy diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile old mode 100644 new mode 100755

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Patch merged into coreboot/master: 3bb0b72 util/xcompile: Print fatal error messages to stderr instead of stdout
by gerrit＠coreboot.org 15 Jul '14

15 Jul '14

the following patch was just integrated into master: commit 3bb0b7230c07cb1d5b71df6976a8323c1cb41ca0 Author: Daniele Forsi <dforsi(a)gmail.com> Date: Mon Jul 14 15:35:42 2014 +0200 util/xcompile: Print fatal error messages to stderr instead of stdout This uses die() which was previously unused. Before this change an unhelpful error message was printed when make tried to parse English text as if it was part of the makefile: .xcompile:1: *** missing separator (did you mean TAB instead of 8 spaces?). Stop. After this change the first error message at least mentions that iasl is missing: ERROR: no iasl found make: -print-libgcc-file-name: Command not found make: -print-libgcc-file-name: Command not found make: -print-libgcc-file-name: Command not found /bin/sh: 0: Illegal option - Makefile.inc:36: *** Please use the coreboot toolchain (or prove that your toolchain works). Stop. Change-Id: I79d5de5993e3828460130192df376daa55f32aa0 Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> Reviewed-on: http://review.coreboot.org/6272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <gaumless(a)gmail.com> See http://review.coreboot.org/6272 for details. -gerrit

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New patch to review for coreboot: 582e191 build: turn .xcompile into a Makefile target
by Daniele Forsi 15 Jul '14

15 Jul '14

Daniele Forsi (dforsi(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6275 -gerrit commit 582e1916a106b1f3fc10f64383eaa339442bcffe Author: Daniele Forsi <dforsi(a)gmail.com> Date: Mon Jul 14 22:27:38 2014 +0200 build: turn .xcompile into a Makefile target This gives better error messages if util/xcompile/xcompile fails, eg. if iasl is missing: Makefile:33: .xcompile: No such file or directory ERROR: no iasl found Makefile:254: recipe for target '.xcompile' failed make: *** [.xcompile] Error 1 This works because if any included makefile is missing, GNU make will print a warning and it will rebuild it if a rule exists, else it will error out, see "Including Other Makefiles" in the manual: https://www.gnu.org/software/make/manual/make.html#Include In this case the warning at Makefile:33 is printed only when make is run in a clean tree, but .xcompile is rebuilt every time (like before) because make always tries to create/update makefiles and this it is a .PHONY target. Change-Id: Ie33ce46e17c8e59e32234576aeb77074879fa7e7 Signed-off-by: Daniele Forsi <dforsi(a)gmail.com> --- Makefile | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile b/Makefile index c8cad4f..cc4e3a4 100644 --- a/Makefile +++ b/Makefile @@ -30,7 +30,6 @@ ## SUCH DAMAGE. ## -$(if $(wildcard .xcompile),,$(eval $(shell bash util/xcompile/xcompile $(XGCCPATH) > .xcompile))) include .xcompile export top := $(CURDIR) @@ -251,6 +250,9 @@ endif cscope: cscope -bR +.xcompile: util/xcompile/xcompile + bash util/xcompile/xcompile $(XGCCPATH) > .xcompile + doxy: doxygen doxygen: $(DOXYGEN) documentation/Doxyfile.coreboot

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Patch set updated for coreboot: a0e6e50 src/superio/ite/it8772f: Separate mainboard from SIO at obj level
by Matt DeVillier 14 Jul '14

14 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6271 -gerrit commit a0e6e507e83e56186f4b26e8faf889debcdf05b0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 14 16:31:25 2014 +1000 src/superio/ite/it8772f: Separate mainboard from SIO at obj level Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/panther/romstage.c | 4 +- src/mainboard/samsung/stumpy/romstage.c | 17 +++--- src/mainboard/samsung/stumpy/smihandler.c | 20 +++---- src/superio/ite/it8772f/Makefile.inc | 1 + src/superio/ite/it8772f/early_init.c | 87 ++++++++++++++++++++++++++++++ src/superio/ite/it8772f/early_serial.c | 88 ------------------------------- src/superio/ite/it8772f/it8772f.h | 21 ++++++-- 7 files changed, 125 insertions(+), 113 deletions(-) diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968..c90c8e7 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -30,11 +30,11 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "gpio.h" #include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/it8772f/early_serial.c" #include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define DUMMY_DEV PNP_DEV(0x2e, 0) const struct rcba_config_instruction rcba_config[] = { @@ -145,7 +145,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Early SuperIO setup */ ite_kill_watchdog(GPIO_DEV); - it8772f_ac_resume_southbridge(); + it8772f_ac_resume_southbridge(DUMMY_DEV); pch_enable_lpc(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 6ab7007..153ce5c 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -34,8 +34,6 @@ #include <bootmode.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -/* FIXME: SUPERIO include.c */ -#include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" @@ -61,6 +59,7 @@ #endif #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) @@ -148,29 +147,29 @@ static void setup_sio_gpios(void) * GPIO10 as USBPWRON12# * GPIO12 as USBPWRON13# */ - it8772f_gpio_setup(1, 0x05, 0x05, 0x00, 0x05, 0x05); + it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); /* * GPIO22 as wake SCI# */ - it8772f_gpio_setup(2, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO32 as EXTSMI# */ - it8772f_gpio_setup(3, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO45 as LED_POWER# */ - it8772f_gpio_setup(4, 0x20, 0x20, 0x20, 0x20, 0x20); + it8772f_gpio_setup(DUMMY_DEV, 4, 0x20, 0x20, 0x20, 0x20, 0x20); /* * GPIO51 as USBPWRON8# * GPIO52 as USBPWRON1# */ - it8772f_gpio_setup(5, 0x06, 0x06, 0x00, 0x06, 0x06); - it8772f_gpio_setup(6, 0x00, 0x00, 0x00, 0x00, 0x00); + it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); + it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } void main(unsigned long bist) @@ -239,7 +238,7 @@ void main(unsigned long bist) setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(); + it8772f_ac_resume_southbridge(DUMMY_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 5c3e1b3..b232584 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -26,8 +26,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> -/* Include romstage serial for SIO helper functions */ -#include <superio/ite/it8772f/early_serial.c> +/* FIXME: Include romstage serial for SIO helper functions */ +#include <superio/ite/it8772f/early_init.c> +//#include <superio/ite/it8772f/it8772f.h> +#define DUMMY_DEV PNP_DEV(0x2e, 0) int mainboard_io_trap_handler(int smif) { @@ -64,18 +66,18 @@ void mainboard_smi_sleep(u8 slp_typ) case 3: case 4: /* Blink LED */ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + it8772f_enter_conf(DUMMY_DEV); + it8772f_sio_write(DUMMY_DEV, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); /* Enable blink pin map */ - it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP, + it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_PINMAP, SIO_GPIO_BLINK_GPIO45); /* Enable 4HZ blink */ - it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02); + it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02); /* Set GPIO to alternate function */ - reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3)); + reg8 = it8772f_sio_read(DUMMY_DEV, GPIO_REG_ENABLE(3)); reg8 &= ~(1 << 5); - it8772f_sio_write(GPIO_REG_ENABLE(3), reg8); - it8772f_exit_conf(); + it8772f_sio_write(DUMMY_DEV, GPIO_REG_ENABLE(3), reg8); + it8772f_exit_conf(DUMMY_DEV); break; case 5: diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index 7b6be2c..438ba84 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c new file mode 100644 index 0000000..1ae80c8 --- /dev/null +++ b/src/superio/ite/it8772f/early_init.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp_def.h> + +#include "it8772f.h" + +/* NOTICE: This file is deprecated, use ite/common instead */ + +/* RAMstage equiv */ +/* u8 pnp_read_config(device_t dev, u8 reg) */ +u8 it8772f_sio_read(device_t dev, u8 reg) +{ + u16 port = dev >> 8; + + outb(reg, port); + return inb(port + 1); +} + +/* RAMstage equiv */ +/* void pnp_write_config(device_t dev, u8 reg, u8 value) */ +void it8772f_sio_write(device_t dev, u8 reg, u8 value) +{ + u16 port = dev >> 8; + + outb(reg, port); + outb(value, port + 1); +} + +void it8772f_enter_conf(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +void it8772f_exit_conf(device_t dev) +{ + it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); +} + +/* Set AC resume to be up to the Southbridge */ +void it8772f_ac_resume_southbridge(device_t dev) +{ + it8772f_enter_conf(dev); + it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); + it8772f_sio_write(dev, 0xf4, 0x60); + it8772f_exit_conf(dev); +} + +/* Configure a set of GPIOs */ +void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, + u8 pullup, u8 output, u8 enable) +{ + set--; /* Set 1 is offset 0 */ + it8772f_enter_conf(dev); + it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + if (set < 5) { + it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); + it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); + it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); + } + it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); + it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); + it8772f_exit_conf(dev); +} diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c deleted file mode 100644 index ee9dbc5..0000000 --- a/src/superio/ite/it8772f/early_serial.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp_def.h> -#include "it8772f.h" - -/* NOTICE: This file is deprecated, use ite/common instead */ - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -/* FIXME: SUPERIO include.c */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ - -u8 it8772f_sio_read(u8 index) -{ - outb(index, SIO_BASE); - return inb(SIO_DATA); -} - -void it8772f_sio_write(u8 index, u8 value) -{ - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8772f_enter_conf(void) -{ - u16 port = SIO_BASE; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8772f_exit_conf(void) -{ - it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02); -} - -/* Set AC resume to be up to the Southbridge */ -void it8772f_ac_resume_southbridge(void) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC); - it8772f_sio_write(0xf4, 0x60); - it8772f_exit_conf(); -} - -/* Configure a set of GPIOs */ -void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup, - u8 output, u8 enable) -{ - set--; /* Set 1 is offset 0 */ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); - if (set < 5) { - it8772f_sio_write(GPIO_REG_SELECT(set), select); - it8772f_sio_write(GPIO_REG_ENABLE(set), enable); - it8772f_sio_write(GPIO_REG_POLARITY(set), polarity); - } - it8772f_sio_write(GPIO_REG_OUTPUT(set), output); - it8772f_sio_write(GPIO_REG_PULLUP(set), pullup); - it8772f_exit_conf(); -} diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 221a932..09eeb8f 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -103,10 +103,21 @@ #define GPIO_REG_ENABLE(x) (0xc0 + (x)) #define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -u8 it8772f_sio_read(u8 index); -void it8772f_sio_write(u8 index, u8 value); -void it8772f_ac_resume_southbridge(void); -void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, - u8 output, u8 enable); +#include <arch/io.h> +#include <stdint.h> + +u8 it8772f_sio_read(device_t dev, u8 reg); +void it8772f_sio_write(device_t dev, u8 reg, u8 value); +void it8772f_ac_resume_southbridge(device_t dev); +void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, + u8 pullup, u8 output, u8 enable); + +/* FIXME: should be static so will be removed later.. */ +/* Global configuration registers. */ +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ + +void it8772f_enter_conf(device_t dev); +void it8772f_exit_conf(device_t dev); #endif /* SUPERIO_ITE_IT8772F_H */

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Patch set updated for coreboot: cea6dbf google/panther: general cleanup, file organization (non-functional)
by Matt DeVillier 14 Jul '14

14 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6270 -gerrit commit cea6dbf3357d53ff9d769222dd15d1508c994564 Author: Matt DeVillier <matt.devillier(a)gmail.com> Date: Sun Jul 13 18:51:28 2014 -0500 google/panther: general cleanup, file organization (non-functional) acpi_tables.c: consolidate/organize headers chromeos.c: consolidate/organize headers; move header, #defines outside of #ifdef fadt.c: organize headers gpio.h: rename include guard; add comment to trailing #endif had_verb.h: add include guard; replace manual array size calculation with std header macro lan.c: remove conditional header inclusion; organize headers; remove pre-processor directive indentations mainboard.c: remove conditional header inclusion; organize headers; replace spaced indentations with tab(s); add comment to trailing #endif onboard.h: move fn prototype after #defines; add comment to trailing #endif romstage.c: consolidate/organize headers smihandler.c: organize headers; remove commented-out/dead code; add comment to trailing #endif thermal.h: add comment to trailing #endif Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- src/mainboard/google/panther/acpi_tables.c | 21 ++++--- src/mainboard/google/panther/chromeos.c | 7 +-- src/mainboard/google/panther/fadt.c | 2 +- src/mainboard/google/panther/gpio.h | 6 +- src/mainboard/google/panther/hda_verb.h | 9 ++- src/mainboard/google/panther/lan.c | 13 ++--- src/mainboard/google/panther/mainboard.c | 30 +++++----- src/mainboard/google/panther/onboard.h | 8 +-- src/mainboard/google/panther/romstage.c | 8 +-- src/mainboard/google/panther/smihandler.c | 91 ++---------------------------- src/mainboard/google/panther/thermal.h | 2 +- 11 files changed, 57 insertions(+), 140 deletions(-) diff --git a/src/mainboard/google/panther/acpi_tables.c b/src/mainboard/google/panther/acpi_tables.c index de67c22..1a9e1e6 100644 --- a/src/mainboard/google/panther/acpi_tables.c +++ b/src/mainboard/google/panther/acpi_tables.c @@ -17,31 +17,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> #include <cbmem.h> -#include <console/console.h> +#include <string.h> +#include <types.h> #include <arch/acpi.h> -#include <arch/ioapic.h> #include <arch/acpigen.h> +#include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <cpu/cpu.h> -#include <cpu/x86/msr.h> -#include <vendorcode/google/chromeos/gnvs.h> #include <ec/google/chromeec/ec.h> +#include <southbridge/intel/lynxpoint/nvs.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include "thermal.h" extern const unsigned char AmlCode[]; #if CONFIG_HAVE_ACPI_SLIC unsigned long acpi_create_slic(unsigned long current); #endif -#include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/nvs.h> -#include "thermal.h" - static void acpi_update_thermal_table(global_nvs_t *gnvs) { gnvs->f4of = FAN4_THRESHOLD_OFF; diff --git a/src/mainboard/google/panther/chromeos.c b/src/mainboard/google/panther/chromeos.c index 074f648..62165da 100644 --- a/src/mainboard/google/panther/chromeos.c +++ b/src/mainboard/google/panther/chromeos.c @@ -18,11 +18,12 @@ */ #include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <vendorcode/google/chromeos/chromeos.h> #define GPIO_SPI_WP 58 #define GPIO_REC_MODE 12 @@ -31,13 +32,11 @@ #define FLAG_REC_MODE 1 #define FLAG_DEV_MODE 2 -#ifndef __PRE_RAM__ -#include <boot/coreboot_tables.h> - #define GPIO_COUNT 6 #define ACTIVE_LOW 0 #define ACTIVE_HIGH 1 +#ifndef __PRE_RAM__ static void fill_lb_gpio(struct lb_gpio *gpio, int num, int polarity, const char *name, int force) { diff --git a/src/mainboard/google/panther/fadt.c b/src/mainboard/google/panther/fadt.c index 7afbbfa..7289712 100644 --- a/src/mainboard/google/panther/fadt.c +++ b/src/mainboard/google/panther/fadt.c @@ -18,9 +18,9 @@ */ #include <string.h> -#include <device/pci.h> #include <arch/acpi.h> #include <cpu/x86/smm.h> +#include <device/pci.h> #include <southbridge/intel/lynxpoint/pch.h> void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) diff --git a/src/mainboard/google/panther/gpio.h b/src/mainboard/google/panther/gpio.h index 9951984..a83b47b 100644 --- a/src/mainboard/google/panther/gpio.h +++ b/src/mainboard/google/panther/gpio.h @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H +#ifndef PANTHER_GPIO_H +#define PANTHER_GPIO_H struct pch_lp_gpio_map; @@ -121,4 +121,4 @@ const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_END }; -#endif +#endif /* PANTHER_GPIO_H */ diff --git a/src/mainboard/google/panther/hda_verb.h b/src/mainboard/google/panther/hda_verb.h index cec56eb..456561b 100644 --- a/src/mainboard/google/panther/hda_verb.h +++ b/src/mainboard/google/panther/hda_verb.h @@ -17,6 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef HDA_VERB_H +#define HDA_VERB_H + +#include <stdlib.h> + static const u32 mainboard_cim_verb_data[] = { /* coreboot specific header */ 0x10ec0283, // Codec Vendor / Device ID: Realtek ALC283 @@ -109,4 +114,6 @@ static const u32 mainboard_pc_beep_verbs[] = { }; static const u32 mainboard_pc_beep_verbs_size = - sizeof(mainboard_pc_beep_verbs) / sizeof(mainboard_pc_beep_verbs[0]); + ARRAY_SIZE(mainboard_pc_beep_verbs); + +#endif /* HDA_VERB_H */ diff --git a/src/mainboard/google/panther/lan.c b/src/mainboard/google/panther/lan.c index 9e941d5..2d7eed0 100644 --- a/src/mainboard/google/panther/lan.c +++ b/src/mainboard/google/panther/lan.c @@ -17,18 +17,15 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> +#include <cbfs.h> #include <string.h> +#include <types.h> #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <southbridge/intel/bd82x6x/pch.h> -#if CONFIG_CHROMEOS #include <vendorcode/google/chromeos/fmap.h> -#else -#include <cbfs.h> -#endif #include "onboard.h" static unsigned int search(char *p, char *a, unsigned int lengthp, @@ -142,11 +139,11 @@ void lan_init(void) u16 io_base = 0; struct device *ethernet_dev = NULL; - #if CONFIG_CHROMEOS +#if CONFIG_CHROMEOS char **vpd_region_ptr = NULL; search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); search_address = (unsigned long)(*vpd_region_ptr); - #else +#else void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin", CBFS_TYPE_RAW, &search_length); if (vpd_file) { @@ -155,7 +152,7 @@ void lan_init(void) search_length = -1; search_address = 0; } - #endif +#endif /* Get NIC's IO base address */ ethernet_dev = dev_find_device(PANTHER_NIC_VENDOR_ID, diff --git a/src/mainboard/google/panther/mainboard.c b/src/mainboard/google/panther/mainboard.c index afa6526..0c59ded 100644 --- a/src/mainboard/google/panther/mainboard.c +++ b/src/mainboard/google/panther/mainboard.c @@ -18,25 +18,24 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <types.h> -#include <string.h> #include <smbios.h> +#include <string.h> +#include <types.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include <console/console.h> #include <device/device.h> #include <device/device.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> -#if CONFIG_VGA_ROM_RUN -#include <x86emu/x86emu.h> -#endif #include <pc80/mc146818rtc.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/interrupt.h> -#include <boot/coreboot_tables.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <x86emu/x86emu.h> #include "hda_verb.h" #include "onboard.h" -#include <southbridge/intel/lynxpoint/pch.h> + void mainboard_suspend_resume(void) { @@ -50,7 +49,7 @@ static int int15_handler(void) int res = 0; printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", - __func__, X86_AX, X86_BX, X86_CX, X86_DX); + __func__, X86_AX, X86_BX, X86_CX, X86_DX); switch (X86_AX) { case 0x5f34: @@ -116,19 +115,19 @@ static int int15_handler(void) default: /* Interrupt was not handled */ printk(BIOS_DEBUG, - "Unknown INT15 5f70 function: 0x%02x\n", + "Unknown INT15 5f70 function: 0x%02x\n", ((X86_CX >> 8) & 0xff)); break; } break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } return res; } -#endif +#endif /* CONFIG_VGA_ROM_RUN */ /* Audio Setup */ @@ -167,4 +166,3 @@ static void mainboard_enable(device_t dev) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; - diff --git a/src/mainboard/google/panther/onboard.h b/src/mainboard/google/panther/onboard.h index 0b67017..4d05dc7 100644 --- a/src/mainboard/google/panther/onboard.h +++ b/src/mainboard/google/panther/onboard.h @@ -1,10 +1,6 @@ #ifndef __MAINBOARD_ONBOARD_H #define __MAINBOARD_ONBOARD_H -#ifndef __ACPI__ -void lan_init(void); -#endif - /* defines for programming the MAC address */ #define PANTHER_NIC_VENDOR_ID 0x10EC #define PANTHER_NIC_DEVICE_ID 0x8168 @@ -18,4 +14,8 @@ void lan_init(void); /* WLAN wake is GPIO 10 */ #define PANTHER_WLAN_WAKE_GPIO 10 +#ifndef __ACPI__ +void lan_init(void); #endif + +#endif /* __MAINBOARD_ONBOARD_H */ diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c90c8e7..dcc935b 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -18,19 +18,19 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cbfs.h> #include <stdint.h> #include <stdlib.h> #include <string.h> -#include <cbfs.h> #include <console/console.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> -#include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> +#include <southbridge/intel/lynxpoint/pch.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8772f/it8772f.h> #include "gpio.h" -#include "superio/ite/it8772f/it8772f.h" -#include "superio/ite/common/ite.h" #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) diff --git a/src/mainboard/google/panther/smihandler.c b/src/mainboard/google/panther/smihandler.c index 2ad2498..3448648 100644 --- a/src/mainboard/google/panther/smihandler.c +++ b/src/mainboard/google/panther/smihandler.c @@ -20,12 +20,12 @@ #include <arch/io.h> #include <console/console.h> +#include <cpu/intel/haswell/haswell.h> #include <cpu/x86/smm.h> +#include <northbridge/intel/haswell/haswell.h> +#include <southbridge/intel/lynxpoint/me.h> #include <southbridge/intel/lynxpoint/nvs.h> #include <southbridge/intel/lynxpoint/pch.h> -#include <southbridge/intel/lynxpoint/me.h> -#include <northbridge/intel/haswell/haswell.h> -#include <cpu/intel/haswell/haswell.h> #include <elog.h> /* GPIO46 controls the WLAN_DISABLE_L signal. */ @@ -49,82 +49,9 @@ int mainboard_io_trap_handler(int smif) * For now, we force the return value to 0 and log all traps to * see what's going on. */ - //gnvs->smif = 0; return 1; } -#if 0 -static u8 mainboard_smi_ec(void) -{ - u8 cmd = 0;// google_chromeec_get_event(); - -#if CONFIG_ELOG_GSMI - /* Log this event */ - if (cmd) - elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); -#endif - - return cmd; -} -#endif - -/* gpi_sts is GPIO 47:32 */ -void mainboard_smi_gpi(u32 gpi_sts) -{ -#if 0 - if (gpi_sts & (1 << (EC_SMI_GPI - 32))) { - /* Process all pending events */ - while (mainboard_smi_ec() != 0); - } -#endif -} - -void mainboard_smi_sleep(u8 slp_typ) -{ - /* Disable USB charging if required */ - switch (slp_typ) { - case 3: - //if (smm_get_gnvs()->s3u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s3u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S3. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); - break; - case 5: - //if (smm_get_gnvs()->s5u0 == 0) - // google_chromeec_set_usb_charge_mode( - // 0, USB_CHARGE_MODE_DISABLED); - //if (smm_get_gnvs()->s5u1 == 0) - // google_chromeec_set_usb_charge_mode( - // 1, USB_CHARGE_MODE_DISABLED); - - /* Prevent leak from standby rail to WLAN rail in S5. */ - //set_gpio(GPIO_WLAN_DISABLE_L, 0); - /* Disable LTE */ - //set_gpio(GPIO_LTE_DISABLE_L, 0); - - /* Enable wake events */ - //google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); - break; - } - - /* Disable SCI and SMI events */ - //google_chromeec_set_smi_mask(0); - //google_chromeec_set_sci_mask(0); - - /* Clear pending events that may trigger immediate wake */ - //while (google_chromeec_get_event() != 0); -} - #define APMC_FINALIZE 0xcb static int mainboard_finalized = 0; @@ -144,17 +71,7 @@ int mainboard_smi_apmc(u8 apmc) mainboard_finalized = 1; break; - case APM_CNT_ACPI_ENABLE: - //google_chromeec_set_smi_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); - break; - case APM_CNT_ACPI_DISABLE: - //google_chromeec_set_sci_mask(0); - /* Clear all pending events */ - //while (google_chromeec_get_event() != 0); - //google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + default: break; } return 0; diff --git a/src/mainboard/google/panther/thermal.h b/src/mainboard/google/panther/thermal.h index 7a96561..1ed7ce7 100644 --- a/src/mainboard/google/panther/thermal.h +++ b/src/mainboard/google/panther/thermal.h @@ -54,4 +54,4 @@ /* Tj_max value for calculating PECI CPU temperature */ #define MAX_TEMPERATURE 100 -#endif +#endif /* THERMAL_H */

1 0

Patch set updated for coreboot: 1a5f8da board_status.sh allow cmd() to not save output
by Martin Roth 14 Jul '14

14 Jul '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6258 -gerrit commit 1a5f8da3ab57e80d57c97f30defc5cb2eaae2a52 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Jul 10 14:57:34 2014 -0600 board_status.sh allow cmd() to not save output - allow for cmd() to be run, but not pipe to a file. Change-Id: I3e1650e421a49a06218e082ceb5a60b7b4808ce8 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- util/board_status/board_status.sh | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 7c321b3..20ba48f 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -60,10 +60,16 @@ _cmd() return $EXIT_FAILURE fi + if [ -n "$3" ]; then + pipe_location="${3}" + else + pipe_location="/dev/null" + fi + if [ "$1" -eq "$REMOTE" ] && [ -n "$REMOTE_HOST" ]; then - ssh root@${REMOTE_HOST} "$2" > "${3}" 2>&1 + ssh root@${REMOTE_HOST} "$2" > "$pipe_location" 2>&1 else - $2 > "${3}" 2>&1 + $2 > "$pipe_location" 2>&1 fi return $?

1 0

Patch merged into coreboot/master: be5340b board_status.sh add non-fatal test_cmd
by gerrit＠coreboot.org 14 Jul '14

14 Jul '14

the following patch was just integrated into master: commit be5340bad23af53b4e78adb143fed926ff199c7c Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Jun 22 21:46:24 2014 -0600 board_status.sh add non-fatal test_cmd - add a non-fatal option to test_cmd. Change-Id: If74693ea7ec8ea24104d5836e4c24bfb135ef0e1 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/6257 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/6257 for details. -gerrit

1 0

Patch set updated for coreboot: c505427 src/superio/ite/it8772f: Separate mainboard from SIO at obj level
by Matt DeVillier 14 Jul '14

14 Jul '14

Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6271 -gerrit commit c505427c3d1eb26043c4d6ffd7e663bf6fe08ec5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Jul 14 16:31:25 2014 +1000 src/superio/ite/it8772f: Separate mainboard from SIO at obj level Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/panther/romstage.c | 3 +- src/mainboard/samsung/stumpy/romstage.c | 17 +++--- src/mainboard/samsung/stumpy/smihandler.c | 20 +++---- src/superio/ite/it8772f/Makefile.inc | 1 + src/superio/ite/it8772f/early_init.c | 87 ++++++++++++++++++++++++++++++ src/superio/ite/it8772f/early_serial.c | 88 ------------------------------- src/superio/ite/it8772f/it8772f.h | 21 ++++++-- 7 files changed, 125 insertions(+), 112 deletions(-) diff --git a/src/mainboard/google/panther/romstage.c b/src/mainboard/google/panther/romstage.c index c367968..adb6395 100644 --- a/src/mainboard/google/panther/romstage.c +++ b/src/mainboard/google/panther/romstage.c @@ -35,6 +35,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) +#define DUMMY_DEV PNP_DEV(0x2e, 0) const struct rcba_config_instruction rcba_config[] = { @@ -145,7 +146,7 @@ void mainboard_romstage_entry(unsigned long bist) /* Early SuperIO setup */ ite_kill_watchdog(GPIO_DEV); - it8772f_ac_resume_southbridge(); + it8772f_ac_resume_southbridge(DUMMY_DEV); pch_enable_lpc(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 6ab7007..153ce5c 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -34,8 +34,6 @@ #include <bootmode.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -/* FIXME: SUPERIO include.c */ -#include "superio/ite/it8772f/early_serial.c" #include "northbridge/intel/sandybridge/sandybridge.h" #include "northbridge/intel/sandybridge/raminit.h" #include "southbridge/intel/bd82x6x/pch.h" @@ -61,6 +59,7 @@ #endif #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ +#define DUMMY_DEV PNP_DEV(0x2e, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) @@ -148,29 +147,29 @@ static void setup_sio_gpios(void) * GPIO10 as USBPWRON12# * GPIO12 as USBPWRON13# */ - it8772f_gpio_setup(1, 0x05, 0x05, 0x00, 0x05, 0x05); + it8772f_gpio_setup(DUMMY_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); /* * GPIO22 as wake SCI# */ - it8772f_gpio_setup(2, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(DUMMY_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO32 as EXTSMI# */ - it8772f_gpio_setup(3, 0x04, 0x04, 0x00, 0x04, 0x04); + it8772f_gpio_setup(DUMMY_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); /* * GPIO45 as LED_POWER# */ - it8772f_gpio_setup(4, 0x20, 0x20, 0x20, 0x20, 0x20); + it8772f_gpio_setup(DUMMY_DEV, 4, 0x20, 0x20, 0x20, 0x20, 0x20); /* * GPIO51 as USBPWRON8# * GPIO52 as USBPWRON1# */ - it8772f_gpio_setup(5, 0x06, 0x06, 0x00, 0x06, 0x06); - it8772f_gpio_setup(6, 0x00, 0x00, 0x00, 0x00, 0x00); + it8772f_gpio_setup(DUMMY_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); + it8772f_gpio_setup(DUMMY_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); } void main(unsigned long bist) @@ -239,7 +238,7 @@ void main(unsigned long bist) setup_sio_gpios(); /* Early SuperIO setup */ - it8772f_ac_resume_southbridge(); + it8772f_ac_resume_southbridge(DUMMY_DEV); ite_kill_watchdog(GPIO_DEV); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/samsung/stumpy/smihandler.c b/src/mainboard/samsung/stumpy/smihandler.c index 5c3e1b3..b232584 100644 --- a/src/mainboard/samsung/stumpy/smihandler.c +++ b/src/mainboard/samsung/stumpy/smihandler.c @@ -26,8 +26,10 @@ #include <northbridge/intel/sandybridge/sandybridge.h> #include <cpu/intel/model_206ax/model_206ax.h> -/* Include romstage serial for SIO helper functions */ -#include <superio/ite/it8772f/early_serial.c> +/* FIXME: Include romstage serial for SIO helper functions */ +#include <superio/ite/it8772f/early_init.c> +//#include <superio/ite/it8772f/it8772f.h> +#define DUMMY_DEV PNP_DEV(0x2e, 0) int mainboard_io_trap_handler(int smif) { @@ -64,18 +66,18 @@ void mainboard_smi_sleep(u8 slp_typ) case 3: case 4: /* Blink LED */ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + it8772f_enter_conf(DUMMY_DEV); + it8772f_sio_write(DUMMY_DEV, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); /* Enable blink pin map */ - it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_PINMAP, + it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_PINMAP, SIO_GPIO_BLINK_GPIO45); /* Enable 4HZ blink */ - it8772f_sio_write(IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02); + it8772f_sio_write(DUMMY_DEV, IT8772F_GPIO_LED_BLINK1_CONTROL, 0x02); /* Set GPIO to alternate function */ - reg8 = it8772f_sio_read(GPIO_REG_ENABLE(3)); + reg8 = it8772f_sio_read(DUMMY_DEV, GPIO_REG_ENABLE(3)); reg8 &= ~(1 << 5); - it8772f_sio_write(GPIO_REG_ENABLE(3), reg8); - it8772f_exit_conf(); + it8772f_sio_write(DUMMY_DEV, GPIO_REG_ENABLE(3), reg8); + it8772f_exit_conf(DUMMY_DEV); break; case 5: diff --git a/src/superio/ite/it8772f/Makefile.inc b/src/superio/ite/it8772f/Makefile.inc index 7b6be2c..438ba84 100644 --- a/src/superio/ite/it8772f/Makefile.inc +++ b/src/superio/ite/it8772f/Makefile.inc @@ -18,4 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8772F) += early_init.c ramstage-$(CONFIG_SUPERIO_ITE_IT8772F) += superio.c diff --git a/src/superio/ite/it8772f/early_init.c b/src/superio/ite/it8772f/early_init.c new file mode 100644 index 0000000..1ae80c8 --- /dev/null +++ b/src/superio/ite/it8772f/early_init.c @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp_def.h> + +#include "it8772f.h" + +/* NOTICE: This file is deprecated, use ite/common instead */ + +/* RAMstage equiv */ +/* u8 pnp_read_config(device_t dev, u8 reg) */ +u8 it8772f_sio_read(device_t dev, u8 reg) +{ + u16 port = dev >> 8; + + outb(reg, port); + return inb(port + 1); +} + +/* RAMstage equiv */ +/* void pnp_write_config(device_t dev, u8 reg, u8 value) */ +void it8772f_sio_write(device_t dev, u8 reg, u8 value) +{ + u16 port = dev >> 8; + + outb(reg, port); + outb(value, port + 1); +} + +void it8772f_enter_conf(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +void it8772f_exit_conf(device_t dev) +{ + it8772f_sio_write(dev, IT8772F_CONFIG_REG_CC, 0x02); +} + +/* Set AC resume to be up to the Southbridge */ +void it8772f_ac_resume_southbridge(device_t dev) +{ + it8772f_enter_conf(dev); + it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_EC); + it8772f_sio_write(dev, 0xf4, 0x60); + it8772f_exit_conf(dev); +} + +/* Configure a set of GPIOs */ +void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, + u8 pullup, u8 output, u8 enable) +{ + set--; /* Set 1 is offset 0 */ + it8772f_enter_conf(dev); + it8772f_sio_write(dev, IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); + if (set < 5) { + it8772f_sio_write(dev, GPIO_REG_SELECT(set), select); + it8772f_sio_write(dev, GPIO_REG_ENABLE(set), enable); + it8772f_sio_write(dev, GPIO_REG_POLARITY(set), polarity); + } + it8772f_sio_write(dev, GPIO_REG_OUTPUT(set), output); + it8772f_sio_write(dev, GPIO_REG_PULLUP(set), pullup); + it8772f_exit_conf(dev); +} diff --git a/src/superio/ite/it8772f/early_serial.c b/src/superio/ite/it8772f/early_serial.c deleted file mode 100644 index ee9dbc5..0000000 --- a/src/superio/ite/it8772f/early_serial.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp_def.h> -#include "it8772f.h" - -/* NOTICE: This file is deprecated, use ite/common instead */ - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -/* FIXME: SUPERIO include.c */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ - -u8 it8772f_sio_read(u8 index) -{ - outb(index, SIO_BASE); - return inb(SIO_DATA); -} - -void it8772f_sio_write(u8 index, u8 value) -{ - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8772f_enter_conf(void) -{ - u16 port = SIO_BASE; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8772f_exit_conf(void) -{ - it8772f_sio_write(IT8772F_CONFIG_REG_CC, 0x02); -} - -/* Set AC resume to be up to the Southbridge */ -void it8772f_ac_resume_southbridge(void) -{ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_EC); - it8772f_sio_write(0xf4, 0x60); - it8772f_exit_conf(); -} - -/* Configure a set of GPIOs */ -void it8772f_gpio_setup(int set, u8 select, u8 polarity, u8 pullup, - u8 output, u8 enable) -{ - set--; /* Set 1 is offset 0 */ - it8772f_enter_conf(); - it8772f_sio_write(IT8772F_CONFIG_REG_LDN, IT8772F_GPIO); - if (set < 5) { - it8772f_sio_write(GPIO_REG_SELECT(set), select); - it8772f_sio_write(GPIO_REG_ENABLE(set), enable); - it8772f_sio_write(GPIO_REG_POLARITY(set), polarity); - } - it8772f_sio_write(GPIO_REG_OUTPUT(set), output); - it8772f_sio_write(GPIO_REG_PULLUP(set), pullup); - it8772f_exit_conf(); -} diff --git a/src/superio/ite/it8772f/it8772f.h b/src/superio/ite/it8772f/it8772f.h index 221a932..09eeb8f 100644 --- a/src/superio/ite/it8772f/it8772f.h +++ b/src/superio/ite/it8772f/it8772f.h @@ -103,10 +103,21 @@ #define GPIO_REG_ENABLE(x) (0xc0 + (x)) #define GPIO_REG_OUTPUT(x) (0xc8 + (x)) -u8 it8772f_sio_read(u8 index); -void it8772f_sio_write(u8 index, u8 value); -void it8772f_ac_resume_southbridge(void); -void it8772f_gpio_setup(int set, u8 func_select, u8 polarity, u8 pullup, - u8 output, u8 enable); +#include <arch/io.h> +#include <stdint.h> + +u8 it8772f_sio_read(device_t dev, u8 reg); +void it8772f_sio_write(device_t dev, u8 reg, u8 value); +void it8772f_ac_resume_southbridge(device_t dev); +void it8772f_gpio_setup(device_t dev, int set, u8 select, u8 polarity, + u8 pullup, u8 output, u8 enable); + +/* FIXME: should be static so will be removed later.. */ +/* Global configuration registers. */ +#define IT8772F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8772F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ + +void it8772f_enter_conf(device_t dev); +void it8772f_exit_conf(device_t dev); #endif /* SUPERIO_ITE_IT8772F_H */

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coreboot-gerrit July 2014