coreboot-gerrit July 2014

coreboot-gerrit@coreboot.org

1 participants
861 discussions

Patch set updated for coreboot: 7d27e0c amd/dinar & torpedo: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6322 -gerrit commit 7d27e0c759dca91274b4f05b9dc87d01d3d118e2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 23:45:01 2014 +0200 amd/dinar & torpedo: Remove a trailing whitespace Change-Id: I4ac14c4f511eb6d56480e5167ce98b861cbed775 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/dinar/agesawrapper.h | 72 +++++++++++++++++----------------- src/mainboard/amd/dinar/buildOpts.c | 22 +++++------ src/mainboard/amd/dinar/platform_cfg.h | 4 +- 3 files changed, 49 insertions(+), 49 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index 70cf4f6..e4deb1b 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -25,44 +25,44 @@ #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MMIO_NP_BIT BIT7 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MMIO_NP_BIT BIT7 /* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 -#define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn #define MmioAddress( BaseAddr, Register ) \ ( (UINTN)BaseAddr + \ (UINTN)(Register) \ diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 958764e..88e3c6f 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -33,8 +33,8 @@ * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ */ #include <stdlib.h> -#include "AGESA.h" -#include "CommonReturns.h" +#include "AGESA.h" +#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE @@ -42,15 +42,15 @@ * coreboot enable -Wundef option, so we should make sure we have all contanstand defined */ /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h index 94f4f0c..0aa3743 100644 --- a/src/mainboard/amd/dinar/platform_cfg.h +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -31,13 +31,13 @@ * Enable check for PCIe endpoint to be ready for PCI enumeration. * */ -//#define EPREADY_WORKAROUND_DISABLED +//#define EPREADY_WORKAROUND_DISABLED /** * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. * */ -#define IOMMU_SUPPORT_DISABLE //TODO: enable it +#define IOMMU_SUPPORT_DISABLE //TODO: enable it /** * Disable server PCIe hotplug support.

1 0

Patch set updated for coreboot: 915fe0d southbridge/via: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6345 -gerrit commit 915fe0d5ea254f97d150b8abcc4d6d8a239097b5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 23:33:40 2014 +0200 southbridge/via: Remove a trailing whitespace Change-Id: I28deda21a7070ea6f14f973b66fd5dd119bc6225 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/via/vt8235/early_smbus.c | 35 ++++++++++++++++---------------- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c index 96da2fa..c346b81 100644 --- a/src/southbridge/via/vt8235/early_smbus.c +++ b/src/southbridge/via/vt8235/early_smbus.c @@ -1,18 +1,18 @@ -#define SMBUS_IO_BASE 0xf00 - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBSLVCTL 0x8 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_IO_BASE 0xf00 + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBSLVCTL 0x8 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf /* Define register settings */ #define HOST_RESET 0xff @@ -21,8 +21,8 @@ #define SMBUS_TIMEOUT (100*1000*10) -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 static void enable_smbus(void) { @@ -244,5 +244,4 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) return host_status_register != 0x02; } - #endif

1 0

Patch set updated for coreboot: a47b41e southbridge/amd: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6334 -gerrit commit a47b41e9c32abe422e290589f00c4fd8fadc51e4 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 23:12:38 2014 +0200 southbridge/amd: Remove a trailing whitespace Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 +- src/southbridge/amd/agesa/hudson/smbus.c | 4 +- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 8 +-- src/southbridge/amd/cimx/sb900/SbPlatform.h | 76 +++++++++++++------------- src/southbridge/amd/sb800/early_setup.c | 4 +- src/southbridge/amd/sb800/smbus.c | 4 +- 6 files changed, 50 insertions(+), 50 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d8fdc27..039df20 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _HUDSON_EARLY_SETUP_C_ -#define _HUDSON_EARLY_SETUP_C_ +#ifndef _HUDSON_EARLY_SETUP_C_ +#define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> #include <arch/io.h> diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 0c04158..519c85d 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _HUDSON_SMBUS_C_ -#define _HUDSON_SMBUS_C_ +#ifndef _HUDSON_SMBUS_C_ +#define _HUDSON_SMBUS_C_ #include <io.h> #include <stdint.h> diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index ea3f719..b26d429 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -21,8 +21,8 @@ * */ -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> @@ -162,7 +162,7 @@ typedef union _PCI_ADDR { #include <spi-generic.h> #endif -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 176ad87..6371bcd 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -21,8 +21,8 @@ * */ -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> @@ -107,48 +107,48 @@ typedef union _PCI_ADDR { * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable */ -#define SB_CIMx_PARAMETER 0x02 +#define SB_CIMx_PARAMETER 0x02 // Generic -#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL // GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimNbSbGen2Default TRUE +#define cimAlinkPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller -#define cimUsbPhyPowerDownDefault FALSE +#define cimUsbPhyPowerDownDefault FALSE // GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 // Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable +#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE // Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index ef0548c..5244490 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB800_EARLY_SETUP_C_ -#define _SB800_EARLY_SETUP_C_ +#ifndef _SB800_EARLY_SETUP_C_ +#define _SB800_EARLY_SETUP_C_ #include <reset.h> #include <arch/acpi.h> diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c index c1a9ded..5c4152a 100644 --- a/src/southbridge/amd/sb800/smbus.c +++ b/src/southbridge/amd/sb800/smbus.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB800_SMBUS_C_ -#define _SB800_SMBUS_C_ +#ifndef _SB800_SMBUS_C_ +#define _SB800_SMBUS_C_ #include "smbus.h"

1 0

Patch set updated for coreboot: 933e709 northbridge/intelsch/raminit.h: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6314 -gerrit commit 933e7096df6e8ac7a2a89a40d2bdeac23af54d6f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 22:53:06 2014 +0200 northbridge/intelsch/raminit.h: Remove a trailing whitespace Change-Id: Ic8d6007898a08ade9d6e5947cd368b7a0545928a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/sch/raminit.h | 148 ++++++++++++++++++------------------ 1 file changed, 74 insertions(+), 74 deletions(-) diff --git a/src/northbridge/intel/sch/raminit.h b/src/northbridge/intel/sch/raminit.h index 179b87d..f139490 100644 --- a/src/northbridge/intel/sch/raminit.h +++ b/src/northbridge/intel/sch/raminit.h @@ -25,51 +25,51 @@ **/ #define BIT(x) (1<<x) -#define EBP_TRP_MASK (BIT(1) | BIT(0)) -#define TRP_LOW 3h -#define TRP_HIGH 5h -#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/ -#define EBP_TRCD_MASK (BIT(3) | BIT(2)) -#define TRCD_LOW 3h -#define TRCD_HIGH 5h -#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/ -#define EBP_TCL_MASK (BIT(5) | BIT(4)) -#define TCL_LOW 3 /* Minimum supported CL*/ -#define TCL_HIGH 5 /* Maximum supported CL*/ -#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/ -#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/ -#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/ -#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/ -#define EBP_FREQ_MASK (BIT(10)| BIT(9)) -#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/ -#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/ -#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/ -#define EBP_REFRESH_MASK (BIT(12)| BIT(11)) -#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/ -#define EBP_REF_DIS 00h /* Mask for refresh disabled*/ -#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/ -#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/ -#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/ -#define EBP_WIDTH_MASK BIT(15) -#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/ -#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/ -#define EBP_DENSITY_MASK (BIT(17)| BIT(16)) -#define EBP_DENSITY_OFFSET 16 -#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/ -#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/ -#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/ -#define EBP_RANKS_MASK BIT(18) -#define EBP_RANKS_OFFSET 18 -#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/ -#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/ -#define EBP_2X_MASK BIT(20) -#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/ -#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/ -#define EBP_DRAM_PARM_MASK BIT(21) -#define EBP_DRAM_PARM_OFFSET 21 -#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/ -#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/ -#define EBP_BOOT_PATH BIT(31) +#define EBP_TRP_MASK (BIT(1) | BIT(0)) +#define TRP_LOW 3h +#define TRP_HIGH 5h +#define EBP_TRP_OFFSET 0 /* Start of TRP field in EBP*/ +#define EBP_TRCD_MASK (BIT(3) | BIT(2)) +#define TRCD_LOW 3h +#define TRCD_HIGH 5h +#define EBP_TRCD_OFFSET 2 /* Start of TRCD field in EBP*/ +#define EBP_TCL_MASK (BIT(5) | BIT(4)) +#define TCL_LOW 3 /* Minimum supported CL*/ +#define TCL_HIGH 5 /* Maximum supported CL*/ +#define EBP_TCL_OFFSET 4 /* EBP bit( )for CL mask*/ +#define EBP_DDR2_CL_5_0 BIT(5) /* CL 5.0 = 10b*/ +#define EBP_DDR2_CL_4_0 BIT(4) /* CL 4.0 = 01b*/ +#define EBP_DDR2_CL_3_0 00h /* CL 3.0 = 00b*/ +#define EBP_FREQ_MASK (BIT(10)| BIT(9)) +#define EBP_FREQ_OFFSET 9 /* EBP bit( )for frequency mask*/ +#define EBP_FREQ_400 0 /* 400MHz EBP[10:9] = 00b*/ +#define EBP_FREQ_533 BIT(9) /* 533MHz EBP[10:9] = 01b*/ +#define EBP_REFRESH_MASK (BIT(12)| BIT(11)) +#define EBP_REFRESH_OFFSET 11 /* Bit offset of refresh field*/ +#define EBP_REF_DIS 00h /* Mask for refresh disabled*/ +#define EBP_REF_128CLK BIT(11) /* Mask for 128 clks referesh rate*/ +#define EBP_REF_3_9 BIT(12) /* Mask for 3.9us refresh rate*/ +#define EBP_REF_7_8 (BIT(12)| BIT(11))/* Mask for 7.8us refresh rate*/ +#define EBP_WIDTH_MASK BIT(15) +#define EBP_WIDTH_OFFSET 15 /* Bit offset of EBP width field*/ +#define EBP_SOCKET_X16 BIT(15) /* Bit mask of x8/x16 bit*/ +#define EBP_DENSITY_MASK (BIT(17)| BIT(16)) +#define EBP_DENSITY_OFFSET 16 +#define EBP_DENSITY_512 BIT(16) /* 512Mbit density*/ +#define EBP_DENSITY_1024 BIT(17) /* 1024Mbit density*/ +#define EBP_DENSITY_2048 (BIT(17)| BIT(16))/* 2048Mbit density*/ +#define EBP_RANKS_MASK BIT(18) +#define EBP_RANKS_OFFSET 18 +#define EBP_RANKS BIT(18) /* Bit offset of # of ranks bit*/ +#define EBP_PACKAGE_TYPE BIT(19) /* Package type (stacked or not)*/ +#define EBP_2X_MASK BIT(20) +#define EBP_2X_OFFSET 20 /* Bit offset of ebp 2x refresh field*/ +#define EBP_2X_AUTO_REFRESH BIT(20) /* Bit mask of 2x refresh field*/ +#define EBP_DRAM_PARM_MASK BIT(21) +#define EBP_DRAM_PARM_OFFSET 21 +#define EBP_DRAM_PARM_SPD 0 /* Use SPD to get DRAM parameters*/ +#define EBP_DRAM_PARM_CMC BIT(21) /* DRAM parameters in CMC binary*/ +#define EBP_BOOT_PATH BIT(31) @@ -105,35 +105,35 @@ /* SCH Message Ports and Registers*/ -#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */ -#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */ -#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */ -#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */ -#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */ -#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */ -#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */ -#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */ -#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */ -#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */ -#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */ -#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */ -#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */ -#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */ -#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */ -#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */ -#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */ -#define DTR_TCL_OFFSET 4 /* CAS latency offset */ -#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */ -#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */ -#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */ -#define DCO_FIELDS 0xF /* Pertinent fields in DCO */ -#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */ -#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */ -#define DCO_IC BIT(7) /* Initialization complete bit */ -#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */ -#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */ -#define SCH_MSG_TEST_PORT 05h /* Test port */ -#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */ +#define SCH_MSG_DUNIT_PORT 0x1 /* DRAM unit port */ +#define SCH_MSG_DUNIT_REG_DRP 0x0 /* DRAM Rank Population and Interface */ +#define DRP_FIELDS 0xFF /* Pertinent fields in DRP */ +#define DRP_RANK0_OFFSET 3 /* Rank 0 enable offset */ +#define DRP_RANK1_OFFSET 7 /* Rank 1 enable offset */ +#define DRP_DENSITY0_OFFSET 1 /* Density offset - Rank 0 */ +#define DRP_DENSITY1_OFFSET 5 /* Density offset - Rank 1 */ +#define DRP_WIDTH0_OFFSET 0 /* Width offset - Rank 0 */ +#define DRP_WIDTH1_OFFSET 4 /* Width offset - Rank 1 */ +#define DRP_CKE_DIS (BIT(14)| BIT(13)) /* CKE disable bits for both ranks */ +#define DRP_CKE_DIS0 BIT(13) /* CKE disable bit - Rank 0 */ +#define DRP_CKE_DIS1 BIT(14) /* CKE disable bit - Rank 1 */ +#define DRP_SCK_DIS (BIT(11)| BIT(10)) /* SCK/SCKB disable bits */ +#define DRP_SCK_DIS1 BIT(11) /* SCK[1]/SCKB[1] disable */ +#define DRP_SCK_DIS0 BIT(10) /* SCK[0]/SCKB[0] disable */ +#define SCH_MSG_DUNIT_REG_DTR 0x01 /* DRAM Timing Register */ +#define DTR_FIELDS 0x3F /* Pertinent fields in DTR */ +#define DTR_TCL_OFFSET 4 /* CAS latency offset */ +#define DTR_TRCD_OFFSET 2 /* RAS CAS Delay Offset */ +#define DTR_TRP_OFFSET 0 /* RAS Precharge Delay Offset */ +#define SCH_MSG_DUNIT_REG_DCO 0x2 /* DRAM Control Register */ +#define DCO_FIELDS 0xF /* Pertinent fields in DCO */ +#define DCO_REFRESH_OFFSET 2 /* Refresh Rate Field Offset */ +#define DCO_FREQ_OFFSET 0 /* DRAM Frequency Field Offset */ +#define DCO_IC BIT(7) /* Initialization complete bit */ +#define SCH_MSG_PUNIT_PORT 04h /* Punit Port */ +#define SCH_MSG_PUNIT_REG_PCR 71h /* Punit Control Register */ +#define SCH_MSG_TEST_PORT 05h /* Test port */ +#define SCH_MSG_TEST_REG_MSR 03h /* Mode and Status Register */ /* Jedec initialization mapping into the MDR address field for DRAM init messages*/

1 0

New patch to review for coreboot: 34a665b broadcom/blast/devicetree.cb: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6346 -gerrit commit 34a665b5e8cd5a0bf4d1d9a7e93e96c77919f130 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 20:53:42 2014 +0200 broadcom/blast/devicetree.cb: Remove a trailing whitespace Change-Id: I76e54669a0e129adf6c7873585c62f692a5d509f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/broadcom/blast/devicetree.cb | 200 ++++++++++++++--------------- 1 file changed, 100 insertions(+), 100 deletions(-) diff --git a/src/mainboard/broadcom/blast/devicetree.cb b/src/mainboard/broadcom/blast/devicetree.cb index 326071b..9de4331 100644 --- a/src/mainboard/broadcom/blast/devicetree.cb +++ b/src/mainboard/broadcom/blast/devicetree.cb @@ -1,117 +1,117 @@ chip northbridge/amd/amdk8/root_complex - device cpu_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end + device cpu_cluster 0 on + chip cpu/amd/socket_940 + device lapic 0 on end + end + end device domain 0 on subsystemid 0x161f 0x3050 inherit chip northbridge/amd/amdk8 device pci 18.0 on # northbridge - # devices on link 0 - chip southbridge/broadcom/bcm5780 # HT2000 - device pci 0.0 on end # PXB 1 0x0130 - device pci 1.0 on # PXB 2 0x0130 - device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 - device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 - end - device pci 2.0 on end # PCI E 1 #0x0132 - device pci 3.0 on end # PCI E 2 - device pci 4.0 on end # PCI E 3 - device pci 5.0 on end # PCI E 4 - end - chip southbridge/broadcom/bcm5785 # HT1000 - device pci 0.0 on # HT PXB 0x0036 - device pci d.0 on end # PPBX 0x0104 - device pci e.0 on end # SATA 0x024a - end - device pci 1.0 on # Legacy pci main 0x0205 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 71 on end #0 pca9554 0 + # devices on link 0 + chip southbridge/broadcom/bcm5780 # HT2000 + device pci 0.0 on end # PXB 1 0x0130 + device pci 1.0 on # PXB 2 0x0130 + device pci 4.0 on end # GB E 0x1668 vid = 0x14e4 + device pci 4.1 on end # GB E 0x1669 vid = 0x14e4 + end + device pci 2.0 on end # PCI E 1 #0x0132 + device pci 3.0 on end # PCI E 2 + device pci 4.0 on end # PCI E 3 + device pci 5.0 on end # PCI E 4 + end + chip southbridge/broadcom/bcm5785 # HT1000 + device pci 0.0 on # HT PXB 0x0036 + device pci d.0 on end # PPBX 0x0104 + device pci e.0 on end # SATA 0x024a + end + device pci 1.0 on # Legacy pci main 0x0205 + chip drivers/i2c/i2cmux2 # pca9554 smbus mux + device i2c 71 on end #0 pca9554 0 device i2c 71 on end #0 pca9554 1 device i2c 71 on end #0 pca9554 2 device i2c 71 on end #0 pca9554 3 device i2c 71 on end #0 pca9554 4 device i2c 71 on end #0 pca9554 5 - device i2c 71 on #0 pca9554 6 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - end - device i2c 71 on #1 pca9554 7 - chip drivers/generic/generic #dimm 1-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 53 on end - end - end - end + device i2c 71 on #0 pca9554 6 + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end + device i2c 71 on #1 pca9554 7 + chip drivers/generic/generic #dimm 1-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 1-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 1-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 1-1-1 + device i2c 53 on end + end + end + end end - device pci 1.1 on end # IDE 0x0214 - device pci 1.2 on # LPC 0x0234 - chip superio/nsc/pc87417 - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 off # Com 2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Com 1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.4 off end # SWC - device pnp 2e.5 off end # Mouse - device pnp 2e.6 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.7 off end # GPIO - device pnp 2e.f off end # XBUS - device pnp 2e.10 on #RTC - io 0x60 = 0x70 - io 0x62 = 0x72 + device pci 1.1 on end # IDE 0x0214 + device pci 1.2 on # LPC 0x0234 + chip superio/nsc/pc87417 + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 end - end - end - device pci 1.3 on end # WDTimer 0x0238 - device pci 1.4 on end # XIOAPIC0 0x0235 - device pci 1.5 on end # XIOAPIC1 - device pci 1.6 on end # XIOAPIC2 - device pci 2.0 on end # USB 0x0223 - device pci 2.1 on end # USB - device pci 2.2 on end # USB - device pci 4.0 on end # it is in bcm5785_0 bus - end - end # device pci 18.0 + device pnp 2e.2 off # Com 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Com 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # SWC + device pnp 2e.5 off end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.7 off end # GPIO + device pnp 2e.f off end # XBUS + device pnp 2e.10 on #RTC + io 0x60 = 0x70 + io 0x62 = 0x72 + end + end + end + device pci 1.3 on end # WDTimer 0x0238 + device pci 1.4 on end # XIOAPIC0 0x0235 + device pci 1.5 on end # XIOAPIC1 + device pci 1.6 on end # XIOAPIC2 + device pci 2.0 on end # USB 0x0223 + device pci 2.1 on end # USB + device pci 2.2 on end # USB + device pci 4.0 on end # it is in bcm5785_0 bus + end + end # device pci 18.0 - device pci 18.0 on end - device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on end device pci 18.1 on end device pci 18.2 on end device pci 18.3 on end

1 0

New patch to review for coreboot: ffebe5f southbridge/via: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6345 -gerrit commit ffebe5f52a276c6525161c0641f55772a9b8e5a8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 20:01:10 2014 +0200 southbridge/via: Remove a trailing whitespace Change-Id: I28deda21a7070ea6f14f973b66fd5dd119bc6225 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/via/vt8235/early_smbus.c | 4 ++-- src/southbridge/via/vt8237r/vt8237r.h | 36 ++++++++++++++++---------------- 2 files changed, 20 insertions(+), 20 deletions(-) diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c index 96da2fa..0d484f3 100644 --- a/src/southbridge/via/vt8235/early_smbus.c +++ b/src/southbridge/via/vt8235/early_smbus.c @@ -21,8 +21,8 @@ #define SMBUS_TIMEOUT (100*1000*10) -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 static void enable_smbus(void) { diff --git a/src/southbridge/via/vt8237r/vt8237r.h b/src/southbridge/via/vt8237r/vt8237r.h index ee5cc82..1c50208 100644 --- a/src/southbridge/via/vt8237r/vt8237r.h +++ b/src/southbridge/via/vt8237r/vt8237r.h @@ -32,26 +32,26 @@ /* PMBASE FIXME mostly taken from ich7 */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14

1 0

New patch to review for coreboot: 54a4ced southbridge/intel/ibexpeak: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6344 -gerrit commit 54a4cedab8a3c71949b2e16936c0d8aa2da0b0a3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:56:48 2014 +0200 southbridge/intel/ibexpeak: Remove a trailing whitespace Change-Id: Ifdb3752c1bc3730f1ef6e63e203f56af6afd989c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/ibexpeak/me.h | 88 +++++++------- src/southbridge/intel/ibexpeak/pch.h | 224 +++++++++++++++++------------------ 2 files changed, 156 insertions(+), 156 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/me.h b/src/southbridge/intel/ibexpeak/me.h index 6e2062d..1bdb475 100644 --- a/src/southbridge/intel/ibexpeak/me.h +++ b/src/southbridge/intel/ibexpeak/me.h @@ -34,37 +34,37 @@ #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ #define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 struct me_hfs { u32 working_state: 4; @@ -93,10 +93,10 @@ struct me_uma { } __attribute__ ((packed)); #define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 struct me_did { u32 uma_base: 16; @@ -106,13 +106,13 @@ struct me_did { } __attribute__ ((packed)); #define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 struct me_gmes { u32 bist_in_prog : 1; @@ -132,8 +132,8 @@ struct me_gmes { } __attribute__ ((packed)); #define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) struct me_heres { diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index df125f0..a98d16f 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -96,9 +96,9 @@ void early_thermal_init(void); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -114,8 +114,8 @@ void early_thermal_init(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) @@ -124,7 +124,7 @@ void early_thermal_init(void); #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -141,16 +141,16 @@ void early_thermal_init(void); #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -162,48 +162,48 @@ void early_thermal_init(void); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -341,9 +341,9 @@ void early_thermal_init(void); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ @@ -443,31 +443,31 @@ void early_thermal_init(void); /* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -475,33 +475,33 @@ void early_thermal_init(void); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -510,7 +510,7 @@ void early_thermal_init(void); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 /* @@ -555,16 +555,16 @@ void early_thermal_init(void); #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ +#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */

1 0

New patch to review for coreboot: 1623baf southbridge/intel/i82801gx: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6343 -gerrit commit 1623bafc2053f9404e4848e9df6fa64866adfc6d Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:55:12 2014 +0200 southbridge/intel/i82801gx: Remove a trailing whitespace Change-Id: I96e507b30c47360a01b58f302e02eecfc21507a0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/i82801gx/ac97.c | 32 ++--- src/southbridge/intel/i82801gx/i82801gx.h | 176 ++++++++++++++-------------- src/southbridge/intel/i82801gx/smi.c | 10 +- src/southbridge/intel/i82801gx/smihandler.c | 10 +- 4 files changed, 114 insertions(+), 114 deletions(-) diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index 576ecce..76a5c84 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -27,28 +27,28 @@ #include "i82801gx.h" #define NAMBAR 0x10 -#define MASTER_VOL 0x02 -#define PAGING 0x24 -#define EXT_AUDIO 0x28 -#define FUNC_SEL 0x66 -#define INFO_IO 0x68 -#define CONNECTOR 0x6a -#define VENDOR_ID1 0x7c -#define VENDOR_ID2 0x7e -#define SEC_VENDOR_ID1 0xfc -#define SEC_VENDOR_ID2 0xfe +#define MASTER_VOL 0x02 +#define PAGING 0x24 +#define EXT_AUDIO 0x28 +#define FUNC_SEL 0x66 +#define INFO_IO 0x68 +#define CONNECTOR 0x6a +#define VENDOR_ID1 0x7c +#define VENDOR_ID2 0x7e +#define SEC_VENDOR_ID1 0xfc +#define SEC_VENDOR_ID2 0xfe #define NABMBAR 0x14 -#define GLOB_CNT 0x2c -#define GLOB_STA 0x30 -#define CAS 0x34 +#define GLOB_CNT 0x2c +#define GLOB_STA 0x30 +#define CAS 0x34 #define MMBAR 0x10 -#define EXT_MODEM_ID1 0x3c -#define EXT_MODEM_ID2 0xbc +#define EXT_MODEM_ID1 0x3c +#define EXT_MODEM_ID2 0xbc #define MBAR 0x14 -#define SEC_CODEC 0x40 +#define SEC_CODEC 0x40 /* FIXME. This table is probably mainboard specific */ diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 1064dde..451fb99 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -61,9 +61,9 @@ int smbus_read_byte(unsigned device, unsigned address); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) /* PCI Configuration Space (D31:F0): LPC */ @@ -80,7 +80,7 @@ int smbus_read_byte(unsigned device, unsigned address); #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -100,48 +100,48 @@ int smbus_read_byte(unsigned device, unsigned address); /* PCI Configuration Space (D31:F1): IDE */ #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 @@ -296,26 +296,26 @@ int smbus_read_byte(unsigned device, unsigned address); /* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -323,39 +323,39 @@ int smbus_read_byte(unsigned device, unsigned address); #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 -#define USB4_STS (1 << 14) -#define PME_B0_STS (1 << 13) -#define USB3_STS (1 << 12) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define AC97_STS (1 << 5) -#define USB2_STS (1 << 4) -#define USB1_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define THRM_STS (1 << 0) +#define USB4_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 8cb11b2..428d072 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -35,11 +35,11 @@ extern unsigned char _binary_smm_size; /* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index ba4d014..7410db4 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -31,11 +31,11 @@ /* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #include "nvs.h"

1 0

New patch to review for coreboot: 99d552c southbridge/intel/lynxpoint: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6342 -gerrit commit 99d552cf2085ff27e8d5405e0697d97823f03909 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:53:54 2014 +0200 southbridge/intel/lynxpoint: Remove a trailing whitespace Change-Id: If6fdfbcde9e5b6d3167f082b55cc0c6617c5d6a0 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/lynxpoint/hda_verb.h | 6 +- src/southbridge/intel/lynxpoint/me.h | 202 ++++++++--------- src/southbridge/intel/lynxpoint/pch.h | 338 ++++++++++++++--------------- 3 files changed, 273 insertions(+), 273 deletions(-) diff --git a/src/southbridge/intel/lynxpoint/hda_verb.h b/src/southbridge/intel/lynxpoint/hda_verb.h index 8b3d27e..b0e9d9f 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.h +++ b/src/southbridge/intel/lynxpoint/hda_verb.h @@ -22,13 +22,13 @@ #define HDA_GCAP_REG 0x00 #define HDA_GCTL_REG 0x08 -#define HDA_GCTL_CRST (1 << 0) +#define HDA_GCTL_CRST (1 << 0) #define HDA_STATESTS_REG 0x0e #define HDA_IC_REG 0x60 #define HDA_IR_REG 0x64 #define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) int hda_codec_detect(u32 base); int hda_codec_write(u32 base, u32 size, const u32 *data); diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h index a72778b..c63c866 100644 --- a/src/southbridge/intel/lynxpoint/me.h +++ b/src/southbridge/intel/lynxpoint/me.h @@ -34,37 +34,37 @@ #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ #define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 struct me_hfs { u32 working_state: 4; @@ -93,11 +93,11 @@ struct me_uma { } __attribute__ ((packed)); #define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 -#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 +#define ME_INIT_STATUS_SUCCESS_OTHER 3 /* SEE ME9 BWG */ struct me_did { u32 uma_base: 16; @@ -113,73 +113,73 @@ struct me_did { */ #define PCI_ME_HFS2 0x48 /* Infrastructure Progress Values */ -#define ME_HFS2_PHASE_ROM 0 -#define ME_HFS2_PHASE_BUP 1 -#define ME_HFS2_PHASE_UKERNEL 2 -#define ME_HFS2_PHASE_POLICY 3 -#define ME_HFS2_PHASE_MODULE_LOAD 4 -#define ME_HFS2_PHASE_UNKNOWN 5 -#define ME_HFS2_PHASE_HOST_COMM 6 +#define ME_HFS2_PHASE_ROM 0 +#define ME_HFS2_PHASE_BUP 1 +#define ME_HFS2_PHASE_UKERNEL 2 +#define ME_HFS2_PHASE_POLICY 3 +#define ME_HFS2_PHASE_MODULE_LOAD 4 +#define ME_HFS2_PHASE_UNKNOWN 5 +#define ME_HFS2_PHASE_HOST_COMM 6 /* Current State - Based on Infra Progress values. */ /* ROM State */ -#define ME_HFS2_STATE_ROM_BEGIN 0 -#define ME_HFS2_STATE_ROM_DISABLE 6 +#define ME_HFS2_STATE_ROM_BEGIN 0 +#define ME_HFS2_STATE_ROM_DISABLE 6 /* BUP State */ -#define ME_HFS2_STATE_BUP_INIT 0 -#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 -#define ME_HFS2_STATE_BUP_FLOW_DET 4 -#define ME_HFS2_STATE_BUP_VSCC_ERR 8 -#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa -#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb -#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd -#define ME_HFS2_STATE_BUP_M3 0x11 -#define ME_HFS2_STATE_BUP_M0 0x12 -#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 -#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 -#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 -#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 -#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c -#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f -#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 -#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 -#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 -#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 -#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 -#define ME_HFS2_STATE_BUP_M0_CLK 0x26 -#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 -#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 -#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 +#define ME_HFS2_STATE_BUP_INIT 0 +#define ME_HFS2_STATE_BUP_DIS_HOST_WAKE 1 +#define ME_HFS2_STATE_BUP_FLOW_DET 4 +#define ME_HFS2_STATE_BUP_VSCC_ERR 8 +#define ME_HFS2_STATE_BUP_CHECK_STRAP 0xa +#define ME_HFS2_STATE_BUP_PWR_OK_TIMEOUT 0xb +#define ME_HFS2_STATE_BUP_MANUF_OVRD_STRAP 0xd +#define ME_HFS2_STATE_BUP_M3 0x11 +#define ME_HFS2_STATE_BUP_M0 0x12 +#define ME_HFS2_STATE_BUP_FLOW_DET_ERR 0x13 +#define ME_HFS2_STATE_BUP_M3_CLK_ERR 0x15 +#define ME_HFS2_STATE_BUP_CPU_RESET_DID_TIMEOUT_MEM_MISSING 0x17 +#define ME_HFS2_STATE_BUP_M3_KERN_LOAD 0x18 +#define ME_HFS2_STATE_BUP_T32_MISSING 0x1c +#define ME_HFS2_STATE_BUP_WAIT_DID 0x1f +#define ME_HFS2_STATE_BUP_WAIT_DID_FAIL 0x20 +#define ME_HFS2_STATE_BUP_DID_NO_FAIL 0x21 +#define ME_HFS2_STATE_BUP_ENABLE_UMA 0x22 +#define ME_HFS2_STATE_BUP_ENABLE_UMA_ERR 0x23 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK 0x24 +#define ME_HFS2_STATE_BUP_SEND_DID_ACK_ERR 0x25 +#define ME_HFS2_STATE_BUP_M0_CLK 0x26 +#define ME_HFS2_STATE_BUP_M0_CLK_ERR 0x27 +#define ME_HFS2_STATE_BUP_TEMP_DIS 0x28 +#define ME_HFS2_STATE_BUP_M0_KERN_LOAD 0x32 /* Policy Module State */ -#define ME_HFS2_STATE_POLICY_ENTRY 0 -#define ME_HFS2_STATE_POLICY_RCVD_S3 3 -#define ME_HFS2_STATE_POLICY_RCVD_S4 4 -#define ME_HFS2_STATE_POLICY_RCVD_S5 5 -#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 -#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 -#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 -#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 -#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa -#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb -#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc -#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd -#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe -#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf -#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 +#define ME_HFS2_STATE_POLICY_ENTRY 0 +#define ME_HFS2_STATE_POLICY_RCVD_S3 3 +#define ME_HFS2_STATE_POLICY_RCVD_S4 4 +#define ME_HFS2_STATE_POLICY_RCVD_S5 5 +#define ME_HFS2_STATE_POLICY_RCVD_UPD 6 +#define ME_HFS2_STATE_POLICY_RCVD_PCR 7 +#define ME_HFS2_STATE_POLICY_RCVD_NPCR 8 +#define ME_HFS2_STATE_POLICY_RCVD_HOST_WAKE 9 +#define ME_HFS2_STATE_POLICY_RCVD_AC_DC 0xa +#define ME_HFS2_STATE_POLICY_RCVD_DID 0xb +#define ME_HFS2_STATE_POLICY_VSCC_NOT_FOUND 0xc +#define ME_HFS2_STATE_POLICY_VSCC_INVALID 0xd +#define ME_HFS2_STATE_POLICY_FPB_ERR 0xe +#define ME_HFS2_STATE_POLICY_DESCRIPTOR_ERR 0xf +#define ME_HFS2_STATE_POLICY_VSCC_NO_MATCH 0x10 /* Current PM Event Values */ -#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 -#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 -#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 -#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 -#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 -#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 -#define ME_HFS2_PMEVENT_S0MO_SXM3 7 -#define ME_HFS2_PMEVENT_SXM3_S0M0 8 -#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa -#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb -#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc +#define ME_HFS2_PMEVENT_CLEAN_MOFF_MX_WAKE 0 +#define ME_HFS2_PMEVENT_MOFF_MX_WAKE_ERROR 1 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET 2 +#define ME_HFS2_PMEVENT_CLEAN_GLOBAL_RESET_ERROR 3 +#define ME_HFS2_PMEVENT_CLEAN_ME_RESET 4 +#define ME_HFS2_PMEVENT_ME_RESET_EXCEPTION 5 +#define ME_HFS2_PMEVENT_PSEUDO_ME_RESET 6 +#define ME_HFS2_PMEVENT_S0MO_SXM3 7 +#define ME_HFS2_PMEVENT_SXM3_S0M0 8 +#define ME_HFS2_PMEVENT_NON_PWR_CYCLE_RESET 9 +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_M3 0xa +#define ME_HFS2_PMEVENT_PWR_CYCLE_RESET_MOFF 0xb +#define ME_HFS2_PMEVENT_SXMX_SXMOFF 0xc struct me_hfs2 { u32 bist_in_progress: 1; @@ -199,11 +199,11 @@ struct me_hfs2 { } __attribute__ ((packed)); #define PCI_ME_H_GS2 0x70 -#define PCI_ME_MBP_GIVE_UP 0x01 +#define PCI_ME_MBP_GIVE_UP 0x01 #define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) struct me_heres { diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9b5cb6f..2614126 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -98,13 +98,13 @@ void usb_xhci_route_all(void); /* State Machine configuration. */ #define RCBA_REG_SIZE_MASK 0x8000 -#define RCBA_REG_SIZE_16 0x8000 -#define RCBA_REG_SIZE_32 0x0000 +#define RCBA_REG_SIZE_16 0x8000 +#define RCBA_REG_SIZE_32 0x0000 #define RCBA_COMMAND_MASK 0x000f -#define RCBA_COMMAND_SET 0x0001 -#define RCBA_COMMAND_READ 0x0002 -#define RCBA_COMMAND_RMW 0x0003 -#define RCBA_COMMAND_END 0x0007 +#define RCBA_COMMAND_SET 0x0001 +#define RCBA_COMMAND_READ 0x0002 +#define RCBA_COMMAND_RMW 0x0003 +#define RCBA_COMMAND_END 0x0007 #define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \ { .command = command_, \ @@ -231,13 +231,13 @@ void pch_enable_lpc(void); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) /* Power Management Control and Status */ #define PCH_PCS 0x84 -#define PCH_PCS_PS_D3HOT 3 +#define PCH_PCS_PS_D3HOT 3 #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -253,8 +253,8 @@ void pch_enable_lpc(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define PMIR 0xac -#define PMIR_CF9LOCK (1 << 31) -#define PMIR_CF9GR (1 << 20) +#define PMIR_CF9LOCK (1 << 31) +#define PMIR_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) @@ -263,7 +263,7 @@ void pch_enable_lpc(void); #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -280,16 +280,16 @@ void pch_enable_lpc(void); #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -302,48 +302,48 @@ void pch_enable_lpc(void); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -363,62 +363,62 @@ void pch_enable_lpc(void); /* EHCI PCI Registers */ #define EHCI_PWR_CTL_STS 0x54 -#define PWR_CTL_SET_MASK 0x3 -#define PWR_CTL_SET_D0 0x0 -#define PWR_CTL_SET_D3 0x3 -#define PWR_CTL_ENABLE_PME (1 << 8) -#define PWR_CTL_STATUS_PME (1 << 15) +#define PWR_CTL_SET_MASK 0x3 +#define PWR_CTL_SET_D0 0x0 +#define PWR_CTL_SET_D3 0x3 +#define PWR_CTL_ENABLE_PME (1 << 8) +#define PWR_CTL_STATUS_PME (1 << 15) /* EHCI Memory Registers */ #define EHCI_USB_CMD 0x20 -#define EHCI_USB_CMD_RUN (1 << 0) -#define EHCI_USB_CMD_PSE (1 << 4) -#define EHCI_USB_CMD_ASE (1 << 5) +#define EHCI_USB_CMD_RUN (1 << 0) +#define EHCI_USB_CMD_PSE (1 << 4) +#define EHCI_USB_CMD_ASE (1 << 5) #define EHCI_PORTSC(port) (0x64 + (port * 4)) -#define EHCI_PORTSC_ENABLED (1 << 2) -#define EHCI_PORTSC_SUSPEND (1 << 7) +#define EHCI_PORTSC_ENABLED (1 << 2) +#define EHCI_PORTSC_SUSPEND (1 << 7) /* XHCI PCI Registers */ #define XHCI_PWR_CTL_STS 0x74 #define XHCI_USB2PR 0xd0 #define XHCI_USB2PRM 0xd4 -#define XHCI_USB2PR_HCSEL 0x7fff +#define XHCI_USB2PR_HCSEL 0x7fff #define XHCI_USB3PR 0xd8 -#define XHCI_USB3PR_SSEN 0x3f +#define XHCI_USB3PR_SSEN 0x3f #define XHCI_USB3PRM 0xdc #define XHCI_USB3FUS 0xe0 -#define XHCI_USB3FUS_SS_MASK 3 -#define XHCI_USB3FUS_SS_SHIFT 3 +#define XHCI_USB3FUS_SS_MASK 3 +#define XHCI_USB3FUS_SS_SHIFT 3 #define XHCI_USB3PDO 0xe8 /* XHCI Memory Registers */ #define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + (port * 0x10)) -#define XHCI_USB3_PORTSC_CHST (0x7f << 17) -#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ -#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ -#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ -#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ -#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ -#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ +#define XHCI_USB3_PORTSC_CHST (0x7f << 17) +#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ +#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ +#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ +#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ +#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ +#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ +#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ +#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ +#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ +#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ +#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ +#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ /* Serial IO IOBP Registers */ #define SIO_IOBP_PORTCTRL0 0xcb000000 /* SDIO D23:F0 */ -#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5) -#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4) +#define SIO_IOBP_PORTCTRL0_ACPI_IRQ_EN (1 << 5) +#define SIO_IOBP_PORTCTRL0_PCI_CONF_DIS (1 << 4) #define SIO_IOBP_PORTCTRL1 0xcb000014 /* SDIO D23:F0 */ -#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13) +#define SIO_IOBP_PORTCTRL1_SNOOP_SELECT(x) (((x) & 3) << 13) #define SIO_IOBP_GPIODF 0xcb000154 -#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4) -#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3) -#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2) -#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1) -#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0) +#define SIO_IOBP_GPIODF_SDIO_IDLE_DET_EN (1 << 4) +#define SIO_IOBP_GPIODF_DMA_IDLE_DET_EN (1 << 3) +#define SIO_IOBP_GPIODF_UART_IDLE_DET_EN (1 << 2) +#define SIO_IOBP_GPIODF_I2C_IDLE_DET_EN (1 << 1) +#define SIO_IOBP_GPIODF_SPI_IDLE_DET_EN (1 << 0) #define SIO_IOBP_PORTCTRL2 0xcb000240 /* DMA D21:F0 */ #define SIO_IOBP_PORTCTRL3 0xcb000248 /* I2C0 D21:F1 */ #define SIO_IOBP_PORTCTRL4 0xcb000250 /* I2C1 D21:F2 */ @@ -428,11 +428,11 @@ void pch_enable_lpc(void); #define SIO_IOBP_PORTCTRL8 0xcb000270 /* UART1 D21:F6 */ #define SIO_IOBP_PORTCTRLX(x) (0xcb000240 + ((x) * 8)) /* PORTCTRL 2-8 have the same layout */ -#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21) -#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20) -#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18) -#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2) -#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1) +#define SIO_IOBP_PORTCTRL_ACPI_IRQ_EN (1 << 21) +#define SIO_IOBP_PORTCTRL_PCI_CONF_DIS (1 << 20) +#define SIO_IOBP_PORTCTRL_SNOOP_SELECT(x) (((x) & 3) << 18) +#define SIO_IOBP_PORTCTRL_INT_PIN(x) (((x) & 0xf) << 2) +#define SIO_IOBP_PORTCTRL_PM_CAP_PRSNT (1 << 1) #define SIO_IOBP_FUNCDIS0 0xce00aa07 /* DMA D21:F0 */ #define SIO_IOBP_FUNCDIS1 0xce00aa47 /* I2C0 D21:F1 */ #define SIO_IOBP_FUNCDIS2 0xce00aa87 /* I2C1 D21:F2 */ @@ -441,7 +441,7 @@ void pch_enable_lpc(void); #define SIO_IOBP_FUNCDIS5 0xce00ab47 /* UART0 D21:F5 */ #define SIO_IOBP_FUNCDIS6 0xce00ab87 /* UART1 D21:F6 */ #define SIO_IOBP_FUNCDIS7 0xce00ae07 /* SDIO D23:F0 */ -#define SIO_IOBP_FUNCDIS_DIS (1 << 8) +#define SIO_IOBP_FUNCDIS_DIS (1 << 8) /* Serial IO Devices */ #define SIO_ID_SDMA 0 /* D21:F0 */ @@ -454,19 +454,19 @@ void pch_enable_lpc(void); #define SIO_ID_SDIO 7 /* D23:F0 */ #define SIO_REG_PPR_CLOCK 0x800 -#define SIO_REG_PPR_CLOCK_EN (1 << 0) +#define SIO_REG_PPR_CLOCK_EN (1 << 0) #define SIO_REG_PPR_RST 0x804 -#define SIO_REG_PPR_RST_ASSERT 0x3 +#define SIO_REG_PPR_RST_ASSERT 0x3 #define SIO_REG_PPR_GEN 0x808 -#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2) -#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3) -#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3) +#define SIO_REG_PPR_GEN_LTR_MODE_MASK (1 << 2) +#define SIO_REG_PPR_GEN_VOLTAGE_MASK (1 << 3) +#define SIO_REG_PPR_GEN_VOLTAGE(x) ((x & 1) << 3) #define SIO_REG_AUTO_LTR 0x814 #define SIO_REG_SDIO_PPR_GEN 0x1008 #define SIO_REG_SDIO_PPR_SW_LTR 0x1010 #define SIO_REG_SDIO_PPR_CMD12 0x3c -#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30) +#define SIO_REG_SDIO_PPR_CMD12_B30 (1 << 30) #define SIO_PIN_INTA 1 /* IRQ5 in ACPI mode */ #define SIO_PIN_INTB 2 /* IRQ6 in ACPI mode */ @@ -601,13 +601,13 @@ void pch_enable_lpc(void); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_READY 0x0001 -#define IOBPS_TX_MASK 0x0006 -#define IOBPS_MASK 0xff00 -#define IOBPS_READ 0x0600 -#define IOBPS_WRITE 0x0700 +#define IOBPS_READY 0x0001 +#define IOBPS_TX_MASK 0x0006 +#define IOBPS_MASK 0xff00 +#define IOBPS_READ 0x0600 +#define IOBPS_WRITE 0x0700 #define IOBPU 0x233a -#define IOBPU_MAGIC 0xf000 +#define IOBPU_MAGIC 0xf000 #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ @@ -696,31 +696,31 @@ void pch_enable_lpc(void); /* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -728,35 +728,35 @@ void pch_enable_lpc(void); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_STS_2 0x24 #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define GPE0_EN_2 0x2c #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -765,7 +765,7 @@ void pch_enable_lpc(void); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 #define ALT_GP_SMI_EN2 0x5c #define ALT_GP_SMI_STS2 0x5e @@ -832,16 +832,16 @@ void pch_enable_lpc(void); #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ +#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */

1 0

New patch to review for coreboot: 344d514 southbridge/intel/bd82x6x: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6341 -gerrit commit 344d5144e3c996f77cd52f15f0acdea2dbcf7ea6 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:52:22 2014 +0200 southbridge/intel/bd82x6x: Remove a trailing whitespace Change-Id: Ica8259c75645d43a5f947e4a3c31071898e9b550 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/bd82x6x/me.h | 88 +++++++------- src/southbridge/intel/bd82x6x/pch.h | 224 ++++++++++++++++++------------------ 2 files changed, 156 insertions(+), 156 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index aaeb24d..c16951f 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -34,37 +34,37 @@ #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ #define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 struct me_hfs { u32 working_state: 4; @@ -93,10 +93,10 @@ struct me_uma { } __attribute__ ((packed)); #define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 struct me_did { u32 uma_base: 16; @@ -106,13 +106,13 @@ struct me_did { } __attribute__ ((packed)); #define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 struct me_gmes { u32 bist_in_prog : 1; @@ -132,8 +132,8 @@ struct me_gmes { } __attribute__ ((packed)); #define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) struct me_heres { diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 90de855..86b36cd 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -91,9 +91,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -109,8 +109,8 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) @@ -119,7 +119,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 7) +#define ACPI_EN (1 << 7) #define BIOS_CNTL 0xDC #define GPIO_BASE 0x48 /* LPC GPIO Base Address Register */ #define GPIO_CNTL 0x4C /* LPC GPIO Control Register */ @@ -136,16 +136,16 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -157,48 +157,48 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -336,9 +336,9 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ @@ -437,31 +437,31 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); /* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -469,33 +469,33 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -504,7 +504,7 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 /* @@ -549,16 +549,16 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer); #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ +#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */

1 0

← Newer
1
...
27
28
29
30
31
32
33
...
87
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2014