coreboot-gerrit July 2014

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New patch to review for coreboot: b2fbf63 southbridge/intel/i82801dx: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6340 -gerrit commit b2fbf63e12a621976625230877286573a91e01e1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:51:08 2014 +0200 southbridge/intel/i82801dx: Remove a trailing whitespace Change-Id: Id0aedcbd72c31d96c0dd72acf1943a42b7a84c88 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/i82801dx/ac97.c | 32 ++++----- src/southbridge/intel/i82801dx/i82801dx.h | 104 ++++++++++++++-------------- src/southbridge/intel/i82801dx/smi.c | 10 +-- src/southbridge/intel/i82801dx/smihandler.c | 10 +-- 4 files changed, 78 insertions(+), 78 deletions(-) diff --git a/src/southbridge/intel/i82801dx/ac97.c b/src/southbridge/intel/i82801dx/ac97.c index a9ec266..c7fb183 100644 --- a/src/southbridge/intel/i82801dx/ac97.c +++ b/src/southbridge/intel/i82801dx/ac97.c @@ -27,28 +27,28 @@ #include "i82801dx.h" #define NAMBAR 0x10 -#define MASTER_VOL 0x02 -#define PAGING 0x24 -#define EXT_AUDIO 0x28 -#define FUNC_SEL 0x66 -#define INFO_IO 0x68 -#define CONNECTOR 0x6a -#define VENDOR_ID1 0x7c -#define VENDOR_ID2 0x7e -#define SEC_VENDOR_ID1 0xfc -#define SEC_VENDOR_ID2 0xfe +#define MASTER_VOL 0x02 +#define PAGING 0x24 +#define EXT_AUDIO 0x28 +#define FUNC_SEL 0x66 +#define INFO_IO 0x68 +#define CONNECTOR 0x6a +#define VENDOR_ID1 0x7c +#define VENDOR_ID2 0x7e +#define SEC_VENDOR_ID1 0xfc +#define SEC_VENDOR_ID2 0xfe #define NABMBAR 0x14 -#define GLOB_CNT 0x2c -#define GLOB_STA 0x30 -#define CAS 0x34 +#define GLOB_CNT 0x2c +#define GLOB_STA 0x30 +#define CAS 0x34 #define MMBAR 0x10 -#define EXT_MODEM_ID1 0x3c -#define EXT_MODEM_ID2 0xbc +#define EXT_MODEM_ID1 0x3c +#define EXT_MODEM_ID2 0xbc #define MBAR 0x14 -#define SEC_CODEC 0x40 +#define SEC_CODEC 0x40 /* FIXME. This table is probably mainboard specific */ diff --git a/src/southbridge/intel/i82801dx/i82801dx.h b/src/southbridge/intel/i82801dx/i82801dx.h index c7d7e77..844104d 100644 --- a/src/southbridge/intel/i82801dx/i82801dx.h +++ b/src/southbridge/intel/i82801dx/i82801dx.h @@ -79,14 +79,14 @@ int smbus_read_byte(unsigned device, unsigned address); #define PCICMD 0x04 #define PMBASE 0x40 -#define PMBASE_ADDR 0x0400 -#define DEFAULT_PMBASE PMBASE_ADDR +#define PMBASE_ADDR 0x0400 +#define DEFAULT_PMBASE PMBASE_ADDR #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 4) +#define ACPI_EN (1 << 4) #define BIOS_CNTL 0x4E #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C -#define GPIOBASE_ADDR 0x0500 +#define GPIOBASE_ADDR 0x0500 #define PIRQA_ROUT 0x60 #define PIRQB_ROUT 0x61 #define PIRQC_ROUT 0x62 @@ -136,26 +136,26 @@ int smbus_read_byte(unsigned device, unsigned address); #define SMBUS_TIMEOUT (100*1000) #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -163,38 +163,38 @@ int smbus_read_byte(unsigned device, unsigned address); #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 -#define PME_B0_STS (1 << 13) -#define USB3_STS (1 << 12) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define GST_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define AC97_STS (1 << 5) -#define USB2_STS (1 << 4) -#define USB1_STS (1 << 3) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) -#define THRM_STS (1 << 0) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define GST_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801dx/smi.c b/src/southbridge/intel/i82801dx/smi.c index d2e3e25..72a0eac 100644 --- a/src/southbridge/intel/i82801dx/smi.c +++ b/src/southbridge/intel/i82801dx/smi.c @@ -35,11 +35,11 @@ extern unsigned char _binary_smm_size; /* I945 */ #define SMRAM 0x90 -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/i82801dx/smihandler.c b/src/southbridge/intel/i82801dx/smihandler.c index 9b0c235..ac05816 100644 --- a/src/southbridge/intel/i82801dx/smihandler.c +++ b/src/southbridge/intel/i82801dx/smihandler.c @@ -31,11 +31,11 @@ /* I830M */ #define SMRAM 0x90 -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #include "nvs.h"

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New patch to review for coreboot: bb6c350 southbridge/intel/i82801ix: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6339 -gerrit commit bb6c3500fcaea8564df93c2c6c70464fd852fca4 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:49:26 2014 +0200 southbridge/intel/i82801ix: Remove a trailing whitespace Change-Id: Ia4d5ec28764da74200e7643a6e9f245b9712e8d7 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/i82801ix/i82801ix.h | 22 +++++++++++----------- src/southbridge/intel/i82801ix/smi.c | 10 +++++----- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index d84af3a..7fd71be 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -46,13 +46,13 @@ #define APM_CNT 0xb2 #define PM1_STS 0x00 -#define PWRBTN_STS (1 << 8) -#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) #define PM1_EN 0x02 -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) #define PM1_CNT 0x04 -#define SCI_EN (1 << 0) +#define SCI_EN (1 << 0) #define PM_LV2 0x14 #define PM_LV3 0x15 #define PM_LV4 0x16 @@ -60,12 +60,12 @@ #define PM_LV6 0x18 #define GPE0_STS 0x20 #define SMI_EN 0x30 -#define PERIODIC_EN (1 << 14) -#define TCO_EN (1 << 13) -#define APMC_EN (1 << 5) -#define BIOS_EN (1 << 2) -#define EOS (1 << 1) -#define GBL_SMI_EN (1 << 0) +#define PERIODIC_EN (1 << 14) +#define TCO_EN (1 << 13) +#define APMC_EN (1 << 5) +#define BIOS_EN (1 << 2) +#define EOS (1 << 1) +#define GBL_SMI_EN (1 << 0) #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index de9931c..3b4ba1c 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -36,11 +36,11 @@ extern unsigned char _binary_smm_size; /* I945/GM45 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value

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New patch to review for coreboot: ae374a6 southbridge/intel/i82801ex: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6338 -gerrit commit ae374a619b4b26f7df18ccde30b4d8c04e318be5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:47:50 2014 +0200 southbridge/intel/i82801ex: Remove a trailing whitespace Change-Id: Ia69d971bfad2639dcfb196f9ff5978d54c474010 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/i82801ex/i82801ex.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/southbridge/intel/i82801ex/i82801ex.h b/src/southbridge/intel/i82801ex/i82801ex.h index 3c7321a..a3ea368 100644 --- a/src/southbridge/intel/i82801ex/i82801ex.h +++ b/src/southbridge/intel/i82801ex/i82801ex.h @@ -14,9 +14,9 @@ extern void i82801ex_enable(device_t dev); #define PMBASE 0x40 #define ACPI_CNTL 0x44 -#define ACPI_EN (1 << 4) +#define ACPI_EN (1 << 4) #define GPIO_BASE 0x58 #define GPIO_CNTL 0x5C -#define GPIO_EN (1 << 4) +#define GPIO_EN (1 << 4) #endif /* I82801EX_H */

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New patch to review for coreboot: aa92964 southbridge/intel/sch: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6337 -gerrit commit aa929643a21d85daf13ea6a092d7fba3adbe2848 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:27:02 2014 +0200 southbridge/intel/sch: Remove a trailing whitespace Change-Id: Ia67a4348ec540010d5c2db19657eb244fc5d763a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/sch/smi.c | 38 +++++++++++++++++----------------- src/southbridge/intel/sch/smihandler.c | 38 +++++++++++++++++----------------- 2 files changed, 38 insertions(+), 38 deletions(-) diff --git a/src/southbridge/intel/sch/smi.c b/src/southbridge/intel/sch/smi.c index 08733a7..9d72039 100644 --- a/src/southbridge/intel/sch/smi.c +++ b/src/southbridge/intel/sch/smi.c @@ -33,11 +33,11 @@ extern unsigned char _binary_smm_size; /* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRAME (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) /* ICH7 */ #define PM1_STS 0x00 @@ -52,20 +52,20 @@ extern unsigned char _binary_smm_size; #define GPE0_STS 0x28 #define GPE0_EN 0x2c #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a diff --git a/src/southbridge/intel/sch/smihandler.c b/src/southbridge/intel/sch/smihandler.c index 5074138..5286e89 100644 --- a/src/southbridge/intel/sch/smihandler.c +++ b/src/southbridge/intel/sch/smihandler.c @@ -29,11 +29,11 @@ /* I945 */ #define SMRAM 0x9d -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRANE (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) +#define D_OPEN (1 << 6) +#define D_CLS (1 << 5) +#define D_LCK (1 << 4) +#define G_SMRANE (1 << 3) +#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) /* ICH7 */ #define PM1_STS 0x00 @@ -48,20 +48,20 @@ #define GPE0_STS 0x28 #define GPE0_EN 0x2c #define SMI_EN 0x30 -#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a

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New patch to review for coreboot: d848582 southbridge/intel/fsp_bd82x6x: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6336 -gerrit commit d8485826ac481453cd9f6abab1b95f930e0fa93d Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:22:29 2014 +0200 southbridge/intel/fsp_bd82x6x: Remove a trailing whitespace Change-Id: I638edd16a277809e2f5d70f1e99610ba0a8b0f34 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/fsp_bd82x6x/azalia.c | 4 +- src/southbridge/intel/fsp_bd82x6x/me.h | 88 ++++++------ src/southbridge/intel/fsp_bd82x6x/pch.h | 222 ++++++++++++++--------------- 3 files changed, 157 insertions(+), 157 deletions(-) diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index 7a280c5..ad923c2 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -29,8 +29,8 @@ #include "pch.h" #define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) +#define HDA_ICII_BUSY (1 << 0) +#define HDA_ICII_VALID (1 << 1) typedef struct southbridge_intel_bd82x6x_config config_t; diff --git a/src/southbridge/intel/fsp_bd82x6x/me.h b/src/southbridge/intel/fsp_bd82x6x/me.h index aaeb24d..c16951f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.h +++ b/src/southbridge/intel/fsp_bd82x6x/me.h @@ -34,37 +34,37 @@ #define PCI_CPU_MEBASE_H 0x74 /* Set by MRC */ #define PCI_ME_HFS 0x40 -#define ME_HFS_CWS_RESET 0 -#define ME_HFS_CWS_INIT 1 -#define ME_HFS_CWS_REC 2 -#define ME_HFS_CWS_NORMAL 5 -#define ME_HFS_CWS_WAIT 6 -#define ME_HFS_CWS_TRANS 7 -#define ME_HFS_CWS_INVALID 8 -#define ME_HFS_STATE_PREBOOT 0 -#define ME_HFS_STATE_M0_UMA 1 -#define ME_HFS_STATE_M3 4 -#define ME_HFS_STATE_M0 5 -#define ME_HFS_STATE_BRINGUP 6 -#define ME_HFS_STATE_ERROR 7 -#define ME_HFS_ERROR_NONE 0 -#define ME_HFS_ERROR_UNCAT 1 -#define ME_HFS_ERROR_IMAGE 3 -#define ME_HFS_ERROR_DEBUG 4 -#define ME_HFS_MODE_NORMAL 0 -#define ME_HFS_MODE_DEBUG 2 -#define ME_HFS_MODE_DIS 3 -#define ME_HFS_MODE_OVER_JMPR 4 -#define ME_HFS_MODE_OVER_MEI 5 -#define ME_HFS_BIOS_DRAM_ACK 1 -#define ME_HFS_ACK_NO_DID 0 -#define ME_HFS_ACK_RESET 1 -#define ME_HFS_ACK_PWR_CYCLE 2 -#define ME_HFS_ACK_S3 3 -#define ME_HFS_ACK_S4 4 -#define ME_HFS_ACK_S5 5 -#define ME_HFS_ACK_GBL_RESET 6 -#define ME_HFS_ACK_CONTINUE 7 +#define ME_HFS_CWS_RESET 0 +#define ME_HFS_CWS_INIT 1 +#define ME_HFS_CWS_REC 2 +#define ME_HFS_CWS_NORMAL 5 +#define ME_HFS_CWS_WAIT 6 +#define ME_HFS_CWS_TRANS 7 +#define ME_HFS_CWS_INVALID 8 +#define ME_HFS_STATE_PREBOOT 0 +#define ME_HFS_STATE_M0_UMA 1 +#define ME_HFS_STATE_M3 4 +#define ME_HFS_STATE_M0 5 +#define ME_HFS_STATE_BRINGUP 6 +#define ME_HFS_STATE_ERROR 7 +#define ME_HFS_ERROR_NONE 0 +#define ME_HFS_ERROR_UNCAT 1 +#define ME_HFS_ERROR_IMAGE 3 +#define ME_HFS_ERROR_DEBUG 4 +#define ME_HFS_MODE_NORMAL 0 +#define ME_HFS_MODE_DEBUG 2 +#define ME_HFS_MODE_DIS 3 +#define ME_HFS_MODE_OVER_JMPR 4 +#define ME_HFS_MODE_OVER_MEI 5 +#define ME_HFS_BIOS_DRAM_ACK 1 +#define ME_HFS_ACK_NO_DID 0 +#define ME_HFS_ACK_RESET 1 +#define ME_HFS_ACK_PWR_CYCLE 2 +#define ME_HFS_ACK_S3 3 +#define ME_HFS_ACK_S4 4 +#define ME_HFS_ACK_S5 5 +#define ME_HFS_ACK_GBL_RESET 6 +#define ME_HFS_ACK_CONTINUE 7 struct me_hfs { u32 working_state: 4; @@ -93,10 +93,10 @@ struct me_uma { } __attribute__ ((packed)); #define PCI_ME_H_GS 0x4c -#define ME_INIT_DONE 1 -#define ME_INIT_STATUS_SUCCESS 0 -#define ME_INIT_STATUS_NOMEM 1 -#define ME_INIT_STATUS_ERROR 2 +#define ME_INIT_DONE 1 +#define ME_INIT_STATUS_SUCCESS 0 +#define ME_INIT_STATUS_NOMEM 1 +#define ME_INIT_STATUS_ERROR 2 struct me_did { u32 uma_base: 16; @@ -106,13 +106,13 @@ struct me_did { } __attribute__ ((packed)); #define PCI_ME_GMES 0x48 -#define ME_GMES_PHASE_ROM 0 -#define ME_GMES_PHASE_BUP 1 -#define ME_GMES_PHASE_UKERNEL 2 -#define ME_GMES_PHASE_POLICY 3 -#define ME_GMES_PHASE_MODULE 4 -#define ME_GMES_PHASE_UNKNOWN 5 -#define ME_GMES_PHASE_HOST 6 +#define ME_GMES_PHASE_ROM 0 +#define ME_GMES_PHASE_BUP 1 +#define ME_GMES_PHASE_UKERNEL 2 +#define ME_GMES_PHASE_POLICY 3 +#define ME_GMES_PHASE_MODULE 4 +#define ME_GMES_PHASE_UNKNOWN 5 +#define ME_GMES_PHASE_HOST 6 struct me_gmes { u32 bist_in_prog : 1; @@ -132,8 +132,8 @@ struct me_gmes { } __attribute__ ((packed)); #define PCI_ME_HERES 0xbc -#define PCI_ME_EXT_SHA1 0x00 -#define PCI_ME_EXT_SHA256 0x02 +#define PCI_ME_EXT_SHA1 0x00 +#define PCI_ME_EXT_SHA256 0x02 #define PCI_ME_HER(x) (0xc0+(4*(x))) struct me_heres { diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index a06ca74..ed72701 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -104,9 +104,9 @@ void display_fd_settings(void); #define SECSTS 0x1e #define INTR 0x3c #define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) +#define SBR (1 << 6) +#define SEE (1 << 1) +#define PERE (1 << 0) #define PCH_EHCI1_DEV PCI_DEV(0, 0x1d, 0) #define PCH_EHCI2_DEV PCI_DEV(0, 0x1a, 0) @@ -121,8 +121,8 @@ void display_fd_settings(void); #define GEN_PMCON_2 0xa2 #define GEN_PMCON_3 0xa4 #define ETR3 0xac -#define ETR3_CWORWRE (1 << 18) -#define ETR3_CF9GR (1 << 20) +#define ETR3_CWORWRE (1 << 18) +#define ETR3_CF9GR (1 << 20) /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) @@ -147,16 +147,16 @@ void display_fd_settings(void); #define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ #define LPC_EN 0x82 /* LPC IF Enables Register */ -#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ -#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ -#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ -#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ -#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ -#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ -#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ -#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ -#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ -#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */ #define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ #define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ @@ -168,48 +168,48 @@ void display_fd_settings(void); #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ -#define IDE_DECODE_ENABLE (1 << 15) -#define IDE_SITRE (1 << 14) -#define IDE_ISP_5_CLOCKS (0 << 12) -#define IDE_ISP_4_CLOCKS (1 << 12) -#define IDE_ISP_3_CLOCKS (2 << 12) -#define IDE_RCT_4_CLOCKS (0 << 8) -#define IDE_RCT_3_CLOCKS (1 << 8) -#define IDE_RCT_2_CLOCKS (2 << 8) -#define IDE_RCT_1_CLOCKS (3 << 8) -#define IDE_DTE1 (1 << 7) -#define IDE_PPE1 (1 << 6) -#define IDE_IE1 (1 << 5) -#define IDE_TIME1 (1 << 4) -#define IDE_DTE0 (1 << 3) -#define IDE_PPE0 (1 << 2) -#define IDE_IE0 (1 << 1) -#define IDE_TIME0 (1 << 0) +#define IDE_DECODE_ENABLE (1 << 15) +#define IDE_SITRE (1 << 14) +#define IDE_ISP_5_CLOCKS (0 << 12) +#define IDE_ISP_4_CLOCKS (1 << 12) +#define IDE_ISP_3_CLOCKS (2 << 12) +#define IDE_RCT_4_CLOCKS (0 << 8) +#define IDE_RCT_3_CLOCKS (1 << 8) +#define IDE_RCT_2_CLOCKS (2 << 8) +#define IDE_RCT_1_CLOCKS (3 << 8) +#define IDE_DTE1 (1 << 7) +#define IDE_PPE1 (1 << 6) +#define IDE_IE1 (1 << 5) +#define IDE_TIME1 (1 << 4) +#define IDE_DTE0 (1 << 3) +#define IDE_PPE0 (1 << 2) +#define IDE_IE0 (1 << 1) +#define IDE_TIME0 (1 << 0) #define IDE_TIM_SEC 0x42 /* IDE timings, secondary */ #define IDE_SDMA_CNT 0x48 /* Synchronous DMA control */ -#define IDE_SSDE1 (1 << 3) -#define IDE_SSDE0 (1 << 2) -#define IDE_PSDE1 (1 << 1) -#define IDE_PSDE0 (1 << 0) +#define IDE_SSDE1 (1 << 3) +#define IDE_SSDE0 (1 << 2) +#define IDE_PSDE1 (1 << 1) +#define IDE_PSDE0 (1 << 0) #define IDE_SDMA_TIM 0x4a #define IDE_CONFIG 0x54 /* IDE I/O Configuration Register */ -#define SIG_MODE_SEC_NORMAL (0 << 18) -#define SIG_MODE_SEC_TRISTATE (1 << 18) -#define SIG_MODE_SEC_DRIVELOW (2 << 18) -#define SIG_MODE_PRI_NORMAL (0 << 16) -#define SIG_MODE_PRI_TRISTATE (1 << 16) -#define SIG_MODE_PRI_DRIVELOW (2 << 16) -#define FAST_SCB1 (1 << 15) -#define FAST_SCB0 (1 << 14) -#define FAST_PCB1 (1 << 13) -#define FAST_PCB0 (1 << 12) -#define SCB1 (1 << 3) -#define SCB0 (1 << 2) -#define PCB1 (1 << 1) -#define PCB0 (1 << 0) +#define SIG_MODE_SEC_NORMAL (0 << 18) +#define SIG_MODE_SEC_TRISTATE (1 << 18) +#define SIG_MODE_SEC_DRIVELOW (2 << 18) +#define SIG_MODE_PRI_NORMAL (0 << 16) +#define SIG_MODE_PRI_TRISTATE (1 << 16) +#define SIG_MODE_PRI_DRIVELOW (2 << 16) +#define FAST_SCB1 (1 << 15) +#define FAST_SCB0 (1 << 14) +#define FAST_PCB1 (1 << 13) +#define FAST_PCB0 (1 << 12) +#define SCB1 (1 << 3) +#define SCB0 (1 << 2) +#define PCB1 (1 << 1) +#define PCB0 (1 << 0) #define SATA_SIRI 0xa0 /* SATA Indexed Register Index */ #define SATA_SIRD 0xa4 /* SATA Indexed Register Data */ @@ -356,9 +356,9 @@ void display_fd_settings(void); #define IOBPIRI 0x2330 #define IOBPD 0x2334 #define IOBPS 0x2338 -#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) -#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) -#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) +#define IOBPS_RW_BX ((1 << 9)|(1 << 10)) +#define IOBPS_WRITE_AX ((1 << 9)|(1 << 10)) +#define IOBPS_READ_AX ((1 << 8)|(1 << 9)|(1 << 10)) #define D31IP 0x3100 /* 32bit */ #define D31IP_TTIP 24 /* Thermal Throttle Pin */ @@ -456,31 +456,31 @@ void display_fd_settings(void); /* ICH7 PMBASE */ #define PM1_STS 0x00 -#define WAK_STS (1 << 15) -#define PCIEXPWAK_STS (1 << 14) -#define PRBTNOR_STS (1 << 11) -#define RTC_STS (1 << 10) -#define PWRBTN_STS (1 << 8) -#define GBL_STS (1 << 5) -#define BM_STS (1 << 4) -#define TMROF_STS (1 << 0) +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 -#define PCIEXPWAK_DIS (1 << 14) -#define RTC_EN (1 << 10) -#define PWRBTN_EN (1 << 8) -#define GBL_EN (1 << 5) -#define TMROF_EN (1 << 0) +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 -#define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) -#define SLP_TYP_S0 0 -#define SLP_TYP_S1 1 -#define SLP_TYP_S3 5 -#define SLP_TYP_S4 6 -#define SLP_TYP_S5 7 -#define GBL_RLS (1 << 2) -#define BM_RLD (1 << 1) -#define SCI_EN (1 << 0) +#define SLP_EN (1 << 13) +#define SLP_TYP (7 << 10) +#define SLP_TYP_S0 0 +#define SLP_TYP_S1 1 +#define SLP_TYP_S3 5 +#define SLP_TYP_S4 6 +#define SLP_TYP_S5 7 +#define GBL_RLS (1 << 2) +#define BM_RLD (1 << 1) +#define SCI_EN (1 << 0) #define PM1_TMR 0x08 #define PROC_CNT 0x10 #define LV2 0x14 @@ -488,33 +488,33 @@ void display_fd_settings(void); #define LV4 0x16 #define PM2_CNT 0x50 // mobile only #define GPE0_STS 0x20 -#define PME_B0_STS (1 << 13) -#define PME_STS (1 << 11) -#define BATLOW_STS (1 << 10) -#define PCI_EXP_STS (1 << 9) -#define RI_STS (1 << 8) -#define SMB_WAK_STS (1 << 7) -#define TCOSCI_STS (1 << 6) -#define SWGPE_STS (1 << 2) -#define HOT_PLUG_STS (1 << 1) +#define PME_B0_STS (1 << 13) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) #define GPE0_EN 0x28 -#define PME_B0_EN (1 << 13) -#define PME_EN (1 << 11) -#define TCOSCI_EN (1 << 6) +#define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) +#define TCOSCI_EN (1 << 6) #define SMI_EN 0x30 -#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic -#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic -#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS -#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) -#define MCSMI_EN (1 << 11) // Trap microcontroller range access -#define BIOS_RLS (1 << 7) // asserts SCI on bit set -#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set -#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# -#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# -#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic -#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit -#define EOS (1 << 1) // End of SMI (deassert SMI#) -#define GBL_SMI_EN (1 << 0) // SMI# generation at all? +#define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic +#define LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic +#define PERIODIC_EN (1 << 14) // SMI on PERIODIC_STS in SMI_STS +#define TCO_EN (1 << 13) // Enable TCO Logic (BIOSWE et al) +#define MCSMI_EN (1 << 11) // Trap microcontroller range access +#define BIOS_RLS (1 << 7) // asserts SCI on bit set +#define SWSMI_TMR_EN (1 << 6) // start software smi timer on bit set +#define APMC_EN (1 << 5) // Writes to APM_CNT cause SMI# +#define SLP_SMI_EN (1 << 4) // Write to SLP_EN in PM1_CNT asserts SMI# +#define LEGACY_USB_EN (1 << 3) // Legacy USB circuit SMI logic +#define BIOS_EN (1 << 2) // Assert SMI# on setting GBL_RLS bit +#define EOS (1 << 1) // End of SMI (deassert SMI#) +#define GBL_SMI_EN (1 << 0) // SMI# generation at all? #define SMI_STS 0x34 #define ALT_GP_SMI_EN 0x38 #define ALT_GP_SMI_STS 0x3a @@ -523,7 +523,7 @@ void display_fd_settings(void); #define SS_CNT 0x50 #define C3_RES 0x54 #define TCO1_STS 0x64 -#define DMISCI_STS (1 << 9) +#define DMISCI_STS (1 << 9) #define TCO2_STS 0x66 /* @@ -568,16 +568,16 @@ void display_fd_settings(void); #define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ #define SPIBAR_HSFS 0x3804 /* SPI hardware sequence status */ -#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ -#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ -#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ -#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ +#define SPIBAR_HSFS_SCIP (1 << 5) /* SPI Cycle In Progress */ +#define SPIBAR_HSFS_AEL (1 << 2) /* SPI Access Error Log */ +#define SPIBAR_HSFS_FCERR (1 << 1) /* SPI Flash Cycle Error */ +#define SPIBAR_HSFS_FDONE (1 << 0) /* SPI Flash Cycle Done */ #define SPIBAR_HSFC 0x3806 /* SPI hardware sequence control */ -#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) -#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ -#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ -#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ -#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ +#define SPIBAR_HSFC_BYTE_COUNT(c) (((c - 1) & 0x3f) << 8) +#define SPIBAR_HSFC_CYCLE_READ (0 << 1) /* Read cycle */ +#define SPIBAR_HSFC_CYCLE_WRITE (2 << 1) /* Write cycle */ +#define SPIBAR_HSFC_CYCLE_ERASE (3 << 1) /* Erase cycle */ +#define SPIBAR_HSFC_GO (1 << 0) /* GO: start SPI transaction */ #define SPIBAR_FADDR 0x3808 /* SPI flash address */ #define SPIBAR_FDATA(n) (0x3810 + (4 * n)) /* SPI flash data */

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New patch to review for coreboot: d7ed4df southbridge/intel/i82371eb: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6335 -gerrit commit d7ed4df3786eac7502619d5b2561f66dd52be2bb Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:19:52 2014 +0200 southbridge/intel/i82371eb: Remove a trailing whitespace Change-Id: I6132e928188ea07efcc15df9c22d918b5ec6cc0e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/intel/i82371eb/i82371eb.h | 64 +++++++++++++++---------------- 1 file changed, 32 insertions(+), 32 deletions(-) diff --git a/src/southbridge/intel/i82371eb/i82371eb.h b/src/southbridge/intel/i82371eb/i82371eb.h index e6062c6..278d517 100644 --- a/src/southbridge/intel/i82371eb/i82371eb.h +++ b/src/southbridge/intel/i82371eb/i82371eb.h @@ -57,59 +57,59 @@ void enable_pm(void); /* SMBus */ #define SMBBA 0x90 /* SMBus base address */ -#define SMBUS_IO_BASE 0x0f00 +#define SMBUS_IO_BASE 0x0f00 #define SMBHSTCFG 0xd2 /* SMBus host configuration */ /* Power management (ACPI) */ #define PMSTS 0x00 /* Power Management Status */ #define PMEN 0x02 /* Power Management Resume Enable */ -#define PWRBTN_EN (1<<8) -#define GBL_EN (1<<5) +#define PWRBTN_EN (1<<8) +#define GBL_EN (1<<5) #define PMCNTRL 0x04 /* Power Management Control */ -#define SUS_EN (1<<13) /* S0-S5 trigger */ -#define SUS_TYP_MSK (7<<10) -#define SUS_TYP_S0 (5<<10) -#define SUS_TYP_S1 (4<<10) -#define SUS_TYP_S2 (3<<10) -//#define SUS_TYP_S2>---(2<<10) -#define SUS_TYP_S3 (1<<10) -#define SUS_TYP_S5 (0<<10) -#define SCI_EN (1<<0) +#define SUS_EN (1<<13) /* S0-S5 trigger */ +#define SUS_TYP_MSK (7<<10) +#define SUS_TYP_S0 (5<<10) +#define SUS_TYP_S1 (4<<10) +#define SUS_TYP_S2 (3<<10) +//#define SUS_TYP_S2>---(2<<10) +#define SUS_TYP_S3 (1<<10) +#define SUS_TYP_S5 (0<<10) +#define SCI_EN (1<<0) #define PMTMR 0x08 /* Power Management Timer */ #define GPSTS 0x0c /* General Purpose Status */ #define GPEN 0x0e /* General Purpose Enable */ -#define THRM_EN (1<<0) +#define THRM_EN (1<<0) #define PCNTRL 0x10 /* Processor control */ #define GLBSTS 0x18 /* Global Status */ -#define IRQ_RSM_STS (1<<11) -#define EXTSMI_STS (1<<10) -#define GSTBY_STS (1<<8) -#define GP_STS (1<<7) -#define BM1_STS (1<<6) -#define APM_STS (1<<5) -#define DEV_STS (1<<4) -#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ -#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define IRQ_RSM_STS (1<<11) +#define EXTSMI_STS (1<<10) +#define GSTBY_STS (1<<8) +#define GP_STS (1<<7) +#define BM1_STS (1<<6) +#define APM_STS (1<<5) +#define DEV_STS (1<<4) +#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ +#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ #define DEVSTS 0x1c /* Device Status */ #define GLBEN 0x20 /* Global Enable */ -#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ -#define GSTBY_EN (1<<8) -#define BM_TRP_EN (1<<1) -#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ -#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ +#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ +#define GSTBY_EN (1<<8) +#define BM_TRP_EN (1<<1) +#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ +#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ #define GLBCTL 0x28 /* Global Control */ -#define EOS (1<<16) /* End of SMI */ -#define SMI_EN (1<<0) /* SMI enable */ +#define EOS (1<<16) /* End of SMI */ +#define SMI_EN (1<<0) /* SMI enable */ #define DEVCTL 0x2c /* Device Control */ -#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ +#define TRP_EN_DEV12 (1<<24) /* SMI on dev12 trap */ #define GPO0 0x34 #define GPO1 0x35 #define GPO2 0x36 #define GPO3 0x37 #define PMBA 0x40 /* Power management base address */ -#define DEFAULT_PMBASE 0xe400 -#define PM_IO_BASE DEFAULT_PMBASE +#define DEFAULT_PMBASE 0xe400 +#define PM_IO_BASE DEFAULT_PMBASE #define PMREGMISC 0x80 /* Miscellaneous power management */ /* Bit definitions */

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New patch to review for coreboot: 4c94cbf southbridge/amd: Remove a trailing whitespace
by HAOUAS Elyes 22 Jul '14

22 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6334 -gerrit commit 4c94cbfc3388fbfdaff2cf722889b92524488eb8 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 19:16:18 2014 +0200 southbridge/amd: Remove a trailing whitespace Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/early_setup.c | 2 +- src/southbridge/amd/agesa/hudson/smbus.c | 2 +- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 2 +- src/southbridge/amd/cimx/sb900/SbPlatform.h | 2 +- src/southbridge/amd/rs690/rs690.h | 6 +++--- src/southbridge/amd/rs780/rs780.h | 6 +++--- src/southbridge/amd/sb800/early_setup.c | 2 +- src/southbridge/amd/sb800/smbus.c | 2 +- 8 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d8fdc27..7f1026a 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -18,7 +18,7 @@ */ #ifndef _HUDSON_EARLY_SETUP_C_ -#define _HUDSON_EARLY_SETUP_C_ +#define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> #include <arch/io.h> diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 0c04158..e5f8e49 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -18,7 +18,7 @@ */ #ifndef _HUDSON_SMBUS_C_ -#define _HUDSON_SMBUS_C_ +#define _HUDSON_SMBUS_C_ #include <io.h> #include <stdint.h> diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index ea3f719..f20b7dc 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -22,7 +22,7 @@ */ #ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 176ad87..ad56870 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -22,7 +22,7 @@ */ #ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> diff --git a/src/southbridge/amd/rs690/rs690.h b/src/southbridge/amd/rs690/rs690.h index 9f143d4..2cc5e48 100644 --- a/src/southbridge/amd/rs690/rs690.h +++ b/src/southbridge/amd/rs690/rs690.h @@ -82,16 +82,16 @@ typedef enum _NB_REVISION_ { ------------------- -----------------------*/ #define PCIE_CI_CNTL 0x20 #define PCIE_LC_LINK_WIDTH 0xa2 -#define PCIE_LC_STATE0 0xa5 +#define PCIE_LC_STATE0 0xa5 #define PCIE_VC0_RESOURCE_STATUS 0x11a /* 16bit read only */ #define PCIE_CORE_INDEX_GFX (0 << 16) /* see 5.2.2 */ #define PCIE_CORE_INDEX_GPPSB (1 << 16) /* contents of PCIE_NBCFG_REG7 */ -#define RECONFIG_GPPSB_EN (1 << 12) +#define RECONFIG_GPPSB_EN (1 << 12) #define RECONFIG_GPPSB_GPPSB (1 << 14) -#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) +#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) #define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17) /* contents of PCIE_VC0_RESOURCE_STATUS */ diff --git a/src/southbridge/amd/rs780/rs780.h b/src/southbridge/amd/rs780/rs780.h index c44a813..1d72c45 100644 --- a/src/southbridge/amd/rs780/rs780.h +++ b/src/southbridge/amd/rs780/rs780.h @@ -150,7 +150,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 ------------------- -----------------------*/ #define PCIE_CI_CNTL 0x20 #define PCIE_LC_LINK_WIDTH 0xa2 -#define PCIE_LC_STATE0 0xa5 +#define PCIE_LC_STATE0 0xa5 #define PCIE_VC0_RESOURCE_STATUS 0x12a /* 16bit read only */ #define PCIE_CORE_INDEX_GFX (0x00 << 16) /* see 5.2.2 */ @@ -159,9 +159,9 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 #define PCIE_CORE_INDEX_BRDCST (0x03 << 16) /* contents of PCIE_NBCFG_REG7 */ -#define RECONFIG_GPPSB_EN (1 << 12) +#define RECONFIG_GPPSB_EN (1 << 12) #define RECONFIG_GPPSB_GPPSB (1 << 14) -#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) +#define RECONFIG_GPPSB_LINK_CONFIG (1 << 15) #define RECONFIG_GPPSB_ATOMIC_RESET (1 << 17) /* contents of PCIE_VC0_RESOURCE_STATUS */ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index ef0548c..f079473 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -18,7 +18,7 @@ */ #ifndef _SB800_EARLY_SETUP_C_ -#define _SB800_EARLY_SETUP_C_ +#define _SB800_EARLY_SETUP_C_ #include <reset.h> #include <arch/acpi.h> diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c index c1a9ded..513a56a 100644 --- a/src/southbridge/amd/sb800/smbus.c +++ b/src/southbridge/amd/sb800/smbus.c @@ -18,7 +18,7 @@ */ #ifndef _SB800_SMBUS_C_ -#define _SB800_SMBUS_C_ +#define _SB800_SMBUS_C_ #include "smbus.h"

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New patch to review for coreboot: 13b4551 AGESA: Drop offset on PCI device enumeration
by Kyösti Mälkki 22 Jul '14

22 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6333 -gerrit commit 13b4551af97dcec1634001e8058507bc6a9a9200 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 21 19:35:16 2014 +0300 AGESA: Drop offset on PCI device enumeration Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/get_bus_conf.c | 24 +------------------ src/mainboard/amd/dinar/irq_tables.c | 8 +++---- src/mainboard/amd/dinar/mptable.c | 5 +--- src/mainboard/amd/inagua/get_bus_conf.c | 18 ++------------ src/mainboard/amd/inagua/irq_tables.c | 8 +++---- src/mainboard/amd/olivehill/get_bus_conf.c | 18 ++------------ src/mainboard/amd/olivehill/irq_tables.c | 8 +++---- src/mainboard/amd/parmer/get_bus_conf.c | 17 ++----------- src/mainboard/amd/parmer/irq_tables.c | 8 +++---- src/mainboard/amd/persimmon/get_bus_conf.c | 17 ++----------- src/mainboard/amd/persimmon/irq_tables.c | 8 +++---- src/mainboard/amd/south_station/get_bus_conf.c | 17 ++----------- src/mainboard/amd/south_station/irq_tables.c | 8 +++---- src/mainboard/amd/thatcher/get_bus_conf.c | 17 ++----------- src/mainboard/amd/thatcher/irq_tables.c | 8 +++---- src/mainboard/amd/torpedo/get_bus_conf.c | 28 +++------------------- src/mainboard/amd/torpedo/irq_tables.c | 8 +++---- src/mainboard/amd/union_station/get_bus_conf.c | 17 ++----------- src/mainboard/amd/union_station/irq_tables.c | 8 +++---- src/mainboard/asrock/e350m1/get_bus_conf.c | 17 ++----------- src/mainboard/asrock/e350m1/irq_tables.c | 8 +++---- src/mainboard/asrock/imb-a180/get_bus_conf.c | 16 ++----------- src/mainboard/asrock/imb-a180/irq_tables.c | 8 +++---- src/mainboard/asus/f2a85-m/get_bus_conf.c | 15 ++---------- src/mainboard/asus/f2a85-m/irq_tables.c | 8 +++---- src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 18 ++------------ src/mainboard/gizmosphere/gizmo/irq_tables.c | 8 +++---- src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 17 ++----------- src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 8 +++---- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 18 ++------------ src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 8 +++---- .../lippert/frontrunner-af/get_bus_conf.c | 18 ++------------ src/mainboard/lippert/frontrunner-af/irq_tables.c | 8 +++---- src/mainboard/lippert/toucan-af/get_bus_conf.c | 17 ++----------- src/mainboard/lippert/toucan-af/irq_tables.c | 8 +++---- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 4 +--- src/mainboard/supermicro/h8qgi/irq_tables.c | 8 +++---- src/mainboard/supermicro/h8qgi/mptable.c | 3 +-- src/mainboard/supermicro/h8scm/get_bus_conf.c | 4 +--- src/mainboard/supermicro/h8scm/irq_tables.c | 8 +++---- src/mainboard/supermicro/h8scm/mptable.c | 3 +-- src/mainboard/tyan/s8226/get_bus_conf.c | 4 +--- src/mainboard/tyan/s8226/irq_tables.c | 8 +++---- src/mainboard/tyan/s8226/mptable.c | 4 +--- 44 files changed, 101 insertions(+), 395 deletions(-) diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index 3104b73..5ab2ddd 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -32,25 +32,6 @@ */ u8 bus_sb700[2]; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* - * HT Chain device num, actually it is unit id base of every ht device in chain, - * assume every chain only have 4 ht device at most - */ -u32 hcdnx[] = { - 0x20202020, -}; - -u32 sbdn_sb700; - void get_bus_conf(void) { device_t dev; @@ -58,17 +39,14 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); - sbdn_sb700 = 0; for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { bus_sb700[i] = 0; } - bus_sb700[0] = (pci1234x[0] >> 16) & 0xff; - /* sb700 */ - dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c index 865d264..8242b4e 100644 --- a/src/mainboard/amd/dinar/irq_tables.c +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb700[2]; -extern unsigned long sbdn_sb700; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -70,8 +68,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb700[0]; - pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -87,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 398ee86..d239a7e 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -29,8 +29,6 @@ #include <cpu/amd/amdfam15.h> extern u8 bus_sb700[2]; -extern u32 sbdn_sb700; - static void *smp_write_config_table(void *v) { @@ -60,8 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sb700 = CONFIG_MAX_CPUS + 1; apicid_rd890 = apicid_sb700 + 1; - //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set sb700 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index c688791..c39decf 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -33,17 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { u32 apicid_base; @@ -52,23 +41,20 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); - // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 98d68d3..305988b 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 508a73c..1dda593 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -35,17 +35,6 @@ u8 bus_yangtze[6]; u32 apicid_yangtze; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_yangtze; - void get_bus_conf(void) { @@ -66,23 +55,20 @@ void get_bus_conf(void) value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); - sbdn_yangtze = 0; memset(bus_yangtze, 0, sizeof(bus_yangtze)); - // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; /* yangtze */ - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 8dbea45..22ed1ab 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_yangtze[6]; -extern unsigned long sbdn_yangtze; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_yangtze[0]; - pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index 490e3c2..8dcd4e5 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -35,17 +35,6 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_hudson; - void get_bus_conf(void) { @@ -56,23 +45,21 @@ void get_bus_conf(void) - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 19f8007..013941c 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 412744c..9434429 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -35,16 +35,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; u32 apicver_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -54,22 +44,19 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index f221a45..53c7953 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -52,16 +42,13 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); @@ -70,7 +57,7 @@ void get_bus_conf(void) } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index b7d6d23..c2dbacd 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -35,17 +35,6 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_hudson; - void get_bus_conf(void) { @@ -54,22 +43,20 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 19f8007..013941c 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 3f8f50e..b88e3fb 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -31,26 +31,6 @@ */ u8 bus_sb900[6]; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - - -u32 sbdn_sb900; - void get_bus_conf(void) { device_t dev; @@ -58,23 +38,21 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__); - sbdn_sb900 = 0; memset(bus_sb900, 0, sizeof(bus_sb900)); - bus_sb900[0] = (pci1234x[0] >> 16) & 0xff; /* sb900 */ - dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb900[0], - PCI_DEVFN(sbdn_sb900 + 0x14, i)); + dev = dev_find_slot(0, + PCI_DEVFN(0x14, i)); if (dev) { bus_sb900[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c index f47d9dc..c501125 100644 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ b/src/mainboard/amd/torpedo/irq_tables.c @@ -45,8 +45,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb900[6]; -extern unsigned long sbdn_sb900; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +70,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb900[0]; - pirq->rtr_devfn = ((sbdn_sb900 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -89,7 +87,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb900[0], ((sbdn_sb900 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index 0b55a2a..52b5d88 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -52,18 +42,15 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); @@ -72,7 +59,7 @@ void get_bus_conf(void) } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 2553588..f2c8056 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -52,22 +42,19 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c index 8610e65..17ff8a5 100644 --- a/src/mainboard/asrock/imb-a180/get_bus_conf.c +++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c @@ -32,16 +32,7 @@ u8 bus_yangtze[6]; u32 apicid_yangtze; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; -u32 sbdn_yangtze; void get_bus_conf(void) { @@ -61,23 +52,20 @@ void get_bus_conf(void) value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); - sbdn_yangtze = 0; memset(bus_yangtze, 0, sizeof(bus_yangtze)); - // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; /* yangtze */ - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index 29dc999..c1c25ba 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_yangtze[6]; -extern unsigned long sbdn_yangtze; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_yangtze[0]; - pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index 389ab8f..fe8253e 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -33,16 +33,7 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; -u32 sbdn_hudson; void get_bus_conf(void) { @@ -51,23 +42,21 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index 8fb6ff3..d0782c8 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -42,8 +42,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -68,8 +66,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -84,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c index 646c543..2cc2c0c 100755 --- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c +++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c @@ -34,17 +34,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { @@ -53,24 +42,21 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 5ce2be9..bb33568 100755 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -45,8 +45,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +70,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -89,7 +87,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c index bd5026d..ef4eeb8 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c @@ -34,17 +34,6 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_hudson; - void get_bus_conf(void) { @@ -53,21 +42,19 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index b0f2a15..e445943 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -42,8 +42,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -68,8 +66,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -84,7 +82,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 8bc5ddf..cc3ffbb 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -36,17 +36,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; u32 apicver_sb800; -/** - * Here you only need to set value in pci1234 for HT-IO that could be - * installed or not. You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { @@ -55,22 +44,19 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 5205a46..a28beb9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -70,8 +68,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -86,7 +84,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* PCI Bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index e736e54..42270af 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -33,17 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { @@ -52,23 +41,20 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index 20dc3ae..eb40c54 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -51,22 +41,19 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 549334e..8531e69 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -31,14 +31,12 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u32 sbdn_sp5100; void get_bus_conf(void) { device_t dev; int i; - sbdn_sp5100 = 0; for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) { bus_sp5100[i] = 0; @@ -47,7 +45,7 @@ void get_bus_conf(void) bus_sp5100[0] = 0; /* sp5100 */ - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 6b1e226..0af225c 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sp5100[0]; - pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 754ed54..3793212 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -29,7 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> extern u8 bus_sp5100[2]; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -59,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 28c4bf7..46ed054 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -31,14 +31,12 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u32 sbdn_sp5100; void get_bus_conf(void) { device_t dev; int i; - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { bus_sp5100[i] = 0; @@ -47,7 +45,7 @@ void get_bus_conf(void) bus_sp5100[0] = 0; /* sp5100 */ - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8scm/irq_tables.c b/src/mainboard/supermicro/h8scm/irq_tables.c index 9770e6d..8f72756 100644 --- a/src/mainboard/supermicro/h8scm/irq_tables.c +++ b/src/mainboard/supermicro/h8scm/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sp5100[0]; - pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -87,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 754ed54..3793212 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -29,7 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> extern u8 bus_sp5100[2]; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -59,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index 7a6876b..087c042 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -30,7 +30,6 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u32 sbdn_sp5100; void get_bus_conf(void); @@ -39,7 +38,6 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { bus_sp5100[i] = 0; @@ -48,7 +46,7 @@ void get_bus_conf(void) bus_sp5100[0] = 0; /* sp5100 */ - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/tyan/s8226/irq_tables.c b/src/mainboard/tyan/s8226/irq_tables.c index 6b1e226..0af225c 100644 --- a/src/mainboard/tyan/s8226/irq_tables.c +++ b/src/mainboard/tyan/s8226/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sp5100[0]; - pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 6a12f2b..3793212 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -29,8 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> extern u8 bus_sp5100[2]; -extern u32 sbdn_sr5650; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -60,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

1 0

New patch to review for coreboot: 123918a AGESA: Drop unused extern declarations
by Kyösti Mälkki 22 Jul '14

22 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6332 -gerrit commit 123918a889db2a7ccc547478c974a552e0b8c437 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 21 19:20:29 2014 +0300 AGESA: Drop unused extern declarations Change-Id: I7f681b40251f49ff717589ed5e7d7e00ee36c7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/inagua/mptable.c | 1 - src/mainboard/amd/olivehill/mptable.c | 1 - src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/persimmon/mptable.c | 1 - src/mainboard/amd/south_station/mptable.c | 1 - src/mainboard/amd/thatcher/mptable.c | 1 - src/mainboard/amd/torpedo/mptable.c | 1 - src/mainboard/amd/union_station/mptable.c | 1 - src/mainboard/asrock/e350m1/mptable.c | 1 - src/mainboard/asrock/imb-a180/mptable.c | 1 - src/mainboard/asus/f2a85-m/mptable.c | 1 - src/mainboard/gizmosphere/gizmo/mptable.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 - src/mainboard/jetway/nf81-t56n-lf/mptable.c | 1 - src/mainboard/lippert/frontrunner-af/mptable.c | 1 - src/mainboard/lippert/toucan-af/mptable.c | 1 - 16 files changed, 16 deletions(-) diff --git a/src/mainboard/amd/inagua/mptable.c b/src/mainboard/amd/inagua/mptable.c index 898b597..5fdac94 100644 --- a/src/mainboard/amd/inagua/mptable.c +++ b/src/mainboard/amd/inagua/mptable.c @@ -31,7 +31,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index 79750e9..4a4b15d 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -31,7 +31,6 @@ #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_yangtze[6]; -extern u32 sbdn_yangtze; extern u32 apicid_yangtze; u8 picr_data[0x54] = { diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index b66cb57..06c1791 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -31,7 +31,6 @@ #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; -extern u32 sbdn_hudson; extern u32 apicid_hudson; u8 picr_data[0x54] = { diff --git a/src/mainboard/amd/persimmon/mptable.c b/src/mainboard/amd/persimmon/mptable.c index e9e208e..1c7e86a 100644 --- a/src/mainboard/amd/persimmon/mptable.c +++ b/src/mainboard/amd/persimmon/mptable.c @@ -35,7 +35,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; extern u32 apicver_sb800; -extern u32 sbdn_sb800; static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/amd/south_station/mptable.c b/src/mainboard/amd/south_station/mptable.c index 591ece5..4b4658c 100644 --- a/src/mainboard/amd/south_station/mptable.c +++ b/src/mainboard/amd/south_station/mptable.c @@ -31,7 +31,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index dfb3b4f..089d260 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -31,7 +31,6 @@ #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; -extern u32 sbdn_hudson; extern u32 apicid_hudson; u8 picr_data[] = { diff --git a/src/mainboard/amd/torpedo/mptable.c b/src/mainboard/amd/torpedo/mptable.c index 6bc1cb3..821bcde 100644 --- a/src/mainboard/amd/torpedo/mptable.c +++ b/src/mainboard/amd/torpedo/mptable.c @@ -33,7 +33,6 @@ extern u8 bus_sb900[6]; -extern u32 sbdn_sb900; u32 apicid_sb900; u8 picr_data[] = { diff --git a/src/mainboard/amd/union_station/mptable.c b/src/mainboard/amd/union_station/mptable.c index 591ece5..4b4658c 100644 --- a/src/mainboard/amd/union_station/mptable.c +++ b/src/mainboard/amd/union_station/mptable.c @@ -31,7 +31,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 689b2b9..198ac21 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -32,7 +32,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 5d91524..a8326a0 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -31,7 +31,6 @@ #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_yangtze[6]; -extern u32 sbdn_yangtze; extern u32 apicid_yangtze; u8 picr_data[0x54] = { diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index d0fd124..cc3e9ec 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -30,7 +30,6 @@ #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; -extern u32 sbdn_hudson; extern u32 apicid_hudson; u8 picr_data[] = { diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index 4cdb131..701cd7b 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -32,7 +32,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index ff40bf7..40b2e04 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -31,7 +31,6 @@ #define IO_APIC_ID CONFIG_MAX_CPUS extern u8 bus_hudson[6]; -extern u32 sbdn_hudson; extern u32 apicid_hudson; u8 picr_data[0x54] = { diff --git a/src/mainboard/jetway/nf81-t56n-lf/mptable.c b/src/mainboard/jetway/nf81-t56n-lf/mptable.c index cc9afbd..1bbe487 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mptable.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mptable.c @@ -37,7 +37,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; extern u32 apicver_sb800; -extern u32 sbdn_sb800; static void *smp_write_config_table(void *v) { diff --git a/src/mainboard/lippert/frontrunner-af/mptable.c b/src/mainboard/lippert/frontrunner-af/mptable.c index d794e56..8b57167 100644 --- a/src/mainboard/lippert/frontrunner-af/mptable.c +++ b/src/mainboard/lippert/frontrunner-af/mptable.c @@ -31,7 +31,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ diff --git a/src/mainboard/lippert/toucan-af/mptable.c b/src/mainboard/lippert/toucan-af/mptable.c index d794e56..8b57167 100644 --- a/src/mainboard/lippert/toucan-af/mptable.c +++ b/src/mainboard/lippert/toucan-af/mptable.c @@ -31,7 +31,6 @@ extern u8 bus_sb800[6]; extern u32 apicid_sb800; -extern u32 sbdn_sb800; u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */

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New patch to review for coreboot: b70a849 AGESA fam15: Drop code that was commented out
by Kyösti Mälkki 22 Jul '14

22 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6331 -gerrit commit b70a8490616a3837faff7f5b1c9cc158961fa737 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 15 16:19:08 2014 +0300 AGESA fam15: Drop code that was commented out Only references to bus_rd890, bus_sp5100 and bus_sr5650 were in code sections that had been commented out. Change-Id: If5552c409ce948c494345f49dbaad790b398bff8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/get_bus_conf.c | 16 +------------ src/mainboard/amd/dinar/mptable.c | 13 ----------- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 33 +-------------------------- src/mainboard/supermicro/h8qgi/mptable.c | 13 ----------- src/mainboard/supermicro/h8scm/get_bus_conf.c | 33 +-------------------------- src/mainboard/supermicro/h8scm/mptable.c | 13 ----------- src/mainboard/tyan/s8226/get_bus_conf.c | 31 +------------------------ src/mainboard/tyan/s8226/mptable.c | 12 ---------- 8 files changed, 4 insertions(+), 160 deletions(-) diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index fdf4b67..3104b73 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -31,7 +31,6 @@ * and acpi_tables busnum is default. */ u8 bus_sb700[2]; -u8 bus_rd890[14]; /* * Here you only need to set value in pci1234 for HT-IO that could be installed or not @@ -51,7 +50,6 @@ u32 hcdnx[] = { }; u32 sbdn_sb700; -u32 sbdn_rd890; void get_bus_conf(void) { @@ -65,13 +63,9 @@ void get_bus_conf(void) for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { bus_sb700[i] = 0; } - for (i = 0; i < ARRAY_SIZE(bus_rd890); i++) { - bus_rd890[i] = 0; - } - bus_rd890[0] = (pci1234x[0] >> 16) & 0xff; - bus_sb700[0] = bus_rd890[0]; + bus_sb700[0] = (pci1234x[0] >> 16) & 0xff; /* sb700 */ dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); @@ -82,13 +76,5 @@ void get_bus_conf(void) bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } - /* rd890 */ - for (i = 1; i < ARRAY_SIZE(bus_rd890); i++) { - dev = dev_find_slot(bus_rd890[0], PCI_DEVFN(sbdn_rd890 + i, 0)); - if (dev) { - bus_rd890[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - End.\n"); } diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 671cd37..398ee86 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -28,9 +28,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/amdfam15.h> -extern u8 bus_rd890[14]; extern u8 bus_sb700[2]; -extern u32 sbdn_rd890; extern u32 sbdn_sb700; @@ -130,17 +128,6 @@ static void *smp_write_config_table(void *v) /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG - /* on board NIC & Slot PCIE. */ - /* configuration B doesnt need dev 5,6,7 */ - /* - * PCI_INT(bus_rd890[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_rd890[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_rd890[0x7], 0x0, 0x0, 0x13); - */ - - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_rd890, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_rd890[13], (((0)<<2)|(1)), apicid_rd890, 0); /* card behind dev13 */ - /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index f604e21..549334e 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -31,11 +31,6 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u8 bus_sr5650[14]; - - - -u32 sbdn_sr5650; u32 sbdn_sp5100; void get_bus_conf(void) @@ -48,13 +43,8 @@ void get_bus_conf(void) for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) { bus_sp5100[i] = 0; } - for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { - bus_sr5650[i] = 0; - } - - bus_sr5650[0] = 0; - bus_sp5100[0] = bus_sr5650[0]; + bus_sp5100[0] = 0; /* sp5100 */ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); @@ -62,25 +52,4 @@ void get_bus_conf(void) if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } - - /* sr5650 */ - for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { - dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); - if (dev) { - bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - -/* - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i)); - if (dev) { - bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } -*/ - - - /* I/O APICs: APIC ID Version State Address */ - } diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 8a248cc..754ed54 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -28,9 +28,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/amdfam10_sysconf.h> -extern u8 bus_sr5650[14]; extern u8 bus_sp5100[2]; -extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) @@ -144,17 +142,6 @@ static void *smp_write_config_table(void *v) /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG - /* on board NIC & Slot PCIE. */ - /* configuration B doesnt need dev 5,6,7 */ - /* - * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); - */ - - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ - /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 3cae35a..28c4bf7 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -31,11 +31,6 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u8 bus_sr5650[14]; - - - -u32 sbdn_sr5650; u32 sbdn_sp5100; void get_bus_conf(void) @@ -48,13 +43,8 @@ void get_bus_conf(void) for (i = 0; i < 0; i++) { bus_sp5100[i] = 0; } - for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { - bus_sr5650[i] = 0; - } - - bus_sr5650[0] = 0; - bus_sp5100[0] = bus_sr5650[0]; + bus_sp5100[0] = 0; /* sp5100 */ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); @@ -62,25 +52,4 @@ void get_bus_conf(void) if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } - - /* sr5650 */ - for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { - dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); - if (dev) { - bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - -/* - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i)); - if (dev) { - bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } -*/ - - - /* I/O APICs: APIC ID Version State Address */ - } diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 8a248cc..754ed54 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -28,9 +28,7 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/amdfam10_sysconf.h> -extern u8 bus_sr5650[14]; extern u8 bus_sp5100[2]; -extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) @@ -144,17 +142,6 @@ static void *smp_write_config_table(void *v) /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG - /* on board NIC & Slot PCIE. */ - /* configuration B doesnt need dev 5,6,7 */ - /* - * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); - */ - - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ - /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14); diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index 3cbe59c..7a6876b 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -30,11 +30,6 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u8 bus_sr5650[14]; - - - -u32 sbdn_sr5650; u32 sbdn_sp5100; void get_bus_conf(void); @@ -49,13 +44,8 @@ void get_bus_conf(void) for (i = 0; i < 0; i++) { bus_sp5100[i] = 0; } - for (i = 0; i < ARRAY_SIZE(bus_sr5650); i++) { - bus_sr5650[i] = 0; - } - - bus_sr5650[0] = 0; - bus_sp5100[0] = bus_sr5650[0]; + bus_sp5100[0] = 0; /* sp5100 */ dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); @@ -63,23 +53,4 @@ void get_bus_conf(void) if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } - - /* sr5650 */ - for (i = 1; i < ARRAY_SIZE(bus_sr5650); i++) { - dev = dev_find_slot(bus_sr5650[0], PCI_DEVFN(sbdn_sr5650 + i, 0)); - if (dev) { - bus_sr5650[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } - -/* - for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, i)); - if (dev) { - bus_sp5100[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - } -*/ - - } diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 8a248cc..6a12f2b 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -28,7 +28,6 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/amdfam10_sysconf.h> -extern u8 bus_sr5650[14]; extern u8 bus_sp5100[2]; extern u32 sbdn_sr5650; extern u32 sbdn_sp5100; @@ -144,17 +143,6 @@ static void *smp_write_config_table(void *v) /* SATA */ PCI_INT(0x0, 0x11, 0x0, 0x16); //6, INTG - /* on board NIC & Slot PCIE. */ - /* configuration B doesnt need dev 5,6,7 */ - /* - * PCI_INT(bus_sr5650[0x5], 0x0, 0x0, 0x11); - * PCI_INT(bus_sr5650[0x6], 0x0, 0x0, 0x12); - * PCI_INT(bus_sr5650[0x7], 0x0, 0x0, 0x13); - */ - - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 28); /* dev d */ - //smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_sr5650[13], (((0)<<2)|(1)), apicid_sr5650, 0); /* card behind dev13 */ - /* PCI slots */ /* PCI_SLOT 0. */ PCI_INT(bus_sp5100[1], 0x5, 0x0, 0x14);

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coreboot-gerrit July 2014