coreboot-gerrit July 2014

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Patch set updated for coreboot: c4f9ed7 Re-structuring Payload loading
by Naman Govil 23 Jul '14

23 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6303 -gerrit commit c4f9ed7c5516f62ba4fcb8bfcc56aa82f280e8c0 Author: Naman Govil <namangov(a)gmail.com> Date: Fri Jul 18 16:20:38 2014 +0530 Re-structuring Payload loading Removing dependency for mapping entire segments for payload loading by segragating segments by reading metadata and then processing them. Change-Id: I87a52cca7f0270cf7575d2bf5133e17fbb6c9470 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/payload_loader.h | 4 + src/lib/loaders/cbfs_payload_loader.c | 18 ++-- src/lib/loaders/load_and_run_payload.c | 3 - src/lib/selfboot.c | 155 ++++++++++++++++++++------------- 4 files changed, 111 insertions(+), 69 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..cac7d27 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <stdint.h> #include <stddef.h> +#include <cbfs_core.h> struct buffer_area { void *data; @@ -32,6 +34,8 @@ struct payload { struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; + struct cbfs_media *media; + struct cbfs_file_handle f; void *entry; }; diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..eccf307 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,21 +20,24 @@ #include <cbfs.h> #include <payload_loader.h> +#include <cbfs_core.h> static int cbfs_locate_payload(struct payload *payload) { - void *buffer; - size_t size; const int type = CBFS_TYPE_PAYLOAD; + struct cbfs_media default_media, *m; + int c; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + m = &default_media; + if(init_default_cbfs_media(m) != 0) + return -1; + + c = cbfs_find_file(m, &payload->f, payload->name, type); - if (buffer == NULL) + if (c < 0) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + payload->media = CBFS_DEFAULT_MEDIA; return 0; } diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..0dcecfb 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,6 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); break; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..7ff65ec 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> - * + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,6 +28,7 @@ #include <lib.h> #include <bootmem.h> #include <payload_loader.h> +#include <cbfs_core.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; @@ -40,9 +41,9 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; unsigned long s_filesz; + unsigned long s_offset; int compression; }; @@ -140,7 +141,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_offset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +177,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_offset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -217,63 +218,78 @@ static int build_self_segment_list( struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + struct cbfs_payload_segment segment; + struct cbfs_media default_media, *media; + unsigned long current_offset; + + media = payload->media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + current_offset = payload->f.data_offset; + media->open(media); + + while(media->read(media, &segment, current_offset, sizeof(segment)) + == sizeof(segment)) { + + printk(BIOS_DEBUG, "Reading segment from offset 0x%lx\n", current_offset); + segment.compression = ntohl(segment.compression); + segment.offset = ntohl(segment.offset); + segment.load_addr = ntohll(segment.load_addr); + segment.mem_len = ntohl(segment.mem_len); + segment.len = ntohl(segment.len); + + switch(segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; + current_offset += sizeof(segment); continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment.type == PAYLOAD_SEGMENT_CODE ? "code" : "data", + segment.compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; + new->s_filesz = segment.len; + new->s_offset = segment.offset; + + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_offset = segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment.load_addr); + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -285,26 +301,20 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; - - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } + current_offset += sizeof(segment); - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert to the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } - + media->close(media); return 1; } @@ -313,8 +323,18 @@ static int load_self_segments( struct payload *payload) { struct segment *ptr; + struct cbfs_media default_media, *media; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + media = payload->media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -362,7 +382,7 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src; + unsigned char *dest; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -378,7 +398,8 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + size_t v_read; + void *v_map; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -388,14 +409,31 @@ static int load_self_segments( switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - len = ulzma(src, dest); + printk(BIOS_DEBUG, "need to map first\n"); + media->open(media); + v_map = media->map(media, payload->f.data_offset + ptr->s_offset, + len); + + media->close(media); + if (v_map == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + printk(BIOS_ERR, "Failed to map\n"); + return -1; + } + len = ulzma(v_map, dest); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + printk(BIOS_DEBUG, "it's not compressed! hence read directly\n"); + media->open(media); + v_read = media->read(media, dest, payload->f.data_offset + ptr->s_offset, + len); + media->close(media); + if (v_read != len) { + printk(BIOS_ERR, "Reading of uncompressed segments not successful\n"); + return -1; + } break; } default: @@ -404,11 +442,10 @@ static int load_self_segments( } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx )\n", (unsigned long)dest, (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)end); /* Zero the extra bytes between middle & end */ if (middle < end) {

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Patch set updated for coreboot: c9100cd Re-structuring Payload loading
by Naman Govil 23 Jul '14

23 Jul '14

Naman Govil (namangov(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6303 -gerrit commit c9100cd53d390dd63848b687314382189b21c0cb Author: Naman Govil <namangov(a)gmail.com> Date: Fri Jul 18 16:20:38 2014 +0530 Re-structuring Payload loading Removing dependency for mapping entire segments for payload loading by segragating segments by reading metadata and then processing them. Change-Id: I87a52cca7f0270cf7575d2bf5133e17fbb6c9470 Signed-off-by: Naman Govil <namangov(a)gmail.com> --- src/include/payload_loader.h | 4 + src/lib/loaders/cbfs_payload_loader.c | 18 ++-- src/lib/loaders/load_and_run_payload.c | 3 - src/lib/selfboot.c | 155 ++++++++++++++++++++------------- 4 files changed, 111 insertions(+), 69 deletions(-) diff --git a/src/include/payload_loader.h b/src/include/payload_loader.h index 7a3f045..cac7d27 100644 --- a/src/include/payload_loader.h +++ b/src/include/payload_loader.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,6 +22,7 @@ #include <stdint.h> #include <stddef.h> +#include <cbfs_core.h> struct buffer_area { void *data; @@ -32,6 +34,8 @@ struct payload { struct buffer_area backing_store; /* Used when payload wants memory coreboot ramstage is running at. */ struct buffer_area bounce; + struct cbfs_media *media; + struct cbfs_file_handle f; void *entry; }; diff --git a/src/lib/loaders/cbfs_payload_loader.c b/src/lib/loaders/cbfs_payload_loader.c index 2c1d179..eccf307 100644 --- a/src/lib/loaders/cbfs_payload_loader.c +++ b/src/lib/loaders/cbfs_payload_loader.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,21 +20,24 @@ #include <cbfs.h> #include <payload_loader.h> +#include <cbfs_core.h> static int cbfs_locate_payload(struct payload *payload) { - void *buffer; - size_t size; const int type = CBFS_TYPE_PAYLOAD; + struct cbfs_media default_media, *m; + int c; - buffer = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, payload->name, - type, &size); + m = &default_media; + if(init_default_cbfs_media(m) != 0) + return -1; + + c = cbfs_find_file(m, &payload->f, payload->name, type); - if (buffer == NULL) + if (c < 0) return -1; - payload->backing_store.data = buffer; - payload->backing_store.size = size; + payload->media = CBFS_DEFAULT_MEDIA; return 0; } diff --git a/src/lib/loaders/load_and_run_payload.c b/src/lib/loaders/load_and_run_payload.c index 2204090..0dcecfb 100644 --- a/src/lib/loaders/load_and_run_payload.c +++ b/src/lib/loaders/load_and_run_payload.c @@ -58,9 +58,6 @@ struct payload *payload_load(void) ops->name); continue; } - printk(BIOS_DEBUG, "%s: located payload @ %p, %zu bytes.\n", - ops->name, payload->backing_store.data, - payload->backing_store.size); break; } diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 8e9e0de..131a956 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -3,7 +3,7 @@ * * Copyright (C) 2003 Eric W. Biederman <ebiederm(a)xmission.com> * Copyright (C) 2009 Ron Minnich <rminnich(a)gmail.com> - * + * Copyright (C) 2014 Naman Govil <namangov(a)gmail.com> * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -28,6 +28,7 @@ #include <lib.h> #include <bootmem.h> #include <payload_loader.h> +#include <cbfs_core.h> /* from ramstage.ld: */ extern unsigned char _ram_seg; @@ -40,9 +41,9 @@ struct segment { struct segment *next; struct segment *prev; unsigned long s_dstaddr; - unsigned long s_srcaddr; unsigned long s_memsz; unsigned long s_filesz; + unsigned long s_offset; int compression; }; @@ -140,7 +141,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) new->s_memsz = len; seg->s_memsz -= len; seg->s_dstaddr += len; - seg->s_srcaddr += len; + seg->s_offset += len; if (seg->s_filesz > len) { new->s_filesz = len; seg->s_filesz -= len; @@ -176,7 +177,7 @@ static int relocate_segment(unsigned long buffer, struct segment *seg) seg->s_memsz = len; new->s_memsz -= len; new->s_dstaddr += len; - new->s_srcaddr += len; + new->s_offset += len; if (seg->s_filesz > len) { seg->s_filesz = len; new->s_filesz -= len; @@ -217,63 +218,78 @@ static int build_self_segment_list( struct payload *payload, uintptr_t *entry) { struct segment *new; - struct segment *ptr; - struct cbfs_payload_segment *segment, *first_segment; - struct cbfs_payload *cbfs_payload; - cbfs_payload = payload->backing_store.data; + struct cbfs_payload_segment segment; + struct cbfs_media default_media, *media; + unsigned long current_offset; + + media = payload->media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } + memset(head, 0, sizeof(*head)); head->next = head->prev = head; - first_segment = segment = &cbfs_payload->segments; - while(1) { - printk(BIOS_DEBUG, "Loading segment from rom address 0x%p\n", segment); - switch(segment->type) { + current_offset = payload->f.data_offset; + media->open(media); + + while(media->read(media, &segment, current_offset, sizeof(segment)) + == sizeof(segment)) { + + printk(BIOS_DEBUG, "Reading segment from offset 0x%x\n", current_offset); + segment.compression = ntohl(segment.compression); + segment.offset = ntohl(segment.offset); + segment.load_addr = ntohll(segment.load_addr); + segment.mem_len = ntohl(segment.mem_len); + segment.len = ntohl(segment.len); + + switch(segment.type) { case PAYLOAD_SEGMENT_PARAMS: printk(BIOS_DEBUG, " parameter section (skipped)\n"); - segment++; + current_offset += sizeof(segment); continue; case PAYLOAD_SEGMENT_CODE: case PAYLOAD_SEGMENT_DATA: printk(BIOS_DEBUG, " %s (compression=%x)\n", - segment->type == PAYLOAD_SEGMENT_CODE ? "code" : "data", - ntohl(segment->compression)); + segment.type == PAYLOAD_SEGMENT_CODE ? "code" : "data", + segment.compression); new = malloc(sizeof(*new)); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); - new->compression = ntohl(segment->compression); - - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_filesz = ntohl(segment->len); - printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx srcaddr 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; + new->compression = segment.compression; + new->s_filesz = segment.len; + new->s_offset = segment.offset; + + printk(BIOS_DEBUG, " New segment dstaddr 0x%lx memsize 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); /* Clean up the values */ if (new->s_filesz > new->s_memsz) { new->s_filesz = new->s_memsz; } - printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx offset 0x%lx filesize 0x%lx\n", - new->s_dstaddr, new->s_memsz, new->s_srcaddr, new->s_filesz); + printk(BIOS_DEBUG, " (cleaned up) New segment addr 0x%lx size 0x%lx src_offset 0x%lx filesize 0x%lx\n", + new->s_dstaddr, new->s_memsz, new->s_offset, new->s_filesz); break; case PAYLOAD_SEGMENT_BSS: - printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", (void *) - (intptr_t)ntohll(segment->load_addr), - ntohl(segment->mem_len)); + printk(BIOS_DEBUG, " BSS 0x%p (%d byte)\n", + (void *)(intptr_t)segment.load_addr, segment.mem_len); new = malloc(sizeof(*new)); new->s_filesz = 0; - new->s_srcaddr = (uintptr_t) - ((unsigned char *)first_segment) - + ntohl(segment->offset); - new->s_dstaddr = ntohll(segment->load_addr); - new->s_memsz = ntohl(segment->mem_len); + new->s_offset = segment.offset; + new->s_dstaddr = segment.load_addr; + new->s_memsz = segment.mem_len; break; case PAYLOAD_SEGMENT_ENTRY: printk(BIOS_DEBUG, " Entry Point 0x%p\n", - (void *)(intptr_t)ntohll(segment->load_addr)); - *entry = ntohll(segment->load_addr); + (void *)(intptr_t)segment.load_addr); + *entry = segment.load_addr; /* Per definition, a payload always has the entry point * as last segment. Thus, we use the occurrence of the * entry point as break condition for the loop. @@ -285,26 +301,20 @@ static int build_self_segment_list( /* We found something that we don't know about. Throw * hands into the sky and run away! */ - printk(BIOS_EMERG, "Bad segment type %x\n", segment->type); + printk(BIOS_EMERG, "Bad segment type %x\n", segment.type); return -1; } /* We have found another CODE, DATA or BSS segment */ - segment++; - - /* Find place where to insert our segment */ - for(ptr = head->next; ptr != head; ptr = ptr->next) { - if (new->s_srcaddr < ntohll(segment->load_addr)) - break; - } + current_offset += sizeof(segment); - /* Order by stream offset */ - new->next = ptr; - new->prev = ptr->prev; - ptr->prev->next = new; - ptr->prev = new; + /* Insert to the end of the list */ + new->next = head; + new->prev = head->prev; + head->prev->next = new; + head->prev = new; } - + media->close(media); return 1; } @@ -313,8 +323,18 @@ static int load_self_segments( struct payload *payload) { struct segment *ptr; + struct cbfs_media default_media, *media; const unsigned long one_meg = (1UL << 20); unsigned long bounce_high = lb_end; + media = payload->media; + + if (media == CBFS_DEFAULT_MEDIA) { + media = &default_media; + if (init_default_cbfs_media(media) != 0) { + printk(BIOS_ERR, "Failed to initialize media\n"); + return -1; + } + } for(ptr = head->next; ptr != head; ptr = ptr->next) { if (bootmem_region_targets_usable_ram(ptr->s_dstaddr, @@ -362,7 +382,7 @@ static int load_self_segments( payload->bounce.size = bounce_size; for(ptr = head->next; ptr != head; ptr = ptr->next) { - unsigned char *dest, *src; + unsigned char *dest; printk(BIOS_DEBUG, "Loading Segment: addr: 0x%016lx memsz: 0x%016lx filesz: 0x%016lx\n", ptr->s_dstaddr, ptr->s_memsz, ptr->s_filesz); @@ -378,7 +398,8 @@ static int load_self_segments( /* Compute the boundaries of the segment */ dest = (unsigned char *)(ptr->s_dstaddr); - src = (unsigned char *)(ptr->s_srcaddr); + size_t v_read; + void *v_map; /* Copy data from the initial buffer */ if (ptr->s_filesz) { @@ -388,14 +409,31 @@ static int load_self_segments( switch(ptr->compression) { case CBFS_COMPRESS_LZMA: { printk(BIOS_DEBUG, "using LZMA\n"); - len = ulzma(src, dest); + printk(BIOS_DEBUG, "need to map first\n"); + media->open(media); + v_map = media->map(media, payload->f.data_offset + ptr->s_offset, + len); + + media->close(media); + if (v_map == CBFS_MEDIA_INVALID_MAP_ADDRESS) { + printk(BIOS_ERR, "Failed to map\n"); + return -1; + } + len = ulzma(v_map, dest); if (!len) /* Decompression Error. */ return 0; break; } case CBFS_COMPRESS_NONE: { - printk(BIOS_DEBUG, "it's not compressed!\n"); - memcpy(dest, src, len); + printk(BIOS_DEBUG, "it's not compressed! hence read directly\n"); + media->open(media); + v_read = media->read(media, dest, payload->f.data_offset + ptr->s_offset, + len); + media->close(media); + if (v_read != len) { + printk(BIOS_ERR, "Reading of uncompressed segments not successful\n"); + return -1; + } break; } default: @@ -404,11 +442,10 @@ static int load_self_segments( } end = dest + ptr->s_memsz; middle = dest + len; - printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx) <- %08lx\n", + printk(BIOS_SPEW, "[ 0x%08lx, %08lx, 0x%08lx )\n", (unsigned long)dest, (unsigned long)middle, - (unsigned long)end, - (unsigned long)src); + (unsigned long)end); /* Zero the extra bytes between middle & end */ if (middle < end) {

1 0

New patch to review for coreboot: 130b03a AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf()
by Kyösti Mälkki 23 Jul '14

23 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6355 -gerrit commit 130b03a476f8d2c8a1658f77e25bcb8f87a152ab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jul 22 15:56:59 2014 +0300 AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf() Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 8 ++++++++ src/mainboard/amd/olivehill/get_bus_conf.c | 5 ----- src/mainboard/amd/parmer/get_bus_conf.c | 5 ----- src/mainboard/amd/thatcher/get_bus_conf.c | 5 ----- src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 5 ----- 5 files changed, 8 insertions(+), 20 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 0453006..f893741 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -24,6 +24,9 @@ #include "agesawrapper.h" #include <northbridge/amd/agesa/agesawrapper_call.h> +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#include <southbridge/amd/agesa/hudson/imc.h> +#endif #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -40,6 +43,11 @@ static void agesawrapper_post_device(void *unused) /* Preparation for write_tables(). */ get_bus_conf(); +#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) + /* AMD AGESA does not enable thermal zone, so we enable it here. */ + enable_imc_thermal_zone(); +#endif + #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 1dda593..a58c61f 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -77,9 +77,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ apicid_base = CONFIG_MAX_CPUS; apicid_yangtze = apicid_base; - -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif } diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index 8dcd4e5..3b3daf9 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -68,9 +68,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; - -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif } diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index c2dbacd..9f5f15a 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -65,9 +65,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; - -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c index ef4eeb8..f0494ab 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c @@ -63,9 +63,4 @@ void get_bus_conf(void) /* I/O APICs: APIC ID Version State Address */ apicid_base = CONFIG_MAX_CPUS; apicid_hudson = apicid_base; - -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) - /* AMD AGESA does not enable thermal zone, so we enable it here. */ - enable_imc_thermal_zone(); -#endif }

1 0

Patch set updated for coreboot: 20a71e1 AGESA: Drop offset on PCI device enumeration
by Kyösti Mälkki 23 Jul '14

23 Jul '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6333 -gerrit commit 20a71e14fa382c319a374034c82b62c03bab4b93 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jul 21 19:35:16 2014 +0300 AGESA: Drop offset on PCI device enumeration Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/get_bus_conf.c | 24 +------------------ src/mainboard/amd/dinar/irq_tables.c | 8 +++---- src/mainboard/amd/dinar/mptable.c | 5 +--- src/mainboard/amd/inagua/get_bus_conf.c | 18 ++------------ src/mainboard/amd/inagua/irq_tables.c | 8 +++---- src/mainboard/amd/olivehill/get_bus_conf.c | 18 ++------------ src/mainboard/amd/olivehill/irq_tables.c | 8 +++---- src/mainboard/amd/parmer/get_bus_conf.c | 17 ++----------- src/mainboard/amd/parmer/irq_tables.c | 8 +++---- src/mainboard/amd/persimmon/get_bus_conf.c | 17 ++----------- src/mainboard/amd/persimmon/irq_tables.c | 8 +++---- src/mainboard/amd/south_station/get_bus_conf.c | 17 ++----------- src/mainboard/amd/south_station/irq_tables.c | 8 +++---- src/mainboard/amd/thatcher/get_bus_conf.c | 17 ++----------- src/mainboard/amd/thatcher/irq_tables.c | 8 +++---- src/mainboard/amd/torpedo/get_bus_conf.c | 28 +++------------------- src/mainboard/amd/torpedo/irq_tables.c | 8 +++---- src/mainboard/amd/union_station/get_bus_conf.c | 17 ++----------- src/mainboard/amd/union_station/irq_tables.c | 8 +++---- src/mainboard/asrock/e350m1/get_bus_conf.c | 17 ++----------- src/mainboard/asrock/e350m1/irq_tables.c | 8 +++---- src/mainboard/asrock/imb-a180/get_bus_conf.c | 16 ++----------- src/mainboard/asrock/imb-a180/irq_tables.c | 8 +++---- src/mainboard/asus/f2a85-m/get_bus_conf.c | 15 ++---------- src/mainboard/asus/f2a85-m/irq_tables.c | 9 ++++--- src/mainboard/gizmosphere/gizmo/get_bus_conf.c | 18 ++------------ src/mainboard/gizmosphere/gizmo/irq_tables.c | 8 +++---- src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c | 17 ++----------- src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c | 9 ++++--- src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c | 18 ++------------ src/mainboard/jetway/nf81-t56n-lf/irq_tables.c | 9 ++++--- .../lippert/frontrunner-af/get_bus_conf.c | 18 ++------------ src/mainboard/lippert/frontrunner-af/irq_tables.c | 8 +++---- src/mainboard/lippert/toucan-af/get_bus_conf.c | 17 ++----------- src/mainboard/lippert/toucan-af/irq_tables.c | 8 +++---- src/mainboard/supermicro/h8qgi/get_bus_conf.c | 4 +--- src/mainboard/supermicro/h8qgi/irq_tables.c | 8 +++---- src/mainboard/supermicro/h8qgi/mptable.c | 3 +-- src/mainboard/supermicro/h8scm/get_bus_conf.c | 4 +--- src/mainboard/supermicro/h8scm/irq_tables.c | 8 +++---- src/mainboard/supermicro/h8scm/mptable.c | 3 +-- src/mainboard/tyan/s8226/get_bus_conf.c | 4 +--- src/mainboard/tyan/s8226/irq_tables.c | 8 +++---- src/mainboard/tyan/s8226/mptable.c | 4 +--- 44 files changed, 104 insertions(+), 395 deletions(-) diff --git a/src/mainboard/amd/dinar/get_bus_conf.c b/src/mainboard/amd/dinar/get_bus_conf.c index 3104b73..5ab2ddd 100644 --- a/src/mainboard/amd/dinar/get_bus_conf.c +++ b/src/mainboard/amd/dinar/get_bus_conf.c @@ -32,25 +32,6 @@ */ u8 bus_sb700[2]; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* - * HT Chain device num, actually it is unit id base of every ht device in chain, - * assume every chain only have 4 ht device at most - */ -u32 hcdnx[] = { - 0x20202020, -}; - -u32 sbdn_sb700; - void get_bus_conf(void) { device_t dev; @@ -58,17 +39,14 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "Mainboard - Get_bus_conf.c - get_bus_conf - Start.\n"); - sbdn_sb700 = 0; for (i = 0; i < ARRAY_SIZE(bus_sb700); i++) { bus_sb700[i] = 0; } - bus_sb700[0] = (pci1234x[0] >> 16) & 0xff; - /* sb700 */ - dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); diff --git a/src/mainboard/amd/dinar/irq_tables.c b/src/mainboard/amd/dinar/irq_tables.c index 865d264..8242b4e 100644 --- a/src/mainboard/amd/dinar/irq_tables.c +++ b/src/mainboard/amd/dinar/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb700[2]; -extern unsigned long sbdn_sb700; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -70,8 +68,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb700[0]; - pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -87,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/dinar/mptable.c b/src/mainboard/amd/dinar/mptable.c index 398ee86..d239a7e 100644 --- a/src/mainboard/amd/dinar/mptable.c +++ b/src/mainboard/amd/dinar/mptable.c @@ -29,8 +29,6 @@ #include <cpu/amd/amdfam15.h> extern u8 bus_sb700[2]; -extern u32 sbdn_sb700; - static void *smp_write_config_table(void *v) { @@ -60,8 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sb700 = CONFIG_MAX_CPUS + 1; apicid_rd890 = apicid_sb700 + 1; - //bus_sb700[0], TODO: why bus_sb700[0] use same value of bus_rd890[0] assigned by get_pci1234(), instead of 0. - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set sb700 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; diff --git a/src/mainboard/amd/inagua/get_bus_conf.c b/src/mainboard/amd/inagua/get_bus_conf.c index c688791..c39decf 100644 --- a/src/mainboard/amd/inagua/get_bus_conf.c +++ b/src/mainboard/amd/inagua/get_bus_conf.c @@ -33,17 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { u32 apicid_base; @@ -52,23 +41,20 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); - // bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/inagua/irq_tables.c b/src/mainboard/amd/inagua/irq_tables.c index 98d68d3..305988b 100644 --- a/src/mainboard/amd/inagua/irq_tables.c +++ b/src/mainboard/amd/inagua/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/olivehill/get_bus_conf.c b/src/mainboard/amd/olivehill/get_bus_conf.c index 508a73c..1dda593 100644 --- a/src/mainboard/amd/olivehill/get_bus_conf.c +++ b/src/mainboard/amd/olivehill/get_bus_conf.c @@ -35,17 +35,6 @@ u8 bus_yangtze[6]; u32 apicid_yangtze; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_yangtze; - void get_bus_conf(void) { @@ -66,23 +55,20 @@ void get_bus_conf(void) value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); - sbdn_yangtze = 0; memset(bus_yangtze, 0, sizeof(bus_yangtze)); - // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; /* yangtze */ - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/olivehill/irq_tables.c b/src/mainboard/amd/olivehill/irq_tables.c index 8dbea45..22ed1ab 100644 --- a/src/mainboard/amd/olivehill/irq_tables.c +++ b/src/mainboard/amd/olivehill/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_yangtze[6]; -extern unsigned long sbdn_yangtze; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_yangtze[0]; - pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/parmer/get_bus_conf.c b/src/mainboard/amd/parmer/get_bus_conf.c index 490e3c2..8dcd4e5 100644 --- a/src/mainboard/amd/parmer/get_bus_conf.c +++ b/src/mainboard/amd/parmer/get_bus_conf.c @@ -35,17 +35,6 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_hudson; - void get_bus_conf(void) { @@ -56,23 +45,21 @@ void get_bus_conf(void) - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/parmer/irq_tables.c b/src/mainboard/amd/parmer/irq_tables.c index 19f8007..013941c 100644 --- a/src/mainboard/amd/parmer/irq_tables.c +++ b/src/mainboard/amd/parmer/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/persimmon/get_bus_conf.c b/src/mainboard/amd/persimmon/get_bus_conf.c index 412744c..9434429 100644 --- a/src/mainboard/amd/persimmon/get_bus_conf.c +++ b/src/mainboard/amd/persimmon/get_bus_conf.c @@ -35,16 +35,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; u32 apicver_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -54,22 +44,19 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/persimmon/irq_tables.c b/src/mainboard/amd/persimmon/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/amd/persimmon/irq_tables.c +++ b/src/mainboard/amd/persimmon/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/south_station/get_bus_conf.c b/src/mainboard/amd/south_station/get_bus_conf.c index f221a45..53c7953 100644 --- a/src/mainboard/amd/south_station/get_bus_conf.c +++ b/src/mainboard/amd/south_station/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -52,16 +42,13 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); @@ -70,7 +57,7 @@ void get_bus_conf(void) } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/south_station/irq_tables.c b/src/mainboard/amd/south_station/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/amd/south_station/irq_tables.c +++ b/src/mainboard/amd/south_station/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/thatcher/get_bus_conf.c b/src/mainboard/amd/thatcher/get_bus_conf.c index b7d6d23..c2dbacd 100644 --- a/src/mainboard/amd/thatcher/get_bus_conf.c +++ b/src/mainboard/amd/thatcher/get_bus_conf.c @@ -35,17 +35,6 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_hudson; - void get_bus_conf(void) { @@ -54,22 +43,20 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/thatcher/irq_tables.c b/src/mainboard/amd/thatcher/irq_tables.c index 19f8007..013941c 100644 --- a/src/mainboard/amd/thatcher/irq_tables.c +++ b/src/mainboard/amd/thatcher/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/torpedo/get_bus_conf.c b/src/mainboard/amd/torpedo/get_bus_conf.c index 3f8f50e..b88e3fb 100644 --- a/src/mainboard/amd/torpedo/get_bus_conf.c +++ b/src/mainboard/amd/torpedo/get_bus_conf.c @@ -31,26 +31,6 @@ */ u8 bus_sb900[6]; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -/* -* HT Chain device num, actually it is unit id base of every ht device in chain, -* assume every chain only have 4 ht device at most -*/ -u32 hcdnx[] = { - 0x20202020, -}; - - -u32 sbdn_sb900; - void get_bus_conf(void) { device_t dev; @@ -58,23 +38,21 @@ void get_bus_conf(void) printk(BIOS_DEBUG, "Mainboard - %s - %s - Start.\n", __FILE__, __func__); - sbdn_sb900 = 0; memset(bus_sb900, 0, sizeof(bus_sb900)); - bus_sb900[0] = (pci1234x[0] >> 16) & 0xff; /* sb900 */ - dev = dev_find_slot(bus_sb900[0], PCI_DEVFN(sbdn_sb900 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb900[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb900[0], - PCI_DEVFN(sbdn_sb900 + 0x14, i)); + dev = dev_find_slot(0, + PCI_DEVFN(0x14, i)); if (dev) { bus_sb900[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/amd/torpedo/irq_tables.c b/src/mainboard/amd/torpedo/irq_tables.c index f47d9dc..c501125 100644 --- a/src/mainboard/amd/torpedo/irq_tables.c +++ b/src/mainboard/amd/torpedo/irq_tables.c @@ -45,8 +45,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb900[6]; -extern unsigned long sbdn_sb900; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +70,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb900[0]; - pirq->rtr_devfn = ((sbdn_sb900 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -89,7 +87,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb900[0], ((sbdn_sb900 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/amd/union_station/get_bus_conf.c b/src/mainboard/amd/union_station/get_bus_conf.c index 0b55a2a..52b5d88 100644 --- a/src/mainboard/amd/union_station/get_bus_conf.c +++ b/src/mainboard/amd/union_station/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -52,18 +42,15 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); @@ -72,7 +59,7 @@ void get_bus_conf(void) } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/amd/union_station/irq_tables.c b/src/mainboard/amd/union_station/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/amd/union_station/irq_tables.c +++ b/src/mainboard/amd/union_station/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/asrock/e350m1/get_bus_conf.c b/src/mainboard/asrock/e350m1/get_bus_conf.c index 2553588..f2c8056 100644 --- a/src/mainboard/asrock/e350m1/get_bus_conf.c +++ b/src/mainboard/asrock/e350m1/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -52,22 +42,19 @@ void get_bus_conf(void) int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asrock/e350m1/irq_tables.c b/src/mainboard/asrock/e350m1/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/asrock/e350m1/irq_tables.c +++ b/src/mainboard/asrock/e350m1/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/asrock/imb-a180/get_bus_conf.c b/src/mainboard/asrock/imb-a180/get_bus_conf.c index 8610e65..17ff8a5 100644 --- a/src/mainboard/asrock/imb-a180/get_bus_conf.c +++ b/src/mainboard/asrock/imb-a180/get_bus_conf.c @@ -32,16 +32,7 @@ u8 bus_yangtze[6]; u32 apicid_yangtze; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; -u32 sbdn_yangtze; void get_bus_conf(void) { @@ -61,23 +52,20 @@ void get_bus_conf(void) value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); - sbdn_yangtze = 0; memset(bus_yangtze, 0, sizeof(bus_yangtze)); - // bus_yangtze[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_yangtze[0] = (pci1234x[0] >> 16) & 0xff; /* yangtze */ - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_yangtze[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_yangtze[0], PCI_DEVFN(sbdn_yangtze + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_yangtze[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asrock/imb-a180/irq_tables.c b/src/mainboard/asrock/imb-a180/irq_tables.c index 29dc999..c1c25ba 100644 --- a/src/mainboard/asrock/imb-a180/irq_tables.c +++ b/src/mainboard/asrock/imb-a180/irq_tables.c @@ -43,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_yangtze[6]; -extern unsigned long sbdn_yangtze; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -69,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_yangtze[0]; - pirq->rtr_devfn = ((sbdn_yangtze + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -85,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_yangtze[0], ((sbdn_yangtze + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/asus/f2a85-m/get_bus_conf.c b/src/mainboard/asus/f2a85-m/get_bus_conf.c index 389ab8f..fe8253e 100644 --- a/src/mainboard/asus/f2a85-m/get_bus_conf.c +++ b/src/mainboard/asus/f2a85-m/get_bus_conf.c @@ -33,16 +33,7 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; -u32 sbdn_hudson; void get_bus_conf(void) { @@ -51,23 +42,21 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/asus/f2a85-m/irq_tables.c b/src/mainboard/asus/f2a85-m/irq_tables.c index 8fb6ff3..0bab5c9 100644 --- a/src/mainboard/asus/f2a85-m/irq_tables.c +++ b/src/mainboard/asus/f2a85-m/irq_tables.c @@ -20,6 +20,7 @@ #include <arch/pirq_routing.h> #include <console/console.h> #include <cpu/amd/amdfam15.h> +#include <device/pci_def.h> #include <stdint.h> #include <string.h> @@ -42,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -68,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -84,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c index 646c543..2cc2c0c 100755 --- a/src/mainboard/gizmosphere/gizmo/get_bus_conf.c +++ b/src/mainboard/gizmosphere/gizmo/get_bus_conf.c @@ -34,17 +34,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { @@ -53,24 +42,21 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/gizmosphere/gizmo/irq_tables.c b/src/mainboard/gizmosphere/gizmo/irq_tables.c index 5ce2be9..bb33568 100755 --- a/src/mainboard/gizmosphere/gizmo/irq_tables.c +++ b/src/mainboard/gizmosphere/gizmo/irq_tables.c @@ -45,8 +45,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -72,8 +70,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -89,7 +87,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c index bd5026d..ef4eeb8 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/get_bus_conf.c @@ -34,17 +34,6 @@ u8 bus_hudson[6]; u32 apicid_hudson; -/* - * Here you only need to set value in pci1234 for HT-IO that could be installed or not - * You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_hudson; - void get_bus_conf(void) { @@ -53,21 +42,19 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_hudson = 0; memset(bus_hudson, 0, sizeof(bus_hudson)); - bus_hudson[0] = (pci1234x[0] >> 16) & 0xff; /* Hudson */ - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_hudson[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_hudson[0], PCI_DEVFN(sbdn_hudson + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_hudson[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c index b0f2a15..42364e9 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/irq_tables.c @@ -20,6 +20,7 @@ #include <arch/pirq_routing.h> #include <cpu/amd/amdfam15.h> #include <console/console.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> @@ -42,8 +43,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->rfu = rfu; } -extern u8 bus_hudson[6]; -extern unsigned long sbdn_hudson; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -68,8 +67,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_hudson[0]; - pirq->rtr_devfn = ((sbdn_hudson + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -84,7 +83,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_hudson[0], ((sbdn_hudson + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c index 8bc5ddf..cc3ffbb 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c +++ b/src/mainboard/jetway/nf81-t56n-lf/get_bus_conf.c @@ -36,17 +36,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; u32 apicver_sb800; -/** - * Here you only need to set value in pci1234 for HT-IO that could be - * installed or not. You may need to preset pci1234 for HTIO board, - * please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail - */ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { @@ -55,22 +44,19 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c index 5205a46..94a69f9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/irq_tables.c @@ -21,6 +21,7 @@ #include <arch/pirq_routing.h> #include <console/console.h> #include <cpu/amd/amdfam14.h> +#include <device/pci_def.h> #include <string.h> #include <stdint.h> @@ -43,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -70,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -86,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* PCI Bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c index e736e54..42270af 100644 --- a/src/mainboard/lippert/frontrunner-af/get_bus_conf.c +++ b/src/mainboard/lippert/frontrunner-af/get_bus_conf.c @@ -33,17 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; - void get_bus_conf(void) { @@ -52,23 +41,20 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/lippert/frontrunner-af/irq_tables.c b/src/mainboard/lippert/frontrunner-af/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/lippert/frontrunner-af/irq_tables.c +++ b/src/mainboard/lippert/frontrunner-af/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/lippert/toucan-af/get_bus_conf.c b/src/mainboard/lippert/toucan-af/get_bus_conf.c index 20dc3ae..eb40c54 100644 --- a/src/mainboard/lippert/toucan-af/get_bus_conf.c +++ b/src/mainboard/lippert/toucan-af/get_bus_conf.c @@ -33,16 +33,6 @@ u8 bus_sb800[6]; u32 apicid_sb800; -/* -* Here you only need to set value in pci1234 for HT-IO that could be installed or not -* You may need to preset pci1234 for HTIO board, -* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail -*/ -u32 pci1234x[] = { - 0x0000ff0, -}; - -u32 sbdn_sb800; void get_bus_conf(void) { @@ -51,22 +41,19 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sb800 = 0; memset(bus_sb800, 0, sizeof(bus_sb800)); -// bus_sb800[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_sb800[0] = (pci1234x[0] >> 16) & 0xff; /* sb800 */ - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sb800[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); } for (i = 0; i < 4; i++) { - dev = dev_find_slot(bus_sb800[0], PCI_DEVFN(sbdn_sb800 + 0x14, i)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, i)); if (dev) { bus_sb800[2 + i] = pci_read_config8(dev, PCI_SECONDARY_BUS); } diff --git a/src/mainboard/lippert/toucan-af/irq_tables.c b/src/mainboard/lippert/toucan-af/irq_tables.c index 840e7b1..12a64a8 100644 --- a/src/mainboard/lippert/toucan-af/irq_tables.c +++ b/src/mainboard/lippert/toucan-af/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sb800[6]; -extern unsigned long sbdn_sb800; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sb800[0]; - pirq->rtr_devfn = ((sbdn_sb800 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sb800[0], ((sbdn_sb800 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8qgi/get_bus_conf.c b/src/mainboard/supermicro/h8qgi/get_bus_conf.c index 549334e..8531e69 100644 --- a/src/mainboard/supermicro/h8qgi/get_bus_conf.c +++ b/src/mainboard/supermicro/h8qgi/get_bus_conf.c @@ -31,14 +31,12 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u32 sbdn_sp5100; void get_bus_conf(void) { device_t dev; int i; - sbdn_sp5100 = 0; for (i = 0; i < ARRAY_SIZE(bus_sp5100); i++) { bus_sp5100[i] = 0; @@ -47,7 +45,7 @@ void get_bus_conf(void) bus_sp5100[0] = 0; /* sp5100 */ - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8qgi/irq_tables.c b/src/mainboard/supermicro/h8qgi/irq_tables.c index 6b1e226..0af225c 100644 --- a/src/mainboard/supermicro/h8qgi/irq_tables.c +++ b/src/mainboard/supermicro/h8qgi/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sp5100[0]; - pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8qgi/mptable.c b/src/mainboard/supermicro/h8qgi/mptable.c index 754ed54..3793212 100644 --- a/src/mainboard/supermicro/h8qgi/mptable.c +++ b/src/mainboard/supermicro/h8qgi/mptable.c @@ -29,7 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> extern u8 bus_sp5100[2]; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -59,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; diff --git a/src/mainboard/supermicro/h8scm/get_bus_conf.c b/src/mainboard/supermicro/h8scm/get_bus_conf.c index 28c4bf7..46ed054 100644 --- a/src/mainboard/supermicro/h8scm/get_bus_conf.c +++ b/src/mainboard/supermicro/h8scm/get_bus_conf.c @@ -31,14 +31,12 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u32 sbdn_sp5100; void get_bus_conf(void) { device_t dev; int i; - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { bus_sp5100[i] = 0; @@ -47,7 +45,7 @@ void get_bus_conf(void) bus_sp5100[0] = 0; /* sp5100 */ - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/supermicro/h8scm/irq_tables.c b/src/mainboard/supermicro/h8scm/irq_tables.c index 9770e6d..8f72756 100644 --- a/src/mainboard/supermicro/h8scm/irq_tables.c +++ b/src/mainboard/supermicro/h8scm/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sp5100[0]; - pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -87,7 +85,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) slot_num = 0; /* pci bridge */ - write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/supermicro/h8scm/mptable.c b/src/mainboard/supermicro/h8scm/mptable.c index 754ed54..3793212 100644 --- a/src/mainboard/supermicro/h8scm/mptable.c +++ b/src/mainboard/supermicro/h8scm/mptable.c @@ -29,7 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> extern u8 bus_sp5100[2]; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -59,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0; diff --git a/src/mainboard/tyan/s8226/get_bus_conf.c b/src/mainboard/tyan/s8226/get_bus_conf.c index 7a6876b..087c042 100644 --- a/src/mainboard/tyan/s8226/get_bus_conf.c +++ b/src/mainboard/tyan/s8226/get_bus_conf.c @@ -30,7 +30,6 @@ * and acpi_tables busnum is default. */ u8 bus_sp5100[2]; -u32 sbdn_sp5100; void get_bus_conf(void); @@ -39,7 +38,6 @@ void get_bus_conf(void) device_t dev; int i; - sbdn_sp5100 = 0; for (i = 0; i < 0; i++) { bus_sp5100[i] = 0; @@ -48,7 +46,7 @@ void get_bus_conf(void) bus_sp5100[0] = 0; /* sp5100 */ - dev = dev_find_slot(bus_sp5100[0], PCI_DEVFN(sbdn_sp5100 + 0x14, 4)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); if (dev) { bus_sp5100[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); diff --git a/src/mainboard/tyan/s8226/irq_tables.c b/src/mainboard/tyan/s8226/irq_tables.c index 6b1e226..0af225c 100644 --- a/src/mainboard/tyan/s8226/irq_tables.c +++ b/src/mainboard/tyan/s8226/irq_tables.c @@ -44,8 +44,6 @@ static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, pirq_info->slot = slot; pirq_info->rfu = rfu; } -extern u8 bus_sp5100[2]; -extern unsigned long sbdn_sp5100; unsigned long write_pirq_routing_table(unsigned long addr) { @@ -71,8 +69,8 @@ unsigned long write_pirq_routing_table(unsigned long addr) pirq->signature = PIRQ_SIGNATURE; pirq->version = PIRQ_VERSION; - pirq->rtr_bus = bus_sp5100[0]; - pirq->rtr_devfn = ((sbdn_sp5100 + 0x14) << 3) | 4; + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); pirq->exclusive_irqs = 0; @@ -88,7 +86,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) /* pci bridge */ - write_pirq_info(pirq_info, bus_sp5100[0], ((sbdn_sp5100 + 0x14) << 3) | 4, + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; diff --git a/src/mainboard/tyan/s8226/mptable.c b/src/mainboard/tyan/s8226/mptable.c index 6a12f2b..3793212 100644 --- a/src/mainboard/tyan/s8226/mptable.c +++ b/src/mainboard/tyan/s8226/mptable.c @@ -29,8 +29,6 @@ #include <cpu/amd/amdfam10_sysconf.h> extern u8 bus_sp5100[2]; -extern u32 sbdn_sr5650; -extern u32 sbdn_sp5100; static void *smp_write_config_table(void *v) { @@ -60,7 +58,7 @@ static void *smp_write_config_table(void *v) apicid_sp5100 = CONFIG_MAX_CPUS + 1; apicid_sr5650 = apicid_sp5100 + 1; - dev = dev_find_slot(0, PCI_DEVFN(sbdn_sp5100 + 0x14, 0)); + dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); if (dev) { /* Set SP5100 IOAPIC ID */ dword = pci_read_config32(dev, 0x74) & 0xfffffff0;

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Patch set updated for coreboot: d68bef9 southbridge/via: Remove trailing whitespace
by HAOUAS Elyes 23 Jul '14

23 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6345 -gerrit commit d68bef99d3c98acd5c70bac903c2db8976742d32 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 23:33:40 2014 +0200 southbridge/via: Remove trailing whitespace Change-Id: I28deda21a7070ea6f14f973b66fd5dd119bc6225 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/via/vt8235/early_smbus.c | 35 ++++++++++++++++---------------- 1 file changed, 17 insertions(+), 18 deletions(-) diff --git a/src/southbridge/via/vt8235/early_smbus.c b/src/southbridge/via/vt8235/early_smbus.c index 96da2fa..c346b81 100644 --- a/src/southbridge/via/vt8235/early_smbus.c +++ b/src/southbridge/via/vt8235/early_smbus.c @@ -1,18 +1,18 @@ -#define SMBUS_IO_BASE 0xf00 - -#define SMBHSTSTAT 0x0 -#define SMBSLVSTAT 0x1 -#define SMBHSTCTL 0x2 -#define SMBHSTCMD 0x3 -#define SMBXMITADD 0x4 -#define SMBHSTDAT0 0x5 -#define SMBHSTDAT1 0x6 -#define SMBBLKDAT 0x7 -#define SMBSLVCTL 0x8 -#define SMBTRNSADD 0x9 -#define SMBSLVDATA 0xa -#define SMLINK_PIN_CTL 0xe -#define SMBUS_PIN_CTL 0xf +#define SMBUS_IO_BASE 0xf00 + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTL 0x2 +#define SMBHSTCMD 0x3 +#define SMBXMITADD 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBBLKDAT 0x7 +#define SMBSLVCTL 0x8 +#define SMBTRNSADD 0x9 +#define SMBSLVDATA 0xa +#define SMLINK_PIN_CTL 0xe +#define SMBUS_PIN_CTL 0xf /* Define register settings */ #define HOST_RESET 0xff @@ -21,8 +21,8 @@ #define SMBUS_TIMEOUT (100*1000*10) -#define I2C_TRANS_CMD 0x40 -#define CLOCK_SLAVE_ADDRESS 0x69 +#define I2C_TRANS_CMD 0x40 +#define CLOCK_SLAVE_ADDRESS 0x69 static void enable_smbus(void) { @@ -244,5 +244,4 @@ int smbus_read_byte(unsigned device, unsigned address, unsigned char *result) return host_status_register != 0x02; } - #endif

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Patch set updated for coreboot: 661c7cd amd/dinar & torpedo: Remove trailing whitespace
by HAOUAS Elyes 23 Jul '14

23 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6322 -gerrit commit 661c7cdde6e0fc22234fe38aede4fb27456f1b6c Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 23:45:01 2014 +0200 amd/dinar & torpedo: Remove trailing whitespace Change-Id: I4ac14c4f511eb6d56480e5167ce98b861cbed775 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/amd/dinar/agesawrapper.h | 72 +++++++++++++++++----------------- src/mainboard/amd/dinar/buildOpts.c | 22 +++++------ src/mainboard/amd/dinar/platform_cfg.h | 4 +- 3 files changed, 49 insertions(+), 49 deletions(-) diff --git a/src/mainboard/amd/dinar/agesawrapper.h b/src/mainboard/amd/dinar/agesawrapper.h index 70cf4f6..e4deb1b 100644 --- a/src/mainboard/amd/dinar/agesawrapper.h +++ b/src/mainboard/amd/dinar/agesawrapper.h @@ -25,44 +25,44 @@ #include "AGESA.h" /* Define AMD Ontario APPU SSID/SVID */ -#define AMD_APU_SVID 0x1022 -#define AMD_APU_SSID 0x1234 -#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS -#define MMIO_NP_BIT BIT7 +#define AMD_APU_SVID 0x1022 +#define AMD_APU_SSID 0x1234 +#define PCIE_BASE_ADDRESS CONFIG_MMCONF_BASE_ADDRESS +#define MMIO_NP_BIT BIT7 /* Hudson-2 ACPI PmIO Space Define */ -#define SB_ACPI_BASE_ADDRESS 0x0400 -#define ACPI_MMIO_BASE 0xFED80000 -#define SB_CFG_BASE 0x000 // DWORD -#define GPIO_BASE 0x100 // BYTE -#define SMI_BASE 0x200 // DWORD -#define PMIO_BASE 0x300 // DWORD -#define PMIO2_BASE 0x400 // BYTE -#define BIOS_RAM_BASE 0x500 // BYTE -#define CMOS_RAM_BASE 0x600 // BYTE -#define CMOS_BASE 0x700 // BYTE -#define ASF_BASE 0x900 // DWORD -#define SMBUS_BASE 0xA00 // DWORD -#define WATCHDOG_BASE 0xB00 // ?? -#define HPET_BASE 0xC00 // DWORD -#define IOMUX_BASE 0xD00 // BYTE -#define MISC_BASE 0xE00 -#define SERIAL_DEBUG_BASE 0x1000 -#define GFX_DAC_BASE 0x1400 -#define CEC_BASE 0x1800 -#define XHCI_BASE 0x1C00 -#define ACPI_SMI_DATA_PORT 0xB1 -#define R_SB_ACPI_PM1_STATUS 0x00 -#define R_SB_ACPI_PM1_ENABLE 0x02 -#define R_SB_ACPI_PM_CONTROL 0x04 -#define R_SB_ACPI_EVENT_STATUS 0x20 -#define R_SB_ACPI_EVENT_ENABLE 0x24 -#define B_PWR_BTN_STATUS BIT8 -#define B_WAKEUP_STATUS BIT15 -#define B_SCI_EN BIT0 -#define SB_PM_INDEX_PORT 0xCD6 -#define SB_PM_DATA_PORT 0xCD7 -#define SB_PMIOA_REG24 0x24 // AcpiMmioEn +#define SB_ACPI_BASE_ADDRESS 0x0400 +#define ACPI_MMIO_BASE 0xFED80000 +#define SB_CFG_BASE 0x000 // DWORD +#define GPIO_BASE 0x100 // BYTE +#define SMI_BASE 0x200 // DWORD +#define PMIO_BASE 0x300 // DWORD +#define PMIO2_BASE 0x400 // BYTE +#define BIOS_RAM_BASE 0x500 // BYTE +#define CMOS_RAM_BASE 0x600 // BYTE +#define CMOS_BASE 0x700 // BYTE +#define ASF_BASE 0x900 // DWORD +#define SMBUS_BASE 0xA00 // DWORD +#define WATCHDOG_BASE 0xB00 // ?? +#define HPET_BASE 0xC00 // DWORD +#define IOMUX_BASE 0xD00 // BYTE +#define MISC_BASE 0xE00 +#define SERIAL_DEBUG_BASE 0x1000 +#define GFX_DAC_BASE 0x1400 +#define CEC_BASE 0x1800 +#define XHCI_BASE 0x1C00 +#define ACPI_SMI_DATA_PORT 0xB1 +#define R_SB_ACPI_PM1_STATUS 0x00 +#define R_SB_ACPI_PM1_ENABLE 0x02 +#define R_SB_ACPI_PM_CONTROL 0x04 +#define R_SB_ACPI_EVENT_STATUS 0x20 +#define R_SB_ACPI_EVENT_ENABLE 0x24 +#define B_PWR_BTN_STATUS BIT8 +#define B_WAKEUP_STATUS BIT15 +#define B_SCI_EN BIT0 +#define SB_PM_INDEX_PORT 0xCD6 +#define SB_PM_DATA_PORT 0xCD7 +#define SB_PMIOA_REG24 0x24 // AcpiMmioEn #define MmioAddress( BaseAddr, Register ) \ ( (UINTN)BaseAddr + \ (UINTN)(Register) \ diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 958764e..88e3c6f 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -33,8 +33,8 @@ * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ */ #include <stdlib.h> -#include "AGESA.h" -#include "CommonReturns.h" +#include "AGESA.h" +#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE @@ -42,15 +42,15 @@ * coreboot enable -Wundef option, so we should make sure we have all contanstand defined */ /* MEMORY_BUS_SPEED */ -#define DDR400_FREQUENCY 200 ///< DDR 400 -#define DDR533_FREQUENCY 266 ///< DDR 533 -#define DDR667_FREQUENCY 333 ///< DDR 667 -#define DDR800_FREQUENCY 400 ///< DDR 800 -#define DDR1066_FREQUENCY 533 ///< DDR 1066 -#define DDR1333_FREQUENCY 667 ///< DDR 1333 -#define DDR1600_FREQUENCY 800 ///< DDR 1600 -#define DDR1866_FREQUENCY 933 ///< DDR 1866 -#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency +#define DDR400_FREQUENCY 200 ///< DDR 400 +#define DDR533_FREQUENCY 266 ///< DDR 533 +#define DDR667_FREQUENCY 333 ///< DDR 667 +#define DDR800_FREQUENCY 400 ///< DDR 800 +#define DDR1066_FREQUENCY 533 ///< DDR 1066 +#define DDR1333_FREQUENCY 667 ///< DDR 1333 +#define DDR1600_FREQUENCY 800 ///< DDR 1600 +#define DDR1866_FREQUENCY 933 ///< DDR 1866 +#define UNSUPPORTED_DDR_FREQUENCY 934 ///< Highest limit of DDR frequency /* QUANDRANK_TYPE */ #define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM diff --git a/src/mainboard/amd/dinar/platform_cfg.h b/src/mainboard/amd/dinar/platform_cfg.h index 94f4f0c..0aa3743 100644 --- a/src/mainboard/amd/dinar/platform_cfg.h +++ b/src/mainboard/amd/dinar/platform_cfg.h @@ -31,13 +31,13 @@ * Enable check for PCIe endpoint to be ready for PCI enumeration. * */ -//#define EPREADY_WORKAROUND_DISABLED +//#define EPREADY_WORKAROUND_DISABLED /** * Enable IOMMU support. Initialize IOMMU subsystem, generate IVRS ACPI table. * */ -#define IOMMU_SUPPORT_DISABLE //TODO: enable it +#define IOMMU_SUPPORT_DISABLE //TODO: enable it /** * Disable server PCIe hotplug support.

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Patch set updated for coreboot: 22e181d northbridge/amd: Remove trailing whitespace
by HAOUAS Elyes 23 Jul '14

23 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6316 -gerrit commit 22e181d1c3c92eeb7f5eb33c26142e5020ef2aa0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Jul 23 00:01:34 2014 +0200 northbridge/amd: Remove trailing whitespace Change-Id: Iccad59ebac1c47ee3fd16c0c1244b62184cfd1bf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/amd/amdht/AsPsDefs.h | 2 +- src/northbridge/amd/amdmct/wrappers/mcti.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index cf449f7..12588a6 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -294,6 +294,6 @@ #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT) -#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ +#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ #endif diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h index a92fdb8..97aec15 100644 --- a/src/northbridge/amd/amdmct/wrappers/mcti.h +++ b/src/northbridge/amd/amdmct/wrappers/mcti.h @@ -19,19 +19,19 @@ #define SERVER 0 -#define DESKTOP 1 +#define DESKTOP 1 //#define MOBILE 2 #define REV_F 0 #define REV_DR 1 -#define REV_FDR 2 +#define REV_FDR 2 /*---------------------------------------------------------------------------- COMMENT OUT ALL BUT 1 ----------------------------------------------------------------------------*/ -//#define BUILD_VERSION REV_F /*BIOS supports rev F only*/ -//#define BUILD_VERSION REV_DR /*BIOS supports rev 10 only*/ -//#define BUILD_VERSION REV_FDR /*BIOS supports both rev F and 10*/ +//#define BUILD_VERSION REV_F /*BIOS supports rev F only*/ +//#define BUILD_VERSION REV_DR /*BIOS supports rev 10 only*/ +//#define BUILD_VERSION REV_FDR /*BIOS supports both rev F and 10*/ /*---------------------------------------------------------------------------- COMMENT OUT ALL BUT 1

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Patch set updated for coreboot: 8a1cccf southbridge/amd: Remove trailing whitespace
by HAOUAS Elyes 23 Jul '14

23 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6334 -gerrit commit 8a1cccf392e58b3141c4810de212ca5540b2765e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Jul 22 23:12:38 2014 +0200 southbridge/amd: Remove trailing whitespace Change-Id: I25cdfe6b3c8067793620677c62251e78704f7851 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/southbridge/amd/agesa/hudson/early_setup.c | 4 +- src/southbridge/amd/agesa/hudson/smbus.c | 4 +- src/southbridge/amd/cimx/sb800/SBPLATFORM.h | 8 +-- src/southbridge/amd/cimx/sb900/SbPlatform.h | 76 +++++++++++++------------- src/southbridge/amd/sb800/early_setup.c | 4 +- src/southbridge/amd/sb800/smbus.c | 4 +- 6 files changed, 50 insertions(+), 50 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index d8fdc27..039df20 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _HUDSON_EARLY_SETUP_C_ -#define _HUDSON_EARLY_SETUP_C_ +#ifndef _HUDSON_EARLY_SETUP_C_ +#define _HUDSON_EARLY_SETUP_C_ #include <stdint.h> #include <arch/io.h> diff --git a/src/southbridge/amd/agesa/hudson/smbus.c b/src/southbridge/amd/agesa/hudson/smbus.c index 0c04158..519c85d 100644 --- a/src/southbridge/amd/agesa/hudson/smbus.c +++ b/src/southbridge/amd/agesa/hudson/smbus.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _HUDSON_SMBUS_C_ -#define _HUDSON_SMBUS_C_ +#ifndef _HUDSON_SMBUS_C_ +#define _HUDSON_SMBUS_C_ #include <io.h> #include <stdint.h> diff --git a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h index ea3f719..b26d429 100644 --- a/src/southbridge/amd/cimx/sb800/SBPLATFORM.h +++ b/src/southbridge/amd/cimx/sb800/SBPLATFORM.h @@ -21,8 +21,8 @@ * */ -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> @@ -162,7 +162,7 @@ typedef union _PCI_ADDR { #include <spi-generic.h> #endif -#define BIOSRAM_INDEX 0xcd4 -#define BIOSRAM_DATA 0xcd5 +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/cimx/sb900/SbPlatform.h b/src/southbridge/amd/cimx/sb900/SbPlatform.h index 176ad87..6371bcd 100644 --- a/src/southbridge/amd/cimx/sb900/SbPlatform.h +++ b/src/southbridge/amd/cimx/sb900/SbPlatform.h @@ -21,8 +21,8 @@ * */ -#ifndef _AMD_SBPLATFORM_H_ -#define _AMD_SBPLATFORM_H_ +#ifndef _AMD_SBPLATFORM_H_ +#define _AMD_SBPLATFORM_H_ #include <stddef.h> @@ -107,48 +107,48 @@ typedef union _PCI_ADDR { * FusionMsgCMultiCore CIMx take over User (Setup Option) User (Setup Option) Disable * FusionMsgCStage CIMx take over User (Setup Option) User (Setup Option) Disable */ -#define SB_CIMx_PARAMETER 0x02 +#define SB_CIMx_PARAMETER 0x02 // Generic -#define cimSpreadSpectrumDefault TRUE +#define cimSpreadSpectrumDefault TRUE #define cimSpreadSpectrumTypeDefault 0x00 // Normal -#define cimHpetTimerDefault TRUE -#define cimHpetMsiDisDefault FALSE // Enable -#define cimIrConfigDefault 0x00 // Disable -#define cimSpiFastReadEnableDefault 0x00 // Disable -#define cimSpiFastReadSpeedDefault 0x00 // NULL +#define cimHpetTimerDefault TRUE +#define cimHpetMsiDisDefault FALSE // Enable +#define cimIrConfigDefault 0x00 // Disable +#define cimSpiFastReadEnableDefault 0x00 // Disable +#define cimSpiFastReadSpeedDefault 0x00 // NULL // GPP/AB Controller -#define cimNbSbGen2Default TRUE -#define cimAlinkPhyPllPowerDownDefault TRUE -#define cimResetCpuOnSyncFloodDefault TRUE -#define cimGppGen2Default FALSE -#define cimGppMemWrImproveDefault TRUE -#define cimGppPortAspmDefault FALSE -#define cimGppLaneReversalDefault FALSE -#define cimGppPhyPllPowerDownDefault TRUE +#define cimNbSbGen2Default TRUE +#define cimAlinkPhyPllPowerDownDefault TRUE +#define cimResetCpuOnSyncFloodDefault TRUE +#define cimGppGen2Default FALSE +#define cimGppMemWrImproveDefault TRUE +#define cimGppPortAspmDefault FALSE +#define cimGppLaneReversalDefault FALSE +#define cimGppPhyPllPowerDownDefault TRUE // USB Controller -#define cimUsbPhyPowerDownDefault FALSE +#define cimUsbPhyPowerDownDefault FALSE // GEC Controller -#define cimSBGecDebugBusDefault FALSE -#define cimSBGecPwrDefault 0x03 +#define cimSBGecDebugBusDefault FALSE +#define cimSBGecPwrDefault 0x03 // Sata Controller -#define cimSataSetMaxGen2Default 0x00 -#define cimSATARefClkSelDefault 0x10 -#define cimSATARefDivSelDefault 0x80 -#define cimSataAggrLinkPmCapDefault TRUE -#define cimSataPortMultCapDefault TRUE -#define cimSataPscCapDefault 0x00 // Enable -#define cimSataSscCapDefault 0x00 // Enable -#define cimSataFisBasedSwitchingDefault FALSE -#define cimSataCccSupportDefault FALSE -#define cimSataClkAutoOffDefault FALSE -#define cimNativepciesupportDefault FALSE +#define cimSataSetMaxGen2Default 0x00 +#define cimSATARefClkSelDefault 0x10 +#define cimSATARefDivSelDefault 0x80 +#define cimSataAggrLinkPmCapDefault TRUE +#define cimSataPortMultCapDefault TRUE +#define cimSataPscCapDefault 0x00 // Enable +#define cimSataSscCapDefault 0x00 // Enable +#define cimSataFisBasedSwitchingDefault FALSE +#define cimSataCccSupportDefault FALSE +#define cimSataClkAutoOffDefault FALSE +#define cimNativepciesupportDefault FALSE // Fusion Related -#define cimAcDcMsgDefault FALSE -#define cimTimerTickTrackDefault FALSE -#define cimClockInterruptTagDefault FALSE -#define cimOhciTrafficHandingDefault FALSE -#define cimEhciTrafficHandingDefault FALSE -#define cimFusionMsgCMultiCoreDefault FALSE -#define cimFusionMsgCStageDefault FALSE +#define cimAcDcMsgDefault FALSE +#define cimTimerTickTrackDefault FALSE +#define cimClockInterruptTagDefault FALSE +#define cimOhciTrafficHandingDefault FALSE +#define cimEhciTrafficHandingDefault FALSE +#define cimFusionMsgCMultiCoreDefault FALSE +#define cimFusionMsgCStageDefault FALSE #endif // _AMD_SBPLATFORM_H_ diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index ef0548c..5244490 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB800_EARLY_SETUP_C_ -#define _SB800_EARLY_SETUP_C_ +#ifndef _SB800_EARLY_SETUP_C_ +#define _SB800_EARLY_SETUP_C_ #include <reset.h> #include <arch/acpi.h> diff --git a/src/southbridge/amd/sb800/smbus.c b/src/southbridge/amd/sb800/smbus.c index c1a9ded..5c4152a 100644 --- a/src/southbridge/amd/sb800/smbus.c +++ b/src/southbridge/amd/sb800/smbus.c @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SB800_SMBUS_C_ -#define _SB800_SMBUS_C_ +#ifndef _SB800_SMBUS_C_ +#define _SB800_SMBUS_C_ #include "smbus.h"

1 0

Patch set updated for coreboot: 793d878 src/mainboard: Remove trailing whitespace
by HAOUAS Elyes 23 Jul '14

23 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6308 -gerrit commit 793d878a11ce667c82e65721fb737c93ce587f60 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Jul 21 08:07:19 2014 +0200 src/mainboard: Remove trailing whitespace Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/advansus/a785e-i/romstage.c | 10 +++++----- src/mainboard/amd/bimini_fam10/romstage.c | 10 +++++----- src/mainboard/amd/dinar/buildOpts.c | 4 ++-- src/mainboard/amd/dinar/romstage.c | 4 ++-- src/mainboard/amd/inagua/romstage.c | 4 ++-- src/mainboard/amd/mahogany_fam10/romstage.c | 10 +++++----- src/mainboard/amd/olivehill/buildOpts.c | 2 +- src/mainboard/amd/olivehill/romstage.c | 4 ++-- src/mainboard/amd/parmer/buildOpts.c | 2 +- src/mainboard/amd/parmer/romstage.c | 4 ++-- src/mainboard/amd/persimmon/romstage.c | 4 ++-- src/mainboard/amd/serengeti_cheetah/irq_tables.c | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 12 ++++++------ src/mainboard/amd/south_station/romstage.c | 4 ++-- src/mainboard/amd/thatcher/buildOpts.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 4 ++-- src/mainboard/amd/tilapia_fam10/romstage.c | 10 +++++----- src/mainboard/amd/torpedo/buildOpts.c | 4 ++-- src/mainboard/amd/torpedo/romstage.c | 4 ++-- src/mainboard/amd/union_station/romstage.c | 4 ++-- src/mainboard/arima/hdama/mptable.c | 4 ++-- src/mainboard/artecgroup/dbe61/romstage.c | 6 +++--- src/mainboard/asrock/e350m1/romstage.c | 4 ++-- src/mainboard/asrock/imb-a180/buildOpts.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 4 ++-- src/mainboard/asus/a8v-e_deluxe/romstage.c | 2 +- src/mainboard/asus/a8v-e_se/romstage.c | 2 +- src/mainboard/asus/f2a85-m/romstage.c | 4 ++-- src/mainboard/asus/k8v-x/romstage.c | 2 +- src/mainboard/asus/m2v-mx_se/romstage.c | 4 ++-- src/mainboard/asus/m2v/romstage.c | 2 +- src/mainboard/asus/m4a78-em/romstage.c | 10 +++++----- src/mainboard/asus/m4a785-m/romstage.c | 10 +++++----- src/mainboard/asus/m5a88-v/romstage.c | 10 +++++----- src/mainboard/avalue/eax-785e/romstage.c | 10 +++++----- src/mainboard/gigabyte/ma785gm/romstage.c | 10 +++++----- src/mainboard/gigabyte/ma785gmt/romstage.c | 10 +++++----- src/mainboard/gigabyte/ma78gm/romstage.c | 10 +++++----- src/mainboard/gizmosphere/gizmo/romstage.c | 4 ++-- src/mainboard/hp/dl145_g3/mptable.c | 2 +- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 ++-- src/mainboard/iei/kino-780am2-fam10/romstage.c | 10 +++++----- src/mainboard/iwave/iWRainbowG6/romstage.c | 2 +- src/mainboard/iwill/dk8_htx/irq_tables.c | 4 ++-- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 4 ++-- src/mainboard/jetway/pa78vm5/romstage.c | 10 +++++----- src/mainboard/lippert/frontrunner-af/romstage.c | 4 ++-- src/mainboard/lippert/toucan-af/romstage.c | 4 ++-- src/mainboard/supermicro/h8dmr_fam10/romstage.c | 10 +++++----- src/mainboard/supermicro/h8qgi/agesawrapper.c | 4 ++-- src/mainboard/supermicro/h8qgi/romstage.c | 4 ++-- src/mainboard/supermicro/h8qme_fam10/romstage.c | 10 +++++----- src/mainboard/supermicro/h8scm/agesawrapper.c | 4 ++-- src/mainboard/supermicro/h8scm/romstage.c | 4 ++-- src/mainboard/supermicro/h8scm_fam10/romstage.c | 10 +++++----- src/mainboard/tyan/s2882/irq_tables.c | 6 +++--- src/mainboard/tyan/s8226/agesawrapper.c | 4 ++-- src/mainboard/tyan/s8226/romstage.c | 4 ++-- src/mainboard/via/epia-m700/romstage.c | 4 ++-- src/mainboard/via/epia-m850/romstage.c | 2 +- 60 files changed, 163 insertions(+), 163 deletions(-) diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 2402798..20cb703 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -115,10 +115,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 5c5b44f..e6646f5 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -107,10 +107,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -156,7 +156,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 958764e..3aa4e91 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -33,8 +33,8 @@ * @e \$Revision: 6049 $ @e \$Date: 2008-05-14 01:58:02 -0500 (Wed, 14 May 2008) $ */ #include <stdlib.h> -#include "AGESA.h" -#include "CommonReturns.h" +#include "AGESA.h" +#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 1156ec4..842b4f0 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); if(boot_cpu()) { post_code(0x34); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 489e81f..468f896 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 278a3bd..13470e2 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 98151a2..5aa1768 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -250,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList -//#include "KeralaInstall.h" +//#include "KeralaInstall.h" /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 718a057..326a41a 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -68,8 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 3db1e47..a2b0f87 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -251,7 +251,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList -//#include "VirgoInstall.h" +//#include "VirgoInstall.h" /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 7bd3984..7c143f4 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -59,8 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index b0fd12c..5d530b7 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/amd/serengeti_cheetah/irq_tables.c b/src/mainboard/amd/serengeti_cheetah/irq_tables.c index 0dd0dac..4d42f47 100644 --- a/src/mainboard/amd/serengeti_cheetah/irq_tables.c +++ b/src/mainboard/amd/serengeti_cheetah/irq_tables.c @@ -98,13 +98,13 @@ unsigned long write_pirq_routing_table(unsigned long addr) } //pci bridge - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); + printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); + printk(BIOS_DEBUG, "setting Onboard AMD USB\n"); static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 09b86bb..6388b42 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -64,7 +64,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) int ret,i; u8 device = ctrl->spd_switch_addr; - printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id); + printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id); /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ i=2; @@ -215,10 +215,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -278,7 +278,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index a66c2b8..98a042a 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index bc2ff12..07ad168 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -251,7 +251,7 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &TrinityApMtrrSettingsList -//#include "VirgoInstall.h" +//#include "VirgoInstall.h" /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index f3108ff..8ee42bd 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 6e28cbd..f5ac2e0 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index 8b34720..31d1fef 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -34,8 +34,8 @@ */ #include <stdlib.h> -#include "AGESA.h" -#include "CommonReturns.h" +#include "AGESA.h" +#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index febe120..7ed520a 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -68,8 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x36); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 531d3b4..168b57f 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -65,8 +65,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index dc5fd45..6ee2704 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -217,7 +217,7 @@ static void reboot_if_hotswap(void) printk(BIOS_DEBUG, "Looking for bad PCIX MHz input\n"); dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (!dev) - printk(BIOS_DEBUG, "Couldn't find %02x:02.0 \n", bus_chain_0); + printk(BIOS_DEBUG, "Couldn't find %02x:02.0\n", bus_chain_0); else { data = pci_read_config32(dev, 0xa0); if(!(((data>>16)&0x03)==0x03)) { @@ -228,7 +228,7 @@ static void reboot_if_hotswap(void) printk(BIOS_DEBUG, "Looking for bad Hot Swap Enable\n"); dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (!dev) - printk(BIOS_DEBUG, "Couldn't find %02x:01.0 \n", bus_chain_0); + printk(BIOS_DEBUG, "Couldn't find %02x:01.0\n", bus_chain_0); else { data = pci_read_config32(dev, 0x48); if(data & 0x0c) { diff --git a/src/mainboard/artecgroup/dbe61/romstage.c b/src/mainboard/artecgroup/dbe61/romstage.c index 073d2b8..7276b30 100644 --- a/src/mainboard/artecgroup/dbe61/romstage.c +++ b/src/mainboard/artecgroup/dbe61/romstage.c @@ -101,7 +101,7 @@ void main(unsigned long bist) print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); - print_debug(" \n"); + print_debug("\n"); msr = rdmsr(MC_CF1017_DATA); print_debug("MC_CF1017_DATA: "); @@ -110,7 +110,7 @@ void main(unsigned long bist) print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); - print_debug(" \n"); + print_debug("\n"); msr = rdmsr(MC_CF8F_DATA); print_debug("MC_CF8F_DATA: "); @@ -120,6 +120,6 @@ void main(unsigned long bist) print_debug(":"); print_debug_hex32(msr.lo); msr = rdmsr(MC_CF8F_DATA); - print_debug(" \n"); + print_debug("\n"); #endif } diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index a0a2912..5223360 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -71,8 +71,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 520da8b..55df22a 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -250,7 +250,7 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList -//#include "KeralaInstall.h" +//#include "KeralaInstall.h" /* Include the files that instantiate the configuration definitions. */ #include "cpuRegisters.h" diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index b750e44..37f14f6 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -92,8 +92,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ int i; diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 1dea57b..c137b14 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -64,7 +64,7 @@ void soft_reset(void) uint8_t tmp; set_bios_reset(); - print_debug("soft reset \n"); + print_debug("soft reset\n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index abe5f84..5c78ab1 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -64,7 +64,7 @@ void soft_reset(void) uint8_t tmp; set_bios_reset(); - print_debug("soft reset \n"); + print_debug("soft reset\n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 71455fd..bdf03a7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -124,8 +124,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4d6bd60..15b8682 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -62,7 +62,7 @@ void soft_reset(void) uint8_t tmp; set_bios_reset(); - print_debug("soft reset \n"); + print_debug("soft reset\n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index d374828..adcdfc7 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -91,7 +91,7 @@ void soft_reset(void) uint8_t tmp; set_bios_reset(); - print_debug("soft reset \n"); + print_debug("soft reset\n"); /* PCI reset */ tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); @@ -134,7 +134,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); enable_rom_decode(); - printk(BIOS_INFO, "now booting... \n"); + printk(BIOS_INFO, "now booting...\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index a2c6a03..30ba468 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -234,7 +234,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) m2v_it8712f_gpio_init(); ite_enable_3vsbsw(GPIO_DEV); - printk(BIOS_INFO, "now booting... \n"); + printk(BIOS_INFO, "now booting...\n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 2620a13..0a03d59 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -111,10 +111,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index ff04dc7..84d2b97 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -111,10 +111,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -178,7 +178,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 9fca93f..4753bb0 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -112,10 +112,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -160,7 +160,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 883bd11..65f499b 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -116,10 +116,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -164,7 +164,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 @@ -177,7 +177,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 62a9211..a0f9e76 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -106,10 +106,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 62a9211..a0f9e76 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -106,10 +106,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -173,7 +173,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index a437009..b9d27f7 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 420efc3..b4af6d4 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -84,8 +84,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/hp/dl145_g3/mptable.c b/src/mainboard/hp/dl145_g3/mptable.c index bbd8405..6c71bad 100644 --- a/src/mainboard/hp/dl145_g3/mptable.c +++ b/src/mainboard/hp/dl145_g3/mptable.c @@ -124,7 +124,7 @@ static void *smp_write_config_table(void *v) printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0xb); //USB - printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x \n",sysconf.sbdn, m->bus_bcm5785_0); + printk(BIOS_DEBUG, "sysconf.sbdn: %d on bus: %x\n",sysconf.sbdn, m->bus_bcm5785_0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_bcm5785_0, (0x03<<2)|0, m->apicid_bcm5785[0], 0xa); //VGA diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 7855cd1..ea848b4 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -56,8 +56,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 612ff1a..e1230e5 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -109,10 +109,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -158,7 +158,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/iwave/iWRainbowG6/romstage.c b/src/mainboard/iwave/iWRainbowG6/romstage.c index 39fce07..4da6fe7 100644 --- a/src/mainboard/iwave/iWRainbowG6/romstage.c +++ b/src/mainboard/iwave/iWRainbowG6/romstage.c @@ -291,7 +291,7 @@ static void sch_shadow_CMC(void) /* FIXME: proper dest, proper src, and wbinvd, too */ memcpy((void *)CMC_SHADOW, (void *)0xfffd0000, 64 * 1024); - // __asm__ volatile ("wbinvd \n" + // __asm__ volatile ("wbinvd\n" //); printk(BIOS_DEBUG, "copy done "); memcpy((void *)0x3f5f0000, (void *)0x3faf0000, 64 * 1024); diff --git a/src/mainboard/iwill/dk8_htx/irq_tables.c b/src/mainboard/iwill/dk8_htx/irq_tables.c index 0dd0dac..4d42f47 100644 --- a/src/mainboard/iwill/dk8_htx/irq_tables.c +++ b/src/mainboard/iwill/dk8_htx/irq_tables.c @@ -98,13 +98,13 @@ unsigned long write_pirq_routing_table(unsigned long addr) } //pci bridge - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); + printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 }; pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4); write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); + printk(BIOS_DEBUG, "setting Onboard AMD USB\n"); static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11}; pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0); write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 4b2f711..7f91714 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -92,8 +92,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 044d0d8..5121605 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -114,10 +114,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -163,7 +163,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -181,7 +181,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif rs780_htinit(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 05c5019..61fd6bd 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -75,8 +75,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 595faa0..f9b9adf 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -76,8 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* Load MPB */ val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); AGESAWRAPPER(amdinitmmio); diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index cd185f3..b393c34 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -130,10 +130,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) report_bist_failure(bist); val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -176,7 +176,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only @@ -195,7 +195,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif diff --git a/src/mainboard/supermicro/h8qgi/agesawrapper.c b/src/mainboard/supermicro/h8qgi/agesawrapper.c index 8ee89a7..294410c 100644 --- a/src/mainboard/supermicro/h8qgi/agesawrapper.c +++ b/src/mainboard/supermicro/h8qgi/agesawrapper.c @@ -1000,7 +1000,7 @@ static void agesa_critical(EVENT_PARAMS *event) break; case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", + printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", (unsigned int)event->DataParam1, (unsigned int)event->DataParam2, (unsigned int)event->DataParam3); @@ -1184,6 +1184,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } - printk(BIOS_DEBUG, "exit %s \n", __func__); + printk(BIOS_DEBUG, "exit %s\n", __func__); return Status; } diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index 4273fdb..425f677 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -62,8 +62,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 9898a25..24ecb5d 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -197,10 +197,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) report_bist_failure(bist); val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only * need to be done once.*/ @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif init_timer(); // Need to use TMICT to synconize FID/VID diff --git a/src/mainboard/supermicro/h8scm/agesawrapper.c b/src/mainboard/supermicro/h8scm/agesawrapper.c index c52197b..b3c0bd2 100644 --- a/src/mainboard/supermicro/h8scm/agesawrapper.c +++ b/src/mainboard/supermicro/h8scm/agesawrapper.c @@ -1000,7 +1000,7 @@ static void agesa_critical(EVENT_PARAMS *event) break; case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", + printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", (unsigned int)event->DataParam1, (unsigned int)event->DataParam2, (unsigned int)event->DataParam3); @@ -1184,6 +1184,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } - printk(BIOS_DEBUG, "exit %s \n", __func__); + printk(BIOS_DEBUG, "exit %s\n", __func__); return Status; } diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 4084add..da92d97 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -61,8 +61,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 216e5df..fdf49d8 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -120,10 +120,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -171,7 +171,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -189,7 +189,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif sr5650_htinit(); diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c index 20c10da..218ddce 100644 --- a/src/mainboard/tyan/s2882/irq_tables.c +++ b/src/mainboard/tyan/s2882/irq_tables.c @@ -197,13 +197,13 @@ unsigned long write_pirq_routing_table(unsigned long addr) } } - printk(BIOS_DEBUG, "setting Onboard AMD Southbridge \n"); + printk(BIOS_DEBUG, "setting Onboard AMD Southbridge\n"); static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 }; pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4); write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0); pirq_info++; slot_num++; - printk(BIOS_DEBUG, "setting Onboard AMD USB \n"); + printk(BIOS_DEBUG, "setting Onboard AMD USB\n"); static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0); @@ -239,7 +239,7 @@ unsigned long write_pirq_routing_table(unsigned long addr) write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0); pirq_info++; slot_num++; - printk(BIOS_DEBUG, "setting Slot 5 \n"); + printk(BIOS_DEBUG, "setting Slot 5\n"); static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 }; pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4); write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0); diff --git a/src/mainboard/tyan/s8226/agesawrapper.c b/src/mainboard/tyan/s8226/agesawrapper.c index 425054c..9f66b4c 100644 --- a/src/mainboard/tyan/s8226/agesawrapper.c +++ b/src/mainboard/tyan/s8226/agesawrapper.c @@ -1007,7 +1007,7 @@ static void agesa_critical(EVENT_PARAMS *event) break; case HT_EVENT_COH_PROCESSOR_TYPE_MIX: - printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX \n", + printk(BIOS_DEBUG, "Socket %x Link %x TotalSockets %x, HT_EVENT_COH_PROCESSOR_TYPE_MIX\n", (unsigned int)event->DataParam1, (unsigned int)event->DataParam2, (unsigned int)event->DataParam3); @@ -1191,6 +1191,6 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) Status = AmdReadEventLog(&AmdEventParams); } - printk(BIOS_DEBUG, "exit %s \n", __func__); + printk(BIOS_DEBUG, "exit %s\n", __func__); return Status; } diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index 9624af8..dc3bde2 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -61,8 +61,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) console_init(); val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index e01fd4b..6198cda 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -117,7 +117,7 @@ static void enable_mainboard_devices(void) pci_write_config8(dev, 0x5b, 0x01); #endif - print_debug("In enable_mainboard_devices \n"); + print_debug("In enable_mainboard_devices\n"); /* Enable P2P Bridge Header for external PCI bus. */ dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); @@ -634,7 +634,7 @@ void main(unsigned long bist) ); #endif /* This can have function call, because no variable used before this. */ - print_debug("Copy memory to high memory to protect s3 wakeup vector code \n"); + print_debug("Copy memory to high memory to protect s3 wakeup vector code\n"); memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - 0x100000), (unsigned char *)0, 0xa0000); memcpy((unsigned char *)((*(u32 *) WAKE_MEM_INFO) - 64 * 1024 - diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 9368028..ece64d8 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -55,7 +55,7 @@ void main(unsigned long bist) /* Serial console is easy to take care of */ fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); - print_debug("Console initialized. \n"); + print_debug("Console initialized.\n"); vx900_cpu_bus_interface_setup();

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Patch set updated for coreboot: 549c925 mainboard/msi/ms7135/devicetree.cb: Remove trailing whitespace
by HAOUAS Elyes 23 Jul '14

23 Jul '14

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/6349 -gerrit commit 549c92571790324b09b0cdc5ebeba5933878c7d3 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Jul 23 10:04:37 2014 +0200 mainboard/msi/ms7135/devicetree.cb: Remove trailing whitespace Change-Id: I4151e8ac8903d0daa1e7b12ecadbab8ff7adaaeb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/msi/ms7135/devicetree.cb | 144 ++++++++++++++++----------------- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/src/mainboard/msi/ms7135/devicetree.cb b/src/mainboard/msi/ms7135/devicetree.cb index a0c39b4..e3f0c8c 100644 --- a/src/mainboard/msi/ms7135/devicetree.cb +++ b/src/mainboard/msi/ms7135/devicetree.cb @@ -1,75 +1,75 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_754 # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_754 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end - device domain 0 on # PCI domain - subsystemid 0x1462 0x7135 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/ck804 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627thg # Super I/O - device pnp 4e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 4e.1 on # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 4e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 4e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 - device pnp 4e.8 off end # GPIO 2 - device pnp 4e.9 off end # GPIO 3, GPIO 4 - device pnp 4e.a off end # ACPI - device pnp 4e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end # SMbus - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI), N/A - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 (N/A) - device pci c.0 off end # PCI E 2 (N/A) - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end + device domain 0 on # PCI domain + subsystemid 0x1462 0x7135 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627thg # Super I/O + device pnp 4e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 4e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 + device pnp 4e.8 off end # GPIO 2 + device pnp 4e.9 off end # GPIO 3, GPIO 4 + device pnp 4e.a off end # ACPI + device pnp 4e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end # SMbus + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # Onboard audio (ACI) + device pci 4.1 off end # Onboard modem (MCI), N/A + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 (N/A) + device pci c.0 off end # PCI E 2 (N/A) + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end end

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coreboot-gerrit July 2014