coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: a0f4493 mainboard/*: Convert to generic ITE superio romstage component
by Edward O'Callaghan 23 May '14

23 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5737 -gerrit commit a0f44938ec317cfc8099047228d0ab6682114c68 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 19:15:08 2014 +1000 mainboard/*: Convert to generic ITE superio romstage component NOTFORMERGE Convert mainboard's that use model specific romstage functions of it8712f to the generic framework by following the reasoning of: HASHHERE ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2v-mx_se/romstage.c | 4 ++-- src/mainboard/asus/m2v/romstage.c | 4 ++-- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 0085bb4..92ff34e 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -129,8 +129,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); - it8712f_enable_3vsbsw(); + ite_kill_watchdog(); + ite_enable_3vsbsw(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index acf8f91..3bbfb28 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -227,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); enable_rom_decode(); m2v_bus_init(); m2v_it8712f_gpio_init(); - it8712f_enable_3vsbsw(); + ite_enable_3vsbsw(); printk(BIOS_INFO, "now booting... \n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 93810d2..38f97b0 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b360636..14665eb 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 35351b1..fa37395 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -89,7 +89,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 7455df2..9010c4b 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -84,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init();

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New patch to review for coreboot: 07dc99f northbridge/intel/haswell: Silence unused func complaints
by Edward O'Callaghan 23 May '14

23 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5834 -gerrit commit 07dc99fbf563c7e41a9b99b4e6f3135306360dfe Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:09:50 2014 +1000 northbridge/intel/haswell: Silence unused func complaints Clang complains that the function 'to_flash_offset' is unused. Change-Id: I129cf8349e9ee2ebd4a4d0f69a6d830bdbc4ebf0 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/haswell/mrccache.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 88dbf7f..3e847cd 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -33,10 +33,12 @@ #include <vendorcode/google/chromeos/fmap.h> #endif +#if !defined(__PRE_RAM__) /* convert a pointer to flash area into the offset inside the flash */ static inline u32 to_flash_offset(struct spi_flash *flash, void *p) { return ((u32)p + flash->size); } +#endif /* !defined(__PRE_RAM__) */ static struct mrc_data_container *next_mrc_block( struct mrc_data_container *mrc_cache) @@ -124,6 +126,7 @@ static struct mrc_data_container *find_current_mrc_cache_local /* SPI code needs malloc/free. * Also unknown if writing flash from XIP-flash code is a good idea */ + #if !defined(__PRE_RAM__) /* find the first empty block in the MRC cache area. * If there's none, return NULL. @@ -228,7 +231,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; -#endif +#endif /* !defined(__PRE_RAM__) */ struct mrc_data_container *find_current_mrc_cache(void) {

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New patch to review for coreboot: 6ca6e4d mainboard/amd/torpedo Incorrect usage of logical over bitwise and
by Edward O'Callaghan 23 May '14

23 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5833 -gerrit commit 6ca6e4d748b728b9b5332b3154f1f3c1cc7b51a7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:01:38 2014 +1000 mainboard/amd/torpedo Incorrect usage of logical over bitwise and Spotted by Clang Change-Id: I26201c7f5e421c38d3965d8e7e62c4a8e670e449 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/torpedo/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/amd/torpedo/gpio.c b/src/mainboard/amd/torpedo/gpio.c index d2d2bea..a8aba5e 100644 --- a/src/mainboard/amd/torpedo/gpio.c +++ b/src/mainboard/amd/torpedo/gpio.c @@ -255,7 +255,7 @@ gpioEarlyInit( // WAIT POWER READY: GPIO28 (MXM_PWRGD) //while (!(Mmio8 (GpioMmioAddr, SB_GPIO_REG28) && BIT7)){} ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); - while (!(Data8 && BIT7)) + while (!(Data8 & BIT7)) { ReadMEM (GpioMmioAddr + SB_GPIO_REG28, AccWidthUint8, &Data8); }

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New patch to review for coreboot: e21abee southbridge/amd/cimx/sb900: Unused func smbus_delay()
by Edward O'Callaghan 23 May '14

23 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5832 -gerrit commit e21abee4fac183bb82027b9325f21996337f9780 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:03:39 2014 +1000 southbridge/amd/cimx/sb900: Unused func smbus_delay() Spotted by Clang Change-Id: I14c099625db6f38fd0630b8864cf2a702b81d353 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/cimx/sb900/smbus.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/southbridge/amd/cimx/sb900/smbus.c b/src/southbridge/amd/cimx/sb900/smbus.c index 650df5c..fb8e3fb 100644 --- a/src/southbridge/amd/cimx/sb900/smbus.c +++ b/src/southbridge/amd/cimx/sb900/smbus.c @@ -22,11 +22,6 @@ #include "smbus.h" #include <console/console.h> /* printk */ -static inline void smbus_delay(void) -{ - outb(inb(0x80), 0x80); -} - static int smbus_wait_until_ready(u32 smbus_io_base) { u32 loops;

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New patch to review for coreboot: a97fded mainboard/google/link: Fix usage of GNU field designator ext
by Edward O'Callaghan 23 May '14

23 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5831 -gerrit commit a97fded0a720347ba7ea642298a5a28f7ab684fa Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:16:57 2014 +1000 mainboard/google/link: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Id967f6057759cf0603c84514d32b067c3658306f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/link/romstage.c | 44 ++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 66d2067..2f17880 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -157,32 +157,32 @@ void main(unsigned long bist) u16 pm1_sts; struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: CONFIG_MMCONF_BASE_ADDRESS, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: CONFIG_HPET_ADDRESS, - rcba: DEFAULT_RCBABASE, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - thermalbase: 0xfed08000, - system_type: 0, // 0 Mobile, 1 Desktop/Server - tseg_size: CONFIG_SMM_TSEG_SIZE, - ts_addresses: { 0x00, 0x00, 0x00, 0x00 }, - ec_present: 1, - ddr3lv_support: 1, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .ddr3lv_support = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, - max_ddr3_freq: 1600, - usb_port_config: { + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { /* Empty and onboard Ports 0-7, set to un-used pin OC3 */ { 0, 3, 0x0000 }, /* P0: Empty */ { 1, 0, 0x0040 }, /* P1: Left USB 1 (OC0) */

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New patch to review for coreboot: e6b2be0 mainboard/google/falco: Fix usage of GNU field designator ext
by Edward O'Callaghan 23 May '14

23 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5830 -gerrit commit e6b2be03a2ac32cf811700b3c344b50d5c8fc0a9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:15:16 2014 +1000 mainboard/google/falco: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I4e5f2d7e8e6b76703fccce38fc7e3165d763e97f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/google/falco/romstage.c | 48 +++++++++++++++++------------------ 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index ca843e8..11e94fc 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -108,34 +108,34 @@ static void copy_spd(struct pei_data *peid) void mainboard_romstage_entry(unsigned long bist) { struct pei_data pei_data = { - pei_version: PEI_VERSION, - mchbar: DEFAULT_MCHBAR, - dmibar: DEFAULT_DMIBAR, - epbar: DEFAULT_EPBAR, - pciexbar: DEFAULT_PCIEXBAR, - smbusbar: SMBUS_IO_BASE, - wdbbar: 0x4000000, - wdbsize: 0x1000, - hpet_address: HPET_ADDR, - rcba: DEFAULT_RCBA, - pmbase: DEFAULT_PMBASE, - gpiobase: DEFAULT_GPIOBASE, - temp_mmio_base: 0xfed08000, - system_type: 5, /* ULT */ - tseg_size: CONFIG_SMM_TSEG_SIZE, - spd_addresses: { 0xff, 0x00, 0xff, 0x00 }, - ec_present: 1, + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = DEFAULT_PCIEXBAR, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = HPET_ADDR, + .rcba = DEFAULT_RCBA, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .temp_mmio_base = 0xfed08000, + .system_type = 5, /* ULT */ + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xff, 0x00, 0xff, 0x00 }, + .ec_present = 1, // 0 = leave channel enabled // 1 = disable dimm 0 on channel // 2 = disable dimm 1 on channel // 3 = disable dimm 0+1 on channel - dimm_channel0_disabled: 2, - dimm_channel1_disabled: 2, + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, // Enable 2x refresh mode - ddr_refresh_2x: 1, - max_ddr3_freq: 1600, - usb_xhci_on_resume: 1, - usb2_ports: { + .ddr_refresh_2x = 1, + .max_ddr3_freq = 1600, + .usb_xhci_on_resume = 1, + .usb2_ports = { /* Length, Enable, OCn#, Location */ { 0x0064, 1, 0, /* P0: Port A, CN8 */ USB_PORT_BACK_PANEL }, @@ -154,7 +154,7 @@ void mainboard_romstage_entry(unsigned long bist) { 0x0123, 1, 3, /* P7: USB2 Port */ USB_PORT_INTERNAL }, }, - usb3_ports: { + .usb3_ports = { /* Enable, OCn# */ { 1, 0 }, /* P1; Port A, CN8 */ { 1, 0 }, /* P2; Port B, CN9 */

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Patch merged into coreboot/master: 9492b9d superio/winbond/w83697hf: Depreciate romstage component
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 9492b9dab49336904167c19b161e6688dfe086e4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 01:00:43 2014 +1000 superio/winbond/w83697hf: Depreciate romstage component Depreciate the model specific early_serial.c romstage component for this Super I/O in favor of the recent generic winbond romstage framework. Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5727 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/5727 for details. -gerrit

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Patch merged into coreboot/master: 1704637 mainboard/asus/k8v-x: Remove dubious SIO PNP programming in romstage
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 17046377191d14f46fd0af40be04899601a79768 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 22 00:16:39 2014 +1000 mainboard/asus/k8v-x: Remove dubious SIO PNP programming in romstage Remove bogus attempt to double program the Super I/O. Remove also a questionable function that enters Super I/O LDN config space, does no actual LDN programming, rather multi-function register programming and then never leaves the config space. Further, we don't export pnp_ symbols from the early_serial.c component into the global namespace. Change-Id: I7d6b97b174249ae16fe881728da5ca3dd069b696 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5800 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/5800 for details. -gerrit

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Patch merged into coreboot/master: 80b627e Asus F2A85-M: Move to ther proper SIO
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 80b627eb4d37fb503056d37b0910ad6afe9e63b5 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue May 13 16:36:56 2014 +0200 Asus F2A85-M: Move to ther proper SIO The F2A85-M has IT8603E which is a strip down version of IT8728F. Change configuration from provisional IT8712F to the IT8728F. While at it also enable only needed LPC bridge decodes. As the side effect, this change also implements setup of environmental controller, thus it87 driver can detect the temperatures/fans. Change-Id: I22067b13ea27ee37e959a246718d9559c2a3215d Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/4499 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/4499 for details. -gerrit

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Patch merged into coreboot/master: 290bed7 Implement proper IT8728F PNP ops
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 290bed72589a36161c29debc67b7164dade5de3d Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue May 13 16:07:00 2014 +0200 Implement proper IT8728F PNP ops The Asus F2A85-M has IT8306E which is a stripped down version of this SIO. Implement the PNP operations of the SIO. Change-Id: Ibc4f3fafc3ffb1cd799948e63be01e6924b45d6c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/4498 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/4498 for details. -gerrit

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coreboot-gerrit May 2014