coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

1 participants
1066 discussions

New patch to review for coreboot: 9ca771a superio/ite/it8721f: Trivial drop redundant headers
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5839 -gerrit commit 9ca771a363509fee3ad317a51f8f7768c302239c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 09:56:57 2014 +1000 superio/ite/it8721f: Trivial drop redundant headers Change-Id: Ib086cd567c926dd659f67900195f93262ceb50c3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8721f/it8721f.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index ce794cf..162fa5d 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -22,9 +22,6 @@ #ifndef SUPERIO_ITE_IT8721F_H #define SUPERIO_ITE_IT8721F_H -#include <device/pnp.h> -#include <stdint.h> - /* Logical Device Numbers (LDN). */ #define IT8721F_FDC 0x00 /* Floppy */ #define IT8721F_SP1 0x01 /* Com1 */

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Patch set updated for coreboot: 801af34 superio/ite/it8712f: Depreciate model specific early_serial.c
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5838 -gerrit commit 801af3411323b1076e910b643365e48965ce2a2b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 09:18:26 2014 +1000 superio/ite/it8712f: Depreciate model specific early_serial.c We now have common ite_*_*() functions for romstage and hence no longer require the model specific portion of this superio support. Change-Id: I30400abf27008a88072673075bba445f100d9ad3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/pistachio/romstage.c | 1 - src/superio/ite/it8712f/Makefile.inc | 1 - src/superio/ite/it8712f/early_serial.c | 76 ---------------------------------- src/superio/ite/it8712f/it8712f.h | 2 - 4 files changed, 80 deletions(-) diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2971072..af4253d 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -30,7 +30,6 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index ce75645..a9f256c 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c deleted file mode 100644 index 1317248..0000000 --- a/src/superio/ite/it8712f/early_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8712f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ -#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ - -static void it8712f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8712f_exit_conf(void) -{ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - -/* - * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - * - * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - * - * Enable 3VSBSW#. (For System Suspend-to-RAM) - * 0: 3VSBSW# will be always inactive. - * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ -void it8712f_enable_3vsbsw(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 8ff528d..0eca633 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,6 +35,4 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -void it8712f_enable_3vsbsw(void); - #endif /* SUPERIO_ITE_IT8712F_H */

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Patch set updated for coreboot: f89864b superio/ite/it8712f: Depreciate model specific early_serial.c
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5838 -gerrit commit f89864b820c3cfb2724f8195332be22a57b90049 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 09:18:26 2014 +1000 superio/ite/it8712f: Depreciate model specific early_serial.c We now have common ite_*_*() functions for romstage and hence no longer require the model specific portion of this superio support. Change-Id: I30400abf27008a88072673075bba445f100d9ad3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8712f/Makefile.inc | 1 - src/superio/ite/it8712f/early_serial.c | 76 ---------------------------------- src/superio/ite/it8712f/it8712f.h | 2 - 3 files changed, 79 deletions(-) diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index ce75645..a9f256c 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c deleted file mode 100644 index 1317248..0000000 --- a/src/superio/ite/it8712f/early_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8712f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ -#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ - -static void it8712f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8712f_exit_conf(void) -{ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - -/* - * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - * - * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - * - * Enable 3VSBSW#. (For System Suspend-to-RAM) - * 0: 3VSBSW# will be always inactive. - * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ -void it8712f_enable_3vsbsw(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 8ff528d..0eca633 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,6 +35,4 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -void it8712f_enable_3vsbsw(void); - #endif /* SUPERIO_ITE_IT8712F_H */

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Patch set updated for coreboot: 5c01303 superio/ite/it8712f: Drop model specific sio func for generic ver
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5837 -gerrit commit 5c0130316f0c1d37fcefe9d93f8c51a1cafc9124 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 09:11:31 2014 +1000 superio/ite/it8712f: Drop model specific sio func for generic ver Drop it8712f_kill_watchdog() in favor of common ite_kill_watchdog() introduced in commit rev: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I9fc4d3ee7992618b5b14e35166e848d6e1cffa8b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8712f/early_serial.c | 7 ------- src/superio/ite/it8712f/it8712f.h | 1 - 2 files changed, 8 deletions(-) diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index d678f3f..1317248 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -74,10 +74,3 @@ void it8712f_enable_3vsbsw(void) it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); it8712f_exit_conf(); } - -void it8712f_kill_watchdog(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index b40e473..8ff528d 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,7 +35,6 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -void it8712f_kill_watchdog(void); void it8712f_enable_3vsbsw(void); #endif /* SUPERIO_ITE_IT8712F_H */

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Patch set updated for coreboot: b419c1a mainboard/*: Convert to generic ITE superio romstage component
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5737 -gerrit commit b419c1ac7ba86a7f5cd25b4cac74f4a22f117ab7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 19:15:08 2014 +1000 mainboard/*: Convert to generic ITE superio romstage component Convert mainboard's that use model specific romstage functions of it8712f to the generic framework by following the reasoning of: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2v-mx_se/romstage.c | 6 +++--- src/mainboard/asus/m2v/romstage.c | 6 +++--- src/mainboard/asus/m4a78-em/romstage.c | 3 ++- src/mainboard/asus/m4a785-m/romstage.c | 3 ++- src/mainboard/siemens/sitemp_g1p1/romstage.c | 3 ++- src/mainboard/technexion/tim5690/romstage.c | 3 ++- src/mainboard/technexion/tim8690/romstage.c | 3 ++- 7 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 0085bb4..d374828 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -46,7 +46,7 @@ unsigned int get_sbdn(unsigned bus); #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -129,8 +129,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); - it8712f_enable_3vsbsw(); + ite_kill_watchdog(GPIO_DEV); + ite_enable_3vsbsw(GPIO_DEV); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index acf8f91..a2c6a03 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -46,7 +46,7 @@ unsigned int get_sbdn(unsigned bus); #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define IT8712F_GPIO_BASE 0x0a20 @@ -227,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); enable_rom_decode(); m2v_bus_init(); m2v_it8712f_gpio_init(); - it8712f_enable_3vsbsw(); + ite_enable_3vsbsw(GPIO_DEV); printk(BIOS_INFO, "now booting... \n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 93810d2..2620a13 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b360636..ff04dc7 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index b8af354..eca7af2 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ static void memreset(int controllers, const struct mem_controller *ctrl) @@ -107,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 35351b1..68373b9 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -40,6 +40,7 @@ #include "southbridge/amd/sb600/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 7455df2..0ba0fce 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -40,6 +40,7 @@ #include "southbridge/amd/sb600/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -84,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init();

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Patch set updated for coreboot: 9d20e0d AGESA fam12 fam14 fam15: Declare local callouts static
by Kyösti Mälkki 24 May '14

24 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5685 -gerrit commit 9d20e0d6a7ed978f989942930c735f45fa4c13b9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 18:56:33 2014 +0300 AGESA fam12 fam14 fam15: Declare local callouts static Change-Id: I2ff70cafdd808a235ed4f0663e182d306f493c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/BiosCallOuts.c | 6 ++++-- src/mainboard/amd/inagua/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/persimmon/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/south_station/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/torpedo/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/union_station/BiosCallOuts.c | 11 +++++++---- src/mainboard/asrock/e350m1/BiosCallOuts.c | 6 ++++-- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 6 ++++-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 11 +++++++---- src/mainboard/lippert/frontrunner-af/BiosCallOuts.c | 6 ++++-- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 6 ++++-- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 6 ++++-- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 6 ++++-- src/mainboard/tyan/s8226/BiosCallOuts.c | 6 ++++-- src/northbridge/amd/agesa/family12/fam12_callouts.h | 4 ---- src/northbridge/amd/agesa/family14/fam14_callouts.h | 4 ---- src/northbridge/amd/agesa/family15/fam15_callouts.h | 2 -- 17 files changed, 74 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index e9715ba..eb9ecd1 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -86,13 +86,15 @@ static void restore_socket(void) } #endif +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer}, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -128,7 +130,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index adb3b27..a764313 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -59,7 +62,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -142,7 +145,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 153c939..74e2a7e 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -63,7 +66,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. @@ -72,7 +75,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 345d0d3..219a0a8 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -61,7 +64,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -144,7 +147,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 889f75b..6c170f3 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -37,6 +37,9 @@ #define SB_GPIO_REG27 27 #endif +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -46,9 +49,9 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -80,7 +83,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -131,7 +134,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 345d0d3..219a0a8 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -61,7 +64,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -144,7 +147,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index a199152..7525cbc 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -30,6 +30,8 @@ * might need implementation to drive some GPIOs. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -40,7 +42,7 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, }; @@ -70,7 +72,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 1f8fb68..94a3a9e 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -31,6 +31,8 @@ #define SPD_CRC_HI 127 #define SPD_CRC_LO 126 +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -41,7 +43,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -120,7 +122,7 @@ AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { // Unlike AMD/Inagua, this board is unable to vary the RAM voltage. // Make sure the right speed settings are selected. diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index f4b8586..87475c4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -26,6 +26,9 @@ #include <vendorcode/amd/cimx/sb800/SB800.h> #include <stdint.h> +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -35,8 +38,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -65,7 +68,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. * Make sure the right speed settings are selected. @@ -75,7 +78,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; uint32_t FcnData; diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 751a26a..cc5043a 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -28,6 +28,8 @@ * Dedicated reset is not needed for the on-board Intel I210 GbE controller. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -38,7 +40,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -67,7 +69,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { MEM_DATA_STRUCT *MemData = ConfigPtr; diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 9329837..bd229b1 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -29,6 +29,8 @@ * and it's not needed for the on-board Intel I210 GbE controller. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -39,7 +41,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit}, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit}, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -68,7 +70,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { MEM_DATA_STRUCT *MemData = ConfigPtr; diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 0251b29..894ee53 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -71,13 +71,15 @@ static void restore_socket(UINT8 original_value) } #endif +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, @@ -107,7 +109,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 8e9aff5..4cef34d 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -25,13 +25,15 @@ #include "heapManager.h" #include <northbridge/amd/agesa/family15/dimmSpd.h> +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, @@ -63,7 +65,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 5a711d7..0d1817a 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -79,13 +79,15 @@ static void restore_socket(UINT8 original_value) } #endif +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, @@ -115,7 +117,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/northbridge/amd/agesa/family12/fam12_callouts.h b/src/northbridge/amd/agesa/family12/fam12_callouts.h index 90a262b..7259594 100644 --- a/src/northbridge/amd/agesa/family12/fam12_callouts.h +++ b/src/northbridge/amd/agesa/family12/fam12_callouts.h @@ -51,9 +51,5 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); #endif /* CALLOUTS_AMD_AGESA_FAM12_H */ diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index 304d88c..2ad6258 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -53,9 +53,5 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); #endif /* CALLOUTS_AMD_AGESA_FAM14_H */ diff --git a/src/northbridge/amd/agesa/family15/fam15_callouts.h b/src/northbridge/amd/agesa/family15/fam15_callouts.h index 8f74878..5e95c43 100644 --- a/src/northbridge/amd/agesa/family15/fam15_callouts.h +++ b/src/northbridge/amd/agesa/family15/fam15_callouts.h @@ -49,8 +49,6 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* AGESA ADVANCED CALLOUTS - MEMORY */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

1 0

New patch to review for coreboot: 58cc4d2 superio/ite/it8712f: Depreciate model specific early_serial.c
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5838 -gerrit commit 58cc4d20d3e73816e763189f7898898edddc842c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 09:18:26 2014 +1000 superio/ite/it8712f: Depreciate model specific early_serial.c We now have common ite_*_*() functions for romstage and hence no longer require the model specific portion of this superio support. Change-Id: I30400abf27008a88072673075bba445f100d9ad3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8712f/Makefile.inc | 1 - src/superio/ite/it8712f/early_serial.c | 76 ---------------------------------- src/superio/ite/it8712f/it8712f.h | 2 - 3 files changed, 79 deletions(-) diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index ce75645..a9f256c 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c deleted file mode 100644 index 1317248..0000000 --- a/src/superio/ite/it8712f/early_serial.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8712f.h" - -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ -#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ - -static void it8712f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8712f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8712f_exit_conf(void) -{ - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); -} - -/* - * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - * - * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - * - * Enable 3VSBSW#. (For System Suspend-to-RAM) - * 0: 3VSBSW# will be always inactive. - * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ -void it8712f_enable_3vsbsw(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 8ff528d..0eca633 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,6 +35,4 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -void it8712f_enable_3vsbsw(void); - #endif /* SUPERIO_ITE_IT8712F_H */

1 0

Patch set updated for coreboot: 6f63dcb AGESA fam12 fam14 fam15: Declare local callouts static
by Kyösti Mälkki 24 May '14

24 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5685 -gerrit commit 6f63dcbaad4f249ae170742e80abfb14834004dd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 18:56:33 2014 +0300 AGESA fam12 fam14 fam15: Declare local callouts static Change-Id: I2ff70cafdd808a235ed4f0663e182d306f493c7e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/BiosCallOuts.c | 6 ++++-- src/mainboard/amd/inagua/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/persimmon/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/south_station/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/torpedo/BiosCallOuts.c | 11 +++++++---- src/mainboard/amd/union_station/BiosCallOuts.c | 11 +++++++---- src/mainboard/asrock/e350m1/BiosCallOuts.c | 6 ++++-- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 6 ++++-- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 12 ++++++++---- src/mainboard/lippert/frontrunner-af/BiosCallOuts.c | 6 ++++-- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 6 ++++-- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 6 ++++-- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 6 ++++-- src/mainboard/tyan/s8226/BiosCallOuts.c | 6 ++++-- src/northbridge/amd/agesa/family12/fam12_callouts.h | 4 ---- src/northbridge/amd/agesa/family14/fam14_callouts.h | 4 ---- src/northbridge/amd/agesa/family15/fam15_callouts.h | 2 -- 17 files changed, 75 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index e9715ba..eb9ecd1 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -86,13 +86,15 @@ static void restore_socket(void) } #endif +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer}, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -128,7 +130,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index adb3b27..a764313 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -59,7 +62,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -142,7 +145,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index 153c939..74e2a7e 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -63,7 +66,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { // Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. // Make sure the right speed settings are selected. @@ -72,7 +75,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 345d0d3..219a0a8 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -61,7 +64,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -144,7 +147,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index 889f75b..6c170f3 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -37,6 +37,9 @@ #define SB_GPIO_REG27 27 #endif +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -46,9 +49,9 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -80,7 +83,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -131,7 +134,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 345d0d3..219a0a8 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -24,6 +24,9 @@ #include "SB800.h" #include <northbridge/amd/agesa/family14/dimmSpd.h> +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -33,8 +36,8 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -61,7 +64,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; @@ -144,7 +147,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index a199152..7525cbc 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -30,6 +30,8 @@ * might need implementation to drive some GPIOs. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -40,7 +42,7 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, }; @@ -70,7 +72,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; UINTN FcnData; diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 1f8fb68..94a3a9e 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -31,6 +31,8 @@ #define SPD_CRC_HI 127 #define SPD_CRC_LO 126 +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -41,7 +43,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -120,7 +122,7 @@ AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { // Unlike AMD/Inagua, this board is unable to vary the RAM voltage. // Make sure the right speed settings are selected. diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index f4b8586..fb7991e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -26,6 +26,9 @@ #include <vendorcode/amd/cimx/sb800/SB800.h> #include <stdint.h> +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -35,8 +38,9 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, - {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_GNB_PCIE_SLOT_RESET, board_GnbPcieSlotReset }, + {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -65,7 +69,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { /* Unlike e.g. AMD Inagua, Persimmon is unable to vary the RAM voltage. * Make sure the right speed settings are selected. @@ -75,7 +79,7 @@ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_GnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; uint32_t FcnData; diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index 751a26a..cc5043a 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -28,6 +28,8 @@ * Dedicated reset is not needed for the on-board Intel I210 GbE controller. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -38,7 +40,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -67,7 +69,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { MEM_DATA_STRUCT *MemData = ConfigPtr; diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 9329837..bd229b1 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -29,6 +29,8 @@ * and it's not needed for the on-board Intel I210 GbE controller. */ +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, @@ -39,7 +41,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit}, + {AGESA_HOOKBEFORE_DRAM_INIT, board_BeforeDramInit}, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -68,7 +70,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } /* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { MEM_DATA_STRUCT *MemData = ConfigPtr; diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 0251b29..894ee53 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -71,13 +71,15 @@ static void restore_socket(UINT8 original_value) } #endif +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, @@ -107,7 +109,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 8e9aff5..4cef34d 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -25,13 +25,15 @@ #include "heapManager.h" #include <northbridge/amd/agesa/family15/dimmSpd.h> +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, @@ -63,7 +65,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 5a711d7..0d1817a 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -79,13 +79,15 @@ static void restore_socket(UINT8 original_value) } #endif +static AGESA_STATUS board_ReadSpd (UINT32 Func,UINT32 Data, VOID *ConfigPtr); + STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = { {AGESA_ALLOCATE_BUFFER, BiosAllocateBuffer }, {AGESA_DEALLOCATE_BUFFER, BiosDeallocateBuffer }, {AGESA_LOCATE_BUFFER, BiosLocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd }, + {AGESA_READ_SPD, board_ReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, @@ -115,7 +117,7 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return CalloutStatus; } -AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +static AGESA_STATUS board_ReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; #ifdef __PRE_RAM__ diff --git a/src/northbridge/amd/agesa/family12/fam12_callouts.h b/src/northbridge/amd/agesa/family12/fam12_callouts.h index 90a262b..7259594 100644 --- a/src/northbridge/amd/agesa/family12/fam12_callouts.h +++ b/src/northbridge/amd/agesa/family12/fam12_callouts.h @@ -51,9 +51,5 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); #endif /* CALLOUTS_AMD_AGESA_FAM12_H */ diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index 304d88c..2ad6258 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -53,9 +53,5 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* PCIE slot reset control */ -AGESA_STATUS BiosGnbPcieSlotReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); #endif /* CALLOUTS_AMD_AGESA_FAM14_H */ diff --git a/src/northbridge/amd/agesa/family15/fam15_callouts.h b/src/northbridge/amd/agesa/family15/fam15_callouts.h index 8f74878..5e95c43 100644 --- a/src/northbridge/amd/agesa/family15/fam15_callouts.h +++ b/src/northbridge/amd/agesa/family15/fam15_callouts.h @@ -49,8 +49,6 @@ AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -/* AGESA ADVANCED CALLOUTS - MEMORY */ -AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); /* Call the host environment interface to provide a user hook opportunity. */ AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr);

1 0

New patch to review for coreboot: cb5042b superio/ite/it8712f: Drop model specific sio func for generic ver
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5837 -gerrit commit cb5042b1eab5c62a3d7f781302f5b575247a910d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 09:11:31 2014 +1000 superio/ite/it8712f: Drop model specific sio func for generic ver Drop it8712f_kill_watchdog() in favor of common ite_kill_watchdog() introduced in commit rev: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I9fc4d3ee7992618b5b14e35166e848d6e1cffa8b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8712f/early_serial.c | 7 ------- src/superio/ite/it8712f/it8712f.h | 1 - 2 files changed, 8 deletions(-) diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index d678f3f..1317248 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -74,10 +74,3 @@ void it8712f_enable_3vsbsw(void) it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); it8712f_exit_conf(); } - -void it8712f_kill_watchdog(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index b40e473..8ff528d 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -35,7 +35,6 @@ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ -void it8712f_kill_watchdog(void); void it8712f_enable_3vsbsw(void); #endif /* SUPERIO_ITE_IT8712F_H */

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Patch set updated for coreboot: 83c7490 mainboard/*: Convert to generic ITE superio romstage component
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5737 -gerrit commit 83c749040bb51102ff1aa7393ff9a2ed4d225fe4 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 19:15:08 2014 +1000 mainboard/*: Convert to generic ITE superio romstage component Convert mainboard's that use model specific romstage functions of it8712f to the generic framework by following the reasoning of: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2v-mx_se/romstage.c | 6 +++--- src/mainboard/asus/m2v/romstage.c | 6 +++--- src/mainboard/asus/m4a78-em/romstage.c | 3 ++- src/mainboard/asus/m4a785-m/romstage.c | 3 ++- src/mainboard/siemens/sitemp_g1p1/romstage.c | 3 ++- src/mainboard/technexion/tim5690/romstage.c | 3 ++- src/mainboard/technexion/tim8690/romstage.c | 3 ++- 7 files changed, 16 insertions(+), 11 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 0085bb4..0043076 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -46,7 +46,7 @@ unsigned int get_sbdn(unsigned bus); #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -129,8 +129,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); - it8712f_enable_3vsbsw(); + ite_kill_watchdog(GPIO_DEV); + ite_enable_3vsbsw(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index acf8f91..8630021 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -46,7 +46,7 @@ unsigned int get_sbdn(unsigned bus); #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define IT8712F_GPIO_BASE 0x0a20 @@ -227,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); enable_rom_decode(); m2v_bus_init(); m2v_it8712f_gpio_init(); - it8712f_enable_3vsbsw(); + ite_enable_3vsbsw(); printk(BIOS_INFO, "now booting... \n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 93810d2..2620a13 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b360636..ff04dc7 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index b8af354..eca7af2 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ static void memreset(int controllers, const struct mem_controller *ctrl) @@ -107,7 +108,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 1) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 35351b1..68373b9 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -40,6 +40,7 @@ #include "southbridge/amd/sb600/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -89,7 +90,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 7455df2..0ba0fce 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -40,6 +40,7 @@ #include "southbridge/amd/sb600/early_setup.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -84,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(GPIO_DEV); console_init();

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coreboot-gerrit May 2014