coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

1 participants
1066 discussions

New patch to review for coreboot: 0ba28d6 northbridge/intel/e7505/raminit.c: Silence warn of unused func
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5845 -gerrit commit 0ba28d64f750e755b60673ecb8b7a2942bb461b7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 25 06:33:29 2014 +1000 northbridge/intel/e7505/raminit.c: Silence warn of unused func Spotted by Clang. Change-Id: Iec34a23d0cf193ca6a4af0407b0763bf77ea03b3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/e7505/raminit.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/e7505/raminit.c b/src/northbridge/intel/e7505/raminit.c index 455f3ab..e5920df 100644 --- a/src/northbridge/intel/e7505/raminit.c +++ b/src/northbridge/intel/e7505/raminit.c @@ -104,6 +104,7 @@ static const uint32_t refresh_rate_map[] = { #define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) +#ifdef VALIDATE_DIMM_COMPATIBILITY // SPD parameters that must match for dual-channel operation static const uint8_t dual_channel_parameters[] = { SPD_MEMORY_TYPE, @@ -114,6 +115,7 @@ static const uint8_t dual_channel_parameters[] = { SPD_PRIMARY_SDRAM_WIDTH, SPD_NUM_BANKS_PER_SDRAM }; +#endif /* VALIDATE_DIMM_COMPATIBILITY */ /* Comments here are remains of e7501 or even 855PM. * They might be partially (in)correct for e7505. @@ -623,7 +625,7 @@ static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) break; } } -#endif +#endif /* VALIDATE_DIMM_COMPATIBILITY */ // Code around ROMCC bug in optimization of "if" statements #ifdef ROMCC_IF_BUG_FIXED

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New patch to review for coreboot: d467200 northbridge/intel/i3100/raminit.c: Uninitialized variable
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5844 -gerrit commit d4672005679350f2064f7544492ea0c79c69ab07 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 25 06:30:35 2014 +1000 northbridge/intel/i3100/raminit.c: Uninitialized variable Spotted by Clang Change-Id: If524a5cd984602a332c4ca28a8167a3597206b94 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/i3100/raminit.c | 2 +- src/northbridge/intel/i3100/raminit_ep80579.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c index e83feaa..443972e 100644 --- a/src/northbridge/intel/i3100/raminit.c +++ b/src/northbridge/intel/i3100/raminit.c @@ -634,7 +634,7 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { u8 c1,c2; u32 dimm,i; - u32 data32; + u32 data32 = 0; u32 t4; /* Set up northbridge values */ diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c index 682b1fc..90c1005 100644 --- a/src/northbridge/intel/i3100/raminit_ep80579.c +++ b/src/northbridge/intel/i3100/raminit_ep80579.c @@ -503,8 +503,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) static void set_on_dimm_termination_enable(const struct mem_controller *ctrl) { u8 c1,c2; - u32 dimm,i; - u32 data32; + u32 dimm, i; + u32 data32 = 0; u32 t4; /* Set up northbridge values */

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New patch to review for coreboot: d1308fb nb/intel/i945/raminit.c: duplicate 'const' declaration specifier
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5843 -gerrit commit d1308fb41f0974e5c8e30d4ed415a933bcf04966 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 25 06:24:39 2014 +1000 nb/intel/i945/raminit.c: duplicate 'const' declaration specifier Spotted by Clang Change-Id: I7e91f3edfa773560131e267a7776d8bf1ff7e295 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/intel/i945/raminit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 6943fd9..885b49d 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -1735,14 +1735,14 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) u32 temp_drt; int i, page_size; - static const u8 const drt0_table[] = { + static const u8 drt0_table[] = { /* CL 3, 4, 5 */ 3, 4, 5, /* FSB533/400, DDR533/400 */ 4, 5, 6, /* FSB667, DDR533/400 */ 4, 5, 6, /* FSB667, DDR667 */ }; - static const u8 const cas_table[] = { + static const u8 cas_table[] = { 2, 1, 0, 3 };

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Patch merged into coreboot/master: 8f9132f mainboard/amd: Incorrect usage of logical vs. bitwise and
by gerrit＠coreboot.org 24 May '14

24 May '14

the following patch was just integrated into master: commit 8f9132fab10603abf75b8862418000669dfe9a27 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 04:01:38 2014 +1000 mainboard/amd: Incorrect usage of logical vs. bitwise and Spotted by Clang Change-Id: I26201c7f5e421c38d3965d8e7e62c4a8e670e449 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5833 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martin.roth(a)se-eng.com> See http://review.coreboot.org/5833 for details. -gerrit

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New patch to review for coreboot: 66f97c2 NOTFORMERGE: WIP VBT pasrser.
by Vladimir Serbinenko 24 May '14

24 May '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5842 -gerrit commit 66f97c28f4003d7bc7e29703d045068d40e4af5b Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat May 24 16:34:29 2014 +0200 NOTFORMERGE: WIP VBT pasrser. Change-Id: I32f6505dbf683478bf5a25b73db7ab0c60eff29c Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- util/intelvbttool/intelvbttool.c | 441 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 441 insertions(+) diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c new file mode 100644 index 0000000..3ac2fd7 --- /dev/null +++ b/util/intelvbttool/intelvbttool.c @@ -0,0 +1,441 @@ +#include <stdio.h> +#include <sys/mman.h> +#include <stdint.h> +#include <string.h> +#include <stdlib.h> +#include <unistd.h> +#include <sys/types.h> +#include <sys/stat.h> +#include <fcntl.h> +#include <errno.h> + +typedef uint8_t u8; +typedef uint16_t u16; +typedef uint32_t u32; + + +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +struct vbt_header { + u8 signature[20]; + u16 version; + u16 header_size; + u16 vbt_size; + u8 vbt_checksum; + u8 reserved0; + u32 bdb_offset; + u32 aim_offset[4]; +} __attribute__((packed)); + +struct bdb_header { + u8 signature[16]; + u16 version; + u16 header_size; + u16 bdb_size; +}; + +struct vbios_data { + u8 type; /* 0 == desktop, 1 == mobile */ + u8 relstage; + u8 chipset; + u8 lvds_present:1; + u8 tv_present:1; + u8 rsvd2:6; /* finish byte */ + u8 rsvd3[4]; + u8 signon[155]; + u8 copyright[61]; + u16 code_segment; + u8 dos_boot_mode; + u8 bandwidth_percent; + u8 rsvd4; /* popup memory size */ + u8 resize_pci_bios; + u8 rsvd5; /* is crt already on ddc2 */ +} __attribute__((packed)); + +struct bdb_general_features { + /* bits 1 */ + u8 panel_fitting:2; + u8 flexaim:1; + u8 msg_enable:1; + u8 clear_screen:3; + u8 color_flip:1; + + /* bits 2 */ + u8 download_ext_vbt:1; + u8 enable_ssc:1; + u8 ssc_freq:1; + u8 enable_lfp_on_override:1; + u8 disable_ssc_ddt:1; + u8 rsvd7:1; + u8 display_clock_mode:1; + u8 rsvd8:1; /* finish byte */ + + /* bits 3 */ + u8 disable_smooth_vision:1; + u8 single_dvi:1; + u8 rsvd9:1; + u8 fdi_rx_polarity_inverted:1; + u8 rsvd10:4; /* finish byte */ + + /* bits 4 */ + u8 legacy_monitor_detect; + + /* bits 5 */ + u8 int_crt_support:1; + u8 int_tv_support:1; + u8 int_efp_support:1; + u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ + u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ + u8 rsvd11:3; /* finish byte */ +} __attribute__((packed)); + +struct common_child_dev_config { + u16 handle; + u16 device_type; + u8 not_common1[12]; + u8 dvo_port; + u8 i2c_pin; + u8 slave_addr; + u8 ddc_pin; + u16 edid_ptr; + u8 not_common3[6]; + u8 dvo_wiring; + u8 not_common4[4]; +} __attribute__((packed)); + +struct bdb_general_definitions { + /* DDC GPIO */ + u8 crt_ddc_gmbus_pin; + + /* DPMS bits */ + u8 dpms_acpi:1; + u8 skip_boot_crt_detect:1; + u8 dpms_aim:1; + u8 rsvd1:5; /* finish byte */ + + /* boot device bits */ + u8 boot_display[2]; + u8 child_dev_size; + + /* + * Device info: + * If TV is present, it'll be at devices[0]. + * LVDS will be next, either devices[0] or [1], if present. + * On some platforms the number of device is 6. But could be as few as + * 4 if both TV and LVDS are missing. + * And the device num is related with the size of general definition + * block. It is obtained by using the following formula: + * number = (block_size - sizeof(bdb_general_definitions))/ + * sizeof(child_device_config); + */ + struct common_child_dev_config devices[0]; +} __attribute__((packed)); + +struct bdb_driver_features { + u8 boot_dev_algorithm:1; + u8 block_display_switch:1; + u8 allow_display_switch:1; + u8 hotplug_dvo:1; + u8 dual_view_zoom:1; + u8 int15h_hook:1; + u8 sprite_in_clone:1; + u8 primary_lfp_id:1; + + u16 boot_mode_x; + u16 boot_mode_y; + u8 boot_mode_bpp; + u8 boot_mode_refresh; + + u16 enable_lfp_primary:1; + u16 selective_mode_pruning:1; + u16 dual_frequency:1; + u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ + u16 nt_clone_support:1; + u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ + u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ + u16 cui_aspect_scaling:1; + u16 preserve_aspect_ratio:1; + u16 sdvo_device_power_down:1; + u16 crt_hotplug:1; + u16 lvds_config:2; + u16 tv_hotplug:1; + u16 hdmi_config:2; + + u8 static_display:1; + u8 reserved2:7; + u16 legacy_crt_max_x; + u16 legacy_crt_max_y; + u8 legacy_crt_max_refresh; + + u8 hdmi_termination; + u8 custom_vbt_version; +} __attribute__((packed)); + +struct bdb_lvds_options { + u8 panel_type; + u8 rsvd1; + /* LVDS capabilities, stored in a dword */ + u8 pfit_mode:2; + u8 pfit_text_mode_enhanced:1; + u8 pfit_gfx_mode_enhanced:1; + u8 pfit_ratio_auto:1; + u8 pixel_dither:1; + u8 lvds_edid:1; + u8 rsvd2:1; + u8 rsvd4; +} __attribute__((packed)); + +struct bdb_sdvo_lvds_options { + u8 panel_backlight; + u8 h40_set_panel_type; + u8 panel_type; + u8 ssc_clk_freq; + u16 als_low_trip; + u16 als_high_trip; + u8 sclalarcoeff_tab_row_num; + u8 sclalarcoeff_tab_row_size; + u8 coefficient[8]; + u8 panel_misc_bits_1; + u8 panel_misc_bits_2; + u8 panel_misc_bits_3; + u8 panel_misc_bits_4; +} __attribute__((packed)); + + +#define BDB_GENERAL_FEATURES 1 +#define BDB_GENERAL_DEFINITIONS 2 + +#define BDB_DRIVER_FEATURES 12 +#define BDB_SDVO_LVDS_OPTIONS 22 +#define BDB_SDVO_PANEL_DTDS 23 +#define BDB_LVDS_OPTIONS 40 +#define BDB_LVDS_LFP_DATA_PTRS 41 +#define BDB_LVDS_LFP_DATA 42 + +#define BDB_SKIP 254 + +static void parse_vbt(const void *vbt) +{ + const struct vbt_header *head = vbt; + const struct bdb_header *bdb; + int i; + const u8 *ptr; + int is_first_skip = 1; + + if (memcmp(head->signature, "$VBT", 4) != 0) { + fprintf (stderr, "invalid VBT signature\n"); + exit(1); + } + printf ("signature: <%20.20s>\n", head->signature); + printf ("version: %d.%02d\n", head->version / 100, + head->version % 100); + if (head->header_size != sizeof (struct vbt_header)) + printf ("header size: 0x%x\n", head->header_size); + printf ("VBT size: 0x%x\n", head->vbt_size); + printf ("VBT checksum: 0x%x\n", head->vbt_checksum); + if (head->reserved0) + printf ("header reserved0: 0x%x\n", head->reserved0); + if (head->bdb_offset != sizeof (struct vbt_header)) + printf ("BDB offset: 0x%x\n", head->bdb_offset); + + for (i = 0; i < 4; i++) + if (head->aim_offset[i]) + printf ("AIM[%d] offset: 0x%x\n", i, + head->aim_offset[i]); + bdb = (const void *) ((const char *) vbt + head->bdb_offset); + + if (memcmp ("BIOS_DATA_BLOCK ", bdb->signature, 16) != 0) { + fprintf(stderr, "invalid BDB signature:%s\n", + bdb->signature); + exit (1); + } + printf ("BDB version: %d.%02d\n", bdb->version / 100, + bdb->version % 100); + if (bdb->header_size != sizeof (struct bdb_header)) + printf ("BDB header size: 0x%x\n", bdb->header_size); + if (bdb->bdb_size != head->vbt_size - head->bdb_offset) + printf ("BDB size: 0x%x\n", bdb->bdb_size); + for (ptr = (const u8 *) bdb + bdb->header_size; + ptr < (const u8 *) bdb + bdb->bdb_size;) { + u16 secsz = (ptr[1] | (ptr[2] << 8)); + u8 sectype = ptr[0]; + const u8 *section = ptr + 3; + + printf ("section type %d, size 0x%x\n", sectype, secsz); + ptr += secsz + 3; + switch(sectype) + { + case BDB_GENERAL_FEATURES: { + const struct bdb_general_features *sec = (const void *) section; + printf ("General features:\n"); + + if(sec->panel_fitting) printf("\tpanel_fitting = 0x%x\n", sec->panel_fitting); + if(sec->flexaim) printf("\tflexaim = 0x%x\n", sec->flexaim); + if(sec->msg_enable) printf("\tmsg_enable = 0x%x\n", sec->msg_enable); + if(sec->clear_screen) printf("\tclear_screen = 0x%x\n", sec->clear_screen); + if(sec->color_flip) printf("\tcolor_flip = 0x%x\n", sec->color_flip); + if(sec->download_ext_vbt) printf("\tdownload_ext_vbt = 0x%x\n", sec->download_ext_vbt); + printf("\t*enable_ssc = 0x%x\n", sec->enable_ssc); + printf("\t*ssc_freq = 0x%x\n", sec->ssc_freq); + if(sec->enable_lfp_on_override) printf("\tenable_lfp_on_override = 0x%x\n", sec->enable_lfp_on_override); + if(sec->disable_ssc_ddt) printf("\tdisable_ssc_ddt = 0x%x\n", sec->disable_ssc_ddt); + if(sec->rsvd7) printf("\trsvd7 = 0x%x\n", sec->rsvd7); + printf("\t*display_clock_mode = 0x%x\n", sec->display_clock_mode); + if(sec->rsvd8) printf("\trsvd8 = 0x%x\n", sec->rsvd8); + printf("\tdisable_smooth_vision = 0x%x\n", sec->disable_smooth_vision); + if(sec->single_dvi) printf("\tsingle_dvi = 0x%x\n", sec->single_dvi); + if(sec->rsvd9) printf("\trsvd9 = 0x%x\n", sec->rsvd9); + printf("\t*fdi_rx_polarity_inverted = 0x%x\n", sec->fdi_rx_polarity_inverted); + if(sec->rsvd10) printf("\trsvd10 = 0x%x\n", sec->rsvd10); + if(sec->legacy_monitor_detect) printf("\tlegacy_monitor_detect = 0x%x\n", sec->legacy_monitor_detect); + printf("\t*int_crt_support = 0x%x\n", sec->int_crt_support); + printf("\t*int_tv_support = 0x%x\n", sec->int_tv_support); + if(sec->int_efp_support) printf("\tint_efp_support = 0x%x\n", sec->int_efp_support); + if(sec->dp_ssc_enb) printf("\tdp_ssc_enb = 0x%x\n", sec->dp_ssc_enb); + if(sec->dp_ssc_freq) printf("\tdp_ssc_freq = 0x%x\n", sec->dp_ssc_freq); + if(sec->rsvd11) printf("\trsvd11 = 0x%x\n", sec->rsvd11); + break; + } + case BDB_DRIVER_FEATURES: { + const struct bdb_driver_features *sec = (const void *) section; + printf("\t*LVDS config: %d\n", sec->lvds_config); + printf("\t*Dual frequency: %d\n", sec->dual_frequency); + + break; + } + case BDB_SDVO_LVDS_OPTIONS: { + const struct bdb_sdvo_lvds_options *sec = (const void *) section; + printf("\t*Panel type: %d\n", sec->panel_type); + + break; + } + case BDB_GENERAL_DEFINITIONS: { + const struct bdb_general_definitions *sec = (const void *) section; + printf("\t*CRT DDC GMBUS pin: %d\n", sec->crt_ddc_gmbus_pin); + + printf("\tDPMS ACPI: %d\n", sec->dpms_acpi); + printf("\tSkip boot CRT detect: %d\n", + sec->skip_boot_crt_detect); + printf("\tDPMS aim: %d\n", + sec->dpms_aim); + if(sec->rsvd1) + printf("\trsvd1: 0x%x\n", sec->rsvd1); + printf("\tboot_display: { %x, %x }\n", + sec->boot_display[0], sec->boot_display[1]); + if (sec->child_dev_size != sizeof(struct common_child_dev_config)) + printf("\tchild_dev_size: %d\n", + sec->child_dev_size); + printf("\t%d devices\n", (secsz - sizeof (*sec)) / sizeof(struct common_child_dev_config)); + for (i = 0; i < (secsz - sizeof (*sec)) / sizeof(struct common_child_dev_config); i++) { + printf ("\t*device type: %x ", + sec->devices[i].device_type); +#define DEVICE_TYPE_INT_LFP 0x1022 +#define DEVICE_TYPE_INT_TV 0x1009 +#define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 + switch (sec->devices[i].device_type) { + case DEVICE_TYPE_INT_LFP: + printf("(flat panel)\n"); + break; + case DEVICE_TYPE_INT_TV: + printf("(TV)\n"); + break; + case DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR: + printf("(DVI)\n"); + break; + case 0: + printf("(Empty)\n"); + break; + default: + printf("(Unknown)\n"); + break; + } + if (!sec->devices[i].device_type) + continue; + printf ("\t *dvo_port: %x\n", sec->devices[i].dvo_port); + printf ("\t *i2c_pin: %x\n", sec->devices[i].i2c_pin); + printf ("\t *slave_addr: %x\n", sec->devices[i].slave_addr); + printf ("\t *ddc_pin: %x\n", sec->devices[i].ddc_pin); + printf ("\t *dvo_wiring: %x\n", sec->devices[i].dvo_wiring); + printf ("\t edid_ptr: %x\n", sec->devices[i].edid_ptr); + } + + break; + } + case BDB_SKIP: { + const struct vbios_data *sec = (const void *) section; + if (!is_first_skip) + break; + is_first_skip = 0; + printf("\ttype: %x\n", sec->type); + printf("\trelstage: %x\n", sec->relstage); + printf("\tchipset: %x\n", sec->chipset); + printf(sec->lvds_present ? "\tLVDS\n" + : "\tNo LVDS\n"); + printf(sec->tv_present ? "\tTV\n" + : "\tNo TV\n"); + if (sec->rsvd2) + printf("\trsvd2: 0x%x\n", sec->rsvd2); + for (i = 0; i < 4; i++) + if (sec->rsvd3[i]) + printf("\trsvd3[%d]: 0x%x\n", i, + sec->rsvd3[i]); + printf("\tSignon: %.155s\n", sec->signon); + printf("\tCopyright: %.155s\n", sec->copyright); + printf("\tCode segment: %x\n", sec->code_segment); + printf("\tDOS Boot mode: %x\n", sec->dos_boot_mode); + printf("\tBandwidth percent: %x\n", + sec->bandwidth_percent); + if (sec->rsvd4) + printf("\trsvd4: 0x%x\n", sec->rsvd4); + printf("\tBandwidth percent: %x\n", + sec->resize_pci_bios); + if (sec->rsvd5) + printf("\trsvd5: 0x%x\n", sec->rsvd5); + break; + } + } + } + +} + +static void parse_vbios(const void *ptr) +{ + const optionrom_header_t *oh; + oh = ptr; + if (oh->signature != 0xaa55) { + fprintf(stderr, "bad oprom signature: %x\n", oh->signature); + return; + } + if (!oh->vbt_offset) { + fprintf(stderr, "no VBT found\n"); + return; + } + parse_vbt((const char *) ptr + oh->vbt_offset); +} + +int +main (int argc, char **argv) +{ + const void *ptr; + int fd; + if (argc == 2) { + fd = open(argv[1], O_RDONLY); + ptr = mmap(0, 65536, PROT_READ, MAP_SHARED, fd, 0); + } else { + fd = open("/dev/mem", O_RDONLY); + ptr = mmap(0, 65536, PROT_READ, MAP_SHARED, fd, 0xc0000); + } + if (ptr == MAP_FAILED) { + fprintf (stderr, "mmap failed: %s\n", strerror (errno)); + return 1; + } + parse_vbios(ptr); + close (fd); + return 0; +}

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New patch to review for coreboot: a6b2784 superio/fintek/f71869ad: Make SIO HWM conf conditional
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5841 -gerrit commit a6b2784ec20cfc631f141c2e43854183e29152a9 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 14:43:03 2014 +1000 superio/fintek/f71869ad: Make SIO HWM conf conditional Not everyone may like to enable the Super I/O HWM on their board or for their purposes. Hence, make hwm configuration conditional in Kconfig. Change-Id: I8f75bda30a1df4d6f33b73f3d0e6dd2e5dc9963f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/Kconfig | 1 + src/superio/fintek/Kconfig | 20 ++++++++++++++++++++ src/superio/fintek/f71869ad/Makefile.inc | 4 ++-- src/superio/fintek/f71869ad/chip.h | 2 ++ src/superio/fintek/f71869ad/superio.c | 2 ++ 5 files changed, 27 insertions(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index d90e7a1..bcb95f6 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 select SUPERIO_FINTEK_F71869AD + select SUPERIO_FINTEK_F71869AD_HWM select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/superio/fintek/Kconfig b/src/superio/fintek/Kconfig index f577898..43f4b4d 100644 --- a/src/superio/fintek/Kconfig +++ b/src/superio/fintek/Kconfig @@ -39,6 +39,26 @@ config SUPERIO_FINTEK_F71869AD bool select SUPERIO_FINTEK_COMMON_ROMSTAGE +choice + prompt "Super I/O Hardware Monitor" + default SUPERIO_NO_HWM + help + Select the method of hardware monitor fan control to be used. + +config SUPERIO_NO_HWM + bool "None" + help + No Super I/O Fan control - Do not set up the HWM fan control registers. + +config SUPERIO_FINTEK_F71869AD_HWM + bool "Fintek F71869AD HWM" + depends on SUPERIO_FINTEK_F71869AD + help + Configure the Fintek Super I/O hardware monitor fan control registers in + devicetree.cb. + +endchoice + config SUPERIO_FINTEK_F71872 bool select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc index 1d8cc6a..4de156d 100644 --- a/src/superio/fintek/f71869ad/Makefile.inc +++ b/src/superio/fintek/f71869ad/Makefile.inc @@ -18,6 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c -ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_hwm.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD_HWM) += f71869ad_multifunc.c +ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD_HWM) += f71869ad_hwm.c ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h index e12e51d..4c6c5d7 100644 --- a/src/superio/fintek/f71869ad/chip.h +++ b/src/superio/fintek/f71869ad/chip.h @@ -24,6 +24,7 @@ #include <stdint.h> struct superio_fintek_f71869ad_config { +#ifdef CONFIG_SUPERIO_FINTEK_F71869AD_HWM /* Member variables are defined in devicetree.cb. */ uint8_t multi_function_register_1; uint8_t multi_function_register_2; @@ -41,6 +42,7 @@ struct superio_fintek_f71869ad_config { uint8_t hwm_fan1_seg2_speed_count; uint8_t hwm_fan1_seg3_speed_count; uint8_t hwm_fan1_temp_map_sel; +#endif /* CONFIG_SUPERIO_FINTEK_F71869AD_HWM */ }; #endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 2664f99..82ad9e0 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -40,10 +40,12 @@ static void f71869ad_init(device_t dev) case F71869AD_KBC: pc_keyboard_init(); break; +#ifdef CONFIG_SUPERIO_FINTEK_F71869AD_HWM case F71869AD_HWM: f71869ad_multifunc_init(dev); f71869ad_hwm_init(dev); break; +#endif /* CONFIG_SUPERIO_FINTEK_F71869AD_HWM */ } }

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New patch to review for coreboot: d93fe33 superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5840 -gerrit commit d93fe33322c7dd969a527a2affbd8bc5eb4d1245 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Change-Id: I0339d6f188c3e9e2ad5bbef116599a52453b0a19 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 3 +-- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++++-- src/superio/intel/i3100/i3100.h | 16 +++++++++------- 6 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..08b1a18 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..4f61339 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,8 +19,12 @@ */ #include <arch/io.h> +#include <device/pnp_def.h> #include "i3100.h" +/* Registers and bit definitions: */ +#define I3100_SIW_CONFIGURATION 0x29 + static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; @@ -38,14 +42,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..8468f95 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H /* * Datasheet: @@ -46,10 +46,6 @@ #define I3100_SP2 0x05 /* Com2 */ #define I3100_WDT 0x06 /* Watchdog timer */ -/* Registers and bit definitions: */ - -#define I3100_SIW_CONFIGURATION 0x29 - /* * SIW_CONFIGURATION[3:2] = UART_CLK predivide * 00: divide by 1 @@ -61,4 +57,10 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +#include <arch/io.h> +#include <stdint.h> + +void i3100_configure_uart_clk(device_t dev, u8 predivide); +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */

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Patch set updated for coreboot: 6a79313 superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 6a793130ac031ad4e54501d9f119635fc7ed9858 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 3 +-- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++++-- src/superio/intel/i3100/i3100.h | 13 ++++++------- 6 files changed, 16 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..08b1a18 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,10 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..4f61339 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,8 +19,12 @@ */ #include <arch/io.h> +#include <device/pnp_def.h> #include "i3100.h" +/* Registers and bit definitions: */ +#define I3100_SIW_CONFIGURATION 0x29 + static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; @@ -38,14 +42,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..053aa79 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H /* * Datasheet: @@ -46,10 +46,6 @@ #define I3100_SP2 0x05 /* Com2 */ #define I3100_WDT 0x06 /* Watchdog timer */ -/* Registers and bit definitions: */ - -#define I3100_SIW_CONFIGURATION 0x29 - /* * SIW_CONFIGURATION[3:2] = UART_CLK predivide * 00: divide by 1 @@ -61,4 +57,7 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */

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Patch set updated for coreboot: 798b1fe superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit 798b1fe74b2b3b1c5b926a281cec7bf5a80e386d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Note that these three Intel boards are ROMCC and so we can not clean up the early_serial #include directives in these particular mainboard/romstage's. However we fix here the Super I/O romstage component so that other boards that are not ROMCC do not include early_serial.c in the future. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 1 + src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++++-- src/superio/intel/i3100/i3100.h | 13 ++++++------- 6 files changed, 16 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..dbe824b 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,6 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..7d01dd3 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,7 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..fe8ab2f 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,9 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..4f61339 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,8 +19,12 @@ */ #include <arch/io.h> +#include <device/pnp_def.h> #include "i3100.h" +/* Registers and bit definitions: */ +#define I3100_SIW_CONFIGURATION 0x29 + static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; @@ -38,14 +42,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..053aa79 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H /* * Datasheet: @@ -46,10 +46,6 @@ #define I3100_SP2 0x05 /* Com2 */ #define I3100_WDT 0x06 /* Watchdog timer */ -/* Registers and bit definitions: */ - -#define I3100_SIW_CONFIGURATION 0x29 - /* * SIW_CONFIGURATION[3:2] = UART_CLK predivide * 00: divide by 1 @@ -61,4 +57,7 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +void i3100_configure_uart_clk(device_t dev, u8 predivide); +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */

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Patch set updated for coreboot: a06f7d4 superio/intel/i3100: Avoid .c includes
by Edward O'Callaghan 24 May '14

24 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438 -gerrit commit a06f7d47045719a6563fd7bd07aec0a1fd5a8717 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Mar 31 21:30:11 2014 +1100 superio/intel/i3100: Avoid .c includes Following the same reasoning as commit: d304331 superio/fintek/f81865f: Avoid .c includes Note that these three Intel boards are ROMCC and so we can not clean up the early_serial #include directives in these particular mainboard/romstage's. However we fix here the Super I/O romstage component so that other boards that are not ROMCC do not include early_serial.c in the future. Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/intel/eagleheights/romstage.c | 1 + src/mainboard/intel/mtarvon/romstage.c | 2 +- src/mainboard/intel/truxton/romstage.c | 2 +- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 8 ++++++-- src/superio/intel/i3100/i3100.h | 14 +++++++------- 6 files changed, 17 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..dbe824b 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,6 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..7d01dd3 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,7 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..fe8ab2f 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -30,9 +30,9 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" -#include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" +#include <superio/intel/i3100/i3100.h> #include "superio/intel/i3100/early_serial.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..4f61339 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,8 +19,12 @@ */ #include <arch/io.h> +#include <device/pnp_def.h> #include "i3100.h" +/* Registers and bit definitions: */ +#define I3100_SIW_CONFIGURATION 0x29 + static void pnp_enter_ext_func_mode(device_t dev) { u16 port = dev >> 8; @@ -38,14 +42,14 @@ static void pnp_exit_ext_func_mode(device_t dev) } /* Enable device interrupts, set UART_CLK predivide. */ -static void i3100_configure_uart_clk(device_t dev, u8 predivide) +void i3100_configure_uart_clk(device_t dev, u8 predivide) { pnp_enter_ext_func_mode(dev); pnp_write_config(dev, I3100_SIW_CONFIGURATION, (predivide << 2) | 1); pnp_exit_ext_func_mode(dev); } -static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..bc92761 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H +#ifndef SUPERIO_INTEL_I3100_H +#define SUPERIO_INTEL_I3100_H /* * Datasheet: @@ -46,10 +46,6 @@ #define I3100_SP2 0x05 /* Com2 */ #define I3100_WDT 0x06 /* Watchdog timer */ -/* Registers and bit definitions: */ - -#define I3100_SIW_CONFIGURATION 0x29 - /* * SIW_CONFIGURATION[3:2] = UART_CLK predivide * 00: divide by 1 @@ -61,4 +57,8 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02 -#endif +// XXX: We leave these commented out until ROMCC boards are EOL'ed.. +//void i3100_configure_uart_clk(device_t dev, u8 predivide); +//void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_H */

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coreboot-gerrit May 2014