coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit a7d14a170e9e36d4b8a0c73c112e5516f378c23a Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue May 13 15:57:47 2014 +0200 ite/common: Introduce common watchdog and 3.3V VSB helpers Introduce the watchog and 3.3 VSB helper functions. The IT8712F can be migrated to use those too. To be used with IT8728F. Change-Id: If21e99b6069c7222f0bc8eb7c7121fe119b8dfe1 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/5728 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/5728 for details. -gerrit

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Patch merged into coreboot/master: 4405b06 superio/ite/it8728f/it8728f_hwm.c: Small fixes
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 4405b06521c186a8b026cb3bc95837a3b605dd30 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue May 13 16:46:21 2014 +0200 superio/ite/it8728f/it8728f_hwm.c: Small fixes Use proper include header in it8728f_hwm.c, fix format error. The base of HWM block starts at offset +5. Change-Id: I6855225b38bbcf5687d506bea9482c951d314684 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Reviewed-on: http://review.coreboot.org/5729 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5729 for details. -gerrit

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Patch merged into coreboot/master: b27d360 mainboard/samsung/stumpy: Fix usage of GNU field designator ext
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit b27d3602e0faad60001debaa4572c23440114502 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 02:40:31 2014 +1000 mainboard/samsung/stumpy: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I6c5cc46385581d6b69d20f6bc9b016b799765d9e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5829 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5829 for details. -gerrit

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Patch merged into coreboot/master: ea4ae2f mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit ea4ae2f02bde5f885ff8a2942478905416b15066 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 02:08:04 2014 +1000 mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: Idda1a49277c156670014fac27b9f1c378f8df0cd Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5827 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5827 for details. -gerrit

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Patch merged into coreboot/master: c686c95 mainboard/intel/baskingridge Fix usage of GNU field designator ext
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit c686c95c9831d66e76cde6fe6f9d8c45abdb5970 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 02:07:18 2014 +1000 mainboard/intel/baskingridge Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I61fe91e467c29f144323af9c4612420f322098b4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5826 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5826 for details. -gerrit

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Patch merged into coreboot/master: 6aa6509 mainboard/intel/wtm2: Fix usage of GNU field designator extension
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 6aa6509caee29342014721e5e6689e437e396aea Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 02:06:10 2014 +1000 mainboard/intel/wtm2: Fix usage of GNU field designator extension Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: I46fad8d236c620ee5dbeb24f4517f20f00db839f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5825 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5825 for details. -gerrit

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Patch merged into coreboot/master: 6f49f69 mainboard/kontron/ktqm77: Fix usage of GNU field designator ext
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit 6f49f69ed0c46efd57c221c3e5ab163becb19897 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 24 02:04:52 2014 +1000 mainboard/kontron/ktqm77: Fix usage of GNU field designator ext Following the reasoning in, 8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension In C99 we defined a syntax for this. GCC's old syntax was deprecated. Change-Id: If948960abbd927aa6d2b471a42a2321a04d992f3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5824 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5824 for details. -gerrit

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Patch merged into coreboot/master: a0427cb vendorcode/intel/fsp/rangeley: remove extra file
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit a0427cb84415d143db595b7b359a5edb55ebdb64 Author: Martin Roth <gaumless(a)gmail.com> Date: Wed May 21 15:03:08 2014 -0600 vendorcode/intel/fsp/rangeley: remove extra file This is an extra file that is included in the Intel GSP release. It's got a coreboot header on it, isn't used, and looks very platform specific. I'm not sure where it belongs, but it doesn't belong in vendorcode. I've sent the contacts at Intel an email letting them know that this file should probably be removed from their FSP release and is getting removed here. Change-Id: I5ac6649235846ce5716bb180af29a5e422f4cce3 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/5809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/5809 for details. -gerrit

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Patch merged into coreboot/master: e9e99e9 drivers/pc80/Kconfig: Revert PS/2 initialization defaults
by gerrit＠coreboot.org 23 May '14

23 May '14

the following patch was just integrated into master: commit e9e99e976e18c21dcaccaeccbf5dc276d771446c Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri May 2 15:19:21 2014 +0200 drivers/pc80/Kconfig: Revert PS/2 initialization defaults Remove the inconsistent behaviour based on unrelated configuration: PS/2 init is now always enabled. This can change once we find a better approach. Change-Id: Ia8d55032f0e5eca0bf82d77df7dab95bcb2b353a Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/5634 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Peter Stuge <peter(a)stuge.se> See http://review.coreboot.org/5634 for details. -gerrit

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Patch set updated for coreboot: 2b1b34c PCI IRQs: Swizzle PCI IRQs for PCI bridges
by Martin Roth 23 May '14

23 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5734 -gerrit commit 2b1b34cd06284383c85e65e1526de04520b703ce Author: Mike Loptien <loptienm(a)gmail.com> Date: Mon May 12 21:46:31 2014 -0600 PCI IRQs: Swizzle PCI IRQs for PCI bridges The PCI Specification states that devices that implement a bridge and a secondary bus must swizzle (rotate) the interrupt pins according to the table below: Child Dev # Child PIN Parent PIN 0,4,8,12... A/B/C/D A/B/C/D 1,5,9,13... A/B/C/D B/C/D/A 2,6,10,14.. A/B/C/D C/D/A/B 3,7,11,15.. A/B/C/D D/A/B/C Which is also described by this equation: PIN_parent = (Pin_child + Dev_child) % 4 When a device is found and its bus number is greater than 0, it is on a bridge and needs to be swizzled. Following the string of parents up to the root bus and swizzling as we go gives us the desired swizzling result. When BIOS_SPEW is defined, it will print out each step of the swizzling process. Change-Id: Icafeadd01983282c86e25f560c831c9482c74e68 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/device/pci_device.c | 150 +++++++++++++++++++++++++++++++++++++++++++++++ src/include/device/pci.h | 2 + 2 files changed, 152 insertions(+) diff --git a/src/device/pci_device.c b/src/device/pci_device.c index f09fcaa..d80225f 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1303,6 +1303,156 @@ unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) return max; } +/** + * Take an INT_PIN number (0, 1 - 4) and convert + * it to a string ("NO PIN", "PIN A" - "PIN D") + * + * @param pin PCI Interrupt Pin number (0, 1 - 4) + * @return A string corresponding to the pin number or "Invalid" + */ +const char *pin_to_str(int pin) +{ + const char *str[5] = { + "NO PIN", + "PIN A", + "PIN B", + "PIN C", + "PIN D", + }; + + if (pin >= 0 || pin <= 4) + return str[pin]; + else + return "Invalid PIN, not 0 - 4"; +} + +/** + * Get the PCI INT_PIN swizzle for a device defined as: + * pin_parent = (pin_child + devn_child) % 4 + 1 + * where PIN A = 1 ... PIN_D = 4 + * + * Given a PCI device structure 'dev', find the interrupt pin + * that will be triggered on its parent bridge device when + * generating an interrupt. For example: Device 1:3.2 may + * use INT_PIN A but will trigger PIN D on its parent bridge + * device. In this case, this function will return 4 (PIN D). + * + * @param dev A PCI device structure to swizzle interrupt pins for + * @param *parent_bdg The PCI device structure for the bridge + * device 'dev' is attached to + * @return The interrupt pin number (1 - 4) that 'dev' will + * trigger when generating an interrupt + */ +static int swizzle_irq_pins(device_t dev, device_t *parent_bridge) +{ + device_t parent; /* Our current device's parent device */ + device_t child; /* The child device of the parent */ + int parent_bus = 0; /* Parent Bus number */ + int parent_devfn = 0; /* Parent Device and Function number */ + int child_devfn = 0; /* Child Device and Function number */ + int swizzled_pin = 0; /* Pin swizzled across a bridge */ + + /* Start with PIN A = 0 ... D = 3 */ + swizzled_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN) - 1; + + /* While our current device has parent devices */ + child = dev; + for (parent = child->bus->dev; parent; parent = parent->bus->dev) { + parent_bus = parent->bus->secondary; + parent_devfn = parent->path.pci.devfn; + child_devfn = child->path.pci.devfn; + + /* Swizzle the INT_PIN for any bridges not on root bus */ + swizzled_pin = (PCI_SLOT(child_devfn) + swizzled_pin) % 4; + printk(BIOS_SPEW, "\tWith INT_PIN swizzled to %s\n" + "\tAttached to bridge device %01X:%02Xh.%02Xh\n", + pin_to_str(swizzled_pin + 1), parent_bus, + PCI_SLOT(parent_devfn), PCI_FUNC(parent_devfn)); + + /* Continue until we find the root bus */ + if (parent_bus > 0) { + /* + * We will go on to the next parent so this parent + * becomes the child + */ + child = parent; + continue; + } else { + /* + * Found the root bridge device, + * fill in the structure and exit + */ + *parent_bridge = parent; + break; + } + } + + /* End with PIN A = 1 ... D = 4 */ + return swizzled_pin + 1; +} + +/** + * Given a device structure 'dev', find its interrupt pin + * and its parent bridge 'parent_bdg' device structure. + * If it is behind a bridge, it will return the interrupt + * pin number (1 - 4) of the parent bridge that the device + * interrupt pin has been swizzled to, otherwise it will + * return the interrupt pin that is programmed into the + * PCI config space of the target device. If 'dev' is + * behind a bridge, it will fill in 'parent_bdg' with the + * device structure of the bridge it is behind, otherwise + * it will copy 'dev' into 'parent_bdg'. + * + * @param dev A PCI device structure to get interrupt pins for. + * @param *parent_bdg The PCI device structure for the bridge + * device 'dev' is attached to. + * @return The interrupt pin number (1 - 4) that 'dev' will + * trigger when generating an interrupt. + * Errors: -1 is returned if the device is not enabled + * -2 is returned if a parent bridge could not be found. + */ +int get_irq_pins(device_t dev, device_t *parent_bdg) +{ + int bus = 0; /* The bus this device is on */ + int devfn = 0; /* This device's device and function numbers */ + int int_pin = 0; /* Interrupt pin used by the device */ + int target_pin = 0; /* Interrupt pin we want to assign an IRQ to */ + + bus = dev->bus->secondary; + devfn = dev->path.pci.devfn; + + /* Make sure this device is enabled */ + if (!(dev->enabled && (dev->path.type == DEVICE_PATH_PCI))) + return -1; + + /* Get and validate the interrupt pin used. Only 1-4 are allowed */ + int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); + if (int_pin < 1 || int_pin > 4) + return -1; + + printk(BIOS_SPEW, "PCI IRQ: Found device %01X:%02Xh.%02Xh using %s\n", + bus, PCI_SLOT(devfn), PCI_FUNC(devfn), pin_to_str(int_pin)); + + /* If this device is on a bridge, swizzle its INT_PIN */ + if (bus) { + /* Swizzle its INT_PINs */ + target_pin = swizzle_irq_pins(dev, parent_bdg); + + /* Make sure the swizzle returned valid structures */ + if (parent_bdg == NULL) { + printk(BIOS_WARNING, + "Warning: Could not find parent bridge for this device!\n"); + return -2; + } + } else { /* Device is not behind a bridge */ + target_pin = int_pin; /* Return its own interrupt pin */ + *parent_bdg = dev; /* Return its own structure */ + } + + /* Target pin is the interrupt pin we want to assign an IRQ to */ + return target_pin; +} + #if CONFIG_PC80_SYSTEM /** * Assign IRQ numbers. diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 5594d29..ee9e84d 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -82,6 +82,8 @@ void pci_dev_set_subsystem(device_t dev, unsigned vendor, unsigned device); void pci_dev_init(struct device *dev); unsigned int pci_match_simple_dev(device_t dev, pci_devfn_t sdev); +const char * pin_to_str(int pin); +int get_irq_pins(device_t dev, device_t *parent_bdg); void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]);

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coreboot-gerrit May 2014