the following patch was just integrated into master:
commit 6ac7f5301ffa3b33cddfd6936b043bc9a6fbd222
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Mar 28 13:17:10 2014 -0500
hp/pavilion_m6_1035dx: Add EC keyboard controller to devicetree
This causes coreboot to call the keyboard initialization code for the
KBC. This is only needed for payloads which do not initialize the
keyboard.
Change-Id: Id0bb77f2a8115fafc0cd6165a8431a7e07f0fac1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5514
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer(a)gmail.com>
See http://review.coreboot.org/5514 for details.
-gerrit
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5514
-gerrit
commit 7485cff0c659a9f7fe129cf18f851eb884fac081
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Mar 28 13:17:10 2014 -0500
hp/pavilion_m6_1035dx: Add EC keyboard controller to devicetree
This causes coreboot to call the keyboard initialization code for the
KBC. This is only needed for payloads which do not initialize the
keyboard.
Change-Id: Id0bb77f2a8115fafc0cd6165a8431a7e07f0fac1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
index fe79a19..683d9ad 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
+++ b/src/mainboard/hp/pavilion_m6_1035dx/devicetree.cb
@@ -54,7 +54,12 @@ chip northbridge/amd/agesa/family15tn/root_complex
end
end # SM
device pci 14.2 on end # HDA 0x4383
- device pci 14.3 on end # LPC 0x439d
+ device pci 14.3 on # LPC 0x439d
+ chip ec/compal/ene932
+ # 60/64 KBC
+ device pnp ff.1 on end # dummy address
+ end
+ end
device pci 14.4 on end # PCI 0x4384 # PCI-b conflict with GPIO.
device pci 14.5 on end # USB 2
device pci 14.6 off end # Gec
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5513
-gerrit
commit f7b289ee27e0c480c1929aeebc8bd42ef99a8c79
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Fri Mar 28 13:37:54 2014 -0500
hp/pavilion_m6_1035dx: Remove irrelevant Kconfig options
These options are not used by the code, and are copy-paste remnants
from older AMD K8 boards. Remove them
Change-Id: I9b967a2d0a5dddc8341204dadeed90460251915c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
index 917fdf2..b9db4fc 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
@@ -31,10 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
select HAVE_SMI_HANDLER
- select SB_HT_CHAIN_UNITID_OFFSET_ONLY
- select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
- select AMDMCT
select HAVE_ACPI_TABLES
select BOARD_ROMSIZE_KB_4096
select GFXUMA
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5512
-gerrit
commit 6845cdcdbe925de289194aea334223c1abebe8fd
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Wed Apr 9 12:24:39 2014 -0500
hp/pavilion_m6_1035dx: Add SMI handler and handle EC requests
The EC may disable some functionality, such as Caps Lock LED and
battery charging if it never receives a command to go in APM mode. If
we start it in APM mode, then immediately switch to ACPI mode, it will
not get its SCIs serviced until an ACPI OS boots. If its SCIs are not
serviced, it may assume the OS has hung.
The way we solve this is to initalize the EC in APM mode, and only
switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE
command. The switch has to be handled in SMM.
Although we aren't yet processing SMIs from the EC, we are reading the
status in order to satisfy the EC that the event is handled.
Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 1 +
src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 2 +
src/mainboard/hp/pavilion_m6_1035dx/ec.c | 18 +++--
src/mainboard/hp/pavilion_m6_1035dx/mainboard.c | 5 ++
.../hp/pavilion_m6_1035dx/mainboard_smi.c | 79 ++++++++++++++++++++++
5 files changed, 100 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
index ff9e7bb..917fdf2 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig
@@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_PIRQ_TABLE
select HAVE_MP_TABLE
select HAVE_ACPI_RESUME
+ select HAVE_SMI_HANDLER
select SB_HT_CHAIN_UNITID_OFFSET_ONLY
select LIFT_BSP_APIC_ID
select SERIAL_CPU_INIT
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc
index 07ea765..7039c72 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc
+++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc
@@ -27,3 +27,5 @@ ramstage-y += agesawrapper.c
ramstage-y += BiosCallOuts.c
ramstage-y += PlatformGnbPcie.c
ramstage-y += ec.c
+
+smm-y += mainboard_smi.c
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/ec.c b/src/mainboard/hp/pavilion_m6_1035dx/ec.c
index d61a2e5..2dd0009 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/ec.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/ec.c
@@ -13,16 +13,24 @@ static void set_keyboard_matrix_us(void)
ec_kbc_write_ib(0xE5);
}
-/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */
-static void enter_acpi_mode(void)
+/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
+static void enter_apm_mode(void)
{
ec_kbc_write_cmd(0x59);
- ec_kbc_write_ib(0xE8);
+ ec_kbc_write_ib(0xE9);
}
void pavilion_m6_1035dx_ec_init(void)
{
set_keyboard_matrix_us();
- /* This could also be done in an SMI, should we decide to use SMM */
- enter_acpi_mode();
+
+ /*
+ * The EC has a special "blinking Caps Lock LED" mode which it normally
+ * enters when it believes the OS is not responding. It occasionally
+ * disables battery charging when in this mode, although other
+ * functionality is unaffected. Although the EC starts in APM mode by
+ * default, it only leaves the "blinking Caps Lock LED" mode after
+ * receiving the following command.
+ */
+ enter_apm_mode();
}
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
index 2e2b72b..578d4fd 100644
--- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.c
@@ -30,6 +30,8 @@
#include <device/pci.h>
#include <device/pci_def.h>
+#include <southbridge/amd/agesa/hudson/smi.h>
+
/*************************************************
* enable the dedicated function in parmer board.
*************************************************/
@@ -39,6 +41,9 @@ static void mainboard_enable(device_t dev)
pavilion_m6_1035dx_ec_init();
+ hudson_enable_gevent_smi(23);
+ hudson_enable_smi_generation();
+
/*
* The mainboard is the first place that we get control in ramstage. Check
* for S3 resume and call the approriate AGESA/CIMx resume functions.
diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c
new file mode 100644
index 0000000..8c7fd3f
--- /dev/null
+++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard_smi.c
@@ -0,0 +1,79 @@
+/*
+ * SMI handler -- mostly takes care of SMIs from the EC
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <delay.h>
+#include <ec/compal/ene932/ec.h>
+#include <southbridge/amd/agesa/hudson/hudson.h>
+
+
+#define EC_SMI_GEVENT (1 << 23)
+
+enum ec_smi_event {
+ EC_SMI_EVENT_IDLE = 0x80,
+};
+
+/* Tell EC to operate in APM mode. Events generate SMIs instead of SCIs */
+static void ec_enter_apm_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE9);
+}
+/* Tell EC to operate in ACPI mode, thus generating SCIs on events, not SMIs */
+static void ec_enter_acpi_mode(void)
+{
+ ec_kbc_write_cmd(0x59);
+ ec_kbc_write_ib(0xE8);
+}
+
+static uint8_t ec_get_smi_event(void)
+{
+ ec_kbc_write_cmd(0x56);
+ return ec_kbc_read_ob();
+}
+
+static void ec_process_smi(uint8_t src)
+{
+ /*
+ * Stub: We aren't processing any events yet, but reading the SMI source
+ * from satisfies the EC in terms of responding to the event.
+ */
+
+ printk(BIOS_DEBUG, "EC_SMI event 0x%x\n", src);
+}
+
+static void handle_ec_smi(void)
+{
+ uint8_t src;
+
+ while ((src = ec_get_smi_event()) != EC_SMI_EVENT_IDLE)
+ ec_process_smi(src);
+}
+
+int mainboard_smi_apmc(uint8_t data)
+{
+ switch (data) {
+ case ACPI_SMI_CMD_ENABLE:
+ printk(BIOS_DEBUG, "Enable ACPI mode\n");
+ ec_enter_acpi_mode();
+ break;
+ case ACPI_SMI_CMD_DISABLE:
+ printk(BIOS_DEBUG, "Disable ACPI mode\n");
+ ec_enter_apm_mode();
+ break;
+ default:
+ printk(BIOS_DEBUG, "Unhandled ACPI command: 0x%x\n", data);
+ }
+ return 0;
+}
+
+void mainboard_smi_gpi(uint32_t gpi_sts)
+{
+ if (gpi_sts & EC_SMI_GEVENT)
+ handle_ec_smi();
+}
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5501
-gerrit
commit 0025b44594ac4b11cef8d9a0d6f24d742b7cbaca
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Apr 15 15:41:38 2014 -0500
cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.
Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/amd/agesa/family15tn/Makefile.inc | 2 ++
src/cpu/amd/agesa/family15tn/udelay.c | 48 +++++++++++++++++++++++++++++++
2 files changed, 50 insertions(+)
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 19a2f0f..a8f644d 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -20,6 +20,8 @@
ramstage-y += chip_name.c
ramstage-y += model_15_init.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+
subdirs-y += ../../mtrr
subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c
new file mode 100644
index 0000000..7992d01
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/udelay.c
@@ -0,0 +1,48 @@
+/*
+ * udelay() impementation for SMI handlers
+ * This is neat in that it never writes to hardware registers, and thus does not
+ * modify the state of the hardware while servicing SMIs.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <delay.h>
+#include <stdint.h>
+
+void udelay(uint32_t us)
+{
+ uint8_t fid, did, pstate_idx;
+ uint64_t tsc_clock, tsc_start, tsc_end, tsc_now;
+ msr_t msr;
+ const uint64_t tsc_base = 100000000;
+
+ /* Get initial timestamp before we do the math */
+ tsc_start = rdtscll();
+
+ /* Get the P-state. This determines which MSR to read */
+ msr = rdmsr(0xc0010063);
+ pstate_idx = msr.lo & 0x07;
+
+ /* Get FID and VID for current P-State */
+ msr = rdmsr(0xc0010064 + pstate_idx);
+
+ /* Extract the FID and VID values */
+ fid = msr.lo & 0x3f;
+ did = (msr.lo >> 6) & 0x7;
+
+ /* Calculate the CPU clock (from base freq of 100MHz) */
+ tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
+
+ /*
+ * No worries about overflow. Even at 10GHz, we have over 55 years
+ * before the TSC overflows.
+ */
+ tsc_end = tsc_start + ((tsc_clock / 1000000) * us);
+
+ do {
+ tsc_now = rdtscll();
+ } while (tsc_now < tsc_end);
+}
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5501
-gerrit
commit f3968c11fc5ed9ce4cd6f9148e4b526fd2ca14ce
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Apr 15 15:41:38 2014 -0500
cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.
Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/amd/agesa/family15tn/Makefile.inc | 2 ++
src/cpu/amd/agesa/family15tn/udelay.c | 49 +++++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 19a2f0f..a8f644d 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -20,6 +20,8 @@
ramstage-y += chip_name.c
ramstage-y += model_15_init.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+
subdirs-y += ../../mtrr
subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c
new file mode 100644
index 0000000..7278fad
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/udelay.c
@@ -0,0 +1,49 @@
+/*
+ * udelay() impementation for SMI handlers
+ * This is neat in that it never writes to hardware registers, and thus does not
+ * modify the state of the hardware while servicing SMIs.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+
+void udelay(uint32_t us)
+{
+ uint8_t fid, did, pstate_idx;
+ uint64_t tsc_clock, tsc_start, tsc_end, tsc_now;
+ msr_t msr;
+ const uint64_t tsc_base = 100000000;
+
+ /* Get initial timestamp before we do the math */
+ tsc_start = rdtscll();
+
+ /* Get the P-state. This determines which MSR to read */
+ msr = rdmsr(0xc0010063);
+ pstate_idx = msr.lo & 0x07;
+
+ /* Get FID and VID for current P-State */
+ msr = rdmsr(0xc0010064 + pstate_idx);
+
+ /* Extract the FID and VID values */
+ fid = msr.lo & 0x3f;
+ did = (msr.lo >> 6) & 0x7;
+
+ /* Calculate the CPU clock (from base freq of 100MHz) */
+ tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
+
+ /*
+ * No worries about overflow. Even at 10GHz, we have over 55 years
+ * before the TSC overflows.
+ */
+ tsc_end = tsc_start + ((tsc_clock / 1000000) * us);
+
+ do {
+ tsc_now = rdtscll();
+ } while (tsc_now < tsc_end);
+}