Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5493
-gerrit
commit bad074d8a214a2494c78ae92f8865a6a1c82940d
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Sat Apr 12 21:57:18 2014 -0500
cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).
There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.
Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/amd/agesa/family15tn/Makefile.inc | 1 +
src/cpu/amd/agesa/family15tn/model_15_init.c | 16 ++++++++++++++++
src/cpu/x86/smm/smmhandler.S | 8 ++++++++
src/cpu/x86/smm/smmrelocate.S | 3 ++-
src/include/cpu/amd/amdfam15.h | 2 ++
5 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index a5a7071..19a2f0f 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-y += chip_name.c
ramstage-y += model_15_init.c
subdirs-y += ../../mtrr
+subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
subdirs-y += ../../../x86/lapic
subdirs-y += ../../../x86/cache
diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c
index f396201..467a301 100644
--- a/src/cpu/amd/agesa/family15tn/model_15_init.c
+++ b/src/cpu/amd/agesa/family15tn/model_15_init.c
@@ -19,6 +19,7 @@
#include <console/console.h>
#include <cpu/x86/msr.h>
+#include <cpu/x86/smm.h>
#include <cpu/amd/mtrr.h>
#include <device/device.h>
#include <string.h>
@@ -43,6 +44,7 @@ static void model_15_init(device_t dev)
u8 i;
msr_t msr;
int msrno;
+ unsigned int cpu_idx;
#if CONFIG_LOGICAL_CPUS
u32 siblings;
#endif
@@ -110,6 +112,20 @@ static void model_15_init(device_t dev)
msr.hi &= ~(1 << (46 - 32));
wrmsr(NB_CFG_MSR, msr);
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ cpu_idx = cpu_info()->index;
+ printk(BIOS_INFO, "Initializing SMM for CPU %u\n", cpu_idx);
+
+ /* Set SMM base address for this CPU */
+ msr = rdmsr(MSR_SMM_BASE);
+ msr.lo = SMM_BASE - (cpu_idx * 0x400);
+ wrmsr(MSR_SMM_BASE, msr);
+
+ /* Enable the SMM memory window */
+ msr = rdmsr(MSR_SMM_MASK);
+ msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
+ wrmsr(MSR_SMM_MASK, msr);
+ }
/* Write protect SMM space with SMMLOCK. */
msr = rdmsr(HWCR_MSR);
diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S
index 774088e..484b643 100644
--- a/src/cpu/x86/smm/smmhandler.S
+++ b/src/cpu/x86/smm/smmhandler.S
@@ -105,6 +105,14 @@ smm_handler_start:
movl (%esi), %ecx
shr $24, %ecx
+ /* This is an ugly hack, and we should find a way to read the CPU index
+ * without relying on the LAPIC ID.
+ */
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN)
+ /* LAPIC IDs start from 0x10; map that to the proper core index */
+ subl $0x10, %ecx
+#endif
+
/* calculate stack offset by multiplying the APIC ID
* by 1024 (0x400), and save that offset in ebp.
*/
diff --git a/src/cpu/x86/smm/smmrelocate.S b/src/cpu/x86/smm/smmrelocate.S
index 71f74e7..bdc9771 100644
--- a/src/cpu/x86/smm/smmrelocate.S
+++ b/src/cpu/x86/smm/smmrelocate.S
@@ -23,7 +23,8 @@
#define __PRE_RAM__
/* On AMD's platforms we can set SMBASE by writing an MSR */
-#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10
+#if !CONFIG_NORTHBRIDGE_AMD_AMDK8 && !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 \
+ && !CONFIG_CPU_AMD_AGESA_FAMILY15_TN
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
diff --git a/src/include/cpu/amd/amdfam15.h b/src/include/cpu/amd/amdfam15.h
index 0c2cf7b..67e7cee 100644
--- a/src/include/cpu/amd/amdfam15.h
+++ b/src/include/cpu/amd/amdfam15.h
@@ -23,6 +23,8 @@
#include <cpu/x86/msr.h>
#define MCI_STATUS 0x00000401
+#define MSR_SMM_BASE 0xC0010111
+#define MSR_SMM_MASK 0xC0010113
#define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f
Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5501
-gerrit
commit 4178eb1ecd646092011de88bcf822fe9258a67b5
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Apr 15 15:41:38 2014 -0500
cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modigy the state of the hardware.
Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/amd/agesa/family15tn/Makefile.inc | 2 ++
src/cpu/amd/agesa/family15tn/udelay.c | 49 +++++++++++++++++++++++++++++++
2 files changed, 51 insertions(+)
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 19a2f0f..a8f644d 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -20,6 +20,8 @@
ramstage-y += chip_name.c
ramstage-y += model_15_init.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+
subdirs-y += ../../mtrr
subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c
new file mode 100644
index 0000000..7278fad
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/udelay.c
@@ -0,0 +1,49 @@
+/*
+ * udelay() impementation for SMI handlers
+ * This is neat in that it never writes to hardware registers, and thus does not
+ * modify the state of the hardware while servicing SMIs.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <delay.h>
+#include <stdint.h>
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+
+void udelay(uint32_t us)
+{
+ uint8_t fid, did, pstate_idx;
+ uint64_t tsc_clock, tsc_start, tsc_end, tsc_now;
+ msr_t msr;
+ const uint64_t tsc_base = 100000000;
+
+ /* Get initial timestamp before we do the math */
+ tsc_start = rdtscll();
+
+ /* Get the P-state. This determines which MSR to read */
+ msr = rdmsr(0xc0010063);
+ pstate_idx = msr.lo & 0x07;
+
+ /* Get FID and VID for current P-State */
+ msr = rdmsr(0xc0010064 + pstate_idx);
+
+ /* Extract the FID and VID values */
+ fid = msr.lo & 0x3f;
+ did = (msr.lo >> 6) & 0x7;
+
+ /* Calculate the CPU clock (from base freq of 100MHz) */
+ tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
+
+ /*
+ * No worries about overflow. Even at 10GHz, we have over 55 years
+ * before the TSC overflows.
+ */
+ tsc_end = tsc_start + ((tsc_clock / 1000000) * us);
+
+ do {
+ tsc_now = rdtscll();
+ } while (tsc_now < tsc_end);
+}
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4773
-gerrit
commit d8a16d9eac826c87f994450dc134070a1ea917f4
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Tue Jan 21 23:03:27 2014 +0100
abuild: break early if building tools fails
Change-Id: I8da04df024a31c780b924a586d056a5351845153
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
util/abuild/abuild | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/abuild/abuild b/util/abuild/abuild
index 7676a9f..a5a57c9 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -613,7 +613,7 @@ build_all_targets()
if [ "$enable_blobs" = "true" ]; then
echo "CONFIG_USE_BLOBS=y" > $TMPCFG
fi
- make -j $cpus DOTCONFIG=$TMPCFG obj=coreboot-builds/temp objutil=coreboot-builds/sharedutils tools
+ make -j $cpus DOTCONFIG=$TMPCFG obj=coreboot-builds/temp objutil=coreboot-builds/sharedutils tools || exit 1
rm -rf coreboot-builds/temp $TMPCFG
for VENDOR in $( vendors ); do
for MAINBOARD in $( mainboards $VENDOR ); do
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5492
-gerrit
commit 46df928c746002fce2fbc09773fde346954c6a60
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Apr 12 21:57:13 2014 +0200
abuild: more verbose configuration step
Also pass V=1 to the configuration step, if requested.
Change-Id: If8b413d65d6bac34efab63614d039d74d920c8db
---
util/abuild/abuild | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/abuild/abuild b/util/abuild/abuild
index ec5c27b..7676a9f 100755
--- a/util/abuild/abuild
+++ b/util/abuild/abuild
@@ -191,7 +191,7 @@ function create_config
printf "$configoptions" >> ${build_dir}/config.build
fi
- yes "" 2>/dev/null | $MAKE oldconfig DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log
+ yes "" 2>/dev/null | $MAKE oldconfig $silent DOTCONFIG=${build_dir}/config.build obj=${build_dir} objutil=$TARGET/sharedutils &> ${build_dir}/config.log
ret=$?
if [ $ret -eq 0 ]; then
printf "ok; "
Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5510
-gerrit
commit 58bca16195bcf5a277813a090b8c41aed91d28c9
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Tue Apr 15 20:14:21 2014 +0200
sconfig: Fix build dependencies
In some cases the build system tried to build main.c before
copying the various "shipped" files (lex/yacc output) where
the place the compiler expects them.
Make the dependency explicit.
Change-Id: Iacef5292aadb9fe7bc967aa4ab5ee6c9fe4df3d7
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
---
util/sconfig/Makefile.inc | 2 ++
1 file changed, 2 insertions(+)
diff --git a/util/sconfig/Makefile.inc b/util/sconfig/Makefile.inc
index f3e8bda..c6ba90f 100644
--- a/util/sconfig/Makefile.inc
+++ b/util/sconfig/Makefile.inc
@@ -41,3 +41,5 @@ $(objutil)/sconfig/%: $(top)/util/sconfig/%_shipped
$(objutil)/sconfig/sconfig: $(addprefix $(objutil)/sconfig/,$(sconfigobj))
printf " HOSTCC $(subst $(obj)/,,$(@)) (link)\n"
$(HOSTCC) $(SCONFIGFLAGS) -o $@ $(addprefix $(objutil)/sconfig/,$(sconfigobj))
+
+$(addprefix $(objutil)/sconfig/,$(sconfigobj)) : $(objutil)/sconfig/sconfig.tab.h $(objutil)/sconfig/sconfig.tab.c $(objutil)/sconfig/lex.yy.c
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5410
-gerrit
commit 478f782f0c71fdad9f0d47cd80c68ec80a827c55
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Feb 26 15:19:04 2014 +0200
build rules: Identify build stage with simple variables
Provide simple environment variables telling which stage of boot is
being built. Also move this to arch-agnostic location.
Change-Id: I8cbb5cf91f53e01c06e7d672b5be3f5c235f911d
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/arch/armv7/include/arch/rules.h | 34 --------------------
src/arch/x86/Makefile.inc | 4 +--
src/arch/x86/include/arch/cpu.h | 2 +-
src/arch/x86/include/arch/io.h | 2 +-
src/arch/x86/include/arch/rules.h | 34 --------------------
src/include/device/device.h | 2 +-
src/include/device/pci.h | 2 +-
src/include/device/pnp.h | 2 +-
src/include/rules.h | 63 +++++++++++++++++++++++++++++++++++++
9 files changed, 70 insertions(+), 75 deletions(-)
diff --git a/src/arch/armv7/include/arch/rules.h b/src/arch/armv7/include/arch/rules.h
deleted file mode 100644
index a790365..0000000
--- a/src/arch/armv7/include/arch/rules.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _ARCH_RULES_H
-#define _ARCH_RULES_H
-
-/* For romstage and ramstage always build with simple device model, ie.
- * PCI, PNP and CPU functions operate without use of devicetree.
- *
- * For ramstage individual source file may define __SIMPLE_DEVICE__
- * before including any header files to force that particular source
- * be built with simple device model.
- */
-
-#if defined(__PRE_RAM__)
-#define __SIMPLE_DEVICE__
-#endif
-
-#endif /* _ARCH_RULES_H */
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index 56f0c5c..f986c3b 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -368,9 +368,9 @@ endif
bootblock_inc += $(objgenerated)/bootblock.inc
bootblock_inc += $(src)/arch/x86/lib/walkcbfs.S
-bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__
+bootblock_romccflags := -mcpu=i386 -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__
ifeq ($(CONFIG_SSE),y)
-bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__
+bootblock_romccflags := -mcpu=k7 -msse -O2 -D__PRE_RAM__ -D__BOOT_BLOCK__
endif
$(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions
diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h
index 281565b..ebb7cdf 100644
--- a/src/arch/x86/include/arch/cpu.h
+++ b/src/arch/x86/include/arch/cpu.h
@@ -2,7 +2,7 @@
#define ARCH_CPU_H
#include <stdint.h>
-#include <arch/rules.h>
+#include <rules.h>
/*
* EFLAGS bits
diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h
index b10fb8a..ce3574e 100644
--- a/src/arch/x86/include/arch/io.h
+++ b/src/arch/x86/include/arch/io.h
@@ -2,7 +2,7 @@
#define _ASM_IO_H
#include <stdint.h>
-#include <arch/rules.h>
+#include <rules.h>
/*
* This file contains the definitions for the x86 IO instructions
diff --git a/src/arch/x86/include/arch/rules.h b/src/arch/x86/include/arch/rules.h
deleted file mode 100644
index 4b84677..0000000
--- a/src/arch/x86/include/arch/rules.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#ifndef _ARCH_RULES_H
-#define _ARCH_RULES_H
-
-/* For romstage and ramstage always build with simple device model, ie.
- * PCI, PNP and CPU functions operate without use of devicetree.
- *
- * For ramstage individual source file may define __SIMPLE_DEVICE__
- * before including any header files to force that particular source
- * be built with simple device model.
- */
-
-#if defined(__PRE_RAM__) || defined(__SMM__)
-#define __SIMPLE_DEVICE__
-#endif
-
-#endif /* _ARCH_RULES_H */
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 74bdbd7..dfebeaa 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -3,7 +3,7 @@
#include <stdint.h>
#include <stddef.h>
-#include <arch/rules.h>
+#include <rules.h>
#include <device/resource.h>
#include <device/path.h>
diff --git a/src/include/device/pci.h b/src/include/device/pci.h
index f729c27..5594d29 100644
--- a/src/include/device/pci.h
+++ b/src/include/device/pci.h
@@ -19,7 +19,7 @@
#include <stdint.h>
#include <stddef.h>
-#include <arch/rules.h>
+#include <rules.h>
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/resource.h>
diff --git a/src/include/device/pnp.h b/src/include/device/pnp.h
index a229edb..43f457b 100644
--- a/src/include/device/pnp.h
+++ b/src/include/device/pnp.h
@@ -2,7 +2,7 @@
#define DEVICE_PNP_H
#include <stdint.h>
-#include <arch/rules.h>
+#include <rules.h>
#include <device/device.h>
#include <device/pnp_def.h>
diff --git a/src/include/rules.h b/src/include/rules.h
new file mode 100644
index 0000000..22111e8
--- /dev/null
+++ b/src/include/rules.h
@@ -0,0 +1,63 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _RULES_H
+#define _RULES_H
+
+/* Useful helpers to tell whether the code is executing in bootblock,
+ * romstage, ramstage or SMM.
+ */
+
+#if defined(__BOOT_BLOCK__)
+#define ENV_BOOTBLOCK 1
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+
+#elif defined(__PRE_RAM__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 1
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 0
+
+#elif defined(__SMM__)
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 0
+#define ENV_SMM 1
+#else
+
+#define ENV_BOOTBLOCK 0
+#define ENV_ROMSTAGE 0
+#define ENV_RAMSTAGE 1
+#define ENV_SMM 0
+#endif
+
+/* For romstage and ramstage always build with simple device model, ie.
+ * PCI, PNP and CPU functions operate without use of devicetree.
+ *
+ * For ramstage individual source file may define __SIMPLE_DEVICE__
+ * before including any header files to force that particular source
+ * be built with simple device model.
+ */
+
+#if defined(__PRE_RAM__) || defined(__SMM__)
+#define __SIMPLE_DEVICE__
+#endif
+
+#endif /* _RULES_H */