Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5501
-gerrit
commit 34192d3f2d3339867440fcb256cf2ddb7d202d4f
Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
Date: Tue Apr 15 15:41:38 2014 -0500
cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.
Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
---
src/cpu/amd/agesa/family15tn/Makefile.inc | 2 ++
src/cpu/amd/agesa/family15tn/udelay.c | 45 +++++++++++++++++++++++++++++++
2 files changed, 47 insertions(+)
diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc
index 19a2f0f..a8f644d 100644
--- a/src/cpu/amd/agesa/family15tn/Makefile.inc
+++ b/src/cpu/amd/agesa/family15tn/Makefile.inc
@@ -20,6 +20,8 @@
ramstage-y += chip_name.c
ramstage-y += model_15_init.c
+smm-$(CONFIG_HAVE_SMI_HANDLER) += udelay.c
+
subdirs-y += ../../mtrr
subdirs-y += ../../smm
subdirs-y += ../../../x86/tsc
diff --git a/src/cpu/amd/agesa/family15tn/udelay.c b/src/cpu/amd/agesa/family15tn/udelay.c
new file mode 100644
index 0000000..5f73396
--- /dev/null
+++ b/src/cpu/amd/agesa/family15tn/udelay.c
@@ -0,0 +1,45 @@
+/*
+ * udelay() impementation for SMI handlers
+ * This is neat in that it never writes to hardware registers, and thus does not
+ * modify the state of the hardware while servicing SMIs.
+ *
+ * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com>
+ * Subject to the GNU GPL v2, or (at your option) any later version.
+ */
+
+#include <cpu/x86/msr.h>
+#include <cpu/x86/tsc.h>
+#include <delay.h>
+#include <stdint.h>
+
+void udelay(uint32_t us)
+{
+ uint8_t fid, did, pstate_idx;
+ uint64_t tsc_clock, tsc_start, tsc_now, tsc_wait_ticks;
+ msr_t msr;
+ const uint64_t tsc_base = 100000000;
+
+ /* Get initial timestamp before we do the math */
+ tsc_start = rdtscll();
+
+ /* Get the P-state. This determines which MSR to read */
+ msr = rdmsr(0xc0010063);
+ pstate_idx = msr.lo & 0x07;
+
+ /* Get FID and VID for current P-State */
+ msr = rdmsr(0xc0010064 + pstate_idx);
+
+ /* Extract the FID and VID values */
+ fid = msr.lo & 0x3f;
+ did = (msr.lo >> 6) & 0x7;
+
+ /* Calculate the CPU clock (from base freq of 100MHz) */
+ tsc_clock = tsc_base * (fid + 0x10) / (1 << did);
+
+ /* Now go on and wait */
+ tsc_wait_ticks = (tsc_clock / 1e6) * us;
+
+ do {
+ tsc_now = rdtscll();
+ } while (tsc_now - tsc_wait_ticks < tsc_start);
+}
the following patch was just integrated into master:
commit 72a1768abab8c2101f833d801aed06c391eadda8
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD hudson yantgze: Drop MAX_PHYSICAL_CPUS
Not used with AGESA vendorcode.
Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5522
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/5522 for details.
-gerrit
the following patch was just integrated into master:
commit fd478f92a425f222a1218870a680ad026cd1d0e8
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD hudson yantgze: Drop APIC_ID_OFFSET
Not used with AGESA vendorcode.
Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5521
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/5521 for details.
-gerrit
the following patch was just integrated into master:
commit 740862c7d3620e57b3e128c1230487c046d4b147
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLY
Not used with AGESA vendorcode.
Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5520
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/5520 for details.
-gerrit
the following patch was just integrated into master:
commit aeb48934d4b8d0d8acfd8fa42f7fe3cbfd681ace
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD AGESA: Drop LIFT_BSP_APIC_ID
Not used with AGESA vendorcode.
Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5519
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Tested-by: build bot (Jenkins)
See http://review.coreboot.org/5519 for details.
-gerrit
the following patch was just integrated into master:
commit ef5ce9a832d5f89d94411f0fb7ff58baad2b6526
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Apr 16 09:43:40 2014 +0300
AMD AGESA: Drop AMDMCT
This config option is fam10 only.
Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5518
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/5518 for details.
-gerrit
the following patch was just integrated into master:
commit 65f0dbc0647f25a7e067a0fe00c38e1c2cbe2d2a
Author: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Date: Mon Mar 10 17:28:33 2014 +0800
AMD Thatcher: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Thatcher.
Change-Id: I959721b4fd8787ac0824f9f873efd4788682eedb
Signed-off-by: WANG Siyuan <SiYuan.Wang(a)amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa(a)gmail.com>
Reviewed-on: http://review.coreboot.org/5359
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com>
See http://review.coreboot.org/5359 for details.
-gerrit