coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 147f703 Drop drivers/generic/debug
by gerrit＠coreboot.org 22 Apr '14

22 Apr '14

the following patch was just integrated into master: commit 147f703aa9296e7b08dfa3c38eaca5ab29ff817c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Dec 22 13:13:17 2013 +0200 Drop drivers/generic/debug Not very popular nor useful nowadays. Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/4554 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/4554 for details. -gerrit

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New patch to review for coreboot: e25733f vendorcode/amd/agesa/f14/Makefile.inc: Use `btver1` for `march` switch
by Paul Menzel 22 Apr '14

22 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5564 -gerrit commit e25733f79b485fc405b8f72eb475e7fb18b45d51 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 21 23:20:44 2014 +0200 vendorcode/amd/agesa/f14/Makefile.inc: Use `btver1` for `march` switch From chapter 3.17.17 of the GCC manual [1]: ‘btver1’ CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit instruction set extensions.) RAM stage on the ASRock E350M1 is eleven bytes bigger with gcc-4.8.real (Debian 4.8.2-19) 4.8.2. $ cbfstool build/coreboot.rom print […] Name Offset Type Size cmos_layout.bin 0x0 cmos_layout 1776 pci1002,9802.rom 0x740 optionrom 65536 fallback/romstage 0x10780 stage 321708 - fallback/coreboot_ram 0x5f080 stage 195854 + fallback/coreboot_ram 0x5f080 stage 195865 fallback/payload 0x8ee00 payload 51782 config 0x9b880 raw 3858 (empty) 0x9c7c0 null 3552152 [1] http://gcc.gnu.org/onlinedocs/gcc/i386-and-x86-64-Options.html#i386-and-x86… 3.17.17 Intel 386 and AMD x86-64 Options Change-Id: I0139df7a0b9157bce55cdb1cfe5f93c6314699be Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index 2e7853c..6db88a3 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -62,7 +62,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem -AGESA_CFLAGS =-march=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS =-march=btver1 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC)

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New patch to review for coreboot: a68969f vendorcode/amd/agesa/f14/Makefile.inc: Remove `-mtune` from `AGESA_FLAGS`
by Paul Menzel 22 Apr '14

22 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5563 -gerrit commit a68969f1b11f323c7ac813616236b720550065f2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Apr 21 23:14:52 2014 +0200 vendorcode/amd/agesa/f14/Makefile.inc: Remove `-mtune` from `AGESA_FLAGS` Specifying the same CPU type in the switch `mtune` as in the switch `march` does not make any sense. -march=k8-sse3 -mtune=k8-sse3 From chapter 3.17.17 of the GCC manual [1]: -mtune=cpu-type Tune to cpu-type everything applicable about the generated code, except for the ABI and the set of available instructions. While picking a specific cpu-type schedules things appropriately for that particular chip, the compiler does not generate any code that cannot run on the default machine type unless you use a -march=cpu-type option. [1] http://gcc.gnu.org/onlinedocs/gcc/i386-and-x86-64-Options.html#i386-and-x86… 3.17.17 Intel 386 and AMD x86-64 Options Change-Id: If51fca03f4137a2937fb6c1ad5dd698c6a3a4d8f Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f14/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Makefile.inc b/src/vendorcode/amd/agesa/f14/Makefile.inc index f457277..2e7853c 100644 --- a/src/vendorcode/amd/agesa/f14/Makefile.inc +++ b/src/vendorcode/amd/agesa/f14/Makefile.inc @@ -62,7 +62,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/GNB AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/Mem -AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing +AGESA_CFLAGS =-march=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing export AGESA_ROOT := $(AGESA_ROOT) export AGESA_INC := $(AGESA_INC)

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Patch set updated for coreboot: 07aee5d Asus F2A85-M: Activate IOMMU support
by Paul Menzel 21 Apr '14

21 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3517 -gerrit commit 07aee5d62484720079844188059d486c27893149 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:12:00 2013 +0200 Asus F2A85-M: Activate IOMMU support Activate the IOMMU support for the Asus F2A85-M, by enabling it in `buildOpts.c` and by adding the device to `devicetree.cb`. The device shows up in the output of `lspci`. $ lspci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit The Linux kernel is also able to set it up. $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] [ 0.465114] [Firmware Bug]: ACPI: no secondary bus range in _CRS […] [ 0.567330] pci 0000:00:00.0: >[1022:1410] type 00 class 0x060000 [ 0.567364] pci 0000:00:00.2: >[1022:1419] type 00 class 0x080600 [ 0.567427] pci 0000:00:01.0: >[1002:9993] type 00 class 0x03000 […] [ 0.597731] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0._PRT] [ 0.597899] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.PIBR._PRT] [ 0.597933] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR0._PRT] [ 0.597972] ACPI: PCI Interrupt Routing Table [\_SB_.PCI0.SBR1._PRT] [ 0.598073] pci0000:00: >Requesting ACPI _OSC control (0x1d) [ 0.603808] pci0000:00: >ACPI _OSC request failed (AE_NOT_FOUND), returned control mask: 0x1d [ 0.612397] ACPI _OSC control for PCIe not granted, disabling ASPM [ 0.620508] Freeing initrd memory: 14876k freed […] [ 0.882674] pci 0000:00:01.0: >Boot video device [ 0.882876] PCI: CLS 64 bytes, default 64 [ 0.897088] AMD-Vi: Enabling IOMMU at 0000:00:00.2 cap 0x40 extended features: PreF PPR GT IA [ 0.905816] pci 0000:00:00.2: >irq 40 for MSI/MSI-X [ 0.917457] AMD-Vi: Lazy IO/TLB flushing enabled [ 0.922076] PCI-DMA: Using software bounce buffering for IO (SWIOTLB) [ 0.928500] software IO TLB [mem 0xbb13d000-0xbf13cfff] (64MB) mapped at [ffff8800bb13d000-ffff8800bf13cfff] [ 0.938535] LVT offset 0 assigned for vector 0x400 [ 0.943338] perf: AMD IBS detected (0x000000ff) [ 0.948037] audit: initializing netlink socket (disabled) [ 0.953432] type=2000 audit(1369659616.800:1): initialized [ 0.977011] HugeTLB registered 2 MB page size, pre-allocated 0 pages […] [ 7.881938] radeon 0000:00:01.0: >VRAM: 512M 0x0000000000000000 - 0x000000001FFFFFFF (512M used) [ 7.881941] radeon 0000:00:01.0: >GTT: 512M 0x0000000020000000 - 0x000000003FFFFFFF […] [ 7.885516] radeon 0000:00:01.0: >irq 48 for MSI/MSI-X [ 7.885525] radeon 0000:00:01.0: >radeon: using MSI. […] [ 8.276775] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae000 flags=0x0010] [ 8.287363] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc00 flags=0x0010] [ 8.297945] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae200 flags=0x0010] [ 8.308527] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae080 flags=0x0010] [ 8.319109] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae240 flags=0x0010] [ 8.329694] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001accc0 flags=0x0010] [ 8.340276] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace80 flags=0x0010] [ 8.350858] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd80 flags=0x0010] [ 8.361441] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae280 flags=0x0010] [ 8.372022] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae180 flags=0x0010] [ 8.382605] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace00 flags=0x0010] [ 8.393188] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acdc0 flags=0x0010] [ 8.403770] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ace40 flags=0x0010] [ 8.414353] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae1c0 flags=0x0010] [ 8.424936] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc40 flags=0x0010] [ 8.435518] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acc80 flags=0x0010] [ 8.446100] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae2c0 flags=0x0010] [ 8.456684] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae300 flags=0x0010] [ 8.467265] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae340 flags=0x0010] [ 8.477849] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae380 flags=0x0010] [ 8.488431] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae3c0 flags=0x0010] [ 8.499013] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae0c0 flags=0x0010] [ 8.509596] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acec0 flags=0x0010] [ 8.520179] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd00 flags=0x0010] [ 8.530761] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad000 flags=0x0010] [ 8.541343] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae400 flags=0x0010] [ 8.551925] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae440 flags=0x0010] [ 8.562509] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf00 flags=0x0010] [ 8.573090] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae480 flags=0x0010] [ 8.583675] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae100 flags=0x0010] [ 8.594257] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae4c0 flags=0x0010] […] [ 8.604840] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf40 flags=0x0010] [ 8.615421] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acd40 flags=0x0010] [ 8.626004] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad140 flags=0x0010] [ 8.636587] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad040 flags=0x0010] [ 8.647169] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad080 flags=0x0010] [ 8.657751] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae500 flags=0x0010] [ 8.668335] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad100 flags=0x0010] [ 8.678917] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad0c0 flags=0x0010] [ 8.689499] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acf80 flags=0x0010] [ 8.700080] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001acfc0 flags=0x0010] [ 8.710664] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae140 flags=0x0010] [ 8.721246] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae040 flags=0x0010] [ 8.731828] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad180 flags=0x0010] [ 8.742412] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae540 flags=0x0010] [ 8.752995] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad280 flags=0x0010] [ 8.763577] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad340 flags=0x0010] [ 8.774160] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad200 flags=0x0010] [ 8.784741] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad300 flags=0x0010] [ 8.795324] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae5c0 flags=0x0010] [ 8.805906] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae640 flags=0x0010] [ 8.816490] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad2c0 flags=0x0010] [ 8.827072] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad1c0 flags=0x0010] [ 8.837655] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad240 flags=0x0010] [ 8.848238] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae580 flags=0x0010] [ 8.858819] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae600 flags=0x0010] [ 8.869402] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad3c0 flags=0x0010] [ 8.879985] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ad380 flags=0x0010] [ 8.890568] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae7c0 flags=0x0010] [ 8.901151] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae740 flags=0x0010] [ 8.911732] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae6c0 flags=0x0010] [ 8.922316] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae780 flags=0x0010] [ 8.932897] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae700 flags=0x0010] [ 8.943480] AMD-Vi: Event logged [IO_PAGE_FAULT device=00:01.0 domain=0x0003 address=0x0000000f001ae680 flags=0x0010] [ 8.963011] [drm] PCIE GART of 512M enabled (table at 0x0000000000040000). [ 8.963165] radeon 0000:00:01.0: >WB enabled […] It is not known, what the implications of the `IO_PAGE_FAULT` are. Change-Id: I0aa530be17d31656e65db6113343f2ea7008b843 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asus/f2a85-m/buildOpts.c | 2 +- src/mainboard/asus/f2a85-m/devicetree.cb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index cbd1071..1b906d3 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -183,7 +183,7 @@ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif -#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID diff --git a/src/mainboard/asus/f2a85-m/devicetree.cb b/src/mainboard/asus/f2a85-m/devicetree.cb index 0014381..1cc610e 100644 --- a/src/mainboard/asus/f2a85-m/devicetree.cb +++ b/src/mainboard/asus/f2a85-m/devicetree.cb @@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15tn/root_complex chip northbridge/amd/agesa/family15tn # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIE SLOT0 x16 blue

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Patch set updated for coreboot: 2db71c6 AMD Fam15tn: Fix IOMMU scratch support in AGESA
by Paul Menzel 21 Apr '14

21 Apr '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3316 -gerrit commit 2db71c690c5b0aaa98dcf0980f4d8071a381da53 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Mon May 27 16:00:25 2013 +0200 AMD Fam15tn: Fix IOMMU scratch support in AGESA The IOMMU support is broken and does not even compile. Adding the header file `GnbIommuScratch.h` for the function `GnbIommuScratchMemoryRangeInterface()` and fixing the 64-bit versus 32-bit address issue, the file compiles now and is therefore hooked up into the build system. Change-Id: I1924a113af12b186edcdf1956cb5ec5453aee34c Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 2 + .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 8 +++- .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 55 ++++++++++++++++++++++ 3 files changed, 64 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 00ace78..70b3880 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -78,6 +78,7 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIvrsLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbIommuLib AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbTable AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV4 +AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbIommuScratch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Debug @@ -241,6 +242,7 @@ libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c libagesa-y += Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c +libagesa-y += Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c libagesa-y += Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c libagesa-y += Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c libagesa-y += Proc/GNB/Modules/GnbNbInitLibV1/GnbNbInitLibV1.c diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index 45d0cd7..9bdc854 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -57,6 +57,7 @@ #include "GnbRegistersTN.h" #include "heapManager.h" #include "Filecode.h" +#include "GnbIommuScratch.h" #define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE /*---------------------------------------------------------------------------------------- * D E F I N I T I O N S A N D M A C R O S @@ -111,9 +112,14 @@ GnbIommuScratchMemoryRangeInterface ( return AGESA_FATAL; } + /* align the address to 64 bytes boundary */ +#ifdef __x86_64__ AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; - +#else + AddressLow = ((((UINT32) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = 0; +#endif GnbHandle = GnbGetHandle (StdHeader); while (GnbHandle != NULL) { if (GnbFmCheckIommuPresent (GnbHandle, StdHeader)) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..4edcb37 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,55 @@ +/* $NoKeywords:$ */ +/** + * @file + * + * NB services + * IOMMU scratch page + * + * + * + * @xrefitem bom "File Content Label" "Release Content" + * @e project: AGESA + * @e sub-project: GNB + * @e \$Revision: $ @e \$Date: $ + * + */ +/* +***************************************************************************** +* + * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY + * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND + * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* *************************************************************************** +* +*/ + +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif

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Patch merged into coreboot/master: 86777e3 southbridge/hudson: Initialize ACPI IO ports separate of FADT
by gerrit＠coreboot.org 21 Apr '14

21 Apr '14

the following patch was just integrated into master: commit 86777e36b3238feaf91558b969c1794057c5ff47 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 20 14:36:29 2014 -0500 southbridge/hudson: Initialize ACPI IO ports separate of FADT The ACPI IO ports, and the respective SMI (for HAVE_SMI_HANDLER), were initialized when the FADT table was written. This works well on a cold boot, but the ACPI ports are not initialized on S3 resume, as ACPI tables are not written. This will not work on S3 resume if the default ports are not what we set them, or if AGESA sets them to some other value. To solve this, move the port configuration to southbridge chip init. Change-Id: Ib4043f0fa5e20f08d320acd12ce84d4d789cd035 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5559 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5559 for details. -gerrit

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Patch merged into coreboot/master: cf38fac hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
by gerrit＠coreboot.org 21 Apr '14

21 Apr '14

the following patch was just integrated into master: commit cf38facbd2255562cfbf2a2bc528794fafa5891a Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 16:22:53 2014 -0500 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18 The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly. Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5556 for details. -gerrit

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Patch merged into coreboot/master: 7efd5fd hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11
by gerrit＠coreboot.org 21 Apr '14

21 Apr '14

the following patch was just integrated into master: commit 7efd5fda490dba79a30aeb83d966349eaf59baea Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 13:36:49 2014 -0500 hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11 Hudson ASL files assume the USB power event notifications are mapped to GPE 0xb. Since that GPE is not used on this board, map these events to GPE11. This GPE is already handled in ACPI via Method(_L0B). We adjust this method to also notify the XHCI controller at PCI 10:0. Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5554 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5554 for details. -gerrit

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Patch merged into coreboot/master: 44f2fab AMD hudson and yangtze boards: Let mainboard declare power button
by gerrit＠coreboot.org 21 Apr '14

21 Apr '14

the following patch was just integrated into master: commit 44f2fab89a099b055e3ad7dc5cfe2fbeb82467e6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 01:42:19 2014 -0500 AMD hudson and yangtze boards: Let mainboard declare power button The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and always had the wake source declared as GPE3. This is not the correct wake source for all boards. On some laptops declaring a wake source is not needed, as the wake mechanism is handled by the EC. Move the declaration of the power button to mainboard ASL files, and scope it as \_SB.PWRB . This also makes the naming consistent with the examples in the ACPI spec. The wake source for the PWRB of HP Pavilion M6 1035dx is removed, as it is incorrect. Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5546 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5546 for details. -gerrit

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Patch set updated for coreboot: afd309d superio/ite/it8721f: Rewrite from hardcoded base addr
by Edward O'Callaghan 21 Apr '14

21 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5561 -gerrit commit afd309dd359768e4acd7bc7901a352c6757a2b0f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon Apr 21 17:34:38 2014 +1000 superio/ite/it8721f: Rewrite from hardcoded base addr Rewrite early_serial.c implementation to honour a passed base address in device_t, removing any hard coding of values. We also expose early sio init functions as romstage symbols to avoid falsely #including "early_serial.c" in romstage.c of board support. Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m5a88-v/romstage.c | 2 +- src/superio/ite/it8721f/Makefile.inc | 2 +- src/superio/ite/it8721f/chip.h | 3 +- src/superio/ite/it8721f/early_serial.c | 74 +++++++++++++++------------------- src/superio/ite/it8721f/it8721f.h | 18 +++++---- src/superio/ite/it8721f/superio.c | 3 +- 6 files changed, 48 insertions(+), 54 deletions(-) diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index db8b7b5..94a1e4e 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -41,7 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8721f/early_serial.c" +#include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc index 712d020..ef616f4 100644 --- a/src/superio/ite/it8721f/Makefile.inc +++ b/src/superio/ite/it8721f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c - diff --git a/src/superio/ite/it8721f/chip.h b/src/superio/ite/it8721f/chip.h index bd04460..e903cd6 100644 --- a/src/superio/ite/it8721f/chip.h +++ b/src/superio/ite/it8721f/chip.h @@ -21,11 +21,10 @@ #ifndef SUPERIO_ITE_IT8721F_CHIP_H #define SUPERIO_ITE_IT8721F_CHIP_H -#include <device/device.h> #include <pc80/keyboard.h> struct superio_ite_it8721f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_ITE_IT8721F_CHIP_H */ diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c index 20e19b6..df66222 100644 --- a/src/superio/ite/it8721f/early_serial.c +++ b/src/superio/ite/it8721f/early_serial.c @@ -3,6 +3,7 @@ * * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -20,30 +21,25 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "it8721f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -static void it8721f_sio_write(u8 ldn, u8 index, u8 value) +static void it8721f_sio_write(device_t dev, u8 index, u8 value) { - outb(IT8721F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); + pnp_set_logical_device(dev); + pnp_write_config(dev, index, value); } -static void it8721f_enter_conf(void) +static void it8721f_enter_conf(device_t dev) { - u16 port = 0x2e; /* TODO: Don't hardcode! */ + u16 port = dev >> 8; outb(0x87, port); outb(0x01, port); @@ -51,43 +47,39 @@ static void it8721f_enter_conf(void) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void it8721f_exit_conf(void) +static void it8721f_exit_conf(device_t dev) { - it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CC, 0x02); + it8721f_sio_write(dev, IT8721F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz default). */ -void it8721f_24mhz_clkin(void) +static void it8721f_reg_write(device_t dev, u8 index, u8 value) { - it8721f_enter_conf(); - it8721f_sio_write(0x00, IT8721F_CONFIG_REG_CLOCKSEL, 0x1); - it8721f_exit_conf(); + it8721f_enter_conf(dev); + it8721f_sio_write(dev, index, value); + it8721f_exit_conf(dev); } -/* Enable the serial port(s). */ -void it8721f_enable_serial(device_t dev, u16 iobase) +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, IT8721F_GPIO) + * and pass: CLKIN_DEV + * IT8721F_UART_CLK_PREDIVIDE_24 + * IT8721F_UART_CLK_PREDIVIDE_48 (default) + */ +void it8721f_conf_clkin(device_t dev, u8 predivide) { - /* (1) Enter the configuration state (MB PnP mode). */ - it8721f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8721f_sio_write(IT8721F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8721f_sio_write(IT8721F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8721f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ - /* (3) Exit the configuration state (MB PnP mode). */ - it8721f_exit_conf(); +/* Enable the serial port(s). */ +void it8721f_enable_serial(device_t dev, u16 iobase) +{ + it8721f_enter_conf(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + it8721f_exit_conf(dev); } diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index 25300e6..9d5a528 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -19,9 +19,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8721F_IT8721F_H -#define SUPERIO_ITE_IT8721F_IT8721F_H +#ifndef SUPERIO_ITE_IT8721F_H +#define SUPERIO_ITE_IT8721F_H +#include <device/pnp.h> +#include <stdint.h> + +/* Logical Device Numbers (LDN). */ #define IT8721F_FDC 0x00 /* Floppy */ #define IT8721F_SP1 0x01 /* Com1 */ #define IT8721F_SP2 0x02 /* Com2 */ @@ -32,10 +36,10 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) -void it8721f_24mhz_clkin(void); -void it8721f_disable_reboot(void); +#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8721F_UART_CLK_PREDIVIDE_24 0x01 + +void it8721f_conf_clkin(device_t dev, u8 predivide); void it8721f_enable_serial(device_t dev, u16 iobase); -#endif -#endif +#endif /* SUPERIO_ITE_IT8721F_H */ diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 27eab49..300a480 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -67,8 +67,7 @@ static struct pnp_info pnp_dev_info[] = { static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &pnp_ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8721f_ops = {

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coreboot-gerrit April 2014