coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

1 participants
779 discussions

Patch set updated for coreboot: 6cb411c superio/ite/it8716f: Rewrite from hardcoded base addr
by Edward O'Callaghan 22 Apr '14

22 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5565 -gerrit commit 6cb411c93542220976da48fc12bfb2288bb1652c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 01:43:38 2014 +1000 superio/ite/it8716f: Rewrite from hardcoded base addr Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2n-e/romstage.c | 11 +++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 10 +++---- src/mainboard/gigabyte/m57sli/romstage.c | 11 ++++--- src/mainboard/via/pc2500e/romstage.c | 2 +- src/superio/ite/it8716f/Makefile.inc | 2 +- src/superio/ite/it8716f/chip.h | 3 +- src/superio/ite/it8716f/early_init.c | 37 ------------------------ src/superio/ite/it8716f/early_serial.c | 41 +++++++++++++++++++-------- src/superio/ite/it8716f/it8716f.h | 18 ++++++------ 9 files changed, 56 insertions(+), 79 deletions(-) diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..6892b28 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,14 +37,14 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -104,11 +104,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */ - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..86158c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,14 +38,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +125,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..44dda27 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,15 +35,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -106,7 +105,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; - uint8_t tmp = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ @@ -118,6 +116,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); +#if 0 + uint8_t tmp = 0; pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); @@ -132,6 +132,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); +#endif + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0728154..e374cf9 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,7 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/ite/it8716f/early_serial.c" +#include <superio/ite/it8716f/it8716f.h> #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 5a67656..6b3c0ce 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c - diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h index 33a265a..afdcd96 100644 --- a/src/superio/ite/it8716f/chip.h +++ b/src/superio/ite/it8716f/chip.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_CHIP_H #define SUPERIO_ITE_IT8716F_CHIP_H -#include <device/device.h> #include <pc80/keyboard.h> struct superio_ite_it8716f_config { @@ -29,4 +28,4 @@ struct superio_ite_it8716f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_ITE_IT8716F_CHIP_H */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c deleted file mode 100644 index cfac2a9..0000000 --- a/src/superio/ite/it8716f/early_init.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8716f.h" - -void it8716f_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void it8716f_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 02f0304..2085a8f 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -2,9 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +21,9 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8716f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -36,7 +31,7 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void it8716f_enter_conf(device_t dev) { u16 port = dev >> 8; @@ -46,17 +41,39 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void it8716f_exit_conf(device_t dev) { pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); } +static void it8716f_reg_write(device_t dev, u8 index, u8 value) +{ + it8716f_enter_conf(dev); + pnp_write_config(dev, index, value); + it8716f_exit_conf(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) + * and pass: CLKIN_DEV + * IT8716F_UART_CLK_PREDIVIDE_24 + * IT8716F_UART_CLK_PREDIVIDE_48 (default) + */ +void it8716f_conf_clkin(device_t dev, u8 predivide) +{ + it8716f_reg_write(dev, IT8716F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + + +/* Enable the serial port(s). */ void it8716f_enable_serial(device_t dev, u16 iobase) { - pnp_enter_ext_func_mode(dev); + it8716f_enter_conf(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + it8716f_exit_conf(dev); } diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 6657db4..12349ad 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8716F_IT8716F_H -#define SUPERIO_ITE_IT8716F_IT8716F_H +#ifndef SUPERIO_ITE_IT8716F_H +#define SUPERIO_ITE_IT8716F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ @@ -36,15 +36,15 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ +#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8716F_UART_CLK_PREDIVIDE_24 0x01 + +void it8716f_conf_clkin(device_t dev, u8 predivide); +void it8716f_enable_serial(device_t dev, u16 iobase); + #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) -void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, u16 iobase); -void it8716f_enable_serial(device_t dev, u16 iobase); -#endif - -#endif +#endif /* SUPERIO_ITE_IT8716F_H */

1 0

Patch set updated for coreboot: 5202df6 superio/ite/it8716f: Rewrite from hardcoded base addr
by Edward O'Callaghan 22 Apr '14

22 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5565 -gerrit commit 5202df6588f704bcd14a53d4588af87366204899 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 01:43:38 2014 +1000 superio/ite/it8716f: Rewrite from hardcoded base addr Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2n-e/romstage.c | 11 +++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 10 +++---- src/mainboard/gigabyte/m57sli/romstage.c | 9 ++++-- src/mainboard/via/pc2500e/romstage.c | 2 +- src/superio/ite/it8716f/Makefile.inc | 2 +- src/superio/ite/it8716f/chip.h | 3 +- src/superio/ite/it8716f/early_init.c | 37 ------------------------ src/superio/ite/it8716f/early_serial.c | 41 +++++++++++++++++++-------- src/superio/ite/it8716f/it8716f.h | 18 ++++++------ 9 files changed, 55 insertions(+), 78 deletions(-) diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..6892b28 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,14 +37,14 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -104,11 +104,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */ - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..86158c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,14 +38,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +125,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..4237b19 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,15 +35,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -118,6 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); +#if 0 pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); @@ -132,6 +132,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); +#endif + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0728154..e374cf9 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,7 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/ite/it8716f/early_serial.c" +#include <superio/ite/it8716f/it8716f.h> #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 5a67656..6b3c0ce 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c - diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h index 33a265a..afdcd96 100644 --- a/src/superio/ite/it8716f/chip.h +++ b/src/superio/ite/it8716f/chip.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_CHIP_H #define SUPERIO_ITE_IT8716F_CHIP_H -#include <device/device.h> #include <pc80/keyboard.h> struct superio_ite_it8716f_config { @@ -29,4 +28,4 @@ struct superio_ite_it8716f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_ITE_IT8716F_CHIP_H */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c deleted file mode 100644 index cfac2a9..0000000 --- a/src/superio/ite/it8716f/early_init.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8716f.h" - -void it8716f_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void it8716f_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 02f0304..3103baf 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -2,9 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +21,9 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8716f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -36,7 +31,7 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void it8716f_enter_conf(device_t dev) { u16 port = dev >> 8; @@ -46,17 +41,39 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void it8716f_exit_conf(device_t dev) { pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); } +static void it8716f_reg_write(device_t dev, u8 index, u8 value) +{ + it8716f_enter_conf(dev); + pnp_write_config(dev, index, value); + it8716f_exit_conf(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) + * and pass: CLKIN_DEV + * IT8716F_UART_CLK_PREDIVIDE_24 + * IT8716F_UART_CLK_PREDIVIDE_48 (default) + */ +void it8716f_conf_clkin(device_t dev, u8 predivide) +{ + it8716f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + + +/* Enable the serial port(s). */ void it8716f_enable_serial(device_t dev, u16 iobase) { - pnp_enter_ext_func_mode(dev); + it8716f_enter_conf(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + it8716f_exit_conf(dev); } diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 6657db4..12349ad 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8716F_IT8716F_H -#define SUPERIO_ITE_IT8716F_IT8716F_H +#ifndef SUPERIO_ITE_IT8716F_H +#define SUPERIO_ITE_IT8716F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ @@ -36,15 +36,15 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ +#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8716F_UART_CLK_PREDIVIDE_24 0x01 + +void it8716f_conf_clkin(device_t dev, u8 predivide); +void it8716f_enable_serial(device_t dev, u16 iobase); + #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) -void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, u16 iobase); -void it8716f_enable_serial(device_t dev, u16 iobase); -#endif - -#endif +#endif /* SUPERIO_ITE_IT8716F_H */

1 0

New patch to review for coreboot: cf2e632 superio/ite/it8716f: Rewrite from hardcoded base addr
by Edward O'Callaghan 22 Apr '14

22 Apr '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5565 -gerrit commit cf2e6325a2b973d88eb729209a256923e848a0b5 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Apr 23 01:43:38 2014 +1000 superio/ite/it8716f: Rewrite from hardcoded base addr Following the same reasoning as: HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr Removing hard coded magics and expose sio pnp api in romstage. Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2n-e/romstage.c | 11 +++---- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 10 +++---- src/mainboard/gigabyte/m57sli/romstage.c | 9 ++++-- src/mainboard/via/pc2500e/romstage.c | 2 +- src/superio/ite/it8716f/Makefile.inc | 2 +- src/superio/ite/it8716f/chip.h | 3 +- src/superio/ite/it8716f/early_init.c | 37 ------------------------ src/superio/ite/it8716f/early_serial.c | 41 +++++++++++++++++++-------- src/superio/ite/it8716f/it8716f.h | 18 ++++++------ 9 files changed, 55 insertions(+), 78 deletions(-) diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..6892b28 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,14 +37,14 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -104,11 +104,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - /* FIXME: This should be part of the Super I/O code/config. */ - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0x01); /* CLKIN = 24MHz */ - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..86158c8 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,14 +38,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -125,10 +125,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - pnp_enter_ext_func_mode(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x23, 0); - it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); - pnp_exit_ext_func_mode(SERIAL_DEV); + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..4237b19 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,15 +35,14 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8716f/early_serial.c" -#include "superio/ite/it8716f/early_init.c" +#include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/nvidia/mcp55/early_ctrl.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -118,6 +117,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); +#if 0 pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ pnp_write_config(SERIAL_DEV, IT8716F_CONFIG_REG_CLOCKSEL, 0x11); @@ -132,6 +132,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); +#endif + it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); + it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index 0728154..e374cf9 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,7 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" -#include "superio/ite/it8716f/early_serial.c" +#include <superio/ite/it8716f/it8716f.h> #include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 5a67656..6b3c0ce 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c - diff --git a/src/superio/ite/it8716f/chip.h b/src/superio/ite/it8716f/chip.h index 33a265a..afdcd96 100644 --- a/src/superio/ite/it8716f/chip.h +++ b/src/superio/ite/it8716f/chip.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_CHIP_H #define SUPERIO_ITE_IT8716F_CHIP_H -#include <device/device.h> #include <pc80/keyboard.h> struct superio_ite_it8716f_config { @@ -29,4 +28,4 @@ struct superio_ite_it8716f_config { struct pc_keyboard keyboard; }; -#endif +#endif /* SUPERIO_ITE_IT8716F_CHIP_H */ diff --git a/src/superio/ite/it8716f/early_init.c b/src/superio/ite/it8716f/early_init.c deleted file mode 100644 index cfac2a9..0000000 --- a/src/superio/ite/it8716f/early_init.c +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include "it8716f.h" - -void it8716f_disable_dev(device_t dev) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); -} - -void it8716f_enable_dev(device_t dev, u16 iobase) -{ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); -} diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c index 02f0304..3103baf 100644 --- a/src/superio/ite/it8716f/early_serial.c +++ b/src/superio/ite/it8716f/early_serial.c @@ -2,9 +2,8 @@ * This file is part of the coreboot project. * * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * - * Copyright (C) 2007 AMD - * Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -22,13 +21,9 @@ */ #include <arch/io.h> +#include <device/pnp.h> #include "it8716f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ @@ -36,7 +31,7 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -static void pnp_enter_ext_func_mode(device_t dev) +static void it8716f_enter_conf(device_t dev) { u16 port = dev >> 8; @@ -46,17 +41,39 @@ static void pnp_enter_ext_func_mode(device_t dev) outb((port == 0x4e) ? 0xaa : 0x55, port); } -static void pnp_exit_ext_func_mode(device_t dev) +static void it8716f_exit_conf(device_t dev) { pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); } +static void it8716f_reg_write(device_t dev, u8 index, u8 value) +{ + it8716f_enter_conf(dev); + pnp_write_config(dev, index, value); + it8716f_exit_conf(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) + * and pass: CLKIN_DEV + * IT8716F_UART_CLK_PREDIVIDE_24 + * IT8716F_UART_CLK_PREDIVIDE_48 (default) + */ +void it8716f_conf_clkin(device_t dev, u8 predivide) +{ + it8716f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + + +/* Enable the serial port(s). */ void it8716f_enable_serial(device_t dev, u16 iobase) { - pnp_enter_ext_func_mode(dev); + it8716f_enter_conf(dev); pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); - pnp_exit_ext_func_mode(dev); + it8716f_exit_conf(dev); } diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 6657db4..614fb94 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8716F_IT8716F_H -#define SUPERIO_ITE_IT8716F_IT8716F_H +#ifndef SUPERIO_ITE_IT8716F_H +#define SUPERIO_ITE_IT8716F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ @@ -36,15 +36,15 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ +#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define IT8721F_UART_CLK_PREDIVIDE_24 0x01 + +void it8716f_conf_clkin(device_t dev, u8 predivide); +void it8716f_enable_serial(device_t dev, u16 iobase); + #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); #endif -#if defined(__PRE_RAM__) -void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, u16 iobase); -void it8716f_enable_serial(device_t dev, u16 iobase); -#endif - -#endif +#endif /* SUPERIO_ITE_IT8716F_H */

1 0

Patch set updated for coreboot: 323d3fb AMD: Add common header file for CAR setup
by Kyösti Mälkki 22 Apr '14

22 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4683 -gerrit commit 323d3fb1783c0b186acd04246370523f423c0c05 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 22 16:46:31 2014 +0300 AMD: Add common header file for CAR setup Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 6 +----- src/include/cpu/amd/car.h | 22 ++++++++++++++++++++++ src/include/lib.h | 8 -------- src/mainboard/amd/dinar/romstage.c | 3 +-- src/mainboard/amd/inagua/romstage.c | 1 + src/mainboard/amd/olivehill/romstage.c | 3 +-- src/mainboard/amd/parmer/romstage.c | 3 +-- src/mainboard/amd/persimmon/romstage.c | 3 +-- src/mainboard/amd/south_station/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 3 +-- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 1 + src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 3 +-- src/mainboard/asus/f2a85-m/romstage.c | 4 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo/romstage.c | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 5 +---- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 4 +--- src/mainboard/lippert/frontrunner-af/romstage.c | 3 +-- src/mainboard/lippert/toucan-af/romstage.c | 3 +-- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- 26 files changed, 46 insertions(+), 49 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index f74f915..94ce191 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -5,6 +5,7 @@ #include <arch/stages.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/car.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -75,8 +76,6 @@ static void vErrata343(void) #endif } -void cache_as_ram_switch_stack(void *resume_backup_memory); - void post_cache_as_ram(void) { void *resume_backup_memory = NULL; @@ -113,9 +112,6 @@ void post_cache_as_ram(void) } void -cache_as_ram_new_stack (void *resume_backup_memory); - -void cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) { /* We can put data to stack again */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h new file mode 100644 index 0000000..443ce13 --- /dev/null +++ b/src/include/cpu/amd/car.h @@ -0,0 +1,22 @@ +#ifndef _CPU_AMD_CAR_H +#define _CPU_AMD_CAR_H + +#if CONFIG_CPU_AMD_GEODE_LX +void done_cache_as_ram_main(void); +#endif + +#if !(CONFIG_CPU_AMD_GEODE_LX || CONFIG_CPU_AMD_GEODE_GX1 || CONFIG_CPU_AMD_GEODE_GX2) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +#endif + +#if CONFIG_CPU_AMD_AGESA +void disable_cache_as_ram(void); +#endif + +#if CONFIG_CPU_AMD_MODEL_FXX || CONFIG_CPU_AMD_MODEL_10XXX +void cache_as_ram_switch_stack(void *resume_backup_memory); +void cache_as_ram_new_stack(void *resume_backup_memory); +void post_cache_as_ram(void); +#endif + +#endif diff --git a/src/include/lib.h b/src/include/lib.h index db2e9c7..c272eb5 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -50,14 +50,6 @@ int checkstack(void *top_of_stack, int core); extern unsigned char _estack[]; #endif -/* Defined in romstage.c */ -#if CONFIG_CPU_AMD_GEODE_LX -void cache_as_ram_main(void); -#else -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#endif -void post_cache_as_ram(void); - /* Defined in src/lib/hexdump.c */ void hexdump(const void *memory, size_t length); void hexdump32(char LEVEL, const void *d, int len); diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 91b385f..776ecd5 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 718d2b2..98c74d6 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9431d4a..6422393 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 202442c..a5d041f 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e082f60..c031c99 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/f81865f/f81865f.h> @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5614f88..4f29799 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/f81865f/f81865f.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 6bf8ac6..9c3cf5b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index f6204b9..58b88d0 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" @@ -38,7 +39,6 @@ #include <arch/cpu.h> #include "platform_cfg.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 6868755..0a7ef7c 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf850a3..cbfa743 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627hf/early_serial.c" @@ -38,7 +39,6 @@ #include <sb_cimx.h> #include "SBPLATFORM.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1) diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 9b069b7..59d95f9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index ee9983d..4aa4b04 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -26,6 +26,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/amd/agesa/s3_resume.h> +#include "cpu/amd/car.h" #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> @@ -40,9 +41,6 @@ #include <drivers/pc80/i8259.c> #include <superio/ite/it8712f/early_serial.c> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index cc2fc4b..b96f8ae 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -8,6 +8,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -75,6 +76,5 @@ void main(unsigned long bist) /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 705d429..f639d1f 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "drivers/pc80/i8254.c" @@ -45,8 +46,6 @@ #define MSR_MTRR_VARIABLE_MASK6 0x020D #define MSR_PSTATE_CONTROL 0xC0010062 -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index dd19679..24751f4 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -27,6 +27,7 @@ #include <cpu/amd/agesa/s3_resume.h> #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> +#include <cpu/amd/car.h> #include <device/pci_def.h> #include <device/pci_ids.h> #include <stdint.h> @@ -36,10 +37,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3406edf..ab68a93 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -38,6 +38,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/car.h> #include <sb_cimx.h> #include <southbridge/amd/cimx/sb800/SBPLATFORM.h> #include "superio/fintek/f71869ad/f71869ad.h" @@ -46,9 +47,6 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 9ecd087..16fb8ab 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 4f62268..9f8cf1a 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627dhg/w83627dhg.h" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index c3f964d..1c4ae09 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -162,6 +163,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 6946900..18453ac 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -186,6 +187,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ea4ed8e..acb05ab 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -33,7 +34,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 9ee1dfa..8801c45 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a6c33e8..49361a8 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0)

1 0

Patch set updated for coreboot: 00a476b AMD: Add common header file for CAR setup
by Kyösti Mälkki 22 Apr '14

22 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4683 -gerrit commit 00a476b508df293ce5ebf065eb1fea466cc8c036 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 22 16:46:31 2014 +0300 AMD: Add common header file for CAR setup Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 6 +----- src/include/cpu/amd/car.h | 22 ++++++++++++++++++++++ src/include/lib.h | 8 -------- src/mainboard/amd/dinar/romstage.c | 3 +-- src/mainboard/amd/inagua/romstage.c | 1 + src/mainboard/amd/olivehill/romstage.c | 3 +-- src/mainboard/amd/parmer/romstage.c | 3 +-- src/mainboard/amd/persimmon/romstage.c | 3 +-- src/mainboard/amd/south_station/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 3 +-- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 1 + src/mainboard/asrock/e350m1/romstage.c | 2 +- src/mainboard/asrock/imb-a180/romstage.c | 3 +-- src/mainboard/asus/f2a85-m/romstage.c | 4 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo/romstage.c | 3 +-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 ---- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 3 --- src/mainboard/lippert/frontrunner-af/romstage.c | 3 +-- src/mainboard/lippert/toucan-af/romstage.c | 3 +-- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- 26 files changed, 44 insertions(+), 49 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index f74f915..94ce191 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -5,6 +5,7 @@ #include <arch/stages.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/car.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -75,8 +76,6 @@ static void vErrata343(void) #endif } -void cache_as_ram_switch_stack(void *resume_backup_memory); - void post_cache_as_ram(void) { void *resume_backup_memory = NULL; @@ -113,9 +112,6 @@ void post_cache_as_ram(void) } void -cache_as_ram_new_stack (void *resume_backup_memory); - -void cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) { /* We can put data to stack again */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h new file mode 100644 index 0000000..443ce13 --- /dev/null +++ b/src/include/cpu/amd/car.h @@ -0,0 +1,22 @@ +#ifndef _CPU_AMD_CAR_H +#define _CPU_AMD_CAR_H + +#if CONFIG_CPU_AMD_GEODE_LX +void done_cache_as_ram_main(void); +#endif + +#if !(CONFIG_CPU_AMD_GEODE_LX || CONFIG_CPU_AMD_GEODE_GX1 || CONFIG_CPU_AMD_GEODE_GX2) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +#endif + +#if CONFIG_CPU_AMD_AGESA +void disable_cache_as_ram(void); +#endif + +#if CONFIG_CPU_AMD_MODEL_FXX || CONFIG_CPU_AMD_MODEL_10XXX +void cache_as_ram_switch_stack(void *resume_backup_memory); +void cache_as_ram_new_stack(void *resume_backup_memory); +void post_cache_as_ram(void); +#endif + +#endif diff --git a/src/include/lib.h b/src/include/lib.h index db2e9c7..c272eb5 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -50,14 +50,6 @@ int checkstack(void *top_of_stack, int core); extern unsigned char _estack[]; #endif -/* Defined in romstage.c */ -#if CONFIG_CPU_AMD_GEODE_LX -void cache_as_ram_main(void); -#else -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#endif -void post_cache_as_ram(void); - /* Defined in src/lib/hexdump.c */ void hexdump(const void *memory, size_t length); void hexdump32(char LEVEL, const void *d, int len); diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 91b385f..776ecd5 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 718d2b2..98c74d6 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9431d4a..6422393 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 202442c..a5d041f 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e082f60..c031c99 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/f81865f/f81865f.h> @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5614f88..4f29799 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/f81865f/f81865f.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 6bf8ac6..9c3cf5b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index f6204b9..58b88d0 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" @@ -38,7 +39,6 @@ #include <arch/cpu.h> #include "platform_cfg.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 6868755..0a7ef7c 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf850a3..cbfa743 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627hf/early_serial.c" @@ -38,7 +39,6 @@ #include <sb_cimx.h> #include "SBPLATFORM.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1) diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 9b069b7..59d95f9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index ee9983d..4aa4b04 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -26,6 +26,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/amd/agesa/s3_resume.h> +#include "cpu/amd/car.h" #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> @@ -40,9 +41,6 @@ #include <drivers/pc80/i8259.c> #include <superio/ite/it8712f/early_serial.c> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index cc2fc4b..b96f8ae 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -8,6 +8,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -75,6 +76,5 @@ void main(unsigned long bist) /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 705d429..f639d1f 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -30,6 +30,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "drivers/pc80/i8254.c" @@ -45,8 +46,6 @@ #define MSR_MTRR_VARIABLE_MASK6 0x020D #define MSR_PSTATE_CONTROL 0xC0010062 -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index dd19679..271fb91 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -36,10 +36,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3406edf..f9d5136 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -46,9 +46,6 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 9ecd087..16fb8ab 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 4f62268..9f8cf1a 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -29,6 +29,7 @@ #include <console/console.h> #include <console/loglevel.h> #include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627dhg/w83627dhg.h" @@ -42,8 +43,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index c3f964d..1c4ae09 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -162,6 +163,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 6946900..18453ac 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -186,6 +187,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ea4ed8e..acb05ab 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -33,7 +34,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 9ee1dfa..8801c45 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a6c33e8..49361a8 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0)

1 0

Patch set updated for coreboot: 065032f AMD K8: Drop use of lib/generic_sdram.c
by Kyösti Mälkki 22 Apr '14

22 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4682 -gerrit commit 065032f01edd37a761798f39fa9f0831ea878612 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 6 19:24:14 2014 +0200 AMD K8: Drop use of lib/generic_sdram.c Function sdram_enable() requires platform-specific header files, making it non-generic and the file cannot be built as a separate file under lib. Change-Id: I5ce00d9c93f49f440fb05b1565b97febc3a8dc7a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/generic_sdram.c | 21 ------------ src/mainboard/amd/dbm690t/romstage.c | 1 - src/mainboard/amd/mahogany/romstage.c | 1 - src/mainboard/amd/pistachio/romstage.c | 1 - src/mainboard/amd/serengeti_cheetah/romstage.c | 1 - src/mainboard/arima/hdama/romstage.c | 1 - src/mainboard/asrock/939a785gmh/romstage.c | 1 - src/mainboard/asus/a8n_e/romstage.c | 1 - src/mainboard/asus/a8v-e_deluxe/romstage.c | 1 - src/mainboard/asus/a8v-e_se/romstage.c | 1 - src/mainboard/asus/k8v-x/romstage.c | 1 - src/mainboard/asus/m2n-e/romstage.c | 1 - src/mainboard/asus/m2v-mx_se/romstage.c | 1 - src/mainboard/asus/m2v/romstage.c | 1 - src/mainboard/broadcom/blast/romstage.c | 1 - src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 1 - src/mainboard/gigabyte/m57sli/romstage.c | 1 - src/mainboard/hp/dl145_g1/romstage.c | 1 - src/mainboard/hp/dl145_g3/romstage.c | 1 - src/mainboard/ibm/e325/romstage.c | 1 - src/mainboard/ibm/e326/romstage.c | 1 - src/mainboard/iwill/dk8_htx/romstage.c | 1 - src/mainboard/iwill/dk8s2/romstage.c | 1 - src/mainboard/iwill/dk8x/romstage.c | 1 - src/mainboard/kontron/kt690/romstage.c | 1 - src/mainboard/msi/ms7135/romstage.c | 1 - src/mainboard/msi/ms7260/romstage.c | 1 - src/mainboard/msi/ms9185/romstage.c | 1 - src/mainboard/msi/ms9282/romstage.c | 1 - src/mainboard/newisys/khepri/romstage.c | 1 - src/mainboard/nvidia/l1_2pvv/romstage.c | 1 - src/mainboard/siemens/sitemp_g1p1/romstage.c | 1 - src/mainboard/sunw/ultra40/romstage.c | 1 - src/mainboard/supermicro/h8dme/romstage.c | 1 - src/mainboard/supermicro/h8dmr/romstage.c | 1 - src/mainboard/technexion/tim5690/romstage.c | 1 - src/mainboard/technexion/tim8690/romstage.c | 1 - src/mainboard/tyan/s2850/romstage.c | 1 - src/mainboard/tyan/s2875/romstage.c | 1 - src/mainboard/tyan/s2880/romstage.c | 1 - src/mainboard/tyan/s2881/romstage.c | 1 - src/mainboard/tyan/s2882/romstage.c | 1 - src/mainboard/tyan/s2885/romstage.c | 1 - src/mainboard/tyan/s2891/romstage.c | 1 - src/mainboard/tyan/s2892/romstage.c | 1 - src/mainboard/tyan/s2895/romstage.c | 1 - src/mainboard/tyan/s2912/romstage.c | 1 - src/mainboard/tyan/s4880/romstage.c | 1 - src/mainboard/tyan/s4882/romstage.c | 1 - src/mainboard/winent/mb6047/romstage.c | 1 - src/northbridge/amd/amdk8/raminit.c | 44 ++++++++++++++++++++++++++ src/northbridge/amd/amdk8/raminit.h | 2 +- src/northbridge/amd/amdk8/raminit_f.c | 27 ++++++++++++++++ 53 files changed, 72 insertions(+), 71 deletions(-) diff --git a/src/lib/generic_sdram.c b/src/lib/generic_sdram.c index efb61db..3e0335f 100644 --- a/src/lib/generic_sdram.c +++ b/src/lib/generic_sdram.c @@ -10,34 +10,19 @@ static inline void print_debug_sdram_8(const char *strval, uint32_t val) } /* Setup SDRAM */ -#if CONFIG_RAMINIT_SYSINFO -void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) -#else void sdram_initialize(int controllers, const struct mem_controller *ctrl) -#endif { int i; /* Set the registers we can set once to reasonable values */ for(i = 0; i < controllers; i++) { print_debug_sdram_8("Ram1.", i); - - #if CONFIG_RAMINIT_SYSINFO - sdram_set_registers(ctrl + i, sysinfo); - #else sdram_set_registers(ctrl + i); - #endif } /* Now setup those things we can auto detect */ for(i = 0; i < controllers; i++) { print_debug_sdram_8("Ram2.", i); - - #if CONFIG_RAMINIT_SYSINFO - sdram_set_spd_registers(ctrl + i, sysinfo); - #else sdram_set_spd_registers(ctrl + i); - #endif - } /* Now that everything is setup enable the SDRAM. @@ -45,12 +30,6 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl) * we need to it by hand. */ print_debug("Ram3\n"); - - #if CONFIG_RAMINIT_SYSINFO - sdram_enable(controllers, ctrl, sysinfo); - #else sdram_enable(controllers, ctrl); - #endif - print_debug("Ram4\n"); } diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 74b6d1b..45d7e1a 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -55,7 +55,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index b77d4b5..22bd6e1 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -56,7 +56,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 2971072..ab98cad 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -50,7 +50,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index b103389..b360686 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -69,7 +69,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/arima/hdama/romstage.c b/src/mainboard/arima/hdama/romstage.c index 3c7eb58..b9facb1 100644 --- a/src/mainboard/arima/hdama/romstage.c +++ b/src/mainboard/arima/hdama/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index edc5830..9afd978 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -60,7 +60,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..fccd2ce 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -56,7 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" #include "southbridge/nvidia/ck804/early_setup.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index efc4ac7..8c94cf2 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -81,7 +81,6 @@ void soft_reset(void) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 19f5686..c396694 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -81,7 +81,6 @@ void soft_reset(void) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4fe1016..bbe6830 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -79,7 +79,6 @@ void soft_reset(void) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 2f3baf6..5ac8563 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/mcp55/early_setup_ss.h" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..6d714e2 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -60,7 +60,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..62afc78 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -62,7 +62,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index fcdac69..2ca4d62 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -50,7 +50,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 4d215ae..6236a33 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 77eae09..2a71f9f 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index a5df58d..4eb5f30 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -82,7 +82,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 0d8e9d2..47f379f 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -71,7 +71,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include <spd.h> #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/ibm/e325/romstage.c b/src/mainboard/ibm/e325/romstage.c index b44668a..0db6920 100644 --- a/src/mainboard/ibm/e325/romstage.c +++ b/src/mainboard/ibm/e325/romstage.c @@ -54,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/ibm/e326/romstage.c b/src/mainboard/ibm/e326/romstage.c index c703b7a..eebbccb 100644 --- a/src/mainboard/ibm/e326/romstage.c +++ b/src/mainboard/ibm/e326/romstage.c @@ -54,7 +54,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 070fb07..007e912 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/iwill/dk8s2/romstage.c b/src/mainboard/iwill/dk8s2/romstage.c index 7c8d4a5..082699a 100644 --- a/src/mainboard/iwill/dk8s2/romstage.c +++ b/src/mainboard/iwill/dk8s2/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/iwill/dk8x/romstage.c b/src/mainboard/iwill/dk8x/romstage.c index b5a1d71..4f4a2b7 100644 --- a/src/mainboard/iwill/dk8x/romstage.c +++ b/src/mainboard/iwill/dk8x/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 52e54d4..87f93dd 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index ccb420a..ebfb76c 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -60,7 +60,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) } #include "northbridge/amd/amdk8/raminit.c" -#include "lib/generic_sdram.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" #include "southbridge/nvidia/ck804/early_setup_car.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index 68feb3b..0990c42 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index 2cb38a4..d5aa0b8 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -78,7 +78,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 19592f3..2567479 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -76,7 +76,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/mcp55/early_setup_ss.h" diff --git a/src/mainboard/newisys/khepri/romstage.c b/src/mainboard/newisys/khepri/romstage.c index 652104a..9471b4e 100644 --- a/src/mainboard/newisys/khepri/romstage.c +++ b/src/mainboard/newisys/khepri/romstage.c @@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index d411354..5ab0eb7 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -56,7 +56,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6d36524..e8ae2b0 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -73,7 +73,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 7c112da..65d813f 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -48,7 +48,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index df5e2c8..5c69246 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -117,7 +117,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/mcp55/early_setup_ss.h" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 8ed7e6d..8377425 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -58,7 +58,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/mcp55/early_setup_ss.h" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 42c2599..767628a 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -55,7 +55,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 22a1212..9a59d66 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -55,7 +55,6 @@ static inline int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c index 301f81c..4d7755c 100644 --- a/src/mainboard/tyan/s2850/romstage.c +++ b/src/mainboard/tyan/s2850/romstage.c @@ -50,7 +50,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c index 7c9f93a..aa2c94f 100644 --- a/src/mainboard/tyan/s2875/romstage.c +++ b/src/mainboard/tyan/s2875/romstage.c @@ -49,7 +49,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2880/romstage.c b/src/mainboard/tyan/s2880/romstage.c index 13cc01e..31fa09c 100644 --- a/src/mainboard/tyan/s2880/romstage.c +++ b/src/mainboard/tyan/s2880/romstage.c @@ -50,7 +50,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2881/romstage.c b/src/mainboard/tyan/s2881/romstage.c index dad2b6b..0ed35d7 100644 --- a/src/mainboard/tyan/s2881/romstage.c +++ b/src/mainboard/tyan/s2881/romstage.c @@ -49,7 +49,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2882/romstage.c b/src/mainboard/tyan/s2882/romstage.c index 13cc01e..31fa09c 100644 --- a/src/mainboard/tyan/s2882/romstage.c +++ b/src/mainboard/tyan/s2882/romstage.c @@ -50,7 +50,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/resourcemap.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index a2dc990..923875a 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -48,7 +48,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/tyan/s2891/romstage.c b/src/mainboard/tyan/s2891/romstage.c index aa0385b..ddc11ea 100644 --- a/src/mainboard/tyan/s2891/romstage.c +++ b/src/mainboard/tyan/s2891/romstage.c @@ -33,7 +33,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" diff --git a/src/mainboard/tyan/s2892/romstage.c b/src/mainboard/tyan/s2892/romstage.c index 5d6ff2a..3fc4b73 100644 --- a/src/mainboard/tyan/s2892/romstage.c +++ b/src/mainboard/tyan/s2892/romstage.c @@ -32,7 +32,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c index 4f0e552..4ed501c 100644 --- a/src/mainboard/tyan/s2895/romstage.c +++ b/src/mainboard/tyan/s2895/romstage.c @@ -48,7 +48,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index e4a1c65..2c28451 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -57,7 +57,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c index 2b6470c..aaae8c2 100644 --- a/src/mainboard/tyan/s4880/romstage.c +++ b/src/mainboard/tyan/s4880/romstage.c @@ -67,7 +67,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/tyan/s4882/romstage.c b/src/mainboard/tyan/s4882/romstage.c index 60dbdf8..2c8655a 100644 --- a/src/mainboard/tyan/s4882/romstage.c +++ b/src/mainboard/tyan/s4882/romstage.c @@ -75,7 +75,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 07f235c..c18917a 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -33,7 +33,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/early_setup_ss.h" #include "southbridge/nvidia/ck804/early_setup.c" diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index e4fe3df..371bac9 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -2520,3 +2520,47 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, } } } + +/* Setup SDRAM */ +#if CONFIG_RAMINIT_SYSINFO +void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) +#else +void sdram_initialize(int controllers, const struct mem_controller *ctrl) +#endif +{ + int i; + /* Set the registers we can set once to reasonable values */ + for(i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram1.%02x\n", i); + #if CONFIG_RAMINIT_SYSINFO + sdram_set_registers(ctrl + i, sysinfo); + #else + sdram_set_registers(ctrl + i); + #endif + } + + /* Now setup those things we can auto detect */ + for(i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram2.%02x\n", i); + #if CONFIG_RAMINIT_SYSINFO + sdram_set_spd_registers(ctrl + i, sysinfo); + #else + sdram_set_spd_registers(ctrl + i); + #endif + + } + + /* Now that everything is setup enable the SDRAM. + * Some chipsets do the work for us while on others + * we need to it by hand. + */ + print_debug("Ram3\n"); + + #if CONFIG_RAMINIT_SYSINFO + sdram_enable(controllers, ctrl, sysinfo); + #else + sdram_enable(controllers, ctrl); + #endif + + print_debug("Ram4\n"); +} diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 9da8417..a442e6c 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -15,7 +15,7 @@ struct sys_info; void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); void setup_resource_map(const unsigned int *register_values, int max); -#if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO +#if CONFIG_RAMINIT_SYSINFO void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); #else void sdram_initialize(int controllers, const struct mem_controller *ctrl); diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 9c99250..22a1fbc 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -3253,3 +3253,30 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a, } } } + +/* Setup SDRAM */ +void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo) +{ + int i; + /* Set the registers we can set once to reasonable values */ + for(i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram1.%02x\n", i); + sdram_set_registers(ctrl + i, sysinfo); + } + + /* Now setup those things we can auto detect */ + for(i = 0; i < controllers; i++) { + printk(BIOS_DEBUG, "Ram2.%02x\n", i); + sdram_set_spd_registers(ctrl + i, sysinfo); + } + + /* Now that everything is setup enable the SDRAM. + * Some chipsets do the work for us while on others + * we need to it by hand. + */ + print_debug("Ram3\n"); + + sdram_enable(controllers, ctrl, sysinfo); + + print_debug("Ram4\n"); +}

1 0

Patch set updated for coreboot: 4c97982 AMD: Add common header file for CAR setup
by Kyösti Mälkki 22 Apr '14

22 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4683 -gerrit commit 4c97982c4b95fe1c784d023997321e1d012d7f2f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 22 16:46:31 2014 +0300 AMD: Add common header file for CAR setup Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 6 +----- src/include/cpu/amd/car.h | 22 ++++++++++++++++++++++ src/include/lib.h | 8 -------- src/mainboard/amd/dinar/romstage.c | 3 +-- src/mainboard/amd/inagua/romstage.c | 2 +- src/mainboard/amd/olivehill/romstage.c | 3 +-- src/mainboard/amd/parmer/romstage.c | 3 +-- src/mainboard/amd/persimmon/romstage.c | 4 +--- src/mainboard/amd/south_station/romstage.c | 2 +- src/mainboard/amd/thatcher/romstage.c | 3 +-- src/mainboard/amd/torpedo/romstage.c | 2 +- src/mainboard/amd/union_station/romstage.c | 2 +- src/mainboard/asrock/e350m1/romstage.c | 3 +-- src/mainboard/asrock/imb-a180/romstage.c | 3 +-- src/mainboard/asus/f2a85-m/romstage.c | 4 +--- src/mainboard/digitallogic/msm800sev/romstage.c | 2 +- src/mainboard/gizmosphere/gizmo/romstage.c | 4 +--- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 ---- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 3 --- src/mainboard/lippert/frontrunner-af/romstage.c | 4 +--- src/mainboard/lippert/toucan-af/romstage.c | 4 +--- src/mainboard/pcengines/alix1c/romstage.c | 2 +- src/mainboard/pcengines/alix2d/romstage.c | 2 +- src/mainboard/supermicro/h8qgi/romstage.c | 2 +- src/mainboard/supermicro/h8scm/romstage.c | 2 +- src/mainboard/tyan/s8226/romstage.c | 2 +- 26 files changed, 44 insertions(+), 57 deletions(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index f74f915..94ce191 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -5,6 +5,7 @@ #include <arch/stages.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> +#include <cpu/amd/car.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" @@ -75,8 +76,6 @@ static void vErrata343(void) #endif } -void cache_as_ram_switch_stack(void *resume_backup_memory); - void post_cache_as_ram(void) { void *resume_backup_memory = NULL; @@ -113,9 +112,6 @@ void post_cache_as_ram(void) } void -cache_as_ram_new_stack (void *resume_backup_memory); - -void cache_as_ram_new_stack (void *resume_backup_memory __attribute__ ((unused))) { /* We can put data to stack again */ diff --git a/src/include/cpu/amd/car.h b/src/include/cpu/amd/car.h new file mode 100644 index 0000000..443ce13 --- /dev/null +++ b/src/include/cpu/amd/car.h @@ -0,0 +1,22 @@ +#ifndef _CPU_AMD_CAR_H +#define _CPU_AMD_CAR_H + +#if CONFIG_CPU_AMD_GEODE_LX +void done_cache_as_ram_main(void); +#endif + +#if !(CONFIG_CPU_AMD_GEODE_LX || CONFIG_CPU_AMD_GEODE_GX1 || CONFIG_CPU_AMD_GEODE_GX2) +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); +#endif + +#if CONFIG_CPU_AMD_AGESA +void disable_cache_as_ram(void); +#endif + +#if CONFIG_CPU_AMD_MODEL_FXX || CONFIG_CPU_AMD_MODEL_10XXX +void cache_as_ram_switch_stack(void *resume_backup_memory); +void cache_as_ram_new_stack(void *resume_backup_memory); +void post_cache_as_ram(void); +#endif + +#endif diff --git a/src/include/lib.h b/src/include/lib.h index db2e9c7..c272eb5 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -50,14 +50,6 @@ int checkstack(void *top_of_stack, int core); extern unsigned char _estack[]; #endif -/* Defined in romstage.c */ -#if CONFIG_CPU_AMD_GEODE_LX -void cache_as_ram_main(void); -#else -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -#endif -void post_cache_as_ram(void); - /* Defined in src/lib/hexdump.c */ void hexdump(const void *memory, size_t length); void hexdump32(char LEVEL, const void *d, int len); diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 91b385f..776ecd5 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, SMSCSUPERIO_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); u32 agesawrapper_amdinitmmio (void); u32 agesawrapper_amdinitreset (void); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 718d2b2..b836ff5 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -29,7 +29,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9431d4a..6422393 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 202442c..a5d041f 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -37,8 +38,6 @@ #include "src/drivers/pc80/i8259.c" #include "cbmem.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index e082f60..464fe29 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/f81865f/f81865f.h> @@ -42,8 +42,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, F81865F_SP1) diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 5614f88..76395e9 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -29,7 +29,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include <superio/fintek/f81865f/f81865f.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 6bf8ac6..9c3cf5b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index f6204b9..58b88d0 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -27,6 +27,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" @@ -38,7 +39,6 @@ #include <arch/cpu.h> #include "platform_cfg.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 6868755..85fc567 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -29,7 +29,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index bf850a3..39c6072 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627hf/early_serial.c" @@ -38,7 +38,6 @@ #include <sb_cimx.h> #include "SBPLATFORM.h" -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(CONFIG_SIO_PORT, W83627HF_SP1) diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 9b069b7..59d95f9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -28,6 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" @@ -40,8 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index ee9983d..4aa4b04 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -26,6 +26,7 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/amd/agesa/s3_resume.h> +#include "cpu/amd/car.h" #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <device/pci_def.h> @@ -40,9 +41,6 @@ #include <drivers/pc80/i8259.c> #include <superio/ite/it8712f/early_serial.c> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c index cc2fc4b..b96f8ae 100644 --- a/src/mainboard/digitallogic/msm800sev/romstage.c +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -8,6 +8,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" @@ -75,6 +76,5 @@ void main(unsigned long bist) /* we are finding the return does not work on this board. Explicitly call the label that is * after the call to us. This is gross, but sometimes at this level it is the only way out */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 705d429..b8beb84 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -29,7 +29,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "drivers/pc80/i8254.c" @@ -45,8 +45,6 @@ #define MSR_MTRR_VARIABLE_MASK6 0x020D #define MSR_PSTATE_CONTROL 0xC0010062 -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index dd19679..271fb91 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -36,10 +36,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); -void disable_cache_as_ram(void); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 3406edf..f9d5136 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -46,9 +46,6 @@ #include "drivers/pc80/i8254.c" #include "drivers/pc80/i8259.c" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 9ecd087..878ae15 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" @@ -42,8 +42,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1) diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 4f62268..b39d296 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -28,7 +28,7 @@ #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> -#include <cpu/x86/mtrr.h> +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" #include "superio/winbond/w83627dhg/w83627dhg.h" @@ -42,8 +42,6 @@ #include "cpu/amd/mtrr.h" #include "cpu/amd/agesa/s3_resume.h" -void disable_cache_as_ram(void); /* cache_as_ram.inc */ -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx); #define SERIAL_DEV PNP_DEV(0x4e, W83627DHG_SP1) diff --git a/src/mainboard/pcengines/alix1c/romstage.c b/src/mainboard/pcengines/alix1c/romstage.c index c3f964d..1c4ae09 100644 --- a/src/mainboard/pcengines/alix1c/romstage.c +++ b/src/mainboard/pcengines/alix1c/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -162,6 +163,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/pcengines/alix2d/romstage.c b/src/mainboard/pcengines/alix2d/romstage.c index 6946900..18453ac 100644 --- a/src/mainboard/pcengines/alix2d/romstage.c +++ b/src/mainboard/pcengines/alix2d/romstage.c @@ -29,6 +29,7 @@ #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include <cpu/amd/lxdef.h> +#include <cpu/amd/car.h> #include "southbridge/amd/cs5536/cs5536.h" #include "northbridge/amd/lx/raminit.h" @@ -186,6 +187,5 @@ void main(unsigned long bist) * call the label that is after the call to us. This is gross, but * sometimes at this level it is the only way out. */ - void done_cache_as_ram_main(void); done_cache_as_ram_main(); } diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index ea4ed8e..acb05ab 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -33,7 +34,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 9ee1dfa..8801c45 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "superio/nuvoton/wpcm450/wpcm450.h" #include "superio/winbond/w83627dhg/w83627dhg.h" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a6c33e8..49361a8 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" +#include "cpu/amd/car.h" #include "agesawrapper.h" #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> @@ -35,7 +36,6 @@ #include "src/drivers/pc80/i8254.c" #include "src/drivers/pc80/i8259.c" -extern void disable_cache_as_ram(void); /* cache_as_ram.inc */ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0)

1 0

Patch set updated for coreboot: ea95d21 AMD: Declare acpi_is_wakeup_early only once
by Kyösti Mälkki 22 Apr '14

22 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4525 -gerrit commit ea95d21f145b68cfd805d5673cdb3b087335bc6b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Dec 10 09:03:17 2013 +0200 AMD: Declare acpi_is_wakeup_early only once Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/acpi.h | 2 ++ src/cpu/amd/car/post_cache_as_ram.c | 1 + src/mainboard/amd/olivehill/romstage.c | 1 + src/mainboard/amd/parmer/romstage.c | 1 + src/mainboard/amd/persimmon/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 1 + src/mainboard/asrock/imb-a180/romstage.c | 1 + src/mainboard/asus/f2a85-m/romstage.c | 1 + src/mainboard/gizmosphere/gizmo/romstage.c | 1 + src/mainboard/lippert/frontrunner-af/romstage.c | 1 + src/mainboard/lippert/toucan-af/romstage.c | 1 + src/mainboard/via/epia-m700/romstage.c | 1 + src/northbridge/amd/amdk8/raminit.c | 1 + src/southbridge/amd/agesa/hudson/hudson.h | 2 -- src/southbridge/amd/cimx/sb800/sb_cimx.h | 2 -- src/southbridge/amd/sb700/early_setup.c | 2 +- src/southbridge/amd/sb700/sb700.h | 4 ---- src/southbridge/amd/sb800/early_setup.c | 3 ++- src/southbridge/via/vt8237r/early_smbus.c | 5 ++++- 19 files changed, 21 insertions(+), 11 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index d73c046..6df3a18 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -567,6 +567,8 @@ void *acpi_get_wakeup_rsdp(void); void acpi_jump_to_wakeup(void *wakeup_addr); int acpi_get_sleep_type(void); +int acpi_is_wakeup_early(void); + #else /* CONFIG_HAVE_ACPI_RESUME */ #define acpi_slp_type 0 #endif /* CONFIG_HAVE_ACPI_RESUME */ diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 94ce191..a92e6af 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -6,6 +6,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/amd/car.h> +#include <arch/acpi.h> #include "cbmem.h" #include "cpu/amd/car/disable_cache_as_ram.c" diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 6422393..c62b2f7 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index a5d041f..1b9a0bb 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 464fe29..ce8b617 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 9c3cf5b..1697054 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 59d95f9..69474e2 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 4aa4b04..07cef00 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -22,6 +22,7 @@ #include <arch/cpu.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <cbmem.h> #include <console/console.h> diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index b8beb84..7cb5e2a 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -26,6 +26,7 @@ #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> +#include <arch/acpi.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <console/loglevel.h> diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 878ae15..998243b 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index b39d296..bb06a2d 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <arch/stages.h> #include <device/pnp_def.h> #include <arch/cpu.h> diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index fda1bb0..e051cc0 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -28,6 +28,7 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> +#include <arch/acpi.h> #include <device/pnp_def.h> #include <arch/hlt.h> #include <console/console.h> diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c index 371bac9..7d2ad0d 100644 --- a/src/northbridge/amd/amdk8/raminit.c +++ b/src/northbridge/amd/amdk8/raminit.c @@ -8,6 +8,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <stdlib.h> +#include <arch/acpi.h> #include <reset.h> #include "raminit.h" #include "amdk8.h" diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 6f757eb..6659ba5 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -67,8 +67,6 @@ void hudson_clk_output_48Mhz(void); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -int acpi_is_wakeup_early(void); - #else void hudson_enable(device_t dev); void __attribute__((weak)) hudson_setup_sata_phys(struct device *dev); diff --git a/src/southbridge/amd/cimx/sb800/sb_cimx.h b/src/southbridge/amd/cimx/sb800/sb_cimx.h index 6267e1c..cd8c42b 100644 --- a/src/southbridge/amd/cimx/sb800/sb_cimx.h +++ b/src/southbridge/amd/cimx/sb800/sb_cimx.h @@ -32,8 +32,6 @@ void sb_Late_Post(void); void sb_Before_Pci_Restore_Init(void); void sb_After_Pci_Restore_Init(void); -int acpi_is_wakeup_early(void); - /** * CIMX not set the clock to 48Mhz until sbBeforePciInit, * coreboot may need to set this even more earlier diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index ddba1a8..8ecf04d 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -22,12 +22,12 @@ #include <stdint.h> #include <arch/cpu.h> +#include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> #include <cpu/x86/msr.h> #include <reset.h> -#include <arch/cpu.h> #include <cbmem.h> #include "sb700.h" #include "smbus.h" diff --git a/src/southbridge/amd/sb700/sb700.h b/src/southbridge/amd/sb700/sb700.h index b70e395..2cbfdc9 100644 --- a/src/southbridge/amd/sb700/sb700.h +++ b/src/southbridge/amd/sb700/sb700.h @@ -75,10 +75,6 @@ void sb7xx_51xx_setup_sata_phys(struct device *dev); #endif -#if CONFIG_HAVE_ACPI_RESUME -int acpi_is_wakeup_early(void); -#endif - int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); diff --git a/src/southbridge/amd/sb800/early_setup.c b/src/southbridge/amd/sb800/early_setup.c index 213cae9..2c12b39 100644 --- a/src/southbridge/amd/sb800/early_setup.c +++ b/src/southbridge/amd/sb800/early_setup.c @@ -22,6 +22,7 @@ #include <reset.h> #include <arch/cpu.h> +#include <arch/acpi.h> #include <cbmem.h> #include "sb800.h" #include "smbus.c" @@ -666,7 +667,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) } #if CONFIG_HAVE_ACPI_RESUME -static int acpi_is_wakeup_early(void) +int acpi_is_wakeup_early(void) { u16 tmp; tmp = inw(ACPI_PM1_CNT_BLK); diff --git a/src/southbridge/via/vt8237r/early_smbus.c b/src/southbridge/via/vt8237r/early_smbus.c index b41e1ad..1b3e960 100644 --- a/src/southbridge/via/vt8237r/early_smbus.c +++ b/src/southbridge/via/vt8237r/early_smbus.c @@ -20,6 +20,9 @@ */ #include <device/pci_ids.h> +#if CONFIG_HAVE_ACPI_RESUME +#include <arch/acpi.h> +#endif #include <spd.h> #include <stdlib.h> #include "vt8237r.h" @@ -328,7 +331,7 @@ void enable_rom_decode(void) } #if CONFIG_HAVE_ACPI_RESUME -static int acpi_is_wakeup_early(void) { +int acpi_is_wakeup_early(void) { device_t dev; u16 tmp;

1 0

Patch merged into coreboot/master: d6060b7 usbdebug: Add BeagleBone Black
by gerrit＠coreboot.org 22 Apr '14

22 Apr '14

the following patch was just integrated into master: commit d6060b7142310a7a5d3a4912bbd08d230cad90b1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 18:50:13 2013 +0300 usbdebug: Add BeagleBone Black Avoid some confusion as the selection of "BeagleBone" is not compatible with the product "BeagleBone Black". Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/4289 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> See http://review.coreboot.org/4289 for details. -gerrit

1 0

Patch set updated for coreboot: 8e51d95 usbdebug: Add BeagleBone Black
by Kyösti Mälkki 22 Apr '14

22 Apr '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4289 -gerrit commit 8e51d95ebfe114fdddf8582f49a2fba59294809a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Oct 17 18:50:13 2013 +0300 usbdebug: Add BeagleBone Black Avoid some confusion as the selection of "BeagleBone" is not compatible with the product "BeagleBone Black". Change-Id: If73f80565cd26d2b41db972b4474ab85b609c1ad Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/usb/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/drivers/usb/Kconfig b/src/drivers/usb/Kconfig index 28b95c6..f225ac1 100644 --- a/src/drivers/usb/Kconfig +++ b/src/drivers/usb/Kconfig @@ -84,6 +84,11 @@ config USBDEBUG_DONGLE_BEAGLEBONE help Use this to configure the USB hub on BeagleBone board. +config USBDEBUG_DONGLE_BEAGLEBONE_BLACK + bool "BeagleBone Black" + help + Use this with BeagleBone Black. + endchoice config USBDEBUG_OPTIONAL_HUB_PORT

1 0

← Newer
1
...
21
22
23
24
25
26
27
...
78
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2014