coreboot-gerrit April 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 36497a8 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
by Alexandru Gagniuc 20 Apr '14

20 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5556 -gerrit commit 36497a8aaf3b1767dddb74a1eda86026ee5be96d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 16:22:53 2014 -0500 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18 The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly. Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 10 ++++------ src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 2 ++ 3 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 93c46ae..3bf0721 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -65,12 +65,10 @@ Scope(\_GPE) { /* Start Scope GPE */ /* GPIO0 or GEvent8 event */ Method(_L18) { - /* DBGO("\\_GPE\\_L18\n") */ - Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Store("PCI bridge wake event", Debug) + /* Notify PCI bridges of wake event */ + Notify(\_SB.PCI0.PBR4, 0x02) + Notify(\_SB.PCI0.PBR5, 0x02) } /* Azalia SCI event */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8b48476..df0f8fd 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -386,6 +386,7 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, + {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, {SCI_MAP_OHCI_12_0, PME_GPE}, {SCI_MAP_OHCI_13_0, PME_GPE}, {SCI_MAP_XHCI_10_0, PME_GPE}, diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h index 8e51a77..95febb7 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -12,6 +12,7 @@ #define EC_SCI_GEVENT 3 #define EC_LID_GEVENT 22 #define EC_SMI_GEVENT 23 +#define PCIE_GEVENT 8 /* Any GEVENT pin can be mapped to any GPE. We try to keep the mapping 1:1, but * we make the distinction between GEVENT pin and SCI. @@ -19,5 +20,6 @@ #define EC_SCI_GPE EC_SCI_GEVENT #define EC_LID_GPE EC_LID_GEVENT #define PME_GPE 0x0b +#define PCIE_GPE 0x18 #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H */

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Patch set updated for coreboot: 7cbf6f4 hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11
by Alexandru Gagniuc 20 Apr '14

20 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5554 -gerrit commit 7cbf6f4db3b7be3405f24c0eb372afeaf5542e71 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 13:36:49 2014 -0500 hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11 Hudson ASL files assume the USB power event notifications are mapped to GPE 0xb. Since that GPE is not used on this board, map these events to GPE11. This GPE is already handled in ACPI via Method(_L0B). We adjust this method to also notify the XHCI controller at PCI 10:0. Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl | 18 +++++++++--------- src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 13 ++++++++++++- src/mainboard/hp/pavilion_m6_1035dx/mainboard.h | 1 + 3 files changed, 22 insertions(+), 10 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl index 7a78485..93c46ae 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl +++ b/src/mainboard/hp/pavilion_m6_1035dx/acpi/gpe.asl @@ -32,15 +32,15 @@ Scope(\_GPE) { /* Start Scope GPE */ /* USB controller PME# */ Method(_L0B) { - /* DBGO("\\_GPE\\_L0B\n") */ - Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + Store("USB PME", Debug) + /* Notify devices of wake event */ + Notify(\_SB.PCI0.UOH1, 0x02) + Notify(\_SB.PCI0.UOH2, 0x02) + Notify(\_SB.PCI0.UOH3, 0x02) + Notify(\_SB.PCI0.UOH4, 0x02) + Notify(\_SB.PCI0.XHC0, 0x02) + Notify(\_SB.PCI0.UEH1, 0x02) + Notify(\_SB.PWRB, 0x02) } /* ExtEvent0 SCI event */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index cf9ac4f..8b48476 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -374,11 +374,22 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { #define BLDCFG_FCH_GPIO_CONTROL_LIST (&pavilion_m6_1035dx_gpio[0]) +/* These definitions could be moved to a common Hudson header, should we decide + * to provide our own, saner SCI mapping function + */ #define GEVENT_PIN(gpe) ((gpe) + 0x40) +#define SCI_MAP_OHCI_12_0 0x58 +#define SCI_MAP_OHCI_13_0 0x59 +#define SCI_MAP_XHCI_10_0 0x78 +#define SCI_MAP_PWRBTN 0x73 SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, - {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, /* EC_SMI - GPE23 */ + {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, + {SCI_MAP_OHCI_12_0, PME_GPE}, + {SCI_MAP_OHCI_13_0, PME_GPE}, + {SCI_MAP_XHCI_10_0, PME_GPE}, + {SCI_MAP_PWRBTN, PME_GPE}, }; #define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h index bbf9c43..8e51a77 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h +++ b/src/mainboard/hp/pavilion_m6_1035dx/mainboard.h @@ -18,5 +18,6 @@ */ #define EC_SCI_GPE EC_SCI_GEVENT #define EC_LID_GPE EC_LID_GEVENT +#define PME_GPE 0x0b #endif /* _MAINBOARD_HP_PAVILION_M6_1035DX_MAINBOARD_H */

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Patch merged into coreboot/master: 0a57e99 hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resume
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 0a57e999b75d733669383bdc5d4c693b1d675a5d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 15:10:14 2014 -0500 hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resume It's not needed, and puts the EC back into APM mode. The EC does not shut down during S3 sleep, so we don't need to re-initialize it. Lid SMI will have been disabled in the switch to ACPI mode, don't re-enable it. Change-Id: I2c06df140f63427dac32ae095d29e68f64135358 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5555 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5555 for details. -gerrit

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Patch merged into coreboot/master: cf1f9b6 southbridge/hudson: Remove redundant definitions of ACPI IO ports
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit cf1f9b6a5bd1be169756dd1cd9568492a880651c Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 20 13:24:42 2014 -0500 southbridge/hudson: Remove redundant definitions of ACPI IO ports The ACPI IO ports were defined twice, and used inconsistently. Only keep one of the definitions for consistency. Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5558 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5558 for details. -gerrit

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Patch merged into coreboot/master: 991e951 southbridge/amd/agesa/hudson: Refactor SPI controller driver
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit 991e951461bc57debc2df82bac76d0ab57682e66 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 22:21:27 2014 -0500 southbridge/amd/agesa/hudson: Refactor SPI controller driver The SPI controller driver used numerical offsets to access SPI registers, making it unreadable without the datasheet. Use less magic and more #defines to improve readability. Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5557 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5557 for details. -gerrit

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Patch merged into coreboot/master: c38d991 hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPI
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit c38d9913878019bbe476b8b8bc5631846ef2e58f Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 21:29:59 2014 -0500 hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPI This patch completes ACPI support for the lid switch. The lid SCI now notifies the OSPM of the status change when the lid is closed or opened, allowing system to suspend. The wake source is also declares, and the system wakes when the lid is opened. The system resumes successfully, but the display still does not come back on. Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5549 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5549 for details. -gerrit

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Patch merged into coreboot/master: c4e7db5 hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping table
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit c4e7db51fc83b99c43b25a8f698a9d007ed45dc6 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 5 13:40:33 2014 -0500 hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping table Each GEVENT pins can be mapped to a specific GPE via the SCI map. The default mapping is not appropriate for this laptop, so use the AGESA functionality to map currently known events. Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5548 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5548 for details. -gerrit

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Patch merged into coreboot/master: a9a3661 hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file
by gerrit＠coreboot.org 20 Apr '14

20 Apr '14

the following patch was just integrated into master: commit a9a366171006aad3b928307c2dfb7b3e7793d4ef Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Apr 18 19:53:51 2014 -0500 hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file These definitions were scattered in a couple of files, and we risk scattering them all over the place. Provide a common file for these definitions. Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Reviewed-on: http://review.coreboot.org/5547 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5547 for details. -gerrit

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Patch set updated for coreboot: 935e42d southbridge/amd/agesa/hudson: Refactor SPI controller driver
by Alexandru Gagniuc 20 Apr '14

20 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5557 -gerrit commit 935e42d9046dec787c0158c0578b792a62a05113 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sat Apr 19 22:21:27 2014 -0500 southbridge/amd/agesa/hudson: Refactor SPI controller driver The SPI controller driver used numerical offsets to access SPI registers, making it unreadable without the datasheet. Use less magic and more #defines to improve readability. Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/spi.c | 69 ++++++++++++++++++++++++---------- 1 file changed, 50 insertions(+), 19 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index a46bf08..013bb21 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -31,23 +31,54 @@ static int bus_claimed = 0; #endif +#define SPI_REG_OPCODE 0x0 +#define SPI_REG_CNTRL01 0x1 +#define SPI_REG_CNTRL02 0x2 + #define CNTRL02_FIFO_RESET (1 << 4) + #define CNTRL02_EXEC_OPCODE (1 << 0) +#define SPI_REG_CNTRL03 0x3 + #define CNTRL03_SPIBUSY (1 << 7) +#define SPI_REG_FIFO 0xc +#define SPI_REG_CNTRL11 0xd + #define CNTRL11_FIFOPTR_MASK 0x07 + + static u32 spibar; +static inline uint8_t spi_read(uint8_t reg) +{ + return read8(spibar + reg); +} + +static inline void spi_write(uint8_t reg, uint8_t val) +{ + write8(spibar + reg, val); +} + static void reset_internal_fifo_pointer(void) { + uint8_t reg8; + do { - write8(spibar + 2, read8(spibar + 2) | 0x10); - } while (read8(spibar + 0xD) & 0x7); + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_FIFO_RESET; + spi_write(SPI_REG_CNTRL02, reg8); + } while (spi_read(SPI_REG_CNTRL11) & CNTRL11_FIFOPTR_MASK); } static void execute_command(void) { - write8(spibar + 2, read8(spibar + 2) | 1); + uint8_t reg8; + + reg8 = spi_read(SPI_REG_CNTRL02); + reg8 |= CNTRL02_EXEC_OPCODE; + spi_write(SPI_REG_CNTRL02, reg8); - while ((read8(spibar + 2) & 1) && (read8(spibar+3) & 0x80)); + while ((spi_read(SPI_REG_CNTRL02) & CNTRL02_EXEC_OPCODE) && + (spi_read(SPI_REG_CNTRL03) & CNTRL03_SPIBUSY)); } -void spi_init() +void spi_init(void) { device_t dev; @@ -59,13 +90,13 @@ int spi_xfer(struct spi_slave *slave, const void *dout, unsigned int bitsout, void *din, unsigned int bitsin) { /* First byte is cmd which can not being sent through FIFO. */ - u8 cmd = *(u8 *)dout++; - u8 readoffby1; + uint8_t cmd = *(uint8_t *)dout++; + uint8_t readoffby1; #if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE - u8 readwrite; + uint8_t readwrite; #endif - u8 bytesout, bytesin; - u8 count; + uint8_t bytesout, bytesin; + uint8_t count; bitsout -= 8; bytesout = bitsout / 8; @@ -74,19 +105,19 @@ int spi_xfer(struct spi_slave *slave, const void *dout, readoffby1 = bytesout ? 0 : 1; #if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE - write8(spibar + 0x1E, 5); - write8(spibar + 0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ - write8(spibar + 0x1E, 6); - write8(spibar + 0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ + spi_write(0x1E, 5); + spi_write(0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */ + spi_write(0x1E, 6); + spi_write(0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */ #else readwrite = (bytesin + readoffby1) << 4 | bytesout; - write8(spibar + 1, readwrite); + spi_write(SPI_REG_CNTRL01, readwrite); #endif - write8(spibar + 0, cmd); + spi_write(SPI_REG_OPCODE, cmd); reset_internal_fifo_pointer(); for (count = 0; count < bytesout; count++, dout++) { - write8(spibar + 0x0C, *(u8 *)dout); + spi_write(SPI_REG_FIFO, *(uint8_t *)dout); } reset_internal_fifo_pointer(); @@ -95,12 +126,12 @@ int spi_xfer(struct spi_slave *slave, const void *dout, reset_internal_fifo_pointer(); /* Skip the bytes we sent. */ for (count = 0; count < bytesout; count++) { - cmd = read8(spibar + 0x0C); + cmd = spi_read(SPI_REG_FIFO); } reset_internal_fifo_pointer(); for (count = 0; count < bytesin; count++, din++) { - *(u8 *)din = read8(spibar + 0x0C); + *(uint8_t *)din = spi_read(SPI_REG_FIFO); } return 0;

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New patch to review for coreboot: ead53a4 southbridge/hudson: Remove redundant definitions of ACPI IO ports
by Alexandru Gagniuc 20 Apr '14

20 Apr '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5558 -gerrit commit ead53a49d87131537d71223cbec0ae68fd39e4fc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Apr 20 13:24:42 2014 -0500 southbridge/hudson: Remove redundant definitions of ACPI IO ports The ACPI IO ports were defined twice, and used inconsistently. Only keep one of the definitions for consistency. Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/southbridge/amd/agesa/hudson/early_setup.c | 2 +- src/southbridge/amd/agesa/hudson/hudson.c | 2 +- src/southbridge/amd/agesa/hudson/hudson.h | 15 +++++---------- 3 files changed, 7 insertions(+), 12 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index a129512..d8fdc27 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -126,7 +126,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) #if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + u16 tmp = inw(ACPI_PM1_CNT_BLK); tmp = ((tmp & (7 << 10)) >> 10); /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index cd63c3e..39dab23 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -40,7 +40,7 @@ #if CONFIG_HAVE_ACPI_RESUME int acpi_get_sleep_type(void) { - u16 tmp = inw(PM1_CNT_BLK_ADDRESS); + u16 tmp = inw(ACPI_PM1_CNT_BLK); tmp = ((tmp & (7 << 10)) >> 10); /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index 683fd28..6f757eb 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -40,16 +40,6 @@ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */ -#define REV_HUDSON_A11 0x11 -#define REV_HUDSON_A12 0x12 - -#define PM1_EVT_BLK_ADDRESS 0x800 // AcpiPm1EvtBlkAddr; -#define PM1_CNT_BLK_ADDRESS 0x804 // AcpiPm1CntBlkAddr; -#define PM1_TMR_BLK_ADDRESS 0x808 // AcpiPmTmrBlkAddr; -#define CPU_CNT_BLK_ADDRESS 0x810 // CpuControlBlkAddr; -#define GPE0_BLK_ADDRESS 0x820 // AcpiGpe0BlkAddr; -#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 - #define ACPI_SMI_CTL_PORT 0xb2 #define ACPI_SMI_CMD_CST_CONTROL 0xde #define ACPI_SMI_CMD_PST_CONTROL 0xad @@ -57,6 +47,11 @@ #define ACPI_SMI_CMD_ENABLE 0xef #define ACPI_SMI_CMD_S4_REQ 0xc0 +#define REV_HUDSON_A11 0x11 +#define REV_HUDSON_A12 0x12 + +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 + #ifndef __SMM__ void pm_write8(u8 reg, u8 value);

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coreboot-gerrit April 2014